1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2020 Rockchip Electronics Co.
4 * Copyright (c) 2022 Edgeble AI Technologies
5 */
6
7 / {
8 compatible = "edgeble,neural-compute-m
9
10 aliases {
11 mmc0 = &emmc;
12 };
13
14 vccio_flash: vccio-flash-regulator {
15 compatible = "regulator-fixed"
16 enable-active-high;
17 gpio = <&gpio0 RK_PB3 GPIO_ACT
18 pinctrl-names = "default";
19 pinctrl-0 = <&flash_vol_sel>;
20 regulator-name = "vccio_flash"
21 regulator-always-on;
22 regulator-boot-on;
23 regulator-min-microvolt = <180
24 regulator-max-microvolt = <180
25 vin-supply = <&vcc_3v3>;
26 };
27
28 sdio_pwrseq: pwrseq-sdio {
29 compatible = "mmc-pwrseq-simpl
30 clocks = <&rk809 1>;
31 clock-names = "ext_clock";
32 pinctrl-names = "default";
33 pinctrl-0 = <&wifi_enable_h>;
34 reset-gpios = <&gpio1 RK_PD0 G
35 };
36 };
37
38 &cpu0 {
39 cpu-supply = <&vdd_arm>;
40 };
41
42 &emmc {
43 bus-width = <8>;
44 non-removable;
45 pinctrl-names = "default";
46 pinctrl-0 = <&emmc_bus8 &emmc_cmd &emm
47 rockchip,default-sample-phase = <90>;
48 vmmc-supply = <&vcc_3v3>;
49 vqmmc-supply = <&vccio_flash>;
50 status = "okay";
51 };
52
53 &i2c0 {
54 clock-frequency = <400000>;
55 status = "okay";
56
57 rk809: pmic@20 {
58 compatible = "rockchip,rk809";
59 reg = <0x20>;
60 interrupt-parent = <&gpio0>;
61 interrupts = <RK_PB1 IRQ_TYPE_
62 #clock-cells = <1>;
63 clock-output-names = "rk808-cl
64 pinctrl-names = "default";
65 pinctrl-0 = <&pmic_int_l>;
66 rockchip,system-power-controll
67 wakeup-source;
68
69 vcc1-supply = <&vcc5v0_sys>;
70 vcc2-supply = <&vcc5v0_sys>;
71 vcc3-supply = <&vcc5v0_sys>;
72 vcc4-supply = <&vcc5v0_sys>;
73 vcc5-supply = <&vcc_buck5>;
74 vcc6-supply = <&vcc_buck5>;
75 vcc7-supply = <&vcc5v0_sys>;
76 vcc8-supply = <&vcc3v3_sys>;
77 vcc9-supply = <&vcc5v0_sys>;
78
79 regulators {
80 vdd_npu_vepu: DCDC_REG
81 regulator-name
82 regulator-alwa
83 regulator-boot
84 regulator-init
85 regulator-min-
86 regulator-max-
87 regulator-ramp
88 regulator-stat
89 regula
90 };
91 };
92
93 vdd_arm: DCDC_REG2 {
94 regulator-name
95 regulator-alwa
96 regulator-boot
97 regulator-init
98 regulator-min-
99 regulator-max-
100 regulator-ramp
101 regulator-stat
102 regula
103 };
104 };
105
106 vcc_ddr: DCDC_REG3 {
107 regulator-name
108 regulator-alwa
109 regulator-boot
110 regulator-init
111 regulator-stat
112 regula
113 };
114 };
115
116 vcc3v3_sys: DCDC_REG4
117 regulator-name
118 regulator-alwa
119 regulator-boot
120 regulator-init
121 regulator-min-
122 regulator-max-
123 regulator-stat
124 regula
125 regula
126 };
127 };
128
129 vcc_buck5: DCDC_REG5 {
130 regulator-name
131 regulator-alwa
132 regulator-boot
133 regulator-min-
134 regulator-max-
135 regulator-stat
136 regula
137 regula
138 };
139 };
140
141 vcc_0v8: LDO_REG1 {
142 regulator-name
143 regulator-alwa
144 regulator-boot
145 regulator-min-
146 regulator-max-
147 regulator-stat
148 regula
149 };
150 };
151
152 vcc1v8_pmu: LDO_REG2 {
153 regulator-name
154 regulator-alwa
155 regulator-boot
156 regulator-min-
157 regulator-max-
158 regulator-stat
159 regula
160 regula
161 };
162 };
163
164 vdd0v8_pmu: LDO_REG3 {
165 regulator-name
166 regulator-alwa
167 regulator-boot
168 regulator-min-
169 regulator-max-
170 regulator-stat
171 regula
172 regula
173 };
174 };
175
176 vcc_1v8: LDO_REG4 {
177 regulator-name
178 regulator-alwa
179 regulator-boot
180 regulator-min-
181 regulator-max-
182 regulator-stat
183 regula
184 regula
185 };
186 };
187
188 vcc_dovdd: LDO_REG5 {
189 regulator-name
190 regulator-boot
191 regulator-min-
192 regulator-max-
193 regulator-stat
194 regula
195 };
196 };
197
198 vcc_dvdd: LDO_REG6 {
199 regulator-name
200 regulator-min-
201 regulator-max-
202 regulator-stat
203 regula
204 };
205 };
206
207 vcc_avdd: LDO_REG7 {
208 regulator-name
209 regulator-min-
210 regulator-max-
211 regulator-stat
212 regula
213 };
214 };
215
216 vccio_sd: LDO_REG8 {
217 regulator-name
218 regulator-alwa
219 regulator-boot
220 regulator-min-
221 regulator-max-
222 regulator-stat
223 regula
224 };
225 };
226
227 vcc3v3_sd: LDO_REG9 {
228 regulator-name
229 regulator-alwa
230 regulator-boot
231 regulator-min-
232 regulator-max-
233 regulator-stat
234 regula
235 };
236 };
237
238 vcc_5v0: SWITCH_REG1 {
239 regulator-name
240 };
241
242 vcc_3v3: SWITCH_REG2 {
243 regulator-name
244 regulator-alwa
245 regulator-boot
246 };
247 };
248 };
249 };
250
251 &pinctrl {
252 bt {
253 bt_enable: bt-enable {
254 rockchip,pins = <3 RK_
255 };
256 };
257
258 flash {
259 flash_vol_sel: flash-vol-sel {
260 rockchip,pins = <0 RK_
261 };
262 };
263
264 pmic {
265 pmic_int_l: pmic-int-l {
266 rockchip,pins = <0 RK_
267 };
268 };
269
270 wifi {
271 wifi_enable_h: wifi-enable-h {
272 rockchip,pins = <1 RK_
273 };
274 };
275 };
276
277 &pmu_io_domains {
278 pmuio0-supply = <&vcc1v8_pmu>;
279 pmuio1-supply = <&vcc3v3_sys>;
280 vccio1-supply = <&vccio_flash>;
281 vccio2-supply = <&vccio_sd>;
282 vccio3-supply = <&vcc_1v8>;
283 vccio4-supply = <&vcc_dovdd>;
284 vccio5-supply = <&vcc_1v8>;
285 vccio6-supply = <&vcc_1v8>;
286 vccio7-supply = <&vcc_dovdd>;
287 status = "okay";
288 };
289
290 &saradc {
291 vref-supply = <&vcc_1v8>;
292 status = "okay";
293 };
294
295 &sfc {
296 pinctrl-names = "default";
297 pinctrl-0 = <&fspi_pins>;
298 #address-cells = <1>;
299 #size-cells = <0>;
300 status = "okay";
301
302 flash@0 {
303 compatible = "jedec,spi-nor";
304 reg = <0>;
305 spi-max-frequency = <50000000>
306 spi-rx-bus-width = <4>;
307 spi-tx-bus-width = <1>;
308 };
309 };
310
311 &sdio {
312 bus-width = <4>;
313 cap-sd-highspeed;
314 cap-sdio-irq;
315 keep-power-in-suspend;
316 max-frequency = <100000000>;
317 mmc-pwrseq = <&sdio_pwrseq>;
318 non-removable;
319 pinctrl-names = "default";
320 pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &
321 rockchip,default-sample-phase = <90>;
322 sd-uhs-sdr104;
323 vmmc-supply = <&vcc3v3_sys>;
324 vqmmc-supply = <&vcc_1v8>;
325 status = "okay";
326 #address-cells = <1>;
327 #size-cells = <0>;
328 };
329
330 &uart0 {
331 pinctrl-names = "default";
332 pinctrl-0 = <&uart0_xfer &uart0_ctsn &
333 status = "okay";
334
335 bluetooth {
336 compatible = "qcom,qca9377-bt"
337 clocks = <&rk809 1>;
338 enable-gpios = <&gpio3 RK_PA5
339 max-speed = <2000000>;
340 pinctrl-names = "default";
341 pinctrl-0 = <&bt_enable>;
342 vddxo-supply = <&vcc3v3_sys>;
343 vddio-supply = <&vcc_1v8>;
344 };
345 };
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