1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2019 Fuzhou Rockchip Electron
4 */
5
6 #include <dt-bindings/clock/rockchip,rv1126-cr
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm
9 #include <dt-bindings/interrupt-controller/irq
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rockchip,rv1126-po
12 #include <dt-bindings/soc/rockchip,boot-mode.h
13
14 / {
15 #address-cells = <1>;
16 #size-cells = <1>;
17
18 compatible = "rockchip,rv1126";
19
20 interrupt-parent = <&gic>;
21
22 aliases {
23 i2c0 = &i2c0;
24 i2c2 = &i2c2;
25 i2c3 = &i2c3;
26 serial0 = &uart0;
27 serial1 = &uart1;
28 serial2 = &uart2;
29 serial3 = &uart3;
30 serial4 = &uart4;
31 serial5 = &uart5;
32 };
33
34 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 cpu0: cpu@f00 {
39 device_type = "cpu";
40 compatible = "arm,cort
41 reg = <0xf00>;
42 enable-method = "psci"
43 clocks = <&cru ARMCLK>
44 };
45
46 cpu1: cpu@f01 {
47 device_type = "cpu";
48 compatible = "arm,cort
49 reg = <0xf01>;
50 enable-method = "psci"
51 clocks = <&cru ARMCLK>
52 };
53
54 cpu2: cpu@f02 {
55 device_type = "cpu";
56 compatible = "arm,cort
57 reg = <0xf02>;
58 enable-method = "psci"
59 clocks = <&cru ARMCLK>
60 };
61
62 cpu3: cpu@f03 {
63 device_type = "cpu";
64 compatible = "arm,cort
65 reg = <0xf03>;
66 enable-method = "psci"
67 clocks = <&cru ARMCLK>
68 };
69 };
70
71 arm-pmu {
72 compatible = "arm,cortex-a7-pm
73 interrupts = <GIC_SPI 123 IRQ_
74 <GIC_SPI 124 IRQ_
75 <GIC_SPI 125 IRQ_
76 <GIC_SPI 126 IRQ_
77 interrupt-affinity = <&cpu0>,
78 };
79
80 psci {
81 compatible = "arm,psci-1.0";
82 method = "smc";
83 };
84
85 timer {
86 compatible = "arm,armv7-timer"
87 interrupts = <GIC_PPI 13 (GIC_
88 <GIC_PPI 14 (GIC_
89 <GIC_PPI 11 (GIC_
90 <GIC_PPI 10 (GIC_
91 clock-frequency = <24000000>;
92 };
93
94 display_subsystem {
95 compatible = "rockchip,display
96 ports = <&vop_out>;
97 };
98
99 xin24m: oscillator {
100 compatible = "fixed-clock";
101 clock-frequency = <24000000>;
102 clock-output-names = "xin24m";
103 #clock-cells = <0>;
104 };
105
106 grf: syscon@fe000000 {
107 compatible = "rockchip,rv1126-
108 reg = <0xfe000000 0x20000>;
109 };
110
111 pmugrf: syscon@fe020000 {
112 compatible = "rockchip,rv1126-
113 reg = <0xfe020000 0x1000>;
114
115 pmu_io_domains: io-domains {
116 compatible = "rockchip
117 status = "disabled";
118 };
119 };
120
121 qos_emmc: qos@fe860000 {
122 compatible = "rockchip,rv1126-
123 reg = <0xfe860000 0x20>;
124 };
125
126 qos_nandc: qos@fe860080 {
127 compatible = "rockchip,rv1126-
128 reg = <0xfe860080 0x20>;
129 };
130
131 qos_sfc: qos@fe860200 {
132 compatible = "rockchip,rv1126-
133 reg = <0xfe860200 0x20>;
134 };
135
136 qos_sdio: qos@fe86c000 {
137 compatible = "rockchip,rv1126-
138 reg = <0xfe86c000 0x20>;
139 };
140
141 qos_iep: qos@fe8a0000 {
142 compatible = "rockchip,rv1126-
143 reg = <0xfe8a0000 0x20>;
144 };
145
146 qos_rga_rd: qos@fe8a0080 {
147 compatible = "rockchip,rv1126-
148 reg = <0xfe8a0080 0x20>;
149 };
150
151 qos_rga_wr: qos@fe8a0100 {
152 compatible = "rockchip,rv1126-
153 reg = <0xfe8a0100 0x20>;
154 };
155
156 qos_vop: qos@fe8a0180 {
157 compatible = "rockchip,rv1126-
158 reg = <0xfe8a0180 0x20>;
159 };
160
161 gic: interrupt-controller@feff0000 {
162 compatible = "arm,gic-400";
163 interrupt-controller;
164 #interrupt-cells = <3>;
165 #address-cells = <0>;
166
167 reg = <0xfeff1000 0x1000>,
168 <0xfeff2000 0x2000>,
169 <0xfeff4000 0x2000>,
170 <0xfeff6000 0x2000>;
171 interrupts = <GIC_PPI 9 (GIC_C
172 };
173
174 pmu: power-management@ff3e0000 {
175 compatible = "rockchip,rv1126-
176 reg = <0xff3e0000 0x1000>;
177
178 power: power-controller {
179 compatible = "rockchip
180 #power-domain-cells =
181 #address-cells = <1>;
182 #size-cells = <0>;
183
184 power-domain@RV1126_PD
185 reg = <RV1126_
186 clocks = <&cru
187 <&cru
188 <&cru
189 <&cru
190 <&cru
191 <&cru
192 <&cru
193 pm_qos = <&qos
194 <&qos
195 <&qos
196 #power-domain-
197 };
198
199 power-domain@RV1126_PD
200 reg = <RV1126_
201 clocks = <&cru
202 <&cru
203 pm_qos = <&qos
204 #power-domain-
205 };
206
207 power-domain@RV1126_PD
208 reg = <RV1126_
209 clocks = <&cru
210 <&cru
211 <&cru
212 <&cru
213 <&cru
214 <&cru
215 <&cru
216 <&cru
217 <&cru
218 <&cru
219 pm_qos = <&qos
220 <&qos
221 <&qos
222 <&qos
223 #power-domain-
224 };
225 };
226 };
227
228 i2c0: i2c@ff3f0000 {
229 compatible = "rockchip,rv1126-
230 reg = <0xff3f0000 0x1000>;
231 interrupts = <GIC_SPI 4 IRQ_TY
232 rockchip,grf = <&pmugrf>;
233 clocks = <&pmucru CLK_I2C0>, <
234 clock-names = "i2c", "pclk";
235 pinctrl-names = "default";
236 pinctrl-0 = <&i2c0_xfer>;
237 #address-cells = <1>;
238 #size-cells = <0>;
239 status = "disabled";
240 };
241
242 i2c2: i2c@ff400000 {
243 compatible = "rockchip,rv1126-
244 reg = <0xff400000 0x1000>;
245 interrupts = <GIC_SPI 6 IRQ_TY
246 rockchip,grf = <&pmugrf>;
247 clocks = <&pmucru CLK_I2C2>, <
248 clock-names = "i2c", "pclk";
249 pinctrl-names = "default";
250 pinctrl-0 = <&i2c2_xfer>;
251 #address-cells = <1>;
252 #size-cells = <0>;
253 status = "disabled";
254 };
255
256 uart1: serial@ff410000 {
257 compatible = "rockchip,rv1126-
258 reg = <0xff410000 0x100>;
259 interrupts = <GIC_SPI 13 IRQ_T
260 clock-frequency = <24000000>;
261 clocks = <&pmucru SCLK_UART1>,
262 clock-names = "baudclk", "apb_
263 dmas = <&dmac 7>, <&dmac 6>;
264 dma-names = "tx", "rx";
265 pinctrl-names = "default";
266 pinctrl-0 = <&uart1m0_xfer>;
267 reg-shift = <2>;
268 reg-io-width = <4>;
269 status = "disabled";
270 };
271
272 pwm0: pwm@ff430000 {
273 compatible = "rockchip,rv1126-
274 reg = <0xff430000 0x10>;
275 clock-names = "pwm", "pclk";
276 clocks = <&pmucru CLK_PWM0>, <
277 pinctrl-names = "default";
278 pinctrl-0 = <&pwm0m0_pins>;
279 #pwm-cells = <3>;
280 status = "disabled";
281 };
282
283 pwm1: pwm@ff430010 {
284 compatible = "rockchip,rv1126-
285 reg = <0xff430010 0x10>;
286 clock-names = "pwm", "pclk";
287 clocks = <&pmucru CLK_PWM0>, <
288 pinctrl-names = "default";
289 pinctrl-0 = <&pwm1m0_pins>;
290 #pwm-cells = <3>;
291 status = "disabled";
292 };
293
294 pwm2: pwm@ff430020 {
295 compatible = "rockchip,rv1126-
296 reg = <0xff430020 0x10>;
297 clock-names = "pwm", "pclk";
298 clocks = <&pmucru CLK_PWM0>, <
299 pinctrl-names = "default";
300 pinctrl-0 = <&pwm2m0_pins>;
301 #pwm-cells = <3>;
302 status = "disabled";
303 };
304
305 pwm3: pwm@ff430030 {
306 compatible = "rockchip,rv1126-
307 reg = <0xff430030 0x10>;
308 clock-names = "pwm", "pclk";
309 clocks = <&pmucru CLK_PWM0>, <
310 pinctrl-names = "default";
311 pinctrl-0 = <&pwm3m0_pins>;
312 #pwm-cells = <3>;
313 status = "disabled";
314 };
315
316 pwm4: pwm@ff440000 {
317 compatible = "rockchip,rv1126-
318 reg = <0xff440000 0x10>;
319 clock-names = "pwm", "pclk";
320 clocks = <&pmucru CLK_PWM1>, <
321 pinctrl-names = "default";
322 pinctrl-0 = <&pwm4m0_pins>;
323 #pwm-cells = <3>;
324 status = "disabled";
325 };
326
327 pwm5: pwm@ff440010 {
328 compatible = "rockchip,rv1126-
329 reg = <0xff440010 0x10>;
330 clock-names = "pwm", "pclk";
331 clocks = <&pmucru CLK_PWM1>, <
332 pinctrl-names = "default";
333 pinctrl-0 = <&pwm5m0_pins>;
334 #pwm-cells = <3>;
335 status = "disabled";
336 };
337
338 pwm6: pwm@ff440020 {
339 compatible = "rockchip,rv1126-
340 reg = <0xff440020 0x10>;
341 clock-names = "pwm", "pclk";
342 clocks = <&pmucru CLK_PWM1>, <
343 pinctrl-names = "default";
344 pinctrl-0 = <&pwm6m0_pins>;
345 #pwm-cells = <3>;
346 status = "disabled";
347 };
348
349 pwm7: pwm@ff440030 {
350 compatible = "rockchip,rv1126-
351 reg = <0xff440030 0x10>;
352 clock-names = "pwm", "pclk";
353 clocks = <&pmucru CLK_PWM1>, <
354 pinctrl-names = "default";
355 pinctrl-0 = <&pwm7m0_pins>;
356 #pwm-cells = <3>;
357 status = "disabled";
358 };
359
360 pmucru: clock-controller@ff480000 {
361 compatible = "rockchip,rv1126-
362 reg = <0xff480000 0x1000>;
363 rockchip,grf = <&grf>;
364 #clock-cells = <1>;
365 #reset-cells = <1>;
366 };
367
368 cru: clock-controller@ff490000 {
369 compatible = "rockchip,rv1126-
370 reg = <0xff490000 0x1000>;
371 clocks = <&xin24m>;
372 clock-names = "xin24m";
373 rockchip,grf = <&grf>;
374 #clock-cells = <1>;
375 #reset-cells = <1>;
376 };
377
378 dmac: dma-controller@ff4e0000 {
379 compatible = "arm,pl330", "arm
380 reg = <0xff4e0000 0x4000>;
381 interrupts = <GIC_SPI 1 IRQ_TY
382 <GIC_SPI 2 IRQ_TY
383 #dma-cells = <1>;
384 arm,pl330-periph-burst;
385 clocks = <&cru ACLK_DMAC>;
386 clock-names = "apb_pclk";
387 };
388
389 i2c3: i2c@ff520000 {
390 compatible = "rockchip,rv1126-
391 reg = <0xff520000 0x1000>;
392 interrupts = <GIC_SPI 7 IRQ_TY
393 clocks = <&cru CLK_I2C3>, <&cr
394 clock-names = "i2c", "pclk";
395 pinctrl-names = "default";
396 pinctrl-0 = <&i2c3m0_xfer>;
397 rockchip,grf = <&pmugrf>;
398 #address-cells = <1>;
399 #size-cells = <0>;
400 status = "disabled";
401 };
402
403 pwm8: pwm@ff550000 {
404 compatible = "rockchip,rv1126-
405 reg = <0xff550000 0x10>;
406 clock-names = "pwm", "pclk";
407 clocks = <&cru CLK_PWM2>, <&cr
408 pinctrl-0 = <&pwm8m0_pins>;
409 pinctrl-names = "default";
410 #pwm-cells = <3>;
411 status = "disabled";
412 };
413
414 pwm9: pwm@ff550010 {
415 compatible = "rockchip,rv1126-
416 reg = <0xff550010 0x10>;
417 clock-names = "pwm", "pclk";
418 clocks = <&cru CLK_PWM2>, <&cr
419 pinctrl-0 = <&pwm9m0_pins>;
420 pinctrl-names = "default";
421 #pwm-cells = <3>;
422 status = "disabled";
423 };
424
425 pwm10: pwm@ff550020 {
426 compatible = "rockchip,rv1126-
427 reg = <0xff550020 0x10>;
428 clock-names = "pwm", "pclk";
429 clocks = <&cru CLK_PWM2>, <&cr
430 pinctrl-0 = <&pwm10m0_pins>;
431 pinctrl-names = "default";
432 #pwm-cells = <3>;
433 status = "disabled";
434 };
435
436 pwm11: pwm@ff550030 {
437 compatible = "rockchip,rv1126-
438 reg = <0xff550030 0x10>;
439 clock-names = "pwm", "pclk";
440 clocks = <&cru CLK_PWM2>, <&cr
441 pinctrl-0 = <&pwm11m0_pins>;
442 pinctrl-names = "default";
443 #pwm-cells = <3>;
444 status = "disabled";
445 };
446
447 uart0: serial@ff560000 {
448 compatible = "rockchip,rv1126-
449 reg = <0xff560000 0x100>;
450 interrupts = <GIC_SPI 12 IRQ_T
451 clock-frequency = <24000000>;
452 clocks = <&cru SCLK_UART0>, <&
453 clock-names = "baudclk", "apb_
454 dmas = <&dmac 5>, <&dmac 4>;
455 dma-names = "tx", "rx";
456 pinctrl-names = "default";
457 pinctrl-0 = <&uart0_xfer>;
458 reg-shift = <2>;
459 reg-io-width = <4>;
460 status = "disabled";
461 };
462
463 uart2: serial@ff570000 {
464 compatible = "rockchip,rv1126-
465 reg = <0xff570000 0x100>;
466 interrupts = <GIC_SPI 14 IRQ_T
467 clock-frequency = <24000000>;
468 clocks = <&cru SCLK_UART2>, <&
469 clock-names = "baudclk", "apb_
470 dmas = <&dmac 9>, <&dmac 8>;
471 dma-names = "tx", "rx";
472 pinctrl-names = "default";
473 pinctrl-0 = <&uart2m1_xfer>;
474 reg-shift = <2>;
475 reg-io-width = <4>;
476 status = "disabled";
477 };
478
479 uart3: serial@ff580000 {
480 compatible = "rockchip,rv1126-
481 reg = <0xff580000 0x100>;
482 interrupts = <GIC_SPI 15 IRQ_T
483 clock-frequency = <24000000>;
484 clocks = <&cru SCLK_UART3>, <&
485 clock-names = "baudclk", "apb_
486 dmas = <&dmac 11>, <&dmac 10>;
487 dma-names = "tx", "rx";
488 pinctrl-names = "default";
489 pinctrl-0 = <&uart3m0_xfer>;
490 reg-shift = <2>;
491 reg-io-width = <4>;
492 status = "disabled";
493 };
494
495 uart4: serial@ff590000 {
496 compatible = "rockchip,rv1126-
497 reg = <0xff590000 0x100>;
498 interrupts = <GIC_SPI 16 IRQ_T
499 clock-frequency = <24000000>;
500 clocks = <&cru SCLK_UART4>, <&
501 clock-names = "baudclk", "apb_
502 dmas = <&dmac 13>, <&dmac 12>;
503 dma-names = "tx", "rx";
504 pinctrl-names = "default";
505 pinctrl-0 = <&uart4m0_xfer>;
506 reg-shift = <2>;
507 reg-io-width = <4>;
508 status = "disabled";
509 };
510
511 uart5: serial@ff5a0000 {
512 compatible = "rockchip,rv1126-
513 reg = <0xff5a0000 0x100>;
514 interrupts = <GIC_SPI 17 IRQ_T
515 clock-frequency = <24000000>;
516 clocks = <&cru SCLK_UART5>, <&
517 clock-names = "baudclk", "apb_
518 dmas = <&dmac 15>, <&dmac 14>;
519 dma-names = "tx", "rx";
520 pinctrl-names = "default";
521 pinctrl-0 = <&uart5m0_xfer>;
522 reg-shift = <2>;
523 reg-io-width = <4>;
524 status = "disabled";
525 };
526
527 saradc: adc@ff5e0000 {
528 compatible = "rockchip,rv1126-
529 reg = <0xff5e0000 0x100>;
530 interrupts = <GIC_SPI 40 IRQ_T
531 #io-channel-cells = <1>;
532 clocks = <&cru CLK_SARADC>, <&
533 clock-names = "saradc", "apb_p
534 resets = <&cru SRST_SARADC_P>;
535 reset-names = "saradc-apb";
536 status = "disabled";
537 };
538
539 timer0: timer@ff660000 {
540 compatible = "rockchip,rv1126-
541 reg = <0xff660000 0x20>;
542 interrupts = <GIC_SPI 24 IRQ_T
543 clocks = <&cru PCLK_TIMER>, <&
544 clock-names = "pclk", "timer";
545 };
546
547 i2s0: i2s@ff800000 {
548 compatible = "rockchip,rv1126-
549 reg = <0xff800000 0x1000>;
550 interrupts = <GIC_SPI 46 IRQ_T
551 clocks = <&cru MCLK_I2S0_TX>,
552 clock-names = "mclk_tx", "mclk
553 dmas = <&dmac 20>, <&dmac 19>;
554 dma-names = "tx", "rx";
555 pinctrl-names = "default";
556 pinctrl-0 = <&i2s0m0_sclk_tx>,
557 <&i2s0m0_sclk_rx>
558 <&i2s0m0_mclk>,
559 <&i2s0m0_lrck_tx>
560 <&i2s0m0_lrck_rx>
561 <&i2s0m0_sdi0>,
562 <&i2s0m0_sdo0>,
563 <&i2s0m0_sdo1_sdi
564 <&i2s0m0_sdo2_sdi
565 <&i2s0m0_sdo3_sdi
566 resets = <&cru SRST_I2S0_TX_M>
567 reset-names = "tx-m", "rx-m";
568 rockchip,grf = <&grf>;
569 #sound-dai-cells = <0>;
570 status = "disabled";
571 };
572
573 vop: vop@ffb00000 {
574 compatible = "rockchip,rv1126-
575 reg = <0xffb00000 0x200>, <0xf
576 interrupts = <GIC_SPI 59 IRQ_T
577 clock-names = "aclk_vop", "dcl
578 clocks = <&cru ACLK_VOP>, <&cr
579 reset-names = "axi", "ahb", "d
580 resets = <&cru SRST_VOP_A>, <&
581 iommus = <&vop_mmu>;
582 power-domains = <&power RV1126
583 status = "disabled";
584
585 vop_out: port {
586 #address-cells = <1>;
587 #size-cells = <0>;
588
589 vop_out_rgb: endpoint@
590 reg = <0>;
591 };
592
593 vop_out_dsi: endpoint@
594 reg = <1>;
595 };
596 };
597 };
598
599 vop_mmu: iommu@ffb00f00 {
600 compatible = "rockchip,iommu";
601 reg = <0xffb00f00 0x100>;
602 interrupts = <GIC_SPI 59 IRQ_T
603 clock-names = "aclk", "iface";
604 clocks = <&cru ACLK_VOP>, <&cr
605 #iommu-cells = <0>;
606 power-domains = <&power RV1126
607 status = "disabled";
608 };
609
610 gmac: ethernet@ffc40000 {
611 compatible = "rockchip,rv1126-
612 reg = <0xffc40000 0x4000>;
613 interrupts = <GIC_SPI 95 IRQ_T
614 <GIC_SPI 96 IRQ_T
615 interrupt-names = "macirq", "e
616 rockchip,grf = <&grf>;
617 clocks = <&cru CLK_GMAC_SRC>,
618 <&cru CLK_GMAC_TX_RX>
619 <&cru ACLK_GMAC>, <&c
620 <&cru CLK_GMAC_TX_RX>
621 clock-names = "stmmaceth", "ma
622 "mac_clk_tx", "c
623 "aclk_mac", "pcl
624 "clk_mac_speed",
625 resets = <&cru SRST_GMAC_A>;
626 reset-names = "stmmaceth";
627
628 snps,mixed-burst;
629 snps,tso;
630
631 snps,axi-config = <&stmmac_axi
632 snps,mtl-rx-config = <&mtl_rx_
633 snps,mtl-tx-config = <&mtl_tx_
634 status = "disabled";
635
636 mdio: mdio {
637 compatible = "snps,dwm
638 #address-cells = <0x1>
639 #size-cells = <0x0>;
640 };
641
642 stmmac_axi_setup: stmmac-axi-c
643 snps,wr_osr_lmt = <4>;
644 snps,rd_osr_lmt = <8>;
645 snps,blen = <0 0 0 0 1
646 };
647
648 mtl_rx_setup: rx-queues-config
649 snps,rx-queues-to-use
650 queue0 {};
651 };
652
653 mtl_tx_setup: tx-queues-config
654 snps,tx-queues-to-use
655 queue0 {};
656 };
657 };
658
659 emmc: mmc@ffc50000 {
660 compatible = "rockchip,rv1126-
661 reg = <0xffc50000 0x4000>;
662 interrupts = <GIC_SPI 78 IRQ_T
663 clocks = <&cru HCLK_EMMC>, <&c
664 <&cru SCLK_EMMC_DRV>,
665 clock-names = "biu", "ciu", "c
666 fifo-depth = <0x100>;
667 max-frequency = <200000000>;
668 power-domains = <&power RV1126
669 status = "disabled";
670 };
671
672 sdmmc: mmc@ffc60000 {
673 compatible = "rockchip,rv1126-
674 reg = <0xffc60000 0x4000>;
675 interrupts = <GIC_SPI 76 IRQ_T
676 clocks = <&cru HCLK_SDMMC>, <&
677 <&cru SCLK_SDMMC_DRV>
678 clock-names = "biu", "ciu", "c
679 fifo-depth = <0x100>;
680 max-frequency = <200000000>;
681 status = "disabled";
682 };
683
684 sdio: mmc@ffc70000 {
685 compatible = "rockchip,rv1126-
686 reg = <0xffc70000 0x4000>;
687 interrupts = <GIC_SPI 77 IRQ_T
688 clocks = <&cru HCLK_SDIO>, <&c
689 <&cru SCLK_SDIO_DRV>,
690 clock-names = "biu", "ciu", "c
691 fifo-depth = <0x100>;
692 max-frequency = <200000000>;
693 power-domains = <&power RV1126
694 status = "disabled";
695 };
696
697 sfc: spi@ffc90000 {
698 compatible = "rockchip,sfc";
699 reg = <0xffc90000 0x4000>;
700 interrupts = <GIC_SPI 80 IRQ_T
701 assigned-clocks = <&cru SCLK_S
702 assigned-clock-rates = <800000
703 clock-names = "clk_sfc", "hclk
704 clocks = <&cru SCLK_SFC>, <&cr
705 power-domains = <&power RV1126
706 status = "disabled";
707 };
708
709 pinctrl: pinctrl {
710 compatible = "rockchip,rv1126-
711 rockchip,grf = <&grf>;
712 rockchip,pmu = <&pmugrf>;
713 #address-cells = <1>;
714 #size-cells = <1>;
715 ranges;
716
717 gpio0: gpio@ff460000 {
718 compatible = "rockchip
719 reg = <0xff460000 0x10
720 interrupts = <GIC_SPI
721 clocks = <&pmucru PCLK
722 gpio-controller;
723 #gpio-cells = <2>;
724 interrupt-controller;
725 #interrupt-cells = <2>
726 };
727
728 gpio1: gpio@ff620000 {
729 compatible = "rockchip
730 reg = <0xff620000 0x10
731 interrupts = <GIC_SPI
732 clocks = <&cru PCLK_GP
733 gpio-controller;
734 #gpio-cells = <2>;
735 interrupt-controller;
736 #interrupt-cells = <2>
737 };
738
739 gpio2: gpio@ff630000 {
740 compatible = "rockchip
741 reg = <0xff630000 0x10
742 interrupts = <GIC_SPI
743 clocks = <&cru PCLK_GP
744 gpio-controller;
745 #gpio-cells = <2>;
746 interrupt-controller;
747 #interrupt-cells = <2>
748 };
749
750 gpio3: gpio@ff640000 {
751 compatible = "rockchip
752 reg = <0xff640000 0x10
753 interrupts = <GIC_SPI
754 clocks = <&cru PCLK_GP
755 gpio-controller;
756 #gpio-cells = <2>;
757 interrupt-controller;
758 #interrupt-cells = <2>
759 };
760
761 gpio4: gpio@ff650000 {
762 compatible = "rockchip
763 reg = <0xff650000 0x10
764 interrupts = <GIC_SPI
765 clocks = <&cru PCLK_GP
766 gpio-controller;
767 #gpio-cells = <2>;
768 interrupt-controller;
769 #interrupt-cells = <2>
770 };
771 };
772 };
773
774 #include "rv1126-pinctrl.dtsi"
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