1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (c) 2019 Fuzhou Rockchip Electron 3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
4 */ 4 */
5 5
6 #include <dt-bindings/clock/rockchip,rv1126-cr 6 #include <dt-bindings/clock/rockchip,rv1126-cru.h>
7 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq 9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h> 10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rockchip,rv1126-po 11 #include <dt-bindings/power/rockchip,rv1126-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h 12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 13
14 / { 14 / {
15 #address-cells = <1>; 15 #address-cells = <1>;
16 #size-cells = <1>; 16 #size-cells = <1>;
17 17
18 compatible = "rockchip,rv1126"; 18 compatible = "rockchip,rv1126";
19 19
20 interrupt-parent = <&gic>; 20 interrupt-parent = <&gic>;
21 21
22 aliases { 22 aliases {
23 i2c0 = &i2c0; 23 i2c0 = &i2c0;
24 i2c2 = &i2c2; 24 i2c2 = &i2c2;
25 i2c3 = &i2c3; <<
26 serial0 = &uart0; 25 serial0 = &uart0;
27 serial1 = &uart1; 26 serial1 = &uart1;
28 serial2 = &uart2; 27 serial2 = &uart2;
29 serial3 = &uart3; 28 serial3 = &uart3;
30 serial4 = &uart4; 29 serial4 = &uart4;
31 serial5 = &uart5; 30 serial5 = &uart5;
32 }; 31 };
33 32
34 cpus { 33 cpus {
35 #address-cells = <1>; 34 #address-cells = <1>;
36 #size-cells = <0>; 35 #size-cells = <0>;
37 36
38 cpu0: cpu@f00 { 37 cpu0: cpu@f00 {
39 device_type = "cpu"; 38 device_type = "cpu";
40 compatible = "arm,cort 39 compatible = "arm,cortex-a7";
41 reg = <0xf00>; 40 reg = <0xf00>;
42 enable-method = "psci" 41 enable-method = "psci";
43 clocks = <&cru ARMCLK> 42 clocks = <&cru ARMCLK>;
44 }; 43 };
45 44
46 cpu1: cpu@f01 { 45 cpu1: cpu@f01 {
47 device_type = "cpu"; 46 device_type = "cpu";
48 compatible = "arm,cort 47 compatible = "arm,cortex-a7";
49 reg = <0xf01>; 48 reg = <0xf01>;
50 enable-method = "psci" 49 enable-method = "psci";
51 clocks = <&cru ARMCLK> 50 clocks = <&cru ARMCLK>;
52 }; 51 };
53 52
54 cpu2: cpu@f02 { 53 cpu2: cpu@f02 {
55 device_type = "cpu"; 54 device_type = "cpu";
56 compatible = "arm,cort 55 compatible = "arm,cortex-a7";
57 reg = <0xf02>; 56 reg = <0xf02>;
58 enable-method = "psci" 57 enable-method = "psci";
59 clocks = <&cru ARMCLK> 58 clocks = <&cru ARMCLK>;
60 }; 59 };
61 60
62 cpu3: cpu@f03 { 61 cpu3: cpu@f03 {
63 device_type = "cpu"; 62 device_type = "cpu";
64 compatible = "arm,cort 63 compatible = "arm,cortex-a7";
65 reg = <0xf03>; 64 reg = <0xf03>;
66 enable-method = "psci" 65 enable-method = "psci";
67 clocks = <&cru ARMCLK> 66 clocks = <&cru ARMCLK>;
68 }; 67 };
69 }; 68 };
70 69
71 arm-pmu { 70 arm-pmu {
72 compatible = "arm,cortex-a7-pm 71 compatible = "arm,cortex-a7-pmu";
73 interrupts = <GIC_SPI 123 IRQ_ 72 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
74 <GIC_SPI 124 IRQ_ 73 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
75 <GIC_SPI 125 IRQ_ 74 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
76 <GIC_SPI 126 IRQ_ 75 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
77 interrupt-affinity = <&cpu0>, 76 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
78 }; 77 };
79 78
80 psci { 79 psci {
81 compatible = "arm,psci-1.0"; 80 compatible = "arm,psci-1.0";
82 method = "smc"; 81 method = "smc";
83 }; 82 };
84 83
85 timer { 84 timer {
86 compatible = "arm,armv7-timer" 85 compatible = "arm,armv7-timer";
87 interrupts = <GIC_PPI 13 (GIC_ 86 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
88 <GIC_PPI 14 (GIC_ 87 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
89 <GIC_PPI 11 (GIC_ 88 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
90 <GIC_PPI 10 (GIC_ 89 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
91 clock-frequency = <24000000>; 90 clock-frequency = <24000000>;
92 }; 91 };
93 92
94 display_subsystem { 93 display_subsystem {
95 compatible = "rockchip,display 94 compatible = "rockchip,display-subsystem";
96 ports = <&vop_out>; 95 ports = <&vop_out>;
97 }; 96 };
98 97
99 xin24m: oscillator { 98 xin24m: oscillator {
100 compatible = "fixed-clock"; 99 compatible = "fixed-clock";
101 clock-frequency = <24000000>; 100 clock-frequency = <24000000>;
102 clock-output-names = "xin24m"; 101 clock-output-names = "xin24m";
103 #clock-cells = <0>; 102 #clock-cells = <0>;
104 }; 103 };
105 104
106 grf: syscon@fe000000 { 105 grf: syscon@fe000000 {
107 compatible = "rockchip,rv1126- 106 compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd";
108 reg = <0xfe000000 0x20000>; 107 reg = <0xfe000000 0x20000>;
109 }; 108 };
110 109
111 pmugrf: syscon@fe020000 { 110 pmugrf: syscon@fe020000 {
112 compatible = "rockchip,rv1126- 111 compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd";
113 reg = <0xfe020000 0x1000>; 112 reg = <0xfe020000 0x1000>;
114 113
115 pmu_io_domains: io-domains { 114 pmu_io_domains: io-domains {
116 compatible = "rockchip 115 compatible = "rockchip,rv1126-pmu-io-voltage-domain";
117 status = "disabled"; 116 status = "disabled";
118 }; 117 };
119 }; 118 };
120 119
121 qos_emmc: qos@fe860000 { 120 qos_emmc: qos@fe860000 {
122 compatible = "rockchip,rv1126- 121 compatible = "rockchip,rv1126-qos", "syscon";
123 reg = <0xfe860000 0x20>; 122 reg = <0xfe860000 0x20>;
124 }; 123 };
125 124
126 qos_nandc: qos@fe860080 { 125 qos_nandc: qos@fe860080 {
127 compatible = "rockchip,rv1126- 126 compatible = "rockchip,rv1126-qos", "syscon";
128 reg = <0xfe860080 0x20>; 127 reg = <0xfe860080 0x20>;
129 }; 128 };
130 129
131 qos_sfc: qos@fe860200 { 130 qos_sfc: qos@fe860200 {
132 compatible = "rockchip,rv1126- 131 compatible = "rockchip,rv1126-qos", "syscon";
133 reg = <0xfe860200 0x20>; 132 reg = <0xfe860200 0x20>;
134 }; 133 };
135 134
136 qos_sdio: qos@fe86c000 { 135 qos_sdio: qos@fe86c000 {
137 compatible = "rockchip,rv1126- 136 compatible = "rockchip,rv1126-qos", "syscon";
138 reg = <0xfe86c000 0x20>; 137 reg = <0xfe86c000 0x20>;
139 }; 138 };
140 139
141 qos_iep: qos@fe8a0000 { 140 qos_iep: qos@fe8a0000 {
142 compatible = "rockchip,rv1126- 141 compatible = "rockchip,rv1126-qos", "syscon";
143 reg = <0xfe8a0000 0x20>; 142 reg = <0xfe8a0000 0x20>;
144 }; 143 };
145 144
146 qos_rga_rd: qos@fe8a0080 { 145 qos_rga_rd: qos@fe8a0080 {
147 compatible = "rockchip,rv1126- 146 compatible = "rockchip,rv1126-qos", "syscon";
148 reg = <0xfe8a0080 0x20>; 147 reg = <0xfe8a0080 0x20>;
149 }; 148 };
150 149
151 qos_rga_wr: qos@fe8a0100 { 150 qos_rga_wr: qos@fe8a0100 {
152 compatible = "rockchip,rv1126- 151 compatible = "rockchip,rv1126-qos", "syscon";
153 reg = <0xfe8a0100 0x20>; 152 reg = <0xfe8a0100 0x20>;
154 }; 153 };
155 154
156 qos_vop: qos@fe8a0180 { 155 qos_vop: qos@fe8a0180 {
157 compatible = "rockchip,rv1126- 156 compatible = "rockchip,rv1126-qos", "syscon";
158 reg = <0xfe8a0180 0x20>; 157 reg = <0xfe8a0180 0x20>;
159 }; 158 };
160 159
161 gic: interrupt-controller@feff0000 { 160 gic: interrupt-controller@feff0000 {
162 compatible = "arm,gic-400"; 161 compatible = "arm,gic-400";
163 interrupt-controller; 162 interrupt-controller;
164 #interrupt-cells = <3>; 163 #interrupt-cells = <3>;
165 #address-cells = <0>; 164 #address-cells = <0>;
166 165
167 reg = <0xfeff1000 0x1000>, 166 reg = <0xfeff1000 0x1000>,
168 <0xfeff2000 0x2000>, 167 <0xfeff2000 0x2000>,
169 <0xfeff4000 0x2000>, 168 <0xfeff4000 0x2000>,
170 <0xfeff6000 0x2000>; 169 <0xfeff6000 0x2000>;
171 interrupts = <GIC_PPI 9 (GIC_C 170 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
172 }; 171 };
173 172
174 pmu: power-management@ff3e0000 { 173 pmu: power-management@ff3e0000 {
175 compatible = "rockchip,rv1126- 174 compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd";
176 reg = <0xff3e0000 0x1000>; 175 reg = <0xff3e0000 0x1000>;
177 176
178 power: power-controller { 177 power: power-controller {
179 compatible = "rockchip 178 compatible = "rockchip,rv1126-power-controller";
180 #power-domain-cells = 179 #power-domain-cells = <1>;
181 #address-cells = <1>; 180 #address-cells = <1>;
182 #size-cells = <0>; 181 #size-cells = <0>;
183 182
184 power-domain@RV1126_PD 183 power-domain@RV1126_PD_NVM {
185 reg = <RV1126_ 184 reg = <RV1126_PD_NVM>;
186 clocks = <&cru 185 clocks = <&cru HCLK_EMMC>,
187 <&cru 186 <&cru CLK_EMMC>,
188 <&cru 187 <&cru HCLK_NANDC>,
189 <&cru 188 <&cru CLK_NANDC>,
190 <&cru 189 <&cru HCLK_SFC>,
191 <&cru 190 <&cru HCLK_SFCXIP>,
192 <&cru 191 <&cru SCLK_SFC>;
193 pm_qos = <&qos 192 pm_qos = <&qos_emmc>,
194 <&qos 193 <&qos_nandc>,
195 <&qos 194 <&qos_sfc>;
196 #power-domain- 195 #power-domain-cells = <0>;
197 }; 196 };
198 197
199 power-domain@RV1126_PD 198 power-domain@RV1126_PD_SDIO {
200 reg = <RV1126_ 199 reg = <RV1126_PD_SDIO>;
201 clocks = <&cru 200 clocks = <&cru HCLK_SDIO>,
202 <&cru 201 <&cru CLK_SDIO>;
203 pm_qos = <&qos 202 pm_qos = <&qos_sdio>;
204 #power-domain- 203 #power-domain-cells = <0>;
205 }; 204 };
206 205
207 power-domain@RV1126_PD 206 power-domain@RV1126_PD_VO {
208 reg = <RV1126_ 207 reg = <RV1126_PD_VO>;
209 clocks = <&cru 208 clocks = <&cru ACLK_RGA>,
210 <&cru 209 <&cru HCLK_RGA>,
211 <&cru 210 <&cru CLK_RGA_CORE>,
212 <&cru 211 <&cru ACLK_VOP>,
213 <&cru 212 <&cru HCLK_VOP>,
214 <&cru 213 <&cru DCLK_VOP>,
215 <&cru 214 <&cru PCLK_DSIHOST>,
216 <&cru 215 <&cru ACLK_IEP>,
217 <&cru 216 <&cru HCLK_IEP>,
218 <&cru 217 <&cru CLK_IEP_CORE>;
219 pm_qos = <&qos 218 pm_qos = <&qos_rga_rd>,
220 <&qos 219 <&qos_rga_wr>,
221 <&qos 220 <&qos_vop>,
222 <&qos 221 <&qos_iep>;
223 #power-domain- 222 #power-domain-cells = <0>;
224 }; 223 };
225 }; 224 };
226 }; 225 };
227 226
228 i2c0: i2c@ff3f0000 { 227 i2c0: i2c@ff3f0000 {
229 compatible = "rockchip,rv1126- 228 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
230 reg = <0xff3f0000 0x1000>; 229 reg = <0xff3f0000 0x1000>;
231 interrupts = <GIC_SPI 4 IRQ_TY 230 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
232 rockchip,grf = <&pmugrf>; 231 rockchip,grf = <&pmugrf>;
233 clocks = <&pmucru CLK_I2C0>, < 232 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
234 clock-names = "i2c", "pclk"; 233 clock-names = "i2c", "pclk";
235 pinctrl-names = "default"; 234 pinctrl-names = "default";
236 pinctrl-0 = <&i2c0_xfer>; 235 pinctrl-0 = <&i2c0_xfer>;
237 #address-cells = <1>; 236 #address-cells = <1>;
238 #size-cells = <0>; 237 #size-cells = <0>;
239 status = "disabled"; 238 status = "disabled";
240 }; 239 };
241 240
242 i2c2: i2c@ff400000 { 241 i2c2: i2c@ff400000 {
243 compatible = "rockchip,rv1126- 242 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
244 reg = <0xff400000 0x1000>; 243 reg = <0xff400000 0x1000>;
245 interrupts = <GIC_SPI 6 IRQ_TY 244 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
246 rockchip,grf = <&pmugrf>; 245 rockchip,grf = <&pmugrf>;
247 clocks = <&pmucru CLK_I2C2>, < 246 clocks = <&pmucru CLK_I2C2>, <&pmucru PCLK_I2C2>;
248 clock-names = "i2c", "pclk"; 247 clock-names = "i2c", "pclk";
249 pinctrl-names = "default"; 248 pinctrl-names = "default";
250 pinctrl-0 = <&i2c2_xfer>; 249 pinctrl-0 = <&i2c2_xfer>;
251 #address-cells = <1>; 250 #address-cells = <1>;
252 #size-cells = <0>; 251 #size-cells = <0>;
253 status = "disabled"; 252 status = "disabled";
254 }; 253 };
255 254
256 uart1: serial@ff410000 { 255 uart1: serial@ff410000 {
257 compatible = "rockchip,rv1126- 256 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
258 reg = <0xff410000 0x100>; 257 reg = <0xff410000 0x100>;
259 interrupts = <GIC_SPI 13 IRQ_T 258 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
260 clock-frequency = <24000000>; 259 clock-frequency = <24000000>;
261 clocks = <&pmucru SCLK_UART1>, 260 clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>;
262 clock-names = "baudclk", "apb_ 261 clock-names = "baudclk", "apb_pclk";
263 dmas = <&dmac 7>, <&dmac 6>; 262 dmas = <&dmac 7>, <&dmac 6>;
264 dma-names = "tx", "rx"; 263 dma-names = "tx", "rx";
265 pinctrl-names = "default"; 264 pinctrl-names = "default";
266 pinctrl-0 = <&uart1m0_xfer>; 265 pinctrl-0 = <&uart1m0_xfer>;
267 reg-shift = <2>; 266 reg-shift = <2>;
268 reg-io-width = <4>; 267 reg-io-width = <4>;
269 status = "disabled"; 268 status = "disabled";
270 }; 269 };
271 270
272 pwm0: pwm@ff430000 { <<
273 compatible = "rockchip,rv1126- <<
274 reg = <0xff430000 0x10>; <<
275 clock-names = "pwm", "pclk"; <<
276 clocks = <&pmucru CLK_PWM0>, < <<
277 pinctrl-names = "default"; <<
278 pinctrl-0 = <&pwm0m0_pins>; <<
279 #pwm-cells = <3>; <<
280 status = "disabled"; <<
281 }; <<
282 <<
283 pwm1: pwm@ff430010 { <<
284 compatible = "rockchip,rv1126- <<
285 reg = <0xff430010 0x10>; <<
286 clock-names = "pwm", "pclk"; <<
287 clocks = <&pmucru CLK_PWM0>, < <<
288 pinctrl-names = "default"; <<
289 pinctrl-0 = <&pwm1m0_pins>; <<
290 #pwm-cells = <3>; <<
291 status = "disabled"; <<
292 }; <<
293 <<
294 pwm2: pwm@ff430020 { 271 pwm2: pwm@ff430020 {
295 compatible = "rockchip,rv1126- 272 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
296 reg = <0xff430020 0x10>; 273 reg = <0xff430020 0x10>;
297 clock-names = "pwm", "pclk"; 274 clock-names = "pwm", "pclk";
298 clocks = <&pmucru CLK_PWM0>, < 275 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
299 pinctrl-names = "default"; 276 pinctrl-names = "default";
300 pinctrl-0 = <&pwm2m0_pins>; 277 pinctrl-0 = <&pwm2m0_pins>;
301 #pwm-cells = <3>; 278 #pwm-cells = <3>;
302 status = "disabled"; 279 status = "disabled";
303 }; 280 };
304 281
305 pwm3: pwm@ff430030 { <<
306 compatible = "rockchip,rv1126- <<
307 reg = <0xff430030 0x10>; <<
308 clock-names = "pwm", "pclk"; <<
309 clocks = <&pmucru CLK_PWM0>, < <<
310 pinctrl-names = "default"; <<
311 pinctrl-0 = <&pwm3m0_pins>; <<
312 #pwm-cells = <3>; <<
313 status = "disabled"; <<
314 }; <<
315 <<
316 pwm4: pwm@ff440000 { <<
317 compatible = "rockchip,rv1126- <<
318 reg = <0xff440000 0x10>; <<
319 clock-names = "pwm", "pclk"; <<
320 clocks = <&pmucru CLK_PWM1>, < <<
321 pinctrl-names = "default"; <<
322 pinctrl-0 = <&pwm4m0_pins>; <<
323 #pwm-cells = <3>; <<
324 status = "disabled"; <<
325 }; <<
326 <<
327 pwm5: pwm@ff440010 { <<
328 compatible = "rockchip,rv1126- <<
329 reg = <0xff440010 0x10>; <<
330 clock-names = "pwm", "pclk"; <<
331 clocks = <&pmucru CLK_PWM1>, < <<
332 pinctrl-names = "default"; <<
333 pinctrl-0 = <&pwm5m0_pins>; <<
334 #pwm-cells = <3>; <<
335 status = "disabled"; <<
336 }; <<
337 <<
338 pwm6: pwm@ff440020 { <<
339 compatible = "rockchip,rv1126- <<
340 reg = <0xff440020 0x10>; <<
341 clock-names = "pwm", "pclk"; <<
342 clocks = <&pmucru CLK_PWM1>, < <<
343 pinctrl-names = "default"; <<
344 pinctrl-0 = <&pwm6m0_pins>; <<
345 #pwm-cells = <3>; <<
346 status = "disabled"; <<
347 }; <<
348 <<
349 pwm7: pwm@ff440030 { <<
350 compatible = "rockchip,rv1126- <<
351 reg = <0xff440030 0x10>; <<
352 clock-names = "pwm", "pclk"; <<
353 clocks = <&pmucru CLK_PWM1>, < <<
354 pinctrl-names = "default"; <<
355 pinctrl-0 = <&pwm7m0_pins>; <<
356 #pwm-cells = <3>; <<
357 status = "disabled"; <<
358 }; <<
359 <<
360 pmucru: clock-controller@ff480000 { 282 pmucru: clock-controller@ff480000 {
361 compatible = "rockchip,rv1126- 283 compatible = "rockchip,rv1126-pmucru";
362 reg = <0xff480000 0x1000>; 284 reg = <0xff480000 0x1000>;
363 rockchip,grf = <&grf>; 285 rockchip,grf = <&grf>;
364 #clock-cells = <1>; 286 #clock-cells = <1>;
365 #reset-cells = <1>; 287 #reset-cells = <1>;
366 }; 288 };
367 289
368 cru: clock-controller@ff490000 { 290 cru: clock-controller@ff490000 {
369 compatible = "rockchip,rv1126- 291 compatible = "rockchip,rv1126-cru";
370 reg = <0xff490000 0x1000>; 292 reg = <0xff490000 0x1000>;
371 clocks = <&xin24m>; 293 clocks = <&xin24m>;
372 clock-names = "xin24m"; 294 clock-names = "xin24m";
373 rockchip,grf = <&grf>; 295 rockchip,grf = <&grf>;
374 #clock-cells = <1>; 296 #clock-cells = <1>;
375 #reset-cells = <1>; 297 #reset-cells = <1>;
376 }; 298 };
377 299
378 dmac: dma-controller@ff4e0000 { 300 dmac: dma-controller@ff4e0000 {
379 compatible = "arm,pl330", "arm 301 compatible = "arm,pl330", "arm,primecell";
380 reg = <0xff4e0000 0x4000>; 302 reg = <0xff4e0000 0x4000>;
381 interrupts = <GIC_SPI 1 IRQ_TY 303 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
382 <GIC_SPI 2 IRQ_TY 304 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
383 #dma-cells = <1>; 305 #dma-cells = <1>;
384 arm,pl330-periph-burst; 306 arm,pl330-periph-burst;
385 clocks = <&cru ACLK_DMAC>; 307 clocks = <&cru ACLK_DMAC>;
386 clock-names = "apb_pclk"; 308 clock-names = "apb_pclk";
387 }; 309 };
388 310
389 i2c3: i2c@ff520000 { <<
390 compatible = "rockchip,rv1126- <<
391 reg = <0xff520000 0x1000>; <<
392 interrupts = <GIC_SPI 7 IRQ_TY <<
393 clocks = <&cru CLK_I2C3>, <&cr <<
394 clock-names = "i2c", "pclk"; <<
395 pinctrl-names = "default"; <<
396 pinctrl-0 = <&i2c3m0_xfer>; <<
397 rockchip,grf = <&pmugrf>; <<
398 #address-cells = <1>; <<
399 #size-cells = <0>; <<
400 status = "disabled"; <<
401 }; <<
402 <<
403 pwm8: pwm@ff550000 { <<
404 compatible = "rockchip,rv1126- <<
405 reg = <0xff550000 0x10>; <<
406 clock-names = "pwm", "pclk"; <<
407 clocks = <&cru CLK_PWM2>, <&cr <<
408 pinctrl-0 = <&pwm8m0_pins>; <<
409 pinctrl-names = "default"; <<
410 #pwm-cells = <3>; <<
411 status = "disabled"; <<
412 }; <<
413 <<
414 pwm9: pwm@ff550010 { <<
415 compatible = "rockchip,rv1126- <<
416 reg = <0xff550010 0x10>; <<
417 clock-names = "pwm", "pclk"; <<
418 clocks = <&cru CLK_PWM2>, <&cr <<
419 pinctrl-0 = <&pwm9m0_pins>; <<
420 pinctrl-names = "default"; <<
421 #pwm-cells = <3>; <<
422 status = "disabled"; <<
423 }; <<
424 <<
425 pwm10: pwm@ff550020 { <<
426 compatible = "rockchip,rv1126- <<
427 reg = <0xff550020 0x10>; <<
428 clock-names = "pwm", "pclk"; <<
429 clocks = <&cru CLK_PWM2>, <&cr <<
430 pinctrl-0 = <&pwm10m0_pins>; <<
431 pinctrl-names = "default"; <<
432 #pwm-cells = <3>; <<
433 status = "disabled"; <<
434 }; <<
435 <<
436 pwm11: pwm@ff550030 { 311 pwm11: pwm@ff550030 {
437 compatible = "rockchip,rv1126- 312 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
438 reg = <0xff550030 0x10>; 313 reg = <0xff550030 0x10>;
439 clock-names = "pwm", "pclk"; 314 clock-names = "pwm", "pclk";
440 clocks = <&cru CLK_PWM2>, <&cr 315 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
441 pinctrl-0 = <&pwm11m0_pins>; 316 pinctrl-0 = <&pwm11m0_pins>;
442 pinctrl-names = "default"; 317 pinctrl-names = "default";
443 #pwm-cells = <3>; 318 #pwm-cells = <3>;
444 status = "disabled"; 319 status = "disabled";
445 }; 320 };
446 321
447 uart0: serial@ff560000 { 322 uart0: serial@ff560000 {
448 compatible = "rockchip,rv1126- 323 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
449 reg = <0xff560000 0x100>; 324 reg = <0xff560000 0x100>;
450 interrupts = <GIC_SPI 12 IRQ_T 325 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
451 clock-frequency = <24000000>; 326 clock-frequency = <24000000>;
452 clocks = <&cru SCLK_UART0>, <& 327 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
453 clock-names = "baudclk", "apb_ 328 clock-names = "baudclk", "apb_pclk";
454 dmas = <&dmac 5>, <&dmac 4>; 329 dmas = <&dmac 5>, <&dmac 4>;
455 dma-names = "tx", "rx"; 330 dma-names = "tx", "rx";
456 pinctrl-names = "default"; 331 pinctrl-names = "default";
457 pinctrl-0 = <&uart0_xfer>; 332 pinctrl-0 = <&uart0_xfer>;
458 reg-shift = <2>; 333 reg-shift = <2>;
459 reg-io-width = <4>; 334 reg-io-width = <4>;
460 status = "disabled"; 335 status = "disabled";
461 }; 336 };
462 337
463 uart2: serial@ff570000 { 338 uart2: serial@ff570000 {
464 compatible = "rockchip,rv1126- 339 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
465 reg = <0xff570000 0x100>; 340 reg = <0xff570000 0x100>;
466 interrupts = <GIC_SPI 14 IRQ_T 341 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
467 clock-frequency = <24000000>; 342 clock-frequency = <24000000>;
468 clocks = <&cru SCLK_UART2>, <& 343 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
469 clock-names = "baudclk", "apb_ 344 clock-names = "baudclk", "apb_pclk";
470 dmas = <&dmac 9>, <&dmac 8>; 345 dmas = <&dmac 9>, <&dmac 8>;
471 dma-names = "tx", "rx"; 346 dma-names = "tx", "rx";
472 pinctrl-names = "default"; 347 pinctrl-names = "default";
473 pinctrl-0 = <&uart2m1_xfer>; 348 pinctrl-0 = <&uart2m1_xfer>;
474 reg-shift = <2>; 349 reg-shift = <2>;
475 reg-io-width = <4>; 350 reg-io-width = <4>;
476 status = "disabled"; 351 status = "disabled";
477 }; 352 };
478 353
479 uart3: serial@ff580000 { 354 uart3: serial@ff580000 {
480 compatible = "rockchip,rv1126- 355 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
481 reg = <0xff580000 0x100>; 356 reg = <0xff580000 0x100>;
482 interrupts = <GIC_SPI 15 IRQ_T 357 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
483 clock-frequency = <24000000>; 358 clock-frequency = <24000000>;
484 clocks = <&cru SCLK_UART3>, <& 359 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
485 clock-names = "baudclk", "apb_ 360 clock-names = "baudclk", "apb_pclk";
486 dmas = <&dmac 11>, <&dmac 10>; 361 dmas = <&dmac 11>, <&dmac 10>;
487 dma-names = "tx", "rx"; 362 dma-names = "tx", "rx";
488 pinctrl-names = "default"; 363 pinctrl-names = "default";
489 pinctrl-0 = <&uart3m0_xfer>; 364 pinctrl-0 = <&uart3m0_xfer>;
490 reg-shift = <2>; 365 reg-shift = <2>;
491 reg-io-width = <4>; 366 reg-io-width = <4>;
492 status = "disabled"; 367 status = "disabled";
493 }; 368 };
494 369
495 uart4: serial@ff590000 { 370 uart4: serial@ff590000 {
496 compatible = "rockchip,rv1126- 371 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
497 reg = <0xff590000 0x100>; 372 reg = <0xff590000 0x100>;
498 interrupts = <GIC_SPI 16 IRQ_T 373 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
499 clock-frequency = <24000000>; 374 clock-frequency = <24000000>;
500 clocks = <&cru SCLK_UART4>, <& 375 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
501 clock-names = "baudclk", "apb_ 376 clock-names = "baudclk", "apb_pclk";
502 dmas = <&dmac 13>, <&dmac 12>; 377 dmas = <&dmac 13>, <&dmac 12>;
503 dma-names = "tx", "rx"; 378 dma-names = "tx", "rx";
504 pinctrl-names = "default"; 379 pinctrl-names = "default";
505 pinctrl-0 = <&uart4m0_xfer>; 380 pinctrl-0 = <&uart4m0_xfer>;
506 reg-shift = <2>; 381 reg-shift = <2>;
507 reg-io-width = <4>; 382 reg-io-width = <4>;
508 status = "disabled"; 383 status = "disabled";
509 }; 384 };
510 385
511 uart5: serial@ff5a0000 { 386 uart5: serial@ff5a0000 {
512 compatible = "rockchip,rv1126- 387 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
513 reg = <0xff5a0000 0x100>; 388 reg = <0xff5a0000 0x100>;
514 interrupts = <GIC_SPI 17 IRQ_T 389 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
515 clock-frequency = <24000000>; 390 clock-frequency = <24000000>;
516 clocks = <&cru SCLK_UART5>, <& 391 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
517 clock-names = "baudclk", "apb_ 392 clock-names = "baudclk", "apb_pclk";
518 dmas = <&dmac 15>, <&dmac 14>; 393 dmas = <&dmac 15>, <&dmac 14>;
519 dma-names = "tx", "rx"; 394 dma-names = "tx", "rx";
520 pinctrl-names = "default"; 395 pinctrl-names = "default";
521 pinctrl-0 = <&uart5m0_xfer>; 396 pinctrl-0 = <&uart5m0_xfer>;
522 reg-shift = <2>; 397 reg-shift = <2>;
523 reg-io-width = <4>; 398 reg-io-width = <4>;
524 status = "disabled"; 399 status = "disabled";
525 }; 400 };
526 401
527 saradc: adc@ff5e0000 { 402 saradc: adc@ff5e0000 {
528 compatible = "rockchip,rv1126- 403 compatible = "rockchip,rv1126-saradc", "rockchip,rk3399-saradc";
529 reg = <0xff5e0000 0x100>; 404 reg = <0xff5e0000 0x100>;
530 interrupts = <GIC_SPI 40 IRQ_T 405 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
531 #io-channel-cells = <1>; 406 #io-channel-cells = <1>;
532 clocks = <&cru CLK_SARADC>, <& 407 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
533 clock-names = "saradc", "apb_p 408 clock-names = "saradc", "apb_pclk";
534 resets = <&cru SRST_SARADC_P>; 409 resets = <&cru SRST_SARADC_P>;
535 reset-names = "saradc-apb"; 410 reset-names = "saradc-apb";
536 status = "disabled"; 411 status = "disabled";
537 }; 412 };
538 413
539 timer0: timer@ff660000 { 414 timer0: timer@ff660000 {
540 compatible = "rockchip,rv1126- 415 compatible = "rockchip,rv1126-timer", "rockchip,rk3288-timer";
541 reg = <0xff660000 0x20>; 416 reg = <0xff660000 0x20>;
542 interrupts = <GIC_SPI 24 IRQ_T 417 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&cru PCLK_TIMER>, <& 418 clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>;
544 clock-names = "pclk", "timer"; 419 clock-names = "pclk", "timer";
545 }; <<
546 <<
547 i2s0: i2s@ff800000 { <<
548 compatible = "rockchip,rv1126- <<
549 reg = <0xff800000 0x1000>; <<
550 interrupts = <GIC_SPI 46 IRQ_T <<
551 clocks = <&cru MCLK_I2S0_TX>, <<
552 clock-names = "mclk_tx", "mclk <<
553 dmas = <&dmac 20>, <&dmac 19>; <<
554 dma-names = "tx", "rx"; <<
555 pinctrl-names = "default"; <<
556 pinctrl-0 = <&i2s0m0_sclk_tx>, <<
557 <&i2s0m0_sclk_rx> <<
558 <&i2s0m0_mclk>, <<
559 <&i2s0m0_lrck_tx> <<
560 <&i2s0m0_lrck_rx> <<
561 <&i2s0m0_sdi0>, <<
562 <&i2s0m0_sdo0>, <<
563 <&i2s0m0_sdo1_sdi <<
564 <&i2s0m0_sdo2_sdi <<
565 <&i2s0m0_sdo3_sdi <<
566 resets = <&cru SRST_I2S0_TX_M> <<
567 reset-names = "tx-m", "rx-m"; <<
568 rockchip,grf = <&grf>; <<
569 #sound-dai-cells = <0>; <<
570 status = "disabled"; <<
571 }; 420 };
572 421
573 vop: vop@ffb00000 { 422 vop: vop@ffb00000 {
574 compatible = "rockchip,rv1126- 423 compatible = "rockchip,rv1126-vop";
575 reg = <0xffb00000 0x200>, <0xf 424 reg = <0xffb00000 0x200>, <0xffb00a00 0x400>;
576 interrupts = <GIC_SPI 59 IRQ_T 425 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
577 clock-names = "aclk_vop", "dcl 426 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
578 clocks = <&cru ACLK_VOP>, <&cr 427 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
579 reset-names = "axi", "ahb", "d 428 reset-names = "axi", "ahb", "dclk";
580 resets = <&cru SRST_VOP_A>, <& 429 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
581 iommus = <&vop_mmu>; 430 iommus = <&vop_mmu>;
582 power-domains = <&power RV1126 431 power-domains = <&power RV1126_PD_VO>;
583 status = "disabled"; 432 status = "disabled";
584 433
585 vop_out: port { 434 vop_out: port {
586 #address-cells = <1>; 435 #address-cells = <1>;
587 #size-cells = <0>; 436 #size-cells = <0>;
588 437
589 vop_out_rgb: endpoint@ 438 vop_out_rgb: endpoint@0 {
590 reg = <0>; 439 reg = <0>;
591 }; 440 };
592 441
593 vop_out_dsi: endpoint@ 442 vop_out_dsi: endpoint@1 {
594 reg = <1>; 443 reg = <1>;
595 }; 444 };
596 }; 445 };
597 }; 446 };
598 447
599 vop_mmu: iommu@ffb00f00 { 448 vop_mmu: iommu@ffb00f00 {
600 compatible = "rockchip,iommu"; 449 compatible = "rockchip,iommu";
601 reg = <0xffb00f00 0x100>; 450 reg = <0xffb00f00 0x100>;
602 interrupts = <GIC_SPI 59 IRQ_T 451 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
603 clock-names = "aclk", "iface"; 452 clock-names = "aclk", "iface";
604 clocks = <&cru ACLK_VOP>, <&cr 453 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
605 #iommu-cells = <0>; 454 #iommu-cells = <0>;
606 power-domains = <&power RV1126 455 power-domains = <&power RV1126_PD_VO>;
607 status = "disabled"; 456 status = "disabled";
608 }; 457 };
609 458
610 gmac: ethernet@ffc40000 { 459 gmac: ethernet@ffc40000 {
611 compatible = "rockchip,rv1126- 460 compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a";
612 reg = <0xffc40000 0x4000>; 461 reg = <0xffc40000 0x4000>;
613 interrupts = <GIC_SPI 95 IRQ_T 462 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 96 IRQ_T 463 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
615 interrupt-names = "macirq", "e 464 interrupt-names = "macirq", "eth_wake_irq";
616 rockchip,grf = <&grf>; 465 rockchip,grf = <&grf>;
617 clocks = <&cru CLK_GMAC_SRC>, 466 clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
618 <&cru CLK_GMAC_TX_RX> 467 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>,
619 <&cru ACLK_GMAC>, <&c 468 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
620 <&cru CLK_GMAC_TX_RX> 469 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_PTPREF>;
621 clock-names = "stmmaceth", "ma 470 clock-names = "stmmaceth", "mac_clk_rx",
622 "mac_clk_tx", "c 471 "mac_clk_tx", "clk_mac_ref",
623 "aclk_mac", "pcl 472 "aclk_mac", "pclk_mac",
624 "clk_mac_speed", 473 "clk_mac_speed", "ptp_ref";
625 resets = <&cru SRST_GMAC_A>; 474 resets = <&cru SRST_GMAC_A>;
626 reset-names = "stmmaceth"; 475 reset-names = "stmmaceth";
627 476
628 snps,mixed-burst; 477 snps,mixed-burst;
629 snps,tso; 478 snps,tso;
630 479
631 snps,axi-config = <&stmmac_axi 480 snps,axi-config = <&stmmac_axi_setup>;
632 snps,mtl-rx-config = <&mtl_rx_ 481 snps,mtl-rx-config = <&mtl_rx_setup>;
633 snps,mtl-tx-config = <&mtl_tx_ 482 snps,mtl-tx-config = <&mtl_tx_setup>;
634 status = "disabled"; 483 status = "disabled";
635 484
636 mdio: mdio { 485 mdio: mdio {
637 compatible = "snps,dwm 486 compatible = "snps,dwmac-mdio";
638 #address-cells = <0x1> 487 #address-cells = <0x1>;
639 #size-cells = <0x0>; 488 #size-cells = <0x0>;
640 }; 489 };
641 490
642 stmmac_axi_setup: stmmac-axi-c 491 stmmac_axi_setup: stmmac-axi-config {
643 snps,wr_osr_lmt = <4>; 492 snps,wr_osr_lmt = <4>;
644 snps,rd_osr_lmt = <8>; 493 snps,rd_osr_lmt = <8>;
645 snps,blen = <0 0 0 0 1 494 snps,blen = <0 0 0 0 16 8 4>;
646 }; 495 };
647 496
648 mtl_rx_setup: rx-queues-config 497 mtl_rx_setup: rx-queues-config {
649 snps,rx-queues-to-use 498 snps,rx-queues-to-use = <1>;
650 queue0 {}; 499 queue0 {};
651 }; 500 };
652 501
653 mtl_tx_setup: tx-queues-config 502 mtl_tx_setup: tx-queues-config {
654 snps,tx-queues-to-use 503 snps,tx-queues-to-use = <1>;
655 queue0 {}; 504 queue0 {};
656 }; 505 };
657 }; 506 };
658 507
659 emmc: mmc@ffc50000 { 508 emmc: mmc@ffc50000 {
660 compatible = "rockchip,rv1126- 509 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
661 reg = <0xffc50000 0x4000>; 510 reg = <0xffc50000 0x4000>;
662 interrupts = <GIC_SPI 78 IRQ_T 511 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
663 clocks = <&cru HCLK_EMMC>, <&c 512 clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>,
664 <&cru SCLK_EMMC_DRV>, 513 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
665 clock-names = "biu", "ciu", "c 514 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
666 fifo-depth = <0x100>; 515 fifo-depth = <0x100>;
667 max-frequency = <200000000>; 516 max-frequency = <200000000>;
668 power-domains = <&power RV1126 517 power-domains = <&power RV1126_PD_NVM>;
669 status = "disabled"; 518 status = "disabled";
670 }; 519 };
671 520
672 sdmmc: mmc@ffc60000 { 521 sdmmc: mmc@ffc60000 {
673 compatible = "rockchip,rv1126- 522 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
674 reg = <0xffc60000 0x4000>; 523 reg = <0xffc60000 0x4000>;
675 interrupts = <GIC_SPI 76 IRQ_T 524 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
676 clocks = <&cru HCLK_SDMMC>, <& 525 clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>,
677 <&cru SCLK_SDMMC_DRV> 526 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
678 clock-names = "biu", "ciu", "c 527 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
679 fifo-depth = <0x100>; 528 fifo-depth = <0x100>;
680 max-frequency = <200000000>; 529 max-frequency = <200000000>;
681 status = "disabled"; 530 status = "disabled";
682 }; 531 };
683 532
684 sdio: mmc@ffc70000 { 533 sdio: mmc@ffc70000 {
685 compatible = "rockchip,rv1126- 534 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
686 reg = <0xffc70000 0x4000>; 535 reg = <0xffc70000 0x4000>;
687 interrupts = <GIC_SPI 77 IRQ_T 536 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
688 clocks = <&cru HCLK_SDIO>, <&c 537 clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>,
689 <&cru SCLK_SDIO_DRV>, 538 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
690 clock-names = "biu", "ciu", "c 539 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
691 fifo-depth = <0x100>; 540 fifo-depth = <0x100>;
692 max-frequency = <200000000>; 541 max-frequency = <200000000>;
693 power-domains = <&power RV1126 542 power-domains = <&power RV1126_PD_SDIO>;
694 status = "disabled"; 543 status = "disabled";
695 }; 544 };
696 545
697 sfc: spi@ffc90000 { 546 sfc: spi@ffc90000 {
698 compatible = "rockchip,sfc"; 547 compatible = "rockchip,sfc";
699 reg = <0xffc90000 0x4000>; 548 reg = <0xffc90000 0x4000>;
700 interrupts = <GIC_SPI 80 IRQ_T 549 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
701 assigned-clocks = <&cru SCLK_S 550 assigned-clocks = <&cru SCLK_SFC>;
702 assigned-clock-rates = <800000 551 assigned-clock-rates = <80000000>;
703 clock-names = "clk_sfc", "hclk 552 clock-names = "clk_sfc", "hclk_sfc";
704 clocks = <&cru SCLK_SFC>, <&cr 553 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
705 power-domains = <&power RV1126 554 power-domains = <&power RV1126_PD_NVM>;
706 status = "disabled"; 555 status = "disabled";
707 }; 556 };
708 557
709 pinctrl: pinctrl { 558 pinctrl: pinctrl {
710 compatible = "rockchip,rv1126- 559 compatible = "rockchip,rv1126-pinctrl";
711 rockchip,grf = <&grf>; 560 rockchip,grf = <&grf>;
712 rockchip,pmu = <&pmugrf>; 561 rockchip,pmu = <&pmugrf>;
713 #address-cells = <1>; 562 #address-cells = <1>;
714 #size-cells = <1>; 563 #size-cells = <1>;
715 ranges; 564 ranges;
716 565
717 gpio0: gpio@ff460000 { 566 gpio0: gpio@ff460000 {
718 compatible = "rockchip 567 compatible = "rockchip,gpio-bank";
719 reg = <0xff460000 0x10 568 reg = <0xff460000 0x100>;
720 interrupts = <GIC_SPI 569 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&pmucru PCLK 570 clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
722 gpio-controller; 571 gpio-controller;
723 #gpio-cells = <2>; 572 #gpio-cells = <2>;
724 interrupt-controller; 573 interrupt-controller;
725 #interrupt-cells = <2> 574 #interrupt-cells = <2>;
726 }; 575 };
727 576
728 gpio1: gpio@ff620000 { 577 gpio1: gpio@ff620000 {
729 compatible = "rockchip 578 compatible = "rockchip,gpio-bank";
730 reg = <0xff620000 0x10 579 reg = <0xff620000 0x100>;
731 interrupts = <GIC_SPI 580 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
732 clocks = <&cru PCLK_GP 581 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
733 gpio-controller; 582 gpio-controller;
734 #gpio-cells = <2>; 583 #gpio-cells = <2>;
735 interrupt-controller; 584 interrupt-controller;
736 #interrupt-cells = <2> 585 #interrupt-cells = <2>;
737 }; 586 };
738 587
739 gpio2: gpio@ff630000 { 588 gpio2: gpio@ff630000 {
740 compatible = "rockchip 589 compatible = "rockchip,gpio-bank";
741 reg = <0xff630000 0x10 590 reg = <0xff630000 0x100>;
742 interrupts = <GIC_SPI 591 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
743 clocks = <&cru PCLK_GP 592 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
744 gpio-controller; 593 gpio-controller;
745 #gpio-cells = <2>; 594 #gpio-cells = <2>;
746 interrupt-controller; 595 interrupt-controller;
747 #interrupt-cells = <2> 596 #interrupt-cells = <2>;
748 }; 597 };
749 598
750 gpio3: gpio@ff640000 { 599 gpio3: gpio@ff640000 {
751 compatible = "rockchip 600 compatible = "rockchip,gpio-bank";
752 reg = <0xff640000 0x10 601 reg = <0xff640000 0x100>;
753 interrupts = <GIC_SPI 602 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
754 clocks = <&cru PCLK_GP 603 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
755 gpio-controller; 604 gpio-controller;
756 #gpio-cells = <2>; 605 #gpio-cells = <2>;
757 interrupt-controller; 606 interrupt-controller;
758 #interrupt-cells = <2> 607 #interrupt-cells = <2>;
759 }; 608 };
760 609
761 gpio4: gpio@ff650000 { 610 gpio4: gpio@ff650000 {
762 compatible = "rockchip 611 compatible = "rockchip,gpio-bank";
763 reg = <0xff650000 0x10 612 reg = <0xff650000 0x100>;
764 interrupts = <GIC_SPI 613 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
765 clocks = <&cru PCLK_GP 614 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
766 gpio-controller; 615 gpio-controller;
767 #gpio-cells = <2>; 616 #gpio-cells = <2>;
768 interrupt-controller; 617 interrupt-controller;
769 #interrupt-cells = <2> 618 #interrupt-cells = <2>;
770 }; 619 };
771 }; 620 };
772 }; 621 };
773 622
774 #include "rv1126-pinctrl.dtsi" 623 #include "rv1126-pinctrl.dtsi"
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