1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Samsung's Exynos3250 SoC device tree source 3 * Samsung's Exynos3250 SoC device tree source
4 * 4 *
5 * Copyright (c) 2014 Samsung Electronics Co., 5 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com 6 * http://www.samsung.com
7 * 7 *
8 * Samsung's Exynos3250 SoC device nodes are l 8 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
9 * based board files can include this file and 9 * based board files can include this file and provide values for board specific
10 * bindings. 10 * bindings.
11 * 11 *
12 * Note: This file does not include device nod 12 * Note: This file does not include device nodes for all the controllers in
13 * Exynos3250 SoC. As device tree coverage for 13 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
14 * nodes can be added to this file. 14 * nodes can be added to this file.
15 */ 15 */
16 16
17 #include "exynos4-cpu-thermal.dtsi" 17 #include "exynos4-cpu-thermal.dtsi"
18 #include <dt-bindings/clock/exynos3250.h> 18 #include <dt-bindings/clock/exynos3250.h>
19 #include <dt-bindings/interrupt-controller/arm 19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 #include <dt-bindings/interrupt-controller/irq 20 #include <dt-bindings/interrupt-controller/irq.h>
21 21
22 / { 22 / {
23 compatible = "samsung,exynos3250"; 23 compatible = "samsung,exynos3250";
24 interrupt-parent = <&gic>; 24 interrupt-parent = <&gic>;
25 #address-cells = <1>; 25 #address-cells = <1>;
26 #size-cells = <1>; 26 #size-cells = <1>;
27 27
28 aliases { 28 aliases {
29 pinctrl0 = &pinctrl_0; 29 pinctrl0 = &pinctrl_0;
30 pinctrl1 = &pinctrl_1; 30 pinctrl1 = &pinctrl_1;
31 spi0 = &spi_0; 31 spi0 = &spi_0;
32 spi1 = &spi_1; 32 spi1 = &spi_1;
33 i2c0 = &i2c_0; 33 i2c0 = &i2c_0;
34 i2c1 = &i2c_1; 34 i2c1 = &i2c_1;
35 i2c2 = &i2c_2; 35 i2c2 = &i2c_2;
36 i2c3 = &i2c_3; 36 i2c3 = &i2c_3;
37 i2c4 = &i2c_4; 37 i2c4 = &i2c_4;
38 i2c5 = &i2c_5; 38 i2c5 = &i2c_5;
39 i2c6 = &i2c_6; 39 i2c6 = &i2c_6;
40 i2c7 = &i2c_7; 40 i2c7 = &i2c_7;
41 serial0 = &serial_0; 41 serial0 = &serial_0;
42 serial1 = &serial_1; 42 serial1 = &serial_1;
43 serial2 = &serial_2; 43 serial2 = &serial_2;
44 }; 44 };
45 45
46 bus_dmc: bus-dmc { 46 bus_dmc: bus-dmc {
47 compatible = "samsung,exynos-b 47 compatible = "samsung,exynos-bus";
48 clocks = <&cmu_dmc CLK_DIV_DMC 48 clocks = <&cmu_dmc CLK_DIV_DMC>;
49 clock-names = "bus"; 49 clock-names = "bus";
50 operating-points-v2 = <&bus_dm 50 operating-points-v2 = <&bus_dmc_opp_table>;
51 status = "disabled"; 51 status = "disabled";
52 52
53 bus_dmc_opp_table: opp-table { 53 bus_dmc_opp_table: opp-table {
54 compatible = "operatin 54 compatible = "operating-points-v2";
55 55
56 opp-50000000 { 56 opp-50000000 {
57 opp-hz = /bits 57 opp-hz = /bits/ 64 <50000000>;
58 opp-microvolt 58 opp-microvolt = <800000>;
59 }; 59 };
60 opp-100000000 { 60 opp-100000000 {
61 opp-hz = /bits 61 opp-hz = /bits/ 64 <100000000>;
62 opp-microvolt 62 opp-microvolt = <800000>;
63 }; 63 };
64 opp-134000000 { 64 opp-134000000 {
65 opp-hz = /bits 65 opp-hz = /bits/ 64 <134000000>;
66 opp-microvolt 66 opp-microvolt = <800000>;
67 }; 67 };
68 opp-200000000 { 68 opp-200000000 {
69 opp-hz = /bits 69 opp-hz = /bits/ 64 <200000000>;
70 opp-microvolt 70 opp-microvolt = <825000>;
71 }; 71 };
72 opp-400000000 { 72 opp-400000000 {
73 opp-hz = /bits 73 opp-hz = /bits/ 64 <400000000>;
74 opp-microvolt 74 opp-microvolt = <875000>;
75 }; 75 };
76 }; 76 };
77 }; 77 };
78 78
79 bus_fsys: bus-fsys { 79 bus_fsys: bus-fsys {
80 compatible = "samsung,exynos-b 80 compatible = "samsung,exynos-bus";
81 clocks = <&cmu CLK_DIV_ACLK_20 81 clocks = <&cmu CLK_DIV_ACLK_200>;
82 clock-names = "bus"; 82 clock-names = "bus";
83 operating-points-v2 = <&bus_le 83 operating-points-v2 = <&bus_leftbus_opp_table>;
84 status = "disabled"; 84 status = "disabled";
85 }; 85 };
86 86
87 bus_isp: bus-isp { 87 bus_isp: bus-isp {
88 compatible = "samsung,exynos-b 88 compatible = "samsung,exynos-bus";
89 clocks = <&cmu CLK_DIV_ACLK_26 89 clocks = <&cmu CLK_DIV_ACLK_266>;
90 clock-names = "bus"; 90 clock-names = "bus";
91 operating-points-v2 = <&bus_is 91 operating-points-v2 = <&bus_isp_opp_table>;
92 status = "disabled"; 92 status = "disabled";
93 93
94 bus_isp_opp_table: opp-table { 94 bus_isp_opp_table: opp-table {
95 compatible = "operatin 95 compatible = "operating-points-v2";
96 96
97 opp-50000000 { 97 opp-50000000 {
98 opp-hz = /bits 98 opp-hz = /bits/ 64 <50000000>;
99 }; 99 };
100 opp-80000000 { 100 opp-80000000 {
101 opp-hz = /bits 101 opp-hz = /bits/ 64 <80000000>;
102 }; 102 };
103 opp-100000000 { 103 opp-100000000 {
104 opp-hz = /bits 104 opp-hz = /bits/ 64 <100000000>;
105 }; 105 };
106 opp-200000000 { 106 opp-200000000 {
107 opp-hz = /bits 107 opp-hz = /bits/ 64 <200000000>;
108 }; 108 };
109 opp-300000000 { 109 opp-300000000 {
110 opp-hz = /bits 110 opp-hz = /bits/ 64 <300000000>;
111 }; 111 };
112 }; 112 };
113 }; 113 };
114 114
115 bus_lcd0: bus-lcd0 { 115 bus_lcd0: bus-lcd0 {
116 compatible = "samsung,exynos-b 116 compatible = "samsung,exynos-bus";
117 clocks = <&cmu CLK_DIV_ACLK_16 117 clocks = <&cmu CLK_DIV_ACLK_160>;
118 clock-names = "bus"; 118 clock-names = "bus";
119 operating-points-v2 = <&bus_le 119 operating-points-v2 = <&bus_leftbus_opp_table>;
120 status = "disabled"; 120 status = "disabled";
121 }; 121 };
122 122
123 bus_leftbus: bus-leftbus { 123 bus_leftbus: bus-leftbus {
124 compatible = "samsung,exynos-b 124 compatible = "samsung,exynos-bus";
125 clocks = <&cmu CLK_DIV_GDL>; 125 clocks = <&cmu CLK_DIV_GDL>;
126 clock-names = "bus"; 126 clock-names = "bus";
127 operating-points-v2 = <&bus_le 127 operating-points-v2 = <&bus_leftbus_opp_table>;
128 status = "disabled"; 128 status = "disabled";
129 }; 129 };
130 130
131 bus_mcuisp: bus-mcuisp { 131 bus_mcuisp: bus-mcuisp {
132 compatible = "samsung,exynos-b 132 compatible = "samsung,exynos-bus";
133 clocks = <&cmu CLK_DIV_ACLK_40 133 clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
134 clock-names = "bus"; 134 clock-names = "bus";
135 operating-points-v2 = <&bus_mc 135 operating-points-v2 = <&bus_mcuisp_opp_table>;
136 status = "disabled"; 136 status = "disabled";
137 137
138 bus_mcuisp_opp_table: opp-tabl 138 bus_mcuisp_opp_table: opp-table {
139 compatible = "operatin 139 compatible = "operating-points-v2";
140 140
141 opp-50000000 { 141 opp-50000000 {
142 opp-hz = /bits 142 opp-hz = /bits/ 64 <50000000>;
143 }; 143 };
144 opp-80000000 { 144 opp-80000000 {
145 opp-hz = /bits 145 opp-hz = /bits/ 64 <80000000>;
146 }; 146 };
147 opp-100000000 { 147 opp-100000000 {
148 opp-hz = /bits 148 opp-hz = /bits/ 64 <100000000>;
149 }; 149 };
150 opp-200000000 { 150 opp-200000000 {
151 opp-hz = /bits 151 opp-hz = /bits/ 64 <200000000>;
152 }; 152 };
153 opp-400000000 { 153 opp-400000000 {
154 opp-hz = /bits 154 opp-hz = /bits/ 64 <400000000>;
155 }; 155 };
156 }; 156 };
157 }; 157 };
158 158
159 bus_mfc: bus-mfc { 159 bus_mfc: bus-mfc {
160 compatible = "samsung,exynos-b 160 compatible = "samsung,exynos-bus";
161 clocks = <&cmu CLK_SCLK_MFC>; 161 clocks = <&cmu CLK_SCLK_MFC>;
162 clock-names = "bus"; 162 clock-names = "bus";
163 operating-points-v2 = <&bus_le 163 operating-points-v2 = <&bus_leftbus_opp_table>;
164 status = "disabled"; 164 status = "disabled";
165 }; 165 };
166 166
167 bus_peril: bus-peril { 167 bus_peril: bus-peril {
168 compatible = "samsung,exynos-b 168 compatible = "samsung,exynos-bus";
169 clocks = <&cmu CLK_DIV_ACLK_10 169 clocks = <&cmu CLK_DIV_ACLK_100>;
170 clock-names = "bus"; 170 clock-names = "bus";
171 operating-points-v2 = <&bus_pe 171 operating-points-v2 = <&bus_peril_opp_table>;
172 status = "disabled"; 172 status = "disabled";
173 173
174 bus_peril_opp_table: opp-table 174 bus_peril_opp_table: opp-table {
175 compatible = "operatin 175 compatible = "operating-points-v2";
176 176
177 opp-50000000 { 177 opp-50000000 {
178 opp-hz = /bits 178 opp-hz = /bits/ 64 <50000000>;
179 }; 179 };
180 opp-80000000 { 180 opp-80000000 {
181 opp-hz = /bits 181 opp-hz = /bits/ 64 <80000000>;
182 }; 182 };
183 opp-100000000 { 183 opp-100000000 {
184 opp-hz = /bits 184 opp-hz = /bits/ 64 <100000000>;
185 }; 185 };
186 }; 186 };
187 }; 187 };
188 188
189 bus_rightbus: bus-rightbus { 189 bus_rightbus: bus-rightbus {
190 compatible = "samsung,exynos-b 190 compatible = "samsung,exynos-bus";
191 clocks = <&cmu CLK_DIV_GDR>; 191 clocks = <&cmu CLK_DIV_GDR>;
192 clock-names = "bus"; 192 clock-names = "bus";
193 operating-points-v2 = <&bus_le 193 operating-points-v2 = <&bus_leftbus_opp_table>;
194 status = "disabled"; 194 status = "disabled";
195 }; 195 };
196 196
197 cpus { 197 cpus {
198 #address-cells = <1>; 198 #address-cells = <1>;
199 #size-cells = <0>; 199 #size-cells = <0>;
200 200
201 cpu-map { 201 cpu-map {
202 cluster0 { 202 cluster0 {
203 core0 { 203 core0 {
204 cpu = 204 cpu = <&cpu0>;
205 }; 205 };
206 core1 { 206 core1 {
207 cpu = 207 cpu = <&cpu1>;
208 }; 208 };
209 }; 209 };
210 }; 210 };
211 211
212 cpu0: cpu@0 { 212 cpu0: cpu@0 {
213 device_type = "cpu"; 213 device_type = "cpu";
214 compatible = "arm,cort 214 compatible = "arm,cortex-a7";
215 reg = <0>; 215 reg = <0>;
216 clock-frequency = <100 216 clock-frequency = <1000000000>;
217 clocks = <&cmu CLK_ARM 217 clocks = <&cmu CLK_ARM_CLK>;
218 clock-names = "cpu"; 218 clock-names = "cpu";
219 #cooling-cells = <2>; 219 #cooling-cells = <2>;
220 220
221 operating-points = < 221 operating-points = <
222 1000000 115000 222 1000000 1150000
223 900000 111250 223 900000 1112500
224 800000 107500 224 800000 1075000
225 700000 103750 225 700000 1037500
226 600000 100000 226 600000 1000000
227 500000 962500 227 500000 962500
228 400000 925000 228 400000 925000
229 300000 887500 229 300000 887500
230 200000 850000 230 200000 850000
231 100000 850000 231 100000 850000
232 >; 232 >;
233 }; 233 };
234 234
235 cpu1: cpu@1 { 235 cpu1: cpu@1 {
236 device_type = "cpu"; 236 device_type = "cpu";
237 compatible = "arm,cort 237 compatible = "arm,cortex-a7";
238 reg = <1>; 238 reg = <1>;
239 clock-frequency = <100 239 clock-frequency = <1000000000>;
240 clocks = <&cmu CLK_ARM 240 clocks = <&cmu CLK_ARM_CLK>;
241 clock-names = "cpu"; 241 clock-names = "cpu";
242 #cooling-cells = <2>; 242 #cooling-cells = <2>;
243 243
244 operating-points = < 244 operating-points = <
245 1000000 115000 245 1000000 1150000
246 900000 111250 246 900000 1112500
247 800000 107500 247 800000 1075000
248 700000 103750 248 700000 1037500
249 600000 100000 249 600000 1000000
250 500000 962500 250 500000 962500
251 400000 925000 251 400000 925000
252 300000 887500 252 300000 887500
253 200000 850000 253 200000 850000
254 100000 850000 254 100000 850000
255 >; 255 >;
256 }; 256 };
257 }; 257 };
258 258
259 xusbxti: clock-0 { 259 xusbxti: clock-0 {
260 compatible = "fixed-clock"; 260 compatible = "fixed-clock";
261 clock-frequency = <0>; 261 clock-frequency = <0>;
262 #clock-cells = <0>; 262 #clock-cells = <0>;
263 clock-output-names = "xusbxti" 263 clock-output-names = "xusbxti";
264 }; 264 };
265 265
266 xxti: clock-1 { 266 xxti: clock-1 {
267 compatible = "fixed-clock"; 267 compatible = "fixed-clock";
268 clock-frequency = <0>; 268 clock-frequency = <0>;
269 #clock-cells = <0>; 269 #clock-cells = <0>;
270 clock-output-names = "xxti"; 270 clock-output-names = "xxti";
271 }; 271 };
272 272
273 xtcxo: clock-2 { 273 xtcxo: clock-2 {
274 compatible = "fixed-clock"; 274 compatible = "fixed-clock";
275 clock-frequency = <0>; 275 clock-frequency = <0>;
276 #clock-cells = <0>; 276 #clock-cells = <0>;
277 clock-output-names = "xtcxo"; 277 clock-output-names = "xtcxo";
278 }; 278 };
279 279
280 bus_leftbus_opp_table: opp-table-0 { 280 bus_leftbus_opp_table: opp-table-0 {
281 compatible = "operating-points 281 compatible = "operating-points-v2";
282 282
283 opp-50000000 { 283 opp-50000000 {
284 opp-hz = /bits/ 64 <50 284 opp-hz = /bits/ 64 <50000000>;
285 opp-microvolt = <90000 285 opp-microvolt = <900000>;
286 }; 286 };
287 opp-80000000 { 287 opp-80000000 {
288 opp-hz = /bits/ 64 <80 288 opp-hz = /bits/ 64 <80000000>;
289 opp-microvolt = <90000 289 opp-microvolt = <900000>;
290 }; 290 };
291 opp-100000000 { 291 opp-100000000 {
292 opp-hz = /bits/ 64 <10 292 opp-hz = /bits/ 64 <100000000>;
293 opp-microvolt = <10000 293 opp-microvolt = <1000000>;
294 }; 294 };
295 opp-134000000 { 295 opp-134000000 {
296 opp-hz = /bits/ 64 <13 296 opp-hz = /bits/ 64 <134000000>;
297 opp-microvolt = <10000 297 opp-microvolt = <1000000>;
298 }; 298 };
299 opp-200000000 { 299 opp-200000000 {
300 opp-hz = /bits/ 64 <20 300 opp-hz = /bits/ 64 <200000000>;
301 opp-microvolt = <10000 301 opp-microvolt = <1000000>;
302 }; 302 };
303 }; 303 };
304 304
305 pmu { 305 pmu {
306 compatible = "arm,cortex-a7-pm 306 compatible = "arm,cortex-a7-pmu";
307 interrupts = <GIC_SPI 18 IRQ_T 307 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 19 IRQ_T 308 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
309 }; 309 };
310 310
311 soc: soc { 311 soc: soc {
312 compatible = "simple-bus"; 312 compatible = "simple-bus";
313 #address-cells = <1>; 313 #address-cells = <1>;
314 #size-cells = <1>; 314 #size-cells = <1>;
315 ranges; 315 ranges;
316 316
317 sram@2020000 { 317 sram@2020000 {
318 compatible = "mmio-sra 318 compatible = "mmio-sram";
319 reg = <0x02020000 0x40 319 reg = <0x02020000 0x40000>;
320 #address-cells = <1>; 320 #address-cells = <1>;
321 #size-cells = <1>; 321 #size-cells = <1>;
322 ranges = <0 0x02020000 322 ranges = <0 0x02020000 0x40000>;
323 323
324 smp-sram@0 { 324 smp-sram@0 {
325 compatible = " 325 compatible = "samsung,exynos4210-sysram";
326 reg = <0x0 0x1 326 reg = <0x0 0x1000>;
327 }; 327 };
328 328
329 smp-sram@3f000 { 329 smp-sram@3f000 {
330 compatible = " 330 compatible = "samsung,exynos4210-sysram-ns";
331 reg = <0x3f000 331 reg = <0x3f000 0x1000>;
332 }; 332 };
333 }; 333 };
334 334
335 chipid@10000000 { 335 chipid@10000000 {
336 compatible = "samsung, 336 compatible = "samsung,exynos4210-chipid";
337 reg = <0x10000000 0x10 337 reg = <0x10000000 0x100>;
338 }; 338 };
339 339
340 sys_reg: syscon@10010000 { 340 sys_reg: syscon@10010000 {
341 compatible = "samsung, 341 compatible = "samsung,exynos3-sysreg", "syscon";
342 reg = <0x10010000 0x40 342 reg = <0x10010000 0x400>;
343 }; 343 };
344 344
345 pmu_system_controller: system- 345 pmu_system_controller: system-controller@10020000 {
346 compatible = "samsung, 346 compatible = "samsung,exynos3250-pmu", "simple-mfd", "syscon";
347 reg = <0x10020000 0x40 347 reg = <0x10020000 0x4000>;
348 interrupt-controller; 348 interrupt-controller;
349 #interrupt-cells = <3> 349 #interrupt-cells = <3>;
350 interrupt-parent = <&g 350 interrupt-parent = <&gic>;
351 clock-names = "clkout8 351 clock-names = "clkout8";
352 clocks = <&cmu CLK_FIN 352 clocks = <&cmu CLK_FIN_PLL>;
353 #clock-cells = <1>; 353 #clock-cells = <1>;
354 354
355 mipi_phy: mipi-phy { 355 mipi_phy: mipi-phy {
356 compatible = " 356 compatible = "samsung,s5pv210-mipi-video-phy";
357 #phy-cells = < 357 #phy-cells = <1>;
358 }; 358 };
359 }; 359 };
360 360
361 pd_cam: power-domain@10023c00 361 pd_cam: power-domain@10023c00 {
362 compatible = "samsung, 362 compatible = "samsung,exynos4210-pd";
363 reg = <0x10023c00 0x20 363 reg = <0x10023c00 0x20>;
364 #power-domain-cells = 364 #power-domain-cells = <0>;
365 label = "CAM"; 365 label = "CAM";
366 }; 366 };
367 367
368 pd_mfc: power-domain@10023c40 368 pd_mfc: power-domain@10023c40 {
369 compatible = "samsung, 369 compatible = "samsung,exynos4210-pd";
370 reg = <0x10023c40 0x20 370 reg = <0x10023c40 0x20>;
371 #power-domain-cells = 371 #power-domain-cells = <0>;
372 label = "MFC"; 372 label = "MFC";
373 }; 373 };
374 374
375 pd_g3d: power-domain@10023c60 375 pd_g3d: power-domain@10023c60 {
376 compatible = "samsung, 376 compatible = "samsung,exynos4210-pd";
377 reg = <0x10023c60 0x20 377 reg = <0x10023c60 0x20>;
378 #power-domain-cells = 378 #power-domain-cells = <0>;
379 label = "G3D"; 379 label = "G3D";
380 }; 380 };
381 381
382 pd_lcd0: power-domain@10023c80 382 pd_lcd0: power-domain@10023c80 {
383 compatible = "samsung, 383 compatible = "samsung,exynos4210-pd";
384 reg = <0x10023c80 0x20 384 reg = <0x10023c80 0x20>;
385 #power-domain-cells = 385 #power-domain-cells = <0>;
386 label = "LCD0"; 386 label = "LCD0";
387 }; 387 };
388 388
389 pd_isp: power-domain@10023ca0 389 pd_isp: power-domain@10023ca0 {
390 compatible = "samsung, 390 compatible = "samsung,exynos4210-pd";
391 reg = <0x10023ca0 0x20 391 reg = <0x10023ca0 0x20>;
392 #power-domain-cells = 392 #power-domain-cells = <0>;
393 label = "ISP"; 393 label = "ISP";
394 }; 394 };
395 395
396 cmu: clock-controller@10030000 396 cmu: clock-controller@10030000 {
397 compatible = "samsung, 397 compatible = "samsung,exynos3250-cmu";
398 reg = <0x10030000 0x20 398 reg = <0x10030000 0x20000>;
399 #clock-cells = <1>; 399 #clock-cells = <1>;
400 assigned-clocks = <&cm 400 assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
401 <&cm 401 <&cmu CLK_MOUT_ACLK_266_SUB>;
402 assigned-clock-parents 402 assigned-clock-parents = <&cmu CLK_FIN_PLL>,
403 403 <&cmu CLK_FIN_PLL>;
404 }; 404 };
405 405
406 cmu_dmc: clock-controller@105c 406 cmu_dmc: clock-controller@105c0000 {
407 compatible = "samsung, 407 compatible = "samsung,exynos3250-cmu-dmc";
408 reg = <0x105c0000 0x20 408 reg = <0x105c0000 0x2000>;
409 #clock-cells = <1>; 409 #clock-cells = <1>;
410 }; 410 };
411 411
412 rtc: rtc@10070000 { 412 rtc: rtc@10070000 {
413 compatible = "samsung, 413 compatible = "samsung,s3c6410-rtc";
414 reg = <0x10070000 0x10 414 reg = <0x10070000 0x100>;
415 interrupts = <GIC_SPI 415 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
416 <GIC_SPI 416 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
417 interrupt-parent = <&p 417 interrupt-parent = <&pmu_system_controller>;
418 status = "disabled"; 418 status = "disabled";
419 }; 419 };
420 420
421 tmu: tmu@100c0000 { 421 tmu: tmu@100c0000 {
422 compatible = "samsung, 422 compatible = "samsung,exynos3250-tmu";
423 reg = <0x100c0000 0x10 423 reg = <0x100c0000 0x100>;
424 interrupts = <GIC_SPI 424 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
425 clocks = <&cmu CLK_TMU 425 clocks = <&cmu CLK_TMU_APBIF>;
426 clock-names = "tmu_apb 426 clock-names = "tmu_apbif";
427 #thermal-sensor-cells 427 #thermal-sensor-cells = <0>;
428 status = "disabled"; 428 status = "disabled";
429 }; 429 };
430 430
431 gic: interrupt-controller@1048 431 gic: interrupt-controller@10481000 {
432 compatible = "arm,cort 432 compatible = "arm,cortex-a15-gic";
433 #interrupt-cells = <3> 433 #interrupt-cells = <3>;
434 interrupt-controller; 434 interrupt-controller;
435 reg = <0x10481000 0x10 435 reg = <0x10481000 0x1000>,
436 <0x10482000 0x20 436 <0x10482000 0x2000>,
437 <0x10484000 0x20 437 <0x10484000 0x2000>,
438 <0x10486000 0x20 438 <0x10486000 0x2000>;
439 interrupts = <GIC_PPI 439 interrupts = <GIC_PPI 9
440 (GIC_C 440 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
441 }; 441 };
442 442
443 timer@10050000 { 443 timer@10050000 {
444 compatible = "samsung, 444 compatible = "samsung,exynos3250-mct",
445 "samsung, 445 "samsung,exynos4210-mct";
446 reg = <0x10050000 0x80 446 reg = <0x10050000 0x800>;
447 interrupts = <GIC_SPI 447 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
448 <GIC_SPI 448 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
449 <GIC_SPI 449 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
450 <GIC_SPI 450 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
451 <GIC_SPI 451 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
452 <GIC_SPI 452 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
453 <GIC_SPI 453 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>,
454 <GIC_SPI 454 <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&cmu CLK_FIN 455 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
456 clock-names = "fin_pll 456 clock-names = "fin_pll", "mct";
457 }; 457 };
458 458
459 pinctrl_1: pinctrl@11000000 { 459 pinctrl_1: pinctrl@11000000 {
460 compatible = "samsung, 460 compatible = "samsung,exynos3250-pinctrl";
461 reg = <0x11000000 0x10 461 reg = <0x11000000 0x1000>;
462 interrupts = <GIC_SPI 462 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
463 463
464 wakeup-interrupt-contr 464 wakeup-interrupt-controller {
465 compatible = " 465 compatible = "samsung,exynos4210-wakeup-eint";
466 interrupts = < 466 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
467 }; 467 };
468 }; 468 };
469 469
470 pinctrl_0: pinctrl@11400000 { 470 pinctrl_0: pinctrl@11400000 {
471 compatible = "samsung, 471 compatible = "samsung,exynos3250-pinctrl";
472 reg = <0x11400000 0x10 472 reg = <0x11400000 0x1000>;
473 interrupts = <GIC_SPI 473 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
474 }; 474 };
475 475
476 jpeg: codec@11830000 { 476 jpeg: codec@11830000 {
477 compatible = "samsung, 477 compatible = "samsung,exynos3250-jpeg";
478 reg = <0x11830000 0x10 478 reg = <0x11830000 0x1000>;
479 interrupts = <GIC_SPI 479 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
480 clocks = <&cmu CLK_JPE 480 clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
481 clock-names = "jpeg", 481 clock-names = "jpeg", "sclk";
482 power-domains = <&pd_c 482 power-domains = <&pd_cam>;
483 assigned-clocks = <&cm 483 assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
484 assigned-clock-rates = 484 assigned-clock-rates = <0>, <150000000>;
485 assigned-clock-parents 485 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
486 iommus = <&sysmmu_jpeg 486 iommus = <&sysmmu_jpeg>;
487 status = "disabled"; 487 status = "disabled";
488 }; 488 };
489 489
490 sysmmu_jpeg: sysmmu@11a60000 { 490 sysmmu_jpeg: sysmmu@11a60000 {
491 compatible = "samsung, 491 compatible = "samsung,exynos-sysmmu";
492 reg = <0x11a60000 0x10 492 reg = <0x11a60000 0x1000>;
493 interrupts = <GIC_SPI 493 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
494 clock-names = "sysmmu" 494 clock-names = "sysmmu", "master";
495 clocks = <&cmu CLK_SMM 495 clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
496 power-domains = <&pd_c 496 power-domains = <&pd_cam>;
497 #iommu-cells = <0>; 497 #iommu-cells = <0>;
498 }; 498 };
499 499
500 fimd: fimd@11c00000 { 500 fimd: fimd@11c00000 {
501 compatible = "samsung, 501 compatible = "samsung,exynos3250-fimd";
502 reg = <0x11c00000 0x30 502 reg = <0x11c00000 0x30000>;
503 interrupt-names = "fif 503 interrupt-names = "fifo", "vsync", "lcd_sys";
504 interrupts = <GIC_SPI 504 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
505 <GIC_SPI 505 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
506 <GIC_SPI 506 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
507 clocks = <&cmu CLK_SCL 507 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
508 clock-names = "sclk_fi 508 clock-names = "sclk_fimd", "fimd";
509 power-domains = <&pd_l 509 power-domains = <&pd_lcd0>;
510 iommus = <&sysmmu_fimd 510 iommus = <&sysmmu_fimd0>;
511 samsung,sysreg = <&sys 511 samsung,sysreg = <&sys_reg>;
512 status = "disabled"; 512 status = "disabled";
513 }; 513 };
514 514
515 dsi_0: dsi@11c80000 { 515 dsi_0: dsi@11c80000 {
516 compatible = "samsung, 516 compatible = "samsung,exynos3250-mipi-dsi";
517 reg = <0x11c80000 0x10 517 reg = <0x11c80000 0x10000>;
518 interrupts = <GIC_SPI 518 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
519 samsung,phy-type = <0> 519 samsung,phy-type = <0>;
520 power-domains = <&pd_l 520 power-domains = <&pd_lcd0>;
521 phys = <&mipi_phy 1>; 521 phys = <&mipi_phy 1>;
522 phy-names = "dsim"; 522 phy-names = "dsim";
523 clocks = <&cmu CLK_DSI 523 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
524 clock-names = "bus_clk 524 clock-names = "bus_clk", "pll_clk";
525 #address-cells = <1>; 525 #address-cells = <1>;
526 #size-cells = <0>; 526 #size-cells = <0>;
527 status = "disabled"; 527 status = "disabled";
528 }; 528 };
529 529
530 sysmmu_fimd0: sysmmu@11e20000 530 sysmmu_fimd0: sysmmu@11e20000 {
531 compatible = "samsung, 531 compatible = "samsung,exynos-sysmmu";
532 reg = <0x11e20000 0x10 532 reg = <0x11e20000 0x1000>;
533 interrupts = <GIC_SPI 533 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
534 clock-names = "sysmmu" 534 clock-names = "sysmmu", "master";
535 clocks = <&cmu CLK_SMM 535 clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
536 power-domains = <&pd_l 536 power-domains = <&pd_lcd0>;
537 #iommu-cells = <0>; 537 #iommu-cells = <0>;
538 }; 538 };
539 539
540 hsotg: usb@12480000 { 540 hsotg: usb@12480000 {
541 compatible = "samsung, 541 compatible = "samsung,s3c6400-hsotg";
542 reg = <0x12480000 0x20 542 reg = <0x12480000 0x20000>;
543 interrupts = <GIC_SPI 543 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
544 clocks = <&cmu CLK_USB 544 clocks = <&cmu CLK_USBOTG>;
545 clock-names = "otg"; 545 clock-names = "otg";
546 phys = <&exynos_usbphy 546 phys = <&exynos_usbphy 0>;
547 phy-names = "usb2-phy" 547 phy-names = "usb2-phy";
548 status = "disabled"; 548 status = "disabled";
549 }; 549 };
550 550
551 mshc_0: mmc@12510000 { 551 mshc_0: mmc@12510000 {
552 compatible = "samsung, 552 compatible = "samsung,exynos5420-dw-mshc";
553 reg = <0x12510000 0x10 553 reg = <0x12510000 0x1000>;
554 interrupts = <GIC_SPI 554 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
555 clocks = <&cmu CLK_SDM 555 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
556 clock-names = "biu", " 556 clock-names = "biu", "ciu";
557 fifo-depth = <0x80>; 557 fifo-depth = <0x80>;
558 #address-cells = <1>; 558 #address-cells = <1>;
559 #size-cells = <0>; 559 #size-cells = <0>;
560 status = "disabled"; 560 status = "disabled";
561 }; 561 };
562 562
563 mshc_1: mmc@12520000 { 563 mshc_1: mmc@12520000 {
564 compatible = "samsung, 564 compatible = "samsung,exynos5420-dw-mshc";
565 reg = <0x12520000 0x10 565 reg = <0x12520000 0x1000>;
566 interrupts = <GIC_SPI 566 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
567 clocks = <&cmu CLK_SDM 567 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
568 clock-names = "biu", " 568 clock-names = "biu", "ciu";
569 fifo-depth = <0x80>; 569 fifo-depth = <0x80>;
570 #address-cells = <1>; 570 #address-cells = <1>;
571 #size-cells = <0>; 571 #size-cells = <0>;
572 status = "disabled"; 572 status = "disabled";
573 }; 573 };
574 574
575 mshc_2: mmc@12530000 { 575 mshc_2: mmc@12530000 {
576 compatible = "samsung, 576 compatible = "samsung,exynos5250-dw-mshc";
577 reg = <0x12530000 0x10 577 reg = <0x12530000 0x1000>;
578 interrupts = <GIC_SPI 578 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
579 clocks = <&cmu CLK_SDM 579 clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
580 clock-names = "biu", " 580 clock-names = "biu", "ciu";
581 fifo-depth = <0x80>; 581 fifo-depth = <0x80>;
582 #address-cells = <1>; 582 #address-cells = <1>;
583 #size-cells = <0>; 583 #size-cells = <0>;
584 status = "disabled"; 584 status = "disabled";
585 }; 585 };
586 586
587 exynos_usbphy: usb-phy@125b000 587 exynos_usbphy: usb-phy@125b0000 {
588 compatible = "samsung, 588 compatible = "samsung,exynos3250-usb2-phy";
589 reg = <0x125b0000 0x10 589 reg = <0x125b0000 0x100>;
590 samsung,pmureg-phandle 590 samsung,pmureg-phandle = <&pmu_system_controller>;
591 clocks = <&cmu CLK_USB 591 clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
592 clock-names = "phy", " 592 clock-names = "phy", "ref";
593 #phy-cells = <1>; 593 #phy-cells = <1>;
594 status = "disabled"; 594 status = "disabled";
595 }; 595 };
596 596
597 pdma0: dma-controller@12680000 597 pdma0: dma-controller@12680000 {
598 compatible = "arm,pl33 598 compatible = "arm,pl330", "arm,primecell";
599 reg = <0x12680000 0x10 599 reg = <0x12680000 0x1000>;
600 interrupts = <GIC_SPI 600 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
601 clocks = <&cmu CLK_PDM 601 clocks = <&cmu CLK_PDMA0>;
602 clock-names = "apb_pcl 602 clock-names = "apb_pclk";
603 #dma-cells = <1>; 603 #dma-cells = <1>;
604 }; 604 };
605 605
606 pdma1: dma-controller@12690000 606 pdma1: dma-controller@12690000 {
607 compatible = "arm,pl33 607 compatible = "arm,pl330", "arm,primecell";
608 reg = <0x12690000 0x10 608 reg = <0x12690000 0x1000>;
609 interrupts = <GIC_SPI 609 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
610 clocks = <&cmu CLK_PDM 610 clocks = <&cmu CLK_PDMA1>;
611 clock-names = "apb_pcl 611 clock-names = "apb_pclk";
612 #dma-cells = <1>; 612 #dma-cells = <1>;
613 }; 613 };
614 614
615 adc: adc@126c0000 { 615 adc: adc@126c0000 {
616 compatible = "samsung, 616 compatible = "samsung,exynos3250-adc";
617 reg = <0x126c0000 0x10 617 reg = <0x126c0000 0x100>;
618 interrupts = <GIC_SPI 618 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
619 clock-names = "adc", " 619 clock-names = "adc", "sclk";
620 clocks = <&cmu CLK_TSA 620 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
621 #io-channel-cells = <1 621 #io-channel-cells = <1>;
622 samsung,syscon-phandle 622 samsung,syscon-phandle = <&pmu_system_controller>;
623 status = "disabled"; 623 status = "disabled";
624 }; 624 };
625 625
626 gpu: gpu@13000000 { 626 gpu: gpu@13000000 {
627 compatible = "samsung, 627 compatible = "samsung,exynos4210-mali", "arm,mali-400";
628 reg = <0x13000000 0x10 628 reg = <0x13000000 0x10000>;
629 interrupts = <GIC_SPI 629 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
630 <GIC_SPI 630 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
631 <GIC_SPI 631 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
632 <GIC_SPI 632 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
633 <GIC_SPI 633 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
634 <GIC_SPI 634 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
635 <GIC_SPI 635 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
636 <GIC_SPI 636 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
637 <GIC_SPI 637 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
638 <GIC_SPI 638 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
639 <GIC_SPI 639 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
640 interrupt-names = "gp" 640 interrupt-names = "gp",
641 "gpm 641 "gpmmu",
642 "pp0 642 "pp0",
643 "ppm 643 "ppmmu0",
644 "pp1 644 "pp1",
645 "ppm 645 "ppmmu1",
646 "pp2 646 "pp2",
647 "ppm 647 "ppmmu2",
648 "pp3 648 "pp3",
649 "ppm 649 "ppmmu3",
650 "pmu 650 "pmu";
651 clocks = <&cmu CLK_G3D 651 clocks = <&cmu CLK_G3D>,
652 <&cmu CLK_SCL 652 <&cmu CLK_SCLK_G3D>;
653 clock-names = "bus", " 653 clock-names = "bus", "core";
654 power-domains = <&pd_g 654 power-domains = <&pd_g3d>;
655 status = "disabled"; 655 status = "disabled";
656 /* TODO: operating poi 656 /* TODO: operating points for DVFS, assigned clock as 134 MHz */
657 }; 657 };
658 658
659 mfc: codec@13400000 { 659 mfc: codec@13400000 {
660 compatible = "samsung, 660 compatible = "samsung,exynos3250-mfc", "samsung,mfc-v7";
661 reg = <0x13400000 0x10 661 reg = <0x13400000 0x10000>;
662 interrupts = <GIC_SPI 662 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
663 clock-names = "mfc", " 663 clock-names = "mfc", "sclk_mfc";
664 clocks = <&cmu CLK_MFC 664 clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
665 power-domains = <&pd_m 665 power-domains = <&pd_mfc>;
666 iommus = <&sysmmu_mfc> 666 iommus = <&sysmmu_mfc>;
667 }; 667 };
668 668
669 sysmmu_mfc: sysmmu@13620000 { 669 sysmmu_mfc: sysmmu@13620000 {
670 compatible = "samsung, 670 compatible = "samsung,exynos-sysmmu";
671 reg = <0x13620000 0x10 671 reg = <0x13620000 0x1000>;
672 interrupts = <GIC_SPI 672 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
673 clock-names = "sysmmu" 673 clock-names = "sysmmu", "master";
674 clocks = <&cmu CLK_SMM 674 clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
675 power-domains = <&pd_m 675 power-domains = <&pd_mfc>;
676 #iommu-cells = <0>; 676 #iommu-cells = <0>;
677 }; 677 };
678 678
679 serial_0: serial@13800000 { 679 serial_0: serial@13800000 {
680 compatible = "samsung, 680 compatible = "samsung,exynos4210-uart";
681 reg = <0x13800000 0x10 681 reg = <0x13800000 0x100>;
682 interrupts = <GIC_SPI 682 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
683 clocks = <&cmu CLK_UAR 683 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
684 clock-names = "uart", 684 clock-names = "uart", "clk_uart_baud0";
685 pinctrl-names = "defau 685 pinctrl-names = "default";
686 pinctrl-0 = <&uart0_da 686 pinctrl-0 = <&uart0_data &uart0_fctl>;
687 status = "disabled"; 687 status = "disabled";
688 }; 688 };
689 689
690 serial_1: serial@13810000 { 690 serial_1: serial@13810000 {
691 compatible = "samsung, 691 compatible = "samsung,exynos4210-uart";
692 reg = <0x13810000 0x10 692 reg = <0x13810000 0x100>;
693 interrupts = <GIC_SPI 693 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
694 clocks = <&cmu CLK_UAR 694 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
695 clock-names = "uart", 695 clock-names = "uart", "clk_uart_baud0";
696 pinctrl-names = "defau 696 pinctrl-names = "default";
697 pinctrl-0 = <&uart1_da 697 pinctrl-0 = <&uart1_data>;
698 status = "disabled"; 698 status = "disabled";
699 }; 699 };
700 700
701 serial_2: serial@13820000 { 701 serial_2: serial@13820000 {
702 compatible = "samsung, 702 compatible = "samsung,exynos4210-uart";
703 reg = <0x13820000 0x10 703 reg = <0x13820000 0x100>;
704 interrupts = <GIC_SPI 704 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
705 clocks = <&cmu CLK_UAR 705 clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
706 clock-names = "uart", 706 clock-names = "uart", "clk_uart_baud0";
707 pinctrl-names = "defau 707 pinctrl-names = "default";
708 pinctrl-0 = <&uart2_da 708 pinctrl-0 = <&uart2_data>;
709 status = "disabled"; 709 status = "disabled";
710 }; 710 };
711 711
712 i2c_0: i2c@13860000 { 712 i2c_0: i2c@13860000 {
713 #address-cells = <1>; 713 #address-cells = <1>;
714 #size-cells = <0>; 714 #size-cells = <0>;
715 compatible = "samsung, 715 compatible = "samsung,s3c2440-i2c";
716 reg = <0x13860000 0x10 716 reg = <0x13860000 0x100>;
717 interrupts = <GIC_SPI 717 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
718 clocks = <&cmu CLK_I2C 718 clocks = <&cmu CLK_I2C0>;
719 clock-names = "i2c"; 719 clock-names = "i2c";
720 pinctrl-names = "defau 720 pinctrl-names = "default";
721 pinctrl-0 = <&i2c0_bus 721 pinctrl-0 = <&i2c0_bus>;
722 status = "disabled"; 722 status = "disabled";
723 }; 723 };
724 724
725 i2c_1: i2c@13870000 { 725 i2c_1: i2c@13870000 {
726 #address-cells = <1>; 726 #address-cells = <1>;
727 #size-cells = <0>; 727 #size-cells = <0>;
728 compatible = "samsung, 728 compatible = "samsung,s3c2440-i2c";
729 reg = <0x13870000 0x10 729 reg = <0x13870000 0x100>;
730 interrupts = <GIC_SPI 730 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
731 clocks = <&cmu CLK_I2C 731 clocks = <&cmu CLK_I2C1>;
732 clock-names = "i2c"; 732 clock-names = "i2c";
733 pinctrl-names = "defau 733 pinctrl-names = "default";
734 pinctrl-0 = <&i2c1_bus 734 pinctrl-0 = <&i2c1_bus>;
735 status = "disabled"; 735 status = "disabled";
736 }; 736 };
737 737
738 i2c_2: i2c@13880000 { 738 i2c_2: i2c@13880000 {
739 #address-cells = <1>; 739 #address-cells = <1>;
740 #size-cells = <0>; 740 #size-cells = <0>;
741 compatible = "samsung, 741 compatible = "samsung,s3c2440-i2c";
742 reg = <0x13880000 0x10 742 reg = <0x13880000 0x100>;
743 interrupts = <GIC_SPI 743 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
744 clocks = <&cmu CLK_I2C 744 clocks = <&cmu CLK_I2C2>;
745 clock-names = "i2c"; 745 clock-names = "i2c";
746 pinctrl-names = "defau 746 pinctrl-names = "default";
747 pinctrl-0 = <&i2c2_bus 747 pinctrl-0 = <&i2c2_bus>;
748 status = "disabled"; 748 status = "disabled";
749 }; 749 };
750 750
751 i2c_3: i2c@13890000 { 751 i2c_3: i2c@13890000 {
752 #address-cells = <1>; 752 #address-cells = <1>;
753 #size-cells = <0>; 753 #size-cells = <0>;
754 compatible = "samsung, 754 compatible = "samsung,s3c2440-i2c";
755 reg = <0x13890000 0x10 755 reg = <0x13890000 0x100>;
756 interrupts = <GIC_SPI 756 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
757 clocks = <&cmu CLK_I2C 757 clocks = <&cmu CLK_I2C3>;
758 clock-names = "i2c"; 758 clock-names = "i2c";
759 pinctrl-names = "defau 759 pinctrl-names = "default";
760 pinctrl-0 = <&i2c3_bus 760 pinctrl-0 = <&i2c3_bus>;
761 status = "disabled"; 761 status = "disabled";
762 }; 762 };
763 763
764 i2c_4: i2c@138a0000 { 764 i2c_4: i2c@138a0000 {
765 #address-cells = <1>; 765 #address-cells = <1>;
766 #size-cells = <0>; 766 #size-cells = <0>;
767 compatible = "samsung, 767 compatible = "samsung,s3c2440-i2c";
768 reg = <0x138a0000 0x10 768 reg = <0x138a0000 0x100>;
769 interrupts = <GIC_SPI 769 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
770 clocks = <&cmu CLK_I2C 770 clocks = <&cmu CLK_I2C4>;
771 clock-names = "i2c"; 771 clock-names = "i2c";
772 pinctrl-names = "defau 772 pinctrl-names = "default";
773 pinctrl-0 = <&i2c4_bus 773 pinctrl-0 = <&i2c4_bus>;
774 status = "disabled"; 774 status = "disabled";
775 }; 775 };
776 776
777 i2c_5: i2c@138b0000 { 777 i2c_5: i2c@138b0000 {
778 #address-cells = <1>; 778 #address-cells = <1>;
779 #size-cells = <0>; 779 #size-cells = <0>;
780 compatible = "samsung, 780 compatible = "samsung,s3c2440-i2c";
781 reg = <0x138b0000 0x10 781 reg = <0x138b0000 0x100>;
782 interrupts = <GIC_SPI 782 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
783 clocks = <&cmu CLK_I2C 783 clocks = <&cmu CLK_I2C5>;
784 clock-names = "i2c"; 784 clock-names = "i2c";
785 pinctrl-names = "defau 785 pinctrl-names = "default";
786 pinctrl-0 = <&i2c5_bus 786 pinctrl-0 = <&i2c5_bus>;
787 status = "disabled"; 787 status = "disabled";
788 }; 788 };
789 789
790 i2c_6: i2c@138c0000 { 790 i2c_6: i2c@138c0000 {
791 #address-cells = <1>; 791 #address-cells = <1>;
792 #size-cells = <0>; 792 #size-cells = <0>;
793 compatible = "samsung, 793 compatible = "samsung,s3c2440-i2c";
794 reg = <0x138c0000 0x10 794 reg = <0x138c0000 0x100>;
795 interrupts = <GIC_SPI 795 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
796 clocks = <&cmu CLK_I2C 796 clocks = <&cmu CLK_I2C6>;
797 clock-names = "i2c"; 797 clock-names = "i2c";
798 pinctrl-names = "defau 798 pinctrl-names = "default";
799 pinctrl-0 = <&i2c6_bus 799 pinctrl-0 = <&i2c6_bus>;
800 status = "disabled"; 800 status = "disabled";
801 }; 801 };
802 802
803 i2c_7: i2c@138d0000 { 803 i2c_7: i2c@138d0000 {
804 #address-cells = <1>; 804 #address-cells = <1>;
805 #size-cells = <0>; 805 #size-cells = <0>;
806 compatible = "samsung, 806 compatible = "samsung,s3c2440-i2c";
807 reg = <0x138d0000 0x10 807 reg = <0x138d0000 0x100>;
808 interrupts = <GIC_SPI 808 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
809 clocks = <&cmu CLK_I2C 809 clocks = <&cmu CLK_I2C7>;
810 clock-names = "i2c"; 810 clock-names = "i2c";
811 pinctrl-names = "defau 811 pinctrl-names = "default";
812 pinctrl-0 = <&i2c7_bus 812 pinctrl-0 = <&i2c7_bus>;
813 status = "disabled"; 813 status = "disabled";
814 }; 814 };
815 815
816 spi_0: spi@13920000 { 816 spi_0: spi@13920000 {
817 compatible = "samsung, 817 compatible = "samsung,exynos4210-spi";
818 reg = <0x13920000 0x10 818 reg = <0x13920000 0x100>;
819 interrupts = <GIC_SPI 819 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
820 dmas = <&pdma0 7>, <&p 820 dmas = <&pdma0 7>, <&pdma0 6>;
821 dma-names = "tx", "rx" 821 dma-names = "tx", "rx";
822 #address-cells = <1>; 822 #address-cells = <1>;
823 #size-cells = <0>; 823 #size-cells = <0>;
824 clocks = <&cmu CLK_SPI 824 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
825 clock-names = "spi", " 825 clock-names = "spi", "spi_busclk0";
826 samsung,spi-src-clk = 826 samsung,spi-src-clk = <0>;
827 pinctrl-names = "defau 827 pinctrl-names = "default";
828 pinctrl-0 = <&spi0_bus 828 pinctrl-0 = <&spi0_bus>;
829 fifo-depth = <256>; 829 fifo-depth = <256>;
830 status = "disabled"; 830 status = "disabled";
831 }; 831 };
832 832
833 spi_1: spi@13930000 { 833 spi_1: spi@13930000 {
834 compatible = "samsung, 834 compatible = "samsung,exynos4210-spi";
835 reg = <0x13930000 0x10 835 reg = <0x13930000 0x100>;
836 interrupts = <GIC_SPI 836 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
837 dmas = <&pdma1 7>, <&p 837 dmas = <&pdma1 7>, <&pdma1 6>;
838 dma-names = "tx", "rx" 838 dma-names = "tx", "rx";
839 #address-cells = <1>; 839 #address-cells = <1>;
840 #size-cells = <0>; 840 #size-cells = <0>;
841 clocks = <&cmu CLK_SPI 841 clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
842 clock-names = "spi", " 842 clock-names = "spi", "spi_busclk0";
843 samsung,spi-src-clk = 843 samsung,spi-src-clk = <0>;
844 pinctrl-names = "defau 844 pinctrl-names = "default";
845 pinctrl-0 = <&spi1_bus 845 pinctrl-0 = <&spi1_bus>;
846 fifo-depth = <64>; 846 fifo-depth = <64>;
847 status = "disabled"; 847 status = "disabled";
848 }; 848 };
849 849
850 i2s2: i2s@13970000 { 850 i2s2: i2s@13970000 {
851 compatible = "samsung, 851 compatible = "samsung,s3c6410-i2s";
852 reg = <0x13970000 0x10 852 reg = <0x13970000 0x100>;
853 interrupts = <GIC_SPI 853 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
854 clocks = <&cmu CLK_I2S 854 clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
855 clock-names = "iis", " 855 clock-names = "iis", "i2s_opclk0";
856 dmas = <&pdma0 14>, <& 856 dmas = <&pdma0 14>, <&pdma0 13>;
857 dma-names = "tx", "rx" 857 dma-names = "tx", "rx";
858 pinctrl-0 = <&i2s2_bus 858 pinctrl-0 = <&i2s2_bus>;
859 pinctrl-names = "defau 859 pinctrl-names = "default";
860 status = "disabled"; 860 status = "disabled";
861 }; 861 };
862 862
863 pwm: pwm@139d0000 { 863 pwm: pwm@139d0000 {
864 compatible = "samsung, 864 compatible = "samsung,exynos4210-pwm";
865 reg = <0x139d0000 0x10 865 reg = <0x139d0000 0x1000>;
866 interrupts = <GIC_SPI 866 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
867 <GIC_SPI 867 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
868 <GIC_SPI 868 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
869 <GIC_SPI 869 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
870 <GIC_SPI 870 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
871 #pwm-cells = <3>; 871 #pwm-cells = <3>;
872 status = "disabled"; 872 status = "disabled";
873 }; 873 };
874 874
875 ppmu_dmc0: ppmu@106a0000 { 875 ppmu_dmc0: ppmu@106a0000 {
876 compatible = "samsung, 876 compatible = "samsung,exynos-ppmu";
877 reg = <0x106a0000 0x20 877 reg = <0x106a0000 0x2000>;
878 status = "disabled"; 878 status = "disabled";
879 }; 879 };
880 880
881 ppmu_dmc1: ppmu@106b0000 { 881 ppmu_dmc1: ppmu@106b0000 {
882 compatible = "samsung, 882 compatible = "samsung,exynos-ppmu";
883 reg = <0x106b0000 0x20 883 reg = <0x106b0000 0x2000>;
884 status = "disabled"; 884 status = "disabled";
885 }; 885 };
886 886
887 ppmu_cpu: ppmu@106c0000 { 887 ppmu_cpu: ppmu@106c0000 {
888 compatible = "samsung, 888 compatible = "samsung,exynos-ppmu";
889 reg = <0x106c0000 0x20 889 reg = <0x106c0000 0x2000>;
890 status = "disabled"; 890 status = "disabled";
891 }; 891 };
892 892
893 ppmu_rightbus: ppmu@112a0000 { 893 ppmu_rightbus: ppmu@112a0000 {
894 compatible = "samsung, 894 compatible = "samsung,exynos-ppmu";
895 reg = <0x112a0000 0x20 895 reg = <0x112a0000 0x2000>;
896 clocks = <&cmu CLK_PPM 896 clocks = <&cmu CLK_PPMURIGHT>;
897 clock-names = "ppmu"; 897 clock-names = "ppmu";
898 status = "disabled"; 898 status = "disabled";
899 }; 899 };
900 900
901 ppmu_leftbus: ppmu@116a0000 { 901 ppmu_leftbus: ppmu@116a0000 {
902 compatible = "samsung, 902 compatible = "samsung,exynos-ppmu";
903 reg = <0x116a0000 0x20 903 reg = <0x116a0000 0x2000>;
904 clocks = <&cmu CLK_PPM 904 clocks = <&cmu CLK_PPMULEFT>;
905 clock-names = "ppmu"; 905 clock-names = "ppmu";
906 status = "disabled"; 906 status = "disabled";
907 }; 907 };
908 908
909 ppmu_camif: ppmu@11ac0000 { 909 ppmu_camif: ppmu@11ac0000 {
910 compatible = "samsung, 910 compatible = "samsung,exynos-ppmu";
911 reg = <0x11ac0000 0x20 911 reg = <0x11ac0000 0x2000>;
912 clocks = <&cmu CLK_PPM 912 clocks = <&cmu CLK_PPMUCAMIF>;
913 clock-names = "ppmu"; 913 clock-names = "ppmu";
914 status = "disabled"; 914 status = "disabled";
915 }; 915 };
916 916
917 ppmu_lcd0: ppmu@11e40000 { 917 ppmu_lcd0: ppmu@11e40000 {
918 compatible = "samsung, 918 compatible = "samsung,exynos-ppmu";
919 reg = <0x11e40000 0x20 919 reg = <0x11e40000 0x2000>;
920 clocks = <&cmu CLK_PPM 920 clocks = <&cmu CLK_PPMULCD0>;
921 clock-names = "ppmu"; 921 clock-names = "ppmu";
922 status = "disabled"; 922 status = "disabled";
923 }; 923 };
924 924
925 ppmu_fsys: ppmu@12630000 { 925 ppmu_fsys: ppmu@12630000 {
926 compatible = "samsung, 926 compatible = "samsung,exynos-ppmu";
927 reg = <0x12630000 0x20 927 reg = <0x12630000 0x2000>;
928 clocks = <&cmu CLK_PPM 928 clocks = <&cmu CLK_PPMUFILE>;
929 clock-names = "ppmu"; 929 clock-names = "ppmu";
930 status = "disabled"; 930 status = "disabled";
931 }; 931 };
932 932
933 ppmu_g3d: ppmu@13220000 { 933 ppmu_g3d: ppmu@13220000 {
934 compatible = "samsung, 934 compatible = "samsung,exynos-ppmu";
935 reg = <0x13220000 0x20 935 reg = <0x13220000 0x2000>;
936 clocks = <&cmu CLK_PPM 936 clocks = <&cmu CLK_PPMUG3D>;
937 clock-names = "ppmu"; 937 clock-names = "ppmu";
938 status = "disabled"; 938 status = "disabled";
939 }; 939 };
940 940
941 ppmu_mfc: ppmu@13660000 { 941 ppmu_mfc: ppmu@13660000 {
942 compatible = "samsung, 942 compatible = "samsung,exynos-ppmu";
943 reg = <0x13660000 0x20 943 reg = <0x13660000 0x2000>;
944 clocks = <&cmu CLK_PPM 944 clocks = <&cmu CLK_PPMUMFC_L>;
945 clock-names = "ppmu"; 945 clock-names = "ppmu";
946 status = "disabled"; 946 status = "disabled";
947 }; 947 };
948 }; 948 };
949 }; 949 };
950 950
951 #include "exynos3250-pinctrl.dtsi" 951 #include "exynos3250-pinctrl.dtsi"
952 #include "exynos-syscon-restart.dtsi" 952 #include "exynos-syscon-restart.dtsi"
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