1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Samsung's Exynos3250 SoC device tree source
4 *
5 * Copyright (c) 2014 Samsung Electronics Co.,
6 * http://www.samsung.com
7 *
8 * Samsung's Exynos3250 SoC device nodes are l
9 * based board files can include this file and
10 * bindings.
11 *
12 * Note: This file does not include device nod
13 * Exynos3250 SoC. As device tree coverage for
14 * nodes can be added to this file.
15 */
16
17 #include "exynos4-cpu-thermal.dtsi"
18 #include <dt-bindings/clock/exynos3250.h>
19 #include <dt-bindings/interrupt-controller/arm
20 #include <dt-bindings/interrupt-controller/irq
21
22 / {
23 compatible = "samsung,exynos3250";
24 interrupt-parent = <&gic>;
25 #address-cells = <1>;
26 #size-cells = <1>;
27
28 aliases {
29 pinctrl0 = &pinctrl_0;
30 pinctrl1 = &pinctrl_1;
31 spi0 = &spi_0;
32 spi1 = &spi_1;
33 i2c0 = &i2c_0;
34 i2c1 = &i2c_1;
35 i2c2 = &i2c_2;
36 i2c3 = &i2c_3;
37 i2c4 = &i2c_4;
38 i2c5 = &i2c_5;
39 i2c6 = &i2c_6;
40 i2c7 = &i2c_7;
41 serial0 = &serial_0;
42 serial1 = &serial_1;
43 serial2 = &serial_2;
44 };
45
46 bus_dmc: bus-dmc {
47 compatible = "samsung,exynos-b
48 clocks = <&cmu_dmc CLK_DIV_DMC
49 clock-names = "bus";
50 operating-points-v2 = <&bus_dm
51 status = "disabled";
52
53 bus_dmc_opp_table: opp-table {
54 compatible = "operatin
55
56 opp-50000000 {
57 opp-hz = /bits
58 opp-microvolt
59 };
60 opp-100000000 {
61 opp-hz = /bits
62 opp-microvolt
63 };
64 opp-134000000 {
65 opp-hz = /bits
66 opp-microvolt
67 };
68 opp-200000000 {
69 opp-hz = /bits
70 opp-microvolt
71 };
72 opp-400000000 {
73 opp-hz = /bits
74 opp-microvolt
75 };
76 };
77 };
78
79 bus_fsys: bus-fsys {
80 compatible = "samsung,exynos-b
81 clocks = <&cmu CLK_DIV_ACLK_20
82 clock-names = "bus";
83 operating-points-v2 = <&bus_le
84 status = "disabled";
85 };
86
87 bus_isp: bus-isp {
88 compatible = "samsung,exynos-b
89 clocks = <&cmu CLK_DIV_ACLK_26
90 clock-names = "bus";
91 operating-points-v2 = <&bus_is
92 status = "disabled";
93
94 bus_isp_opp_table: opp-table {
95 compatible = "operatin
96
97 opp-50000000 {
98 opp-hz = /bits
99 };
100 opp-80000000 {
101 opp-hz = /bits
102 };
103 opp-100000000 {
104 opp-hz = /bits
105 };
106 opp-200000000 {
107 opp-hz = /bits
108 };
109 opp-300000000 {
110 opp-hz = /bits
111 };
112 };
113 };
114
115 bus_lcd0: bus-lcd0 {
116 compatible = "samsung,exynos-b
117 clocks = <&cmu CLK_DIV_ACLK_16
118 clock-names = "bus";
119 operating-points-v2 = <&bus_le
120 status = "disabled";
121 };
122
123 bus_leftbus: bus-leftbus {
124 compatible = "samsung,exynos-b
125 clocks = <&cmu CLK_DIV_GDL>;
126 clock-names = "bus";
127 operating-points-v2 = <&bus_le
128 status = "disabled";
129 };
130
131 bus_mcuisp: bus-mcuisp {
132 compatible = "samsung,exynos-b
133 clocks = <&cmu CLK_DIV_ACLK_40
134 clock-names = "bus";
135 operating-points-v2 = <&bus_mc
136 status = "disabled";
137
138 bus_mcuisp_opp_table: opp-tabl
139 compatible = "operatin
140
141 opp-50000000 {
142 opp-hz = /bits
143 };
144 opp-80000000 {
145 opp-hz = /bits
146 };
147 opp-100000000 {
148 opp-hz = /bits
149 };
150 opp-200000000 {
151 opp-hz = /bits
152 };
153 opp-400000000 {
154 opp-hz = /bits
155 };
156 };
157 };
158
159 bus_mfc: bus-mfc {
160 compatible = "samsung,exynos-b
161 clocks = <&cmu CLK_SCLK_MFC>;
162 clock-names = "bus";
163 operating-points-v2 = <&bus_le
164 status = "disabled";
165 };
166
167 bus_peril: bus-peril {
168 compatible = "samsung,exynos-b
169 clocks = <&cmu CLK_DIV_ACLK_10
170 clock-names = "bus";
171 operating-points-v2 = <&bus_pe
172 status = "disabled";
173
174 bus_peril_opp_table: opp-table
175 compatible = "operatin
176
177 opp-50000000 {
178 opp-hz = /bits
179 };
180 opp-80000000 {
181 opp-hz = /bits
182 };
183 opp-100000000 {
184 opp-hz = /bits
185 };
186 };
187 };
188
189 bus_rightbus: bus-rightbus {
190 compatible = "samsung,exynos-b
191 clocks = <&cmu CLK_DIV_GDR>;
192 clock-names = "bus";
193 operating-points-v2 = <&bus_le
194 status = "disabled";
195 };
196
197 cpus {
198 #address-cells = <1>;
199 #size-cells = <0>;
200
201 cpu-map {
202 cluster0 {
203 core0 {
204 cpu =
205 };
206 core1 {
207 cpu =
208 };
209 };
210 };
211
212 cpu0: cpu@0 {
213 device_type = "cpu";
214 compatible = "arm,cort
215 reg = <0>;
216 clock-frequency = <100
217 clocks = <&cmu CLK_ARM
218 clock-names = "cpu";
219 #cooling-cells = <2>;
220
221 operating-points = <
222 1000000 115000
223 900000 111250
224 800000 107500
225 700000 103750
226 600000 100000
227 500000 962500
228 400000 925000
229 300000 887500
230 200000 850000
231 100000 850000
232 >;
233 };
234
235 cpu1: cpu@1 {
236 device_type = "cpu";
237 compatible = "arm,cort
238 reg = <1>;
239 clock-frequency = <100
240 clocks = <&cmu CLK_ARM
241 clock-names = "cpu";
242 #cooling-cells = <2>;
243
244 operating-points = <
245 1000000 115000
246 900000 111250
247 800000 107500
248 700000 103750
249 600000 100000
250 500000 962500
251 400000 925000
252 300000 887500
253 200000 850000
254 100000 850000
255 >;
256 };
257 };
258
259 xusbxti: clock-0 {
260 compatible = "fixed-clock";
261 clock-frequency = <0>;
262 #clock-cells = <0>;
263 clock-output-names = "xusbxti"
264 };
265
266 xxti: clock-1 {
267 compatible = "fixed-clock";
268 clock-frequency = <0>;
269 #clock-cells = <0>;
270 clock-output-names = "xxti";
271 };
272
273 xtcxo: clock-2 {
274 compatible = "fixed-clock";
275 clock-frequency = <0>;
276 #clock-cells = <0>;
277 clock-output-names = "xtcxo";
278 };
279
280 bus_leftbus_opp_table: opp-table-0 {
281 compatible = "operating-points
282
283 opp-50000000 {
284 opp-hz = /bits/ 64 <50
285 opp-microvolt = <90000
286 };
287 opp-80000000 {
288 opp-hz = /bits/ 64 <80
289 opp-microvolt = <90000
290 };
291 opp-100000000 {
292 opp-hz = /bits/ 64 <10
293 opp-microvolt = <10000
294 };
295 opp-134000000 {
296 opp-hz = /bits/ 64 <13
297 opp-microvolt = <10000
298 };
299 opp-200000000 {
300 opp-hz = /bits/ 64 <20
301 opp-microvolt = <10000
302 };
303 };
304
305 pmu {
306 compatible = "arm,cortex-a7-pm
307 interrupts = <GIC_SPI 18 IRQ_T
308 <GIC_SPI 19 IRQ_T
309 };
310
311 soc: soc {
312 compatible = "simple-bus";
313 #address-cells = <1>;
314 #size-cells = <1>;
315 ranges;
316
317 sram@2020000 {
318 compatible = "mmio-sra
319 reg = <0x02020000 0x40
320 #address-cells = <1>;
321 #size-cells = <1>;
322 ranges = <0 0x02020000
323
324 smp-sram@0 {
325 compatible = "
326 reg = <0x0 0x1
327 };
328
329 smp-sram@3f000 {
330 compatible = "
331 reg = <0x3f000
332 };
333 };
334
335 chipid@10000000 {
336 compatible = "samsung,
337 reg = <0x10000000 0x10
338 };
339
340 sys_reg: syscon@10010000 {
341 compatible = "samsung,
342 reg = <0x10010000 0x40
343 };
344
345 pmu_system_controller: system-
346 compatible = "samsung,
347 reg = <0x10020000 0x40
348 interrupt-controller;
349 #interrupt-cells = <3>
350 interrupt-parent = <&g
351 clock-names = "clkout8
352 clocks = <&cmu CLK_FIN
353 #clock-cells = <1>;
354
355 mipi_phy: mipi-phy {
356 compatible = "
357 #phy-cells = <
358 };
359 };
360
361 pd_cam: power-domain@10023c00
362 compatible = "samsung,
363 reg = <0x10023c00 0x20
364 #power-domain-cells =
365 label = "CAM";
366 };
367
368 pd_mfc: power-domain@10023c40
369 compatible = "samsung,
370 reg = <0x10023c40 0x20
371 #power-domain-cells =
372 label = "MFC";
373 };
374
375 pd_g3d: power-domain@10023c60
376 compatible = "samsung,
377 reg = <0x10023c60 0x20
378 #power-domain-cells =
379 label = "G3D";
380 };
381
382 pd_lcd0: power-domain@10023c80
383 compatible = "samsung,
384 reg = <0x10023c80 0x20
385 #power-domain-cells =
386 label = "LCD0";
387 };
388
389 pd_isp: power-domain@10023ca0
390 compatible = "samsung,
391 reg = <0x10023ca0 0x20
392 #power-domain-cells =
393 label = "ISP";
394 };
395
396 cmu: clock-controller@10030000
397 compatible = "samsung,
398 reg = <0x10030000 0x20
399 #clock-cells = <1>;
400 assigned-clocks = <&cm
401 <&cm
402 assigned-clock-parents
403
404 };
405
406 cmu_dmc: clock-controller@105c
407 compatible = "samsung,
408 reg = <0x105c0000 0x20
409 #clock-cells = <1>;
410 };
411
412 rtc: rtc@10070000 {
413 compatible = "samsung,
414 reg = <0x10070000 0x10
415 interrupts = <GIC_SPI
416 <GIC_SPI
417 interrupt-parent = <&p
418 status = "disabled";
419 };
420
421 tmu: tmu@100c0000 {
422 compatible = "samsung,
423 reg = <0x100c0000 0x10
424 interrupts = <GIC_SPI
425 clocks = <&cmu CLK_TMU
426 clock-names = "tmu_apb
427 #thermal-sensor-cells
428 status = "disabled";
429 };
430
431 gic: interrupt-controller@1048
432 compatible = "arm,cort
433 #interrupt-cells = <3>
434 interrupt-controller;
435 reg = <0x10481000 0x10
436 <0x10482000 0x20
437 <0x10484000 0x20
438 <0x10486000 0x20
439 interrupts = <GIC_PPI
440 (GIC_C
441 };
442
443 timer@10050000 {
444 compatible = "samsung,
445 "samsung,
446 reg = <0x10050000 0x80
447 interrupts = <GIC_SPI
448 <GIC_SPI
449 <GIC_SPI
450 <GIC_SPI
451 <GIC_SPI
452 <GIC_SPI
453 <GIC_SPI
454 <GIC_SPI
455 clocks = <&cmu CLK_FIN
456 clock-names = "fin_pll
457 };
458
459 pinctrl_1: pinctrl@11000000 {
460 compatible = "samsung,
461 reg = <0x11000000 0x10
462 interrupts = <GIC_SPI
463
464 wakeup-interrupt-contr
465 compatible = "
466 interrupts = <
467 };
468 };
469
470 pinctrl_0: pinctrl@11400000 {
471 compatible = "samsung,
472 reg = <0x11400000 0x10
473 interrupts = <GIC_SPI
474 };
475
476 jpeg: codec@11830000 {
477 compatible = "samsung,
478 reg = <0x11830000 0x10
479 interrupts = <GIC_SPI
480 clocks = <&cmu CLK_JPE
481 clock-names = "jpeg",
482 power-domains = <&pd_c
483 assigned-clocks = <&cm
484 assigned-clock-rates =
485 assigned-clock-parents
486 iommus = <&sysmmu_jpeg
487 status = "disabled";
488 };
489
490 sysmmu_jpeg: sysmmu@11a60000 {
491 compatible = "samsung,
492 reg = <0x11a60000 0x10
493 interrupts = <GIC_SPI
494 clock-names = "sysmmu"
495 clocks = <&cmu CLK_SMM
496 power-domains = <&pd_c
497 #iommu-cells = <0>;
498 };
499
500 fimd: fimd@11c00000 {
501 compatible = "samsung,
502 reg = <0x11c00000 0x30
503 interrupt-names = "fif
504 interrupts = <GIC_SPI
505 <GIC_SPI
506 <GIC_SPI
507 clocks = <&cmu CLK_SCL
508 clock-names = "sclk_fi
509 power-domains = <&pd_l
510 iommus = <&sysmmu_fimd
511 samsung,sysreg = <&sys
512 status = "disabled";
513 };
514
515 dsi_0: dsi@11c80000 {
516 compatible = "samsung,
517 reg = <0x11c80000 0x10
518 interrupts = <GIC_SPI
519 samsung,phy-type = <0>
520 power-domains = <&pd_l
521 phys = <&mipi_phy 1>;
522 phy-names = "dsim";
523 clocks = <&cmu CLK_DSI
524 clock-names = "bus_clk
525 #address-cells = <1>;
526 #size-cells = <0>;
527 status = "disabled";
528 };
529
530 sysmmu_fimd0: sysmmu@11e20000
531 compatible = "samsung,
532 reg = <0x11e20000 0x10
533 interrupts = <GIC_SPI
534 clock-names = "sysmmu"
535 clocks = <&cmu CLK_SMM
536 power-domains = <&pd_l
537 #iommu-cells = <0>;
538 };
539
540 hsotg: usb@12480000 {
541 compatible = "samsung,
542 reg = <0x12480000 0x20
543 interrupts = <GIC_SPI
544 clocks = <&cmu CLK_USB
545 clock-names = "otg";
546 phys = <&exynos_usbphy
547 phy-names = "usb2-phy"
548 status = "disabled";
549 };
550
551 mshc_0: mmc@12510000 {
552 compatible = "samsung,
553 reg = <0x12510000 0x10
554 interrupts = <GIC_SPI
555 clocks = <&cmu CLK_SDM
556 clock-names = "biu", "
557 fifo-depth = <0x80>;
558 #address-cells = <1>;
559 #size-cells = <0>;
560 status = "disabled";
561 };
562
563 mshc_1: mmc@12520000 {
564 compatible = "samsung,
565 reg = <0x12520000 0x10
566 interrupts = <GIC_SPI
567 clocks = <&cmu CLK_SDM
568 clock-names = "biu", "
569 fifo-depth = <0x80>;
570 #address-cells = <1>;
571 #size-cells = <0>;
572 status = "disabled";
573 };
574
575 mshc_2: mmc@12530000 {
576 compatible = "samsung,
577 reg = <0x12530000 0x10
578 interrupts = <GIC_SPI
579 clocks = <&cmu CLK_SDM
580 clock-names = "biu", "
581 fifo-depth = <0x80>;
582 #address-cells = <1>;
583 #size-cells = <0>;
584 status = "disabled";
585 };
586
587 exynos_usbphy: usb-phy@125b000
588 compatible = "samsung,
589 reg = <0x125b0000 0x10
590 samsung,pmureg-phandle
591 clocks = <&cmu CLK_USB
592 clock-names = "phy", "
593 #phy-cells = <1>;
594 status = "disabled";
595 };
596
597 pdma0: dma-controller@12680000
598 compatible = "arm,pl33
599 reg = <0x12680000 0x10
600 interrupts = <GIC_SPI
601 clocks = <&cmu CLK_PDM
602 clock-names = "apb_pcl
603 #dma-cells = <1>;
604 };
605
606 pdma1: dma-controller@12690000
607 compatible = "arm,pl33
608 reg = <0x12690000 0x10
609 interrupts = <GIC_SPI
610 clocks = <&cmu CLK_PDM
611 clock-names = "apb_pcl
612 #dma-cells = <1>;
613 };
614
615 adc: adc@126c0000 {
616 compatible = "samsung,
617 reg = <0x126c0000 0x10
618 interrupts = <GIC_SPI
619 clock-names = "adc", "
620 clocks = <&cmu CLK_TSA
621 #io-channel-cells = <1
622 samsung,syscon-phandle
623 status = "disabled";
624 };
625
626 gpu: gpu@13000000 {
627 compatible = "samsung,
628 reg = <0x13000000 0x10
629 interrupts = <GIC_SPI
630 <GIC_SPI
631 <GIC_SPI
632 <GIC_SPI
633 <GIC_SPI
634 <GIC_SPI
635 <GIC_SPI
636 <GIC_SPI
637 <GIC_SPI
638 <GIC_SPI
639 <GIC_SPI
640 interrupt-names = "gp"
641 "gpm
642 "pp0
643 "ppm
644 "pp1
645 "ppm
646 "pp2
647 "ppm
648 "pp3
649 "ppm
650 "pmu
651 clocks = <&cmu CLK_G3D
652 <&cmu CLK_SCL
653 clock-names = "bus", "
654 power-domains = <&pd_g
655 status = "disabled";
656 /* TODO: operating poi
657 };
658
659 mfc: codec@13400000 {
660 compatible = "samsung,
661 reg = <0x13400000 0x10
662 interrupts = <GIC_SPI
663 clock-names = "mfc", "
664 clocks = <&cmu CLK_MFC
665 power-domains = <&pd_m
666 iommus = <&sysmmu_mfc>
667 };
668
669 sysmmu_mfc: sysmmu@13620000 {
670 compatible = "samsung,
671 reg = <0x13620000 0x10
672 interrupts = <GIC_SPI
673 clock-names = "sysmmu"
674 clocks = <&cmu CLK_SMM
675 power-domains = <&pd_m
676 #iommu-cells = <0>;
677 };
678
679 serial_0: serial@13800000 {
680 compatible = "samsung,
681 reg = <0x13800000 0x10
682 interrupts = <GIC_SPI
683 clocks = <&cmu CLK_UAR
684 clock-names = "uart",
685 pinctrl-names = "defau
686 pinctrl-0 = <&uart0_da
687 status = "disabled";
688 };
689
690 serial_1: serial@13810000 {
691 compatible = "samsung,
692 reg = <0x13810000 0x10
693 interrupts = <GIC_SPI
694 clocks = <&cmu CLK_UAR
695 clock-names = "uart",
696 pinctrl-names = "defau
697 pinctrl-0 = <&uart1_da
698 status = "disabled";
699 };
700
701 serial_2: serial@13820000 {
702 compatible = "samsung,
703 reg = <0x13820000 0x10
704 interrupts = <GIC_SPI
705 clocks = <&cmu CLK_UAR
706 clock-names = "uart",
707 pinctrl-names = "defau
708 pinctrl-0 = <&uart2_da
709 status = "disabled";
710 };
711
712 i2c_0: i2c@13860000 {
713 #address-cells = <1>;
714 #size-cells = <0>;
715 compatible = "samsung,
716 reg = <0x13860000 0x10
717 interrupts = <GIC_SPI
718 clocks = <&cmu CLK_I2C
719 clock-names = "i2c";
720 pinctrl-names = "defau
721 pinctrl-0 = <&i2c0_bus
722 status = "disabled";
723 };
724
725 i2c_1: i2c@13870000 {
726 #address-cells = <1>;
727 #size-cells = <0>;
728 compatible = "samsung,
729 reg = <0x13870000 0x10
730 interrupts = <GIC_SPI
731 clocks = <&cmu CLK_I2C
732 clock-names = "i2c";
733 pinctrl-names = "defau
734 pinctrl-0 = <&i2c1_bus
735 status = "disabled";
736 };
737
738 i2c_2: i2c@13880000 {
739 #address-cells = <1>;
740 #size-cells = <0>;
741 compatible = "samsung,
742 reg = <0x13880000 0x10
743 interrupts = <GIC_SPI
744 clocks = <&cmu CLK_I2C
745 clock-names = "i2c";
746 pinctrl-names = "defau
747 pinctrl-0 = <&i2c2_bus
748 status = "disabled";
749 };
750
751 i2c_3: i2c@13890000 {
752 #address-cells = <1>;
753 #size-cells = <0>;
754 compatible = "samsung,
755 reg = <0x13890000 0x10
756 interrupts = <GIC_SPI
757 clocks = <&cmu CLK_I2C
758 clock-names = "i2c";
759 pinctrl-names = "defau
760 pinctrl-0 = <&i2c3_bus
761 status = "disabled";
762 };
763
764 i2c_4: i2c@138a0000 {
765 #address-cells = <1>;
766 #size-cells = <0>;
767 compatible = "samsung,
768 reg = <0x138a0000 0x10
769 interrupts = <GIC_SPI
770 clocks = <&cmu CLK_I2C
771 clock-names = "i2c";
772 pinctrl-names = "defau
773 pinctrl-0 = <&i2c4_bus
774 status = "disabled";
775 };
776
777 i2c_5: i2c@138b0000 {
778 #address-cells = <1>;
779 #size-cells = <0>;
780 compatible = "samsung,
781 reg = <0x138b0000 0x10
782 interrupts = <GIC_SPI
783 clocks = <&cmu CLK_I2C
784 clock-names = "i2c";
785 pinctrl-names = "defau
786 pinctrl-0 = <&i2c5_bus
787 status = "disabled";
788 };
789
790 i2c_6: i2c@138c0000 {
791 #address-cells = <1>;
792 #size-cells = <0>;
793 compatible = "samsung,
794 reg = <0x138c0000 0x10
795 interrupts = <GIC_SPI
796 clocks = <&cmu CLK_I2C
797 clock-names = "i2c";
798 pinctrl-names = "defau
799 pinctrl-0 = <&i2c6_bus
800 status = "disabled";
801 };
802
803 i2c_7: i2c@138d0000 {
804 #address-cells = <1>;
805 #size-cells = <0>;
806 compatible = "samsung,
807 reg = <0x138d0000 0x10
808 interrupts = <GIC_SPI
809 clocks = <&cmu CLK_I2C
810 clock-names = "i2c";
811 pinctrl-names = "defau
812 pinctrl-0 = <&i2c7_bus
813 status = "disabled";
814 };
815
816 spi_0: spi@13920000 {
817 compatible = "samsung,
818 reg = <0x13920000 0x10
819 interrupts = <GIC_SPI
820 dmas = <&pdma0 7>, <&p
821 dma-names = "tx", "rx"
822 #address-cells = <1>;
823 #size-cells = <0>;
824 clocks = <&cmu CLK_SPI
825 clock-names = "spi", "
826 samsung,spi-src-clk =
827 pinctrl-names = "defau
828 pinctrl-0 = <&spi0_bus
829 fifo-depth = <256>;
830 status = "disabled";
831 };
832
833 spi_1: spi@13930000 {
834 compatible = "samsung,
835 reg = <0x13930000 0x10
836 interrupts = <GIC_SPI
837 dmas = <&pdma1 7>, <&p
838 dma-names = "tx", "rx"
839 #address-cells = <1>;
840 #size-cells = <0>;
841 clocks = <&cmu CLK_SPI
842 clock-names = "spi", "
843 samsung,spi-src-clk =
844 pinctrl-names = "defau
845 pinctrl-0 = <&spi1_bus
846 fifo-depth = <64>;
847 status = "disabled";
848 };
849
850 i2s2: i2s@13970000 {
851 compatible = "samsung,
852 reg = <0x13970000 0x10
853 interrupts = <GIC_SPI
854 clocks = <&cmu CLK_I2S
855 clock-names = "iis", "
856 dmas = <&pdma0 14>, <&
857 dma-names = "tx", "rx"
858 pinctrl-0 = <&i2s2_bus
859 pinctrl-names = "defau
860 status = "disabled";
861 };
862
863 pwm: pwm@139d0000 {
864 compatible = "samsung,
865 reg = <0x139d0000 0x10
866 interrupts = <GIC_SPI
867 <GIC_SPI
868 <GIC_SPI
869 <GIC_SPI
870 <GIC_SPI
871 #pwm-cells = <3>;
872 status = "disabled";
873 };
874
875 ppmu_dmc0: ppmu@106a0000 {
876 compatible = "samsung,
877 reg = <0x106a0000 0x20
878 status = "disabled";
879 };
880
881 ppmu_dmc1: ppmu@106b0000 {
882 compatible = "samsung,
883 reg = <0x106b0000 0x20
884 status = "disabled";
885 };
886
887 ppmu_cpu: ppmu@106c0000 {
888 compatible = "samsung,
889 reg = <0x106c0000 0x20
890 status = "disabled";
891 };
892
893 ppmu_rightbus: ppmu@112a0000 {
894 compatible = "samsung,
895 reg = <0x112a0000 0x20
896 clocks = <&cmu CLK_PPM
897 clock-names = "ppmu";
898 status = "disabled";
899 };
900
901 ppmu_leftbus: ppmu@116a0000 {
902 compatible = "samsung,
903 reg = <0x116a0000 0x20
904 clocks = <&cmu CLK_PPM
905 clock-names = "ppmu";
906 status = "disabled";
907 };
908
909 ppmu_camif: ppmu@11ac0000 {
910 compatible = "samsung,
911 reg = <0x11ac0000 0x20
912 clocks = <&cmu CLK_PPM
913 clock-names = "ppmu";
914 status = "disabled";
915 };
916
917 ppmu_lcd0: ppmu@11e40000 {
918 compatible = "samsung,
919 reg = <0x11e40000 0x20
920 clocks = <&cmu CLK_PPM
921 clock-names = "ppmu";
922 status = "disabled";
923 };
924
925 ppmu_fsys: ppmu@12630000 {
926 compatible = "samsung,
927 reg = <0x12630000 0x20
928 clocks = <&cmu CLK_PPM
929 clock-names = "ppmu";
930 status = "disabled";
931 };
932
933 ppmu_g3d: ppmu@13220000 {
934 compatible = "samsung,
935 reg = <0x13220000 0x20
936 clocks = <&cmu CLK_PPM
937 clock-names = "ppmu";
938 status = "disabled";
939 };
940
941 ppmu_mfc: ppmu@13660000 {
942 compatible = "samsung,
943 reg = <0x13660000 0x20
944 clocks = <&cmu CLK_PPM
945 clock-names = "ppmu";
946 status = "disabled";
947 };
948 };
949 };
950
951 #include "exynos3250-pinctrl.dtsi"
952 #include "exynos-syscon-restart.dtsi"
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