1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Samsung's Exynos4212 SoC device tree source 3 * Samsung's Exynos4212 SoC device tree source
4 * 4 *
5 * Copyright (c) 2012 Samsung Electronics Co., 5 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com 6 * http://www.samsung.com
7 * 7 *
8 * Samsung's Exynos4212 SoC device nodes are l 8 * Samsung's Exynos4212 SoC device nodes are listed in this file. Exynos4212
9 * based board files can include this file and 9 * based board files can include this file and provide values for board specific
10 * bindings. 10 * bindings.
11 * 11 *
12 * Note: This file does not include device nod 12 * Note: This file does not include device nodes for all the controllers in
13 * Exynos4212 SoC. As device tree coverage for 13 * Exynos4212 SoC. As device tree coverage for Exynos4212 increases, additional
14 * nodes can be added to this file. 14 * nodes can be added to this file.
15 */ 15 */
16 16
17 #include "exynos4x12.dtsi" 17 #include "exynos4x12.dtsi"
18 18
19 / { 19 / {
20 compatible = "samsung,exynos4212", "sa 20 compatible = "samsung,exynos4212", "samsung,exynos4";
21 21
22 cpus { 22 cpus {
23 #address-cells = <1>; 23 #address-cells = <1>;
24 #size-cells = <0>; 24 #size-cells = <0>;
25 25
26 cpu-map { 26 cpu-map {
27 cluster0 { 27 cluster0 {
28 core0 { 28 core0 {
29 cpu = 29 cpu = <&cpu0>;
30 }; 30 };
31 core1 { 31 core1 {
32 cpu = 32 cpu = <&cpu1>;
33 }; 33 };
34 }; 34 };
35 }; 35 };
36 36
37 cpu0: cpu@a00 { 37 cpu0: cpu@a00 {
38 device_type = "cpu"; 38 device_type = "cpu";
39 compatible = "arm,cort 39 compatible = "arm,cortex-a9";
40 reg = <0xa00>; 40 reg = <0xa00>;
41 clocks = <&clock CLK_A 41 clocks = <&clock CLK_ARM_CLK>;
42 clock-names = "cpu"; 42 clock-names = "cpu";
43 operating-points-v2 = 43 operating-points-v2 = <&cpu0_opp_table>;
44 #cooling-cells = <2>; 44 #cooling-cells = <2>; /* min followed by max */
45 }; 45 };
46 46
47 cpu1: cpu@a01 { 47 cpu1: cpu@a01 {
48 device_type = "cpu"; 48 device_type = "cpu";
49 compatible = "arm,cort 49 compatible = "arm,cortex-a9";
50 reg = <0xa01>; 50 reg = <0xa01>;
51 clocks = <&clock CLK_A 51 clocks = <&clock CLK_ARM_CLK>;
52 clock-names = "cpu"; 52 clock-names = "cpu";
53 operating-points-v2 = 53 operating-points-v2 = <&cpu0_opp_table>;
54 #cooling-cells = <2>; 54 #cooling-cells = <2>; /* min followed by max */
55 }; 55 };
56 }; 56 };
57 57
58 cpu0_opp_table: opp-table-0 { 58 cpu0_opp_table: opp-table-0 {
59 compatible = "operating-points 59 compatible = "operating-points-v2";
60 opp-shared; 60 opp-shared;
61 61
62 opp-200000000 { 62 opp-200000000 {
63 opp-hz = /bits/ 64 <20 63 opp-hz = /bits/ 64 <200000000>;
64 opp-microvolt = <90000 64 opp-microvolt = <900000>;
65 clock-latency-ns = <20 65 clock-latency-ns = <200000>;
66 }; 66 };
67 opp-300000000 { 67 opp-300000000 {
68 opp-hz = /bits/ 64 <30 68 opp-hz = /bits/ 64 <300000000>;
69 opp-microvolt = <90000 69 opp-microvolt = <900000>;
70 clock-latency-ns = <20 70 clock-latency-ns = <200000>;
71 }; 71 };
72 opp-400000000 { 72 opp-400000000 {
73 opp-hz = /bits/ 64 <40 73 opp-hz = /bits/ 64 <400000000>;
74 opp-microvolt = <92500 74 opp-microvolt = <925000>;
75 clock-latency-ns = <20 75 clock-latency-ns = <200000>;
76 }; 76 };
77 opp-500000000 { 77 opp-500000000 {
78 opp-hz = /bits/ 64 <50 78 opp-hz = /bits/ 64 <500000000>;
79 opp-microvolt = <95000 79 opp-microvolt = <950000>;
80 clock-latency-ns = <20 80 clock-latency-ns = <200000>;
81 }; 81 };
82 opp-600000000 { 82 opp-600000000 {
83 opp-hz = /bits/ 64 <60 83 opp-hz = /bits/ 64 <600000000>;
84 opp-microvolt = <97500 84 opp-microvolt = <975000>;
85 clock-latency-ns = <20 85 clock-latency-ns = <200000>;
86 }; 86 };
87 opp-700000000 { 87 opp-700000000 {
88 opp-hz = /bits/ 64 <70 88 opp-hz = /bits/ 64 <700000000>;
89 opp-microvolt = <98750 89 opp-microvolt = <987500>;
90 clock-latency-ns = <20 90 clock-latency-ns = <200000>;
91 }; 91 };
92 opp-800000000 { 92 opp-800000000 {
93 opp-hz = /bits/ 64 <80 93 opp-hz = /bits/ 64 <800000000>;
94 opp-microvolt = <10000 94 opp-microvolt = <1000000>;
95 clock-latency-ns = <20 95 clock-latency-ns = <200000>;
96 opp-suspend; 96 opp-suspend;
97 }; 97 };
98 opp-900000000 { 98 opp-900000000 {
99 opp-hz = /bits/ 64 <90 99 opp-hz = /bits/ 64 <900000000>;
100 opp-microvolt = <10375 100 opp-microvolt = <1037500>;
101 clock-latency-ns = <20 101 clock-latency-ns = <200000>;
102 }; 102 };
103 opp-1000000000 { 103 opp-1000000000 {
104 opp-hz = /bits/ 64 <10 104 opp-hz = /bits/ 64 <1000000000>;
105 opp-microvolt = <10875 105 opp-microvolt = <1087500>;
106 clock-latency-ns = <20 106 clock-latency-ns = <200000>;
107 }; 107 };
108 opp-1100000000 { 108 opp-1100000000 {
109 opp-hz = /bits/ 64 <11 109 opp-hz = /bits/ 64 <1100000000>;
110 opp-microvolt = <11375 110 opp-microvolt = <1137500>;
111 clock-latency-ns = <20 111 clock-latency-ns = <200000>;
112 }; 112 };
113 opp-1200000000 { 113 opp-1200000000 {
114 opp-hz = /bits/ 64 <12 114 opp-hz = /bits/ 64 <1200000000>;
115 opp-microvolt = <11875 115 opp-microvolt = <1187500>;
116 clock-latency-ns = <20 116 clock-latency-ns = <200000>;
117 }; 117 };
118 opp-1300000000 { 118 opp-1300000000 {
119 opp-hz = /bits/ 64 <13 119 opp-hz = /bits/ 64 <1300000000>;
120 opp-microvolt = <12500 120 opp-microvolt = <1250000>;
121 clock-latency-ns = <20 121 clock-latency-ns = <200000>;
122 }; 122 };
123 opp-1400000000 { 123 opp-1400000000 {
124 opp-hz = /bits/ 64 <14 124 opp-hz = /bits/ 64 <1400000000>;
125 opp-microvolt = <12875 125 opp-microvolt = <1287500>;
126 clock-latency-ns = <20 126 clock-latency-ns = <200000>;
127 }; 127 };
128 cpu0_opp_1500: opp-1500000000 128 cpu0_opp_1500: opp-1500000000 {
129 opp-hz = /bits/ 64 <15 129 opp-hz = /bits/ 64 <1500000000>;
130 opp-microvolt = <13500 130 opp-microvolt = <1350000>;
131 clock-latency-ns = <20 131 clock-latency-ns = <200000>;
132 turbo-mode; 132 turbo-mode;
133 }; 133 };
134 }; 134 };
135 }; 135 };
136 136
137 &clock { 137 &clock {
138 compatible = "samsung,exynos4212-clock 138 compatible = "samsung,exynos4212-clock";
139 }; 139 };
140 140
141 &combiner { 141 &combiner {
142 samsung,combiner-nr = <18>; 142 samsung,combiner-nr = <18>;
143 }; 143 };
144 144
145 &gic { 145 &gic {
146 cpu-offset = <0x8000>; 146 cpu-offset = <0x8000>;
147 }; 147 };
148 148
149 &pmu { 149 &pmu {
150 interrupts = <2 2>, <3 2>; 150 interrupts = <2 2>, <3 2>;
151 interrupt-affinity = <&cpu0>, <&cpu1>; 151 interrupt-affinity = <&cpu0>, <&cpu1>;
152 status = "okay"; 152 status = "okay";
153 }; 153 };
154 154
155 &pmu_system_controller { 155 &pmu_system_controller {
156 compatible = "samsung,exynos4212-pmu", 156 compatible = "samsung,exynos4212-pmu", "simple-mfd", "syscon";
157 }; 157 };
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