1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Samsung's Exynos4412 SoC device tree source 3 * Samsung's Exynos4412 SoC device tree source
4 * 4 *
5 * Copyright (c) 2012 Samsung Electronics Co., 5 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com 6 * http://www.samsung.com
7 * 7 *
8 * Samsung's Exynos4x12 SoC series device node 8 * Samsung's Exynos4x12 SoC series device nodes are listed in this file.
9 * Particular SoCs from Exynos4x12 series can 9 * Particular SoCs from Exynos4x12 series can include this file and provide
10 * values for SoCs specific bindings. 10 * values for SoCs specific bindings.
11 * 11 *
12 * Note: This file does not include device nod 12 * Note: This file does not include device nodes for all the controllers in
13 * Exynos4x12 SoCs. As device tree coverage fo 13 * Exynos4x12 SoCs. As device tree coverage for Exynos4x12 increases, additional
14 * nodes can be added to this file. 14 * nodes can be added to this file.
15 */ 15 */
16 16
17 #include "exynos4.dtsi" 17 #include "exynos4.dtsi"
18 18
19 #include "exynos4-cpu-thermal.dtsi" 19 #include "exynos4-cpu-thermal.dtsi"
20 20
21 / { 21 / {
22 aliases { 22 aliases {
23 pinctrl0 = &pinctrl_0; 23 pinctrl0 = &pinctrl_0;
24 pinctrl1 = &pinctrl_1; 24 pinctrl1 = &pinctrl_1;
25 pinctrl2 = &pinctrl_2; 25 pinctrl2 = &pinctrl_2;
26 pinctrl3 = &pinctrl_3; 26 pinctrl3 = &pinctrl_3;
27 fimc-lite0 = &fimc_lite_0; 27 fimc-lite0 = &fimc_lite_0;
28 fimc-lite1 = &fimc_lite_1; 28 fimc-lite1 = &fimc_lite_1;
29 }; 29 };
30 30
31 bus_acp: bus-acp { 31 bus_acp: bus-acp {
32 compatible = "samsung,exynos-b 32 compatible = "samsung,exynos-bus";
33 clocks = <&clock CLK_DIV_ACP>; 33 clocks = <&clock CLK_DIV_ACP>;
34 clock-names = "bus"; 34 clock-names = "bus";
35 operating-points-v2 = <&bus_ac 35 operating-points-v2 = <&bus_acp_opp_table>;
36 status = "disabled"; 36 status = "disabled";
37 37
38 bus_acp_opp_table: opp-table { 38 bus_acp_opp_table: opp-table {
39 compatible = "operatin 39 compatible = "operating-points-v2";
40 40
41 opp-100000000 { 41 opp-100000000 {
42 opp-hz = /bits 42 opp-hz = /bits/ 64 <100000000>;
43 }; 43 };
44 opp-134000000 { 44 opp-134000000 {
45 opp-hz = /bits 45 opp-hz = /bits/ 64 <134000000>;
46 }; 46 };
47 opp-160000000 { 47 opp-160000000 {
48 opp-hz = /bits 48 opp-hz = /bits/ 64 <160000000>;
49 }; 49 };
50 opp-267000000 { 50 opp-267000000 {
51 opp-hz = /bits 51 opp-hz = /bits/ 64 <267000000>;
52 }; 52 };
53 }; 53 };
54 }; 54 };
55 55
56 bus_c2c: bus-c2c { 56 bus_c2c: bus-c2c {
57 compatible = "samsung,exynos-b 57 compatible = "samsung,exynos-bus";
58 clocks = <&clock CLK_DIV_C2C>; 58 clocks = <&clock CLK_DIV_C2C>;
59 clock-names = "bus"; 59 clock-names = "bus";
60 operating-points-v2 = <&bus_dm 60 operating-points-v2 = <&bus_dmc_opp_table>;
61 status = "disabled"; 61 status = "disabled";
62 }; 62 };
63 63
64 bus_dmc: bus-dmc { 64 bus_dmc: bus-dmc {
65 compatible = "samsung,exynos-b 65 compatible = "samsung,exynos-bus";
66 clocks = <&clock CLK_DIV_DMC>; 66 clocks = <&clock CLK_DIV_DMC>;
67 clock-names = "bus"; 67 clock-names = "bus";
68 operating-points-v2 = <&bus_dm 68 operating-points-v2 = <&bus_dmc_opp_table>;
69 samsung,data-clock-ratio = <4> 69 samsung,data-clock-ratio = <4>;
70 #interconnect-cells = <0>; 70 #interconnect-cells = <0>;
71 status = "disabled"; 71 status = "disabled";
72 }; 72 };
73 73
74 bus_display: bus-display { 74 bus_display: bus-display {
75 compatible = "samsung,exynos-b 75 compatible = "samsung,exynos-bus";
76 clocks = <&clock CLK_ACLK160>; 76 clocks = <&clock CLK_ACLK160>;
77 clock-names = "bus"; 77 clock-names = "bus";
78 operating-points-v2 = <&bus_di 78 operating-points-v2 = <&bus_display_opp_table>;
79 interconnects = <&bus_leftbus 79 interconnects = <&bus_leftbus &bus_dmc>;
80 #interconnect-cells = <0>; 80 #interconnect-cells = <0>;
81 status = "disabled"; 81 status = "disabled";
82 82
83 bus_display_opp_table: opp-tab 83 bus_display_opp_table: opp-table {
84 compatible = "operatin 84 compatible = "operating-points-v2";
85 85
86 opp-160000000 { 86 opp-160000000 {
87 opp-hz = /bits 87 opp-hz = /bits/ 64 <160000000>;
88 }; 88 };
89 opp-200000000 { 89 opp-200000000 {
90 opp-hz = /bits 90 opp-hz = /bits/ 64 <200000000>;
91 }; 91 };
92 }; 92 };
93 }; 93 };
94 94
95 bus_fsys: bus-fsys { 95 bus_fsys: bus-fsys {
96 compatible = "samsung,exynos-b 96 compatible = "samsung,exynos-bus";
97 clocks = <&clock CLK_ACLK133>; 97 clocks = <&clock CLK_ACLK133>;
98 clock-names = "bus"; 98 clock-names = "bus";
99 operating-points-v2 = <&bus_fs 99 operating-points-v2 = <&bus_fsys_opp_table>;
100 status = "disabled"; 100 status = "disabled";
101 101
102 bus_fsys_opp_table: opp-table 102 bus_fsys_opp_table: opp-table {
103 compatible = "operatin 103 compatible = "operating-points-v2";
104 104
105 opp-100000000 { 105 opp-100000000 {
106 opp-hz = /bits 106 opp-hz = /bits/ 64 <100000000>;
107 }; 107 };
108 opp-134000000 { 108 opp-134000000 {
109 opp-hz = /bits 109 opp-hz = /bits/ 64 <134000000>;
110 }; 110 };
111 }; 111 };
112 }; 112 };
113 113
114 bus_leftbus: bus-leftbus { 114 bus_leftbus: bus-leftbus {
115 compatible = "samsung,exynos-b 115 compatible = "samsung,exynos-bus";
116 clocks = <&clock CLK_DIV_GDL>; 116 clocks = <&clock CLK_DIV_GDL>;
117 clock-names = "bus"; 117 clock-names = "bus";
118 operating-points-v2 = <&bus_le 118 operating-points-v2 = <&bus_leftbus_opp_table>;
119 interconnects = <&bus_dmc>; 119 interconnects = <&bus_dmc>;
120 #interconnect-cells = <0>; 120 #interconnect-cells = <0>;
121 status = "disabled"; 121 status = "disabled";
122 }; 122 };
123 123
124 bus_mfc: bus-mfc { 124 bus_mfc: bus-mfc {
125 compatible = "samsung,exynos-b 125 compatible = "samsung,exynos-bus";
126 clocks = <&clock CLK_SCLK_MFC> 126 clocks = <&clock CLK_SCLK_MFC>;
127 clock-names = "bus"; 127 clock-names = "bus";
128 operating-points-v2 = <&bus_le 128 operating-points-v2 = <&bus_leftbus_opp_table>;
129 status = "disabled"; 129 status = "disabled";
130 }; 130 };
131 131
132 bus_peri: bus-peri { 132 bus_peri: bus-peri {
133 compatible = "samsung,exynos-b 133 compatible = "samsung,exynos-bus";
134 clocks = <&clock CLK_ACLK100>; 134 clocks = <&clock CLK_ACLK100>;
135 clock-names = "bus"; 135 clock-names = "bus";
136 operating-points-v2 = <&bus_pe 136 operating-points-v2 = <&bus_peri_opp_table>;
137 status = "disabled"; 137 status = "disabled";
138 138
139 bus_peri_opp_table: opp-table 139 bus_peri_opp_table: opp-table {
140 compatible = "operatin 140 compatible = "operating-points-v2";
141 141
142 opp-50000000 { 142 opp-50000000 {
143 opp-hz = /bits 143 opp-hz = /bits/ 64 <50000000>;
144 }; 144 };
145 opp-100000000 { 145 opp-100000000 {
146 opp-hz = /bits 146 opp-hz = /bits/ 64 <100000000>;
147 }; 147 };
148 }; 148 };
149 }; 149 };
150 150
151 bus_rightbus: bus-rightbus { 151 bus_rightbus: bus-rightbus {
152 compatible = "samsung,exynos-b 152 compatible = "samsung,exynos-bus";
153 clocks = <&clock CLK_DIV_GDR>; 153 clocks = <&clock CLK_DIV_GDR>;
154 clock-names = "bus"; 154 clock-names = "bus";
155 operating-points-v2 = <&bus_le 155 operating-points-v2 = <&bus_leftbus_opp_table>;
156 status = "disabled"; 156 status = "disabled";
157 }; 157 };
158 158
159 bus_dmc_opp_table: opp-table-1 { 159 bus_dmc_opp_table: opp-table-1 {
160 compatible = "operating-points 160 compatible = "operating-points-v2";
161 161
162 opp-100000000 { 162 opp-100000000 {
163 opp-hz = /bits/ 64 <10 163 opp-hz = /bits/ 64 <100000000>;
164 opp-microvolt = <90000 164 opp-microvolt = <900000>;
165 }; 165 };
166 opp-134000000 { 166 opp-134000000 {
167 opp-hz = /bits/ 64 <13 167 opp-hz = /bits/ 64 <134000000>;
168 opp-microvolt = <90000 168 opp-microvolt = <900000>;
169 }; 169 };
170 opp-160000000 { 170 opp-160000000 {
171 opp-hz = /bits/ 64 <16 171 opp-hz = /bits/ 64 <160000000>;
172 opp-microvolt = <90000 172 opp-microvolt = <900000>;
173 }; 173 };
174 opp-267000000 { 174 opp-267000000 {
175 opp-hz = /bits/ 64 <26 175 opp-hz = /bits/ 64 <267000000>;
176 opp-microvolt = <95000 176 opp-microvolt = <950000>;
177 }; 177 };
178 opp-400000000 { 178 opp-400000000 {
179 opp-hz = /bits/ 64 <40 179 opp-hz = /bits/ 64 <400000000>;
180 opp-microvolt = <10500 180 opp-microvolt = <1050000>;
181 opp-suspend; 181 opp-suspend;
182 }; 182 };
183 }; 183 };
184 184
185 bus_leftbus_opp_table: opp-table-2 { 185 bus_leftbus_opp_table: opp-table-2 {
186 compatible = "operating-points 186 compatible = "operating-points-v2";
187 187
188 opp-100000000 { 188 opp-100000000 {
189 opp-hz = /bits/ 64 <10 189 opp-hz = /bits/ 64 <100000000>;
190 opp-microvolt = <90000 190 opp-microvolt = <900000>;
191 }; 191 };
192 opp-134000000 { 192 opp-134000000 {
193 opp-hz = /bits/ 64 <13 193 opp-hz = /bits/ 64 <134000000>;
194 opp-microvolt = <92500 194 opp-microvolt = <925000>;
195 }; 195 };
196 opp-160000000 { 196 opp-160000000 {
197 opp-hz = /bits/ 64 <16 197 opp-hz = /bits/ 64 <160000000>;
198 opp-microvolt = <95000 198 opp-microvolt = <950000>;
199 }; 199 };
200 opp-200000000 { 200 opp-200000000 {
201 opp-hz = /bits/ 64 <20 201 opp-hz = /bits/ 64 <200000000>;
202 opp-microvolt = <10000 202 opp-microvolt = <1000000>;
203 opp-suspend; 203 opp-suspend;
204 }; 204 };
205 }; 205 };
206 206
207 soc: soc { 207 soc: soc {
208 208
209 pinctrl_0: pinctrl@11400000 { 209 pinctrl_0: pinctrl@11400000 {
210 compatible = "samsung, 210 compatible = "samsung,exynos4x12-pinctrl";
211 reg = <0x11400000 0x10 211 reg = <0x11400000 0x1000>;
212 interrupts = <GIC_SPI 212 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
213 }; 213 };
214 214
215 pinctrl_1: pinctrl@11000000 { 215 pinctrl_1: pinctrl@11000000 {
216 compatible = "samsung, 216 compatible = "samsung,exynos4x12-pinctrl";
217 reg = <0x11000000 0x10 217 reg = <0x11000000 0x1000>;
218 interrupts = <GIC_SPI 218 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
219 219
220 wakup_eint: wakeup-int 220 wakup_eint: wakeup-interrupt-controller {
221 compatible = " 221 compatible = "samsung,exynos4210-wakeup-eint";
222 interrupt-pare 222 interrupt-parent = <&gic>;
223 interrupts = < 223 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
224 }; 224 };
225 }; 225 };
226 226
227 pinctrl_2: pinctrl@3860000 { 227 pinctrl_2: pinctrl@3860000 {
228 compatible = "samsung, 228 compatible = "samsung,exynos4x12-pinctrl";
229 reg = <0x03860000 0x10 229 reg = <0x03860000 0x1000>;
230 interrupt-parent = <&c 230 interrupt-parent = <&combiner>;
231 interrupts = <10 0>; 231 interrupts = <10 0>;
232 }; 232 };
233 233
234 pinctrl_3: pinctrl@106e0000 { 234 pinctrl_3: pinctrl@106e0000 {
235 compatible = "samsung, 235 compatible = "samsung,exynos4x12-pinctrl";
236 reg = <0x106e0000 0x10 236 reg = <0x106e0000 0x1000>;
237 interrupts = <GIC_SPI 237 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
238 }; 238 };
239 239
240 sram@2020000 { 240 sram@2020000 {
241 compatible = "mmio-sra 241 compatible = "mmio-sram";
242 reg = <0x02020000 0x40 242 reg = <0x02020000 0x40000>;
243 #address-cells = <1>; 243 #address-cells = <1>;
244 #size-cells = <1>; 244 #size-cells = <1>;
245 ranges = <0 0x02020000 245 ranges = <0 0x02020000 0x40000>;
246 246
247 smp-sram@0 { 247 smp-sram@0 {
248 compatible = " 248 compatible = "samsung,exynos4210-sysram";
249 reg = <0x0 0x1 249 reg = <0x0 0x1000>;
250 }; 250 };
251 251
252 smp-sram@2f000 { 252 smp-sram@2f000 {
253 compatible = " 253 compatible = "samsung,exynos4210-sysram-ns";
254 reg = <0x2f000 254 reg = <0x2f000 0x1000>;
255 }; 255 };
256 }; 256 };
257 257
258 pd_isp: power-domain@10023ca0 258 pd_isp: power-domain@10023ca0 {
259 compatible = "samsung, 259 compatible = "samsung,exynos4210-pd";
260 reg = <0x10023ca0 0x20 260 reg = <0x10023ca0 0x20>;
261 #power-domain-cells = 261 #power-domain-cells = <0>;
262 label = "ISP"; 262 label = "ISP";
263 }; 263 };
264 264
265 l2c: cache-controller@10502000 265 l2c: cache-controller@10502000 {
266 compatible = "arm,pl31 266 compatible = "arm,pl310-cache";
267 reg = <0x10502000 0x10 267 reg = <0x10502000 0x1000>;
268 cache-unified; 268 cache-unified;
269 cache-level = <2>; 269 cache-level = <2>;
270 prefetch-data = <1>; 270 prefetch-data = <1>;
271 prefetch-instr = <1>; 271 prefetch-instr = <1>;
272 arm,tag-latency = <2 2 272 arm,tag-latency = <2 2 1>;
273 arm,data-latency = <3 273 arm,data-latency = <3 2 1>;
274 arm,double-linefill = 274 arm,double-linefill = <1>;
275 arm,double-linefill-in 275 arm,double-linefill-incr = <0>;
276 arm,double-linefill-wr 276 arm,double-linefill-wrap = <1>;
277 arm,prefetch-drop = <1 277 arm,prefetch-drop = <1>;
278 arm,prefetch-offset = 278 arm,prefetch-offset = <7>;
279 }; 279 };
280 280
281 clock: clock-controller@100300 281 clock: clock-controller@10030000 {
282 reg = <0x10030000 0x18 282 reg = <0x10030000 0x18000>;
283 #clock-cells = <1>; 283 #clock-cells = <1>;
284 }; 284 };
285 285
286 isp_clock: clock-controller@10 286 isp_clock: clock-controller@10048000 {
287 compatible = "samsung, 287 compatible = "samsung,exynos4412-isp-clock";
288 reg = <0x10048000 0x10 288 reg = <0x10048000 0x1000>;
289 #clock-cells = <1>; 289 #clock-cells = <1>;
290 power-domains = <&pd_i 290 power-domains = <&pd_isp>;
291 clocks = <&clock CLK_A 291 clocks = <&clock CLK_ACLK200>,
292 <&clock CLK_A 292 <&clock CLK_ACLK400_MCUISP>;
293 clock-names = "aclk200 293 clock-names = "aclk200", "aclk400_mcuisp";
294 }; 294 };
295 295
296 timer@10050000 { 296 timer@10050000 {
297 compatible = "samsung, 297 compatible = "samsung,exynos4412-mct";
298 reg = <0x10050000 0x80 298 reg = <0x10050000 0x800>;
299 clocks = <&clock CLK_F 299 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
300 clock-names = "fin_pll 300 clock-names = "fin_pll", "mct";
301 interrupts-extended = 301 interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
302 302 <&combiner 12 5>,
303 303 <&combiner 12 6>,
304 304 <&combiner 12 7>,
305 305 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
306 }; 306 };
307 307
308 watchdog: watchdog@10060000 { 308 watchdog: watchdog@10060000 {
309 compatible = "samsung, 309 compatible = "samsung,exynos5250-wdt";
310 reg = <0x10060000 0x10 310 reg = <0x10060000 0x100>;
311 interrupts = <GIC_SPI 311 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
312 clocks = <&clock CLK_W 312 clocks = <&clock CLK_WDT>;
313 clock-names = "watchdo 313 clock-names = "watchdog";
314 samsung,syscon-phandle 314 samsung,syscon-phandle = <&pmu_system_controller>;
315 }; 315 };
316 316
317 adc: adc@126c0000 { 317 adc: adc@126c0000 {
318 compatible = "samsung, 318 compatible = "samsung,exynos4212-adc";
319 reg = <0x126c0000 0x10 319 reg = <0x126c0000 0x100>;
320 interrupt-parent = <&c 320 interrupt-parent = <&combiner>;
321 interrupts = <10 3>; 321 interrupts = <10 3>;
322 clocks = <&clock CLK_T 322 clocks = <&clock CLK_TSADC>;
323 clock-names = "adc"; 323 clock-names = "adc";
324 #io-channel-cells = <1 324 #io-channel-cells = <1>;
325 samsung,syscon-phandle 325 samsung,syscon-phandle = <&pmu_system_controller>;
326 status = "disabled"; 326 status = "disabled";
327 }; 327 };
328 328
329 g2d: g2d@10800000 { 329 g2d: g2d@10800000 {
330 compatible = "samsung, 330 compatible = "samsung,exynos4212-g2d";
331 reg = <0x10800000 0x10 331 reg = <0x10800000 0x1000>;
332 interrupts = <GIC_SPI 332 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&clock CLK_S 333 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
334 clock-names = "sclk_fi 334 clock-names = "sclk_fimg2d", "fimg2d";
335 iommus = <&sysmmu_g2d> 335 iommus = <&sysmmu_g2d>;
336 }; 336 };
337 337
338 mshc_0: mmc@12550000 { 338 mshc_0: mmc@12550000 {
339 compatible = "samsung, 339 compatible = "samsung,exynos4412-dw-mshc";
340 reg = <0x12550000 0x10 340 reg = <0x12550000 0x1000>;
341 interrupts = <GIC_SPI 341 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
342 #address-cells = <1>; 342 #address-cells = <1>;
343 #size-cells = <0>; 343 #size-cells = <0>;
344 fifo-depth = <0x80>; 344 fifo-depth = <0x80>;
345 clocks = <&clock CLK_S 345 clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
346 clock-names = "biu", " 346 clock-names = "biu", "ciu";
347 status = "disabled"; 347 status = "disabled";
348 }; 348 };
349 349
350 sysmmu_g2d: sysmmu@10a40000 { 350 sysmmu_g2d: sysmmu@10a40000 {
351 compatible = "samsung, 351 compatible = "samsung,exynos-sysmmu";
352 reg = <0x10a40000 0x10 352 reg = <0x10a40000 0x1000>;
353 interrupt-parent = <&c 353 interrupt-parent = <&combiner>;
354 interrupts = <4 7>; 354 interrupts = <4 7>;
355 clock-names = "sysmmu" 355 clock-names = "sysmmu", "master";
356 clocks = <&clock CLK_S 356 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
357 #iommu-cells = <0>; 357 #iommu-cells = <0>;
358 }; 358 };
359 359
360 sysmmu_fimc_isp: sysmmu@122600 360 sysmmu_fimc_isp: sysmmu@12260000 {
361 compatible = "samsung, 361 compatible = "samsung,exynos-sysmmu";
362 reg = <0x12260000 0x10 362 reg = <0x12260000 0x1000>;
363 interrupt-parent = <&c 363 interrupt-parent = <&combiner>;
364 interrupts = <16 2>; 364 interrupts = <16 2>;
365 power-domains = <&pd_i 365 power-domains = <&pd_isp>;
366 clock-names = "sysmmu" 366 clock-names = "sysmmu";
367 clocks = <&isp_clock C 367 clocks = <&isp_clock CLK_ISP_SMMU_ISP>;
368 #iommu-cells = <0>; 368 #iommu-cells = <0>;
369 }; 369 };
370 370
371 sysmmu_fimc_drc: sysmmu@122700 371 sysmmu_fimc_drc: sysmmu@12270000 {
372 compatible = "samsung, 372 compatible = "samsung,exynos-sysmmu";
373 reg = <0x12270000 0x10 373 reg = <0x12270000 0x1000>;
374 interrupt-parent = <&c 374 interrupt-parent = <&combiner>;
375 interrupts = <16 3>; 375 interrupts = <16 3>;
376 power-domains = <&pd_i 376 power-domains = <&pd_isp>;
377 clock-names = "sysmmu" 377 clock-names = "sysmmu";
378 clocks = <&isp_clock C 378 clocks = <&isp_clock CLK_ISP_SMMU_DRC>;
379 #iommu-cells = <0>; 379 #iommu-cells = <0>;
380 }; 380 };
381 381
382 sysmmu_fimc_fd: sysmmu@122a000 382 sysmmu_fimc_fd: sysmmu@122a0000 {
383 compatible = "samsung, 383 compatible = "samsung,exynos-sysmmu";
384 reg = <0x122a0000 0x10 384 reg = <0x122a0000 0x1000>;
385 interrupt-parent = <&c 385 interrupt-parent = <&combiner>;
386 interrupts = <16 4>; 386 interrupts = <16 4>;
387 power-domains = <&pd_i 387 power-domains = <&pd_isp>;
388 clock-names = "sysmmu" 388 clock-names = "sysmmu";
389 clocks = <&isp_clock C 389 clocks = <&isp_clock CLK_ISP_SMMU_FD>;
390 #iommu-cells = <0>; 390 #iommu-cells = <0>;
391 }; 391 };
392 392
393 sysmmu_fimc_mcuctl: sysmmu@122 393 sysmmu_fimc_mcuctl: sysmmu@122b0000 {
394 compatible = "samsung, 394 compatible = "samsung,exynos-sysmmu";
395 reg = <0x122b0000 0x10 395 reg = <0x122b0000 0x1000>;
396 interrupt-parent = <&c 396 interrupt-parent = <&combiner>;
397 interrupts = <16 5>; 397 interrupts = <16 5>;
398 power-domains = <&pd_i 398 power-domains = <&pd_isp>;
399 clock-names = "sysmmu" 399 clock-names = "sysmmu";
400 clocks = <&isp_clock C 400 clocks = <&isp_clock CLK_ISP_SMMU_ISPCX>;
401 #iommu-cells = <0>; 401 #iommu-cells = <0>;
402 }; 402 };
403 403
404 sysmmu_fimc_lite0: sysmmu@123b 404 sysmmu_fimc_lite0: sysmmu@123b0000 {
405 compatible = "samsung, 405 compatible = "samsung,exynos-sysmmu";
406 reg = <0x123b0000 0x10 406 reg = <0x123b0000 0x1000>;
407 interrupt-parent = <&c 407 interrupt-parent = <&combiner>;
408 interrupts = <16 0>; 408 interrupts = <16 0>;
409 power-domains = <&pd_i 409 power-domains = <&pd_isp>;
410 clock-names = "sysmmu" 410 clock-names = "sysmmu", "master";
411 clocks = <&isp_clock C 411 clocks = <&isp_clock CLK_ISP_SMMU_LITE0>,
412 <&isp_clock C 412 <&isp_clock CLK_ISP_FIMC_LITE0>;
413 #iommu-cells = <0>; 413 #iommu-cells = <0>;
414 }; 414 };
415 415
416 sysmmu_fimc_lite1: sysmmu@123c 416 sysmmu_fimc_lite1: sysmmu@123c0000 {
417 compatible = "samsung, 417 compatible = "samsung,exynos-sysmmu";
418 reg = <0x123c0000 0x10 418 reg = <0x123c0000 0x1000>;
419 interrupt-parent = <&c 419 interrupt-parent = <&combiner>;
420 interrupts = <16 1>; 420 interrupts = <16 1>;
421 power-domains = <&pd_i 421 power-domains = <&pd_isp>;
422 clock-names = "sysmmu" 422 clock-names = "sysmmu", "master";
423 clocks = <&isp_clock C 423 clocks = <&isp_clock CLK_ISP_SMMU_LITE1>,
424 <&isp_clock C 424 <&isp_clock CLK_ISP_FIMC_LITE1>;
425 #iommu-cells = <0>; 425 #iommu-cells = <0>;
426 }; 426 };
427 }; 427 };
428 }; 428 };
429 429
430 &combiner { 430 &combiner {
431 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL 431 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
432 <GIC_SPI 1 IRQ_TYPE_LEVEL 432 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
433 <GIC_SPI 2 IRQ_TYPE_LEVEL 433 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
434 <GIC_SPI 3 IRQ_TYPE_LEVEL 434 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
435 <GIC_SPI 4 IRQ_TYPE_LEVEL 435 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
436 <GIC_SPI 5 IRQ_TYPE_LEVEL 436 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
437 <GIC_SPI 6 IRQ_TYPE_LEVEL 437 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
438 <GIC_SPI 7 IRQ_TYPE_LEVEL 438 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
439 <GIC_SPI 8 IRQ_TYPE_LEVEL 439 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
440 <GIC_SPI 9 IRQ_TYPE_LEVEL 440 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
441 <GIC_SPI 10 IRQ_TYPE_LEVE 441 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 11 IRQ_TYPE_LEVE 442 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 12 IRQ_TYPE_LEVE 443 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 13 IRQ_TYPE_LEVE 444 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
445 <GIC_SPI 14 IRQ_TYPE_LEVE 445 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
446 <GIC_SPI 15 IRQ_TYPE_LEVE 446 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
447 <GIC_SPI 107 IRQ_TYPE_LEV 447 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
448 <GIC_SPI 108 IRQ_TYPE_LEV 448 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
449 <GIC_SPI 48 IRQ_TYPE_LEVE 449 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
450 <GIC_SPI 42 IRQ_TYPE_LEVE 450 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
451 }; 451 };
452 452
453 &camera { 453 &camera {
454 ranges = <0x0 0x11800000 0xba1000>; <<
455 clocks = <&clock CLK_SCLK_CAM0>, <&clo 454 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
456 <&clock CLK_PIXELASYNCM0>, <& 455 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
457 clock-names = "sclk_cam0", "sclk_cam1" 456 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
458 457
459 /* fimc_[0-3] are configured outside, 458 /* fimc_[0-3] are configured outside, under phandles */
460 fimc_lite_0: fimc-lite@b90000 { !! 459 fimc_lite_0: fimc-lite@12390000 {
461 compatible = "samsung,exynos42 460 compatible = "samsung,exynos4212-fimc-lite";
462 reg = <0x00b90000 0x1000>; !! 461 reg = <0x12390000 0x1000>;
463 interrupts = <GIC_SPI 105 IRQ_ 462 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
464 power-domains = <&pd_isp>; 463 power-domains = <&pd_isp>;
465 clocks = <&isp_clock CLK_ISP_F 464 clocks = <&isp_clock CLK_ISP_FIMC_LITE0>;
466 clock-names = "flite"; 465 clock-names = "flite";
467 iommus = <&sysmmu_fimc_lite0>; 466 iommus = <&sysmmu_fimc_lite0>;
468 status = "disabled"; 467 status = "disabled";
469 }; 468 };
470 469
471 fimc_lite_1: fimc-lite@ba0000 { !! 470 fimc_lite_1: fimc-lite@123a0000 {
472 compatible = "samsung,exynos42 471 compatible = "samsung,exynos4212-fimc-lite";
473 reg = <0x00ba0000 0x1000>; !! 472 reg = <0x123a0000 0x1000>;
474 interrupts = <GIC_SPI 106 IRQ_ 473 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
475 power-domains = <&pd_isp>; 474 power-domains = <&pd_isp>;
476 clocks = <&isp_clock CLK_ISP_F 475 clocks = <&isp_clock CLK_ISP_FIMC_LITE1>;
477 clock-names = "flite"; 476 clock-names = "flite";
478 iommus = <&sysmmu_fimc_lite1>; 477 iommus = <&sysmmu_fimc_lite1>;
479 status = "disabled"; 478 status = "disabled";
480 }; 479 };
481 480
482 fimc_is: fimc-is@800000 { !! 481 fimc_is: fimc-is@12000000 {
483 compatible = "samsung,exynos42 482 compatible = "samsung,exynos4212-fimc-is";
484 reg = <0x00800000 0x260000>; !! 483 reg = <0x12000000 0x260000>;
485 interrupts = <GIC_SPI 90 IRQ_T 484 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
486 <GIC_SPI 95 IRQ_T 485 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
487 power-domains = <&pd_isp>; 486 power-domains = <&pd_isp>;
488 clocks = <&isp_clock CLK_ISP_F 487 clocks = <&isp_clock CLK_ISP_FIMC_LITE0>,
489 <&isp_clock CLK_ISP_F 488 <&isp_clock CLK_ISP_FIMC_LITE1>,
490 <&isp_clock CLK_ISP_P 489 <&isp_clock CLK_ISP_PPMUISPX>,
491 <&isp_clock CLK_ISP_P 490 <&isp_clock CLK_ISP_PPMUISPMX>,
492 <&isp_clock CLK_ISP_F 491 <&isp_clock CLK_ISP_FIMC_ISP>,
493 <&isp_clock CLK_ISP_F 492 <&isp_clock CLK_ISP_FIMC_DRC>,
494 <&isp_clock CLK_ISP_F 493 <&isp_clock CLK_ISP_FIMC_FD>,
495 <&isp_clock CLK_ISP_M 494 <&isp_clock CLK_ISP_MCUISP>,
496 <&isp_clock CLK_ISP_G 495 <&isp_clock CLK_ISP_GICISP>,
497 <&isp_clock CLK_ISP_M 496 <&isp_clock CLK_ISP_MCUCTL_ISP>,
498 <&isp_clock CLK_ISP_P 497 <&isp_clock CLK_ISP_PWM_ISP>,
499 <&isp_clock CLK_ISP_D 498 <&isp_clock CLK_ISP_DIV_ISP0>,
500 <&isp_clock CLK_ISP_D 499 <&isp_clock CLK_ISP_DIV_ISP1>,
501 <&isp_clock CLK_ISP_D 500 <&isp_clock CLK_ISP_DIV_MCUISP0>,
502 <&isp_clock CLK_ISP_D 501 <&isp_clock CLK_ISP_DIV_MCUISP1>,
503 <&clock CLK_MOUT_MPLL 502 <&clock CLK_MOUT_MPLL_USER_T>,
504 <&clock CLK_ACLK200>, 503 <&clock CLK_ACLK200>,
505 <&clock CLK_ACLK400_M 504 <&clock CLK_ACLK400_MCUISP>,
506 <&clock CLK_DIV_ACLK2 505 <&clock CLK_DIV_ACLK200>,
507 <&clock CLK_DIV_ACLK4 506 <&clock CLK_DIV_ACLK400_MCUISP>,
508 <&clock CLK_UART_ISP_ 507 <&clock CLK_UART_ISP_SCLK>;
509 clock-names = "lite0", "lite1" 508 clock-names = "lite0", "lite1", "ppmuispx",
510 "ppmuispmx", "is 509 "ppmuispmx", "isp",
511 "drc", "fd", "mc 510 "drc", "fd", "mcuisp",
512 "gicisp", "mcuct 511 "gicisp", "mcuctl_isp", "pwm_isp",
513 "ispdiv0", "ispd 512 "ispdiv0", "ispdiv1", "mcuispdiv0",
514 "mcuispdiv1", "m 513 "mcuispdiv1", "mpll", "aclk200",
515 "aclk400mcuisp", 514 "aclk400mcuisp", "div_aclk200",
516 "div_aclk400mcui 515 "div_aclk400mcuisp", "uart";
517 iommus = <&sysmmu_fimc_isp>, < 516 iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>,
518 <&sysmmu_fimc_fd>, <& 517 <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>;
519 iommu-names = "isp", "drc", "f 518 iommu-names = "isp", "drc", "fd", "mcuctl";
520 samsung,pmu-syscon = <&pmu_sys <<
521 #address-cells = <1>; 519 #address-cells = <1>;
522 #size-cells = <1>; 520 #size-cells = <1>;
523 ranges; 521 ranges;
524 status = "disabled"; 522 status = "disabled";
525 523
526 i2c1_isp: i2c-isp@940000 { !! 524 pmu@10020000 {
>> 525 reg = <0x10020000 0x3000>;
>> 526 };
>> 527
>> 528 i2c1_isp: i2c-isp@12140000 {
527 compatible = "samsung, 529 compatible = "samsung,exynos4212-i2c-isp";
528 reg = <0x00940000 0x10 !! 530 reg = <0x12140000 0x100>;
529 clocks = <&isp_clock C 531 clocks = <&isp_clock CLK_ISP_I2C1_ISP>;
530 clock-names = "i2c_isp 532 clock-names = "i2c_isp";
531 #address-cells = <1>; 533 #address-cells = <1>;
532 #size-cells = <0>; 534 #size-cells = <0>;
533 }; 535 };
534 }; 536 };
535 }; 537 };
536 538
537 &exynos_usbphy { 539 &exynos_usbphy {
538 compatible = "samsung,exynos4x12-usb2- 540 compatible = "samsung,exynos4x12-usb2-phy";
539 samsung,sysreg-phandle = <&sys_reg>; 541 samsung,sysreg-phandle = <&sys_reg>;
540 }; 542 };
541 543
542 &fimc_0 { 544 &fimc_0 {
543 compatible = "samsung,exynos4212-fimc" 545 compatible = "samsung,exynos4212-fimc";
544 samsung,pix-limits = <4224 8192 1920 4 546 samsung,pix-limits = <4224 8192 1920 4224>;
545 samsung,mainscaler-ext; 547 samsung,mainscaler-ext;
546 samsung,isp-wb; 548 samsung,isp-wb;
547 samsung,cam-if; 549 samsung,cam-if;
548 }; 550 };
549 551
550 &fimc_1 { 552 &fimc_1 {
551 compatible = "samsung,exynos4212-fimc" 553 compatible = "samsung,exynos4212-fimc";
552 samsung,pix-limits = <4224 8192 1920 4 554 samsung,pix-limits = <4224 8192 1920 4224>;
553 samsung,mainscaler-ext; 555 samsung,mainscaler-ext;
554 samsung,isp-wb; 556 samsung,isp-wb;
555 samsung,cam-if; 557 samsung,cam-if;
556 }; 558 };
557 559
558 &fimc_2 { 560 &fimc_2 {
559 compatible = "samsung,exynos4212-fimc" 561 compatible = "samsung,exynos4212-fimc";
560 samsung,pix-limits = <4224 8192 1920 4 562 samsung,pix-limits = <4224 8192 1920 4224>;
561 samsung,mainscaler-ext; 563 samsung,mainscaler-ext;
562 samsung,isp-wb; 564 samsung,isp-wb;
563 samsung,lcd-wb; 565 samsung,lcd-wb;
564 samsung,cam-if; 566 samsung,cam-if;
565 }; 567 };
566 568
567 &fimc_3 { 569 &fimc_3 {
568 compatible = "samsung,exynos4212-fimc" 570 compatible = "samsung,exynos4212-fimc";
569 samsung,pix-limits = <1920 8192 1366 1 571 samsung,pix-limits = <1920 8192 1366 1920>;
570 samsung,rotators = <0>; 572 samsung,rotators = <0>;
571 samsung,mainscaler-ext; 573 samsung,mainscaler-ext;
572 samsung,isp-wb; 574 samsung,isp-wb;
573 samsung,lcd-wb; 575 samsung,lcd-wb;
574 }; 576 };
575 577
576 &gpu { 578 &gpu {
577 interrupts = <GIC_SPI 127 IRQ_TYPE_LEV 579 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
578 <GIC_SPI 122 IRQ_TYPE_LEV 580 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
579 <GIC_SPI 123 IRQ_TYPE_LEV 581 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
580 <GIC_SPI 118 IRQ_TYPE_LEV 582 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
581 <GIC_SPI 124 IRQ_TYPE_LEV 583 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
582 <GIC_SPI 119 IRQ_TYPE_LEV 584 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
583 <GIC_SPI 125 IRQ_TYPE_LEV 585 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 120 IRQ_TYPE_LEV 586 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
585 <GIC_SPI 126 IRQ_TYPE_LEV 587 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
586 <GIC_SPI 121 IRQ_TYPE_LEV 588 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
587 <GIC_SPI 117 IRQ_TYPE_LEV 589 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
588 interrupt-names = "gp", 590 interrupt-names = "gp",
589 "gpmmu", 591 "gpmmu",
590 "pp0", 592 "pp0",
591 "ppmmu0", 593 "ppmmu0",
592 "pp1", 594 "pp1",
593 "ppmmu1", 595 "ppmmu1",
594 "pp2", 596 "pp2",
595 "ppmmu2", 597 "ppmmu2",
596 "pp3", 598 "pp3",
597 "ppmmu3", 599 "ppmmu3",
598 "pmu"; 600 "pmu";
599 operating-points-v2 = <&gpu_opp_table> 601 operating-points-v2 = <&gpu_opp_table>;
600 602
601 gpu_opp_table: opp-table { 603 gpu_opp_table: opp-table {
602 compatible = "operating-points 604 compatible = "operating-points-v2";
603 605
604 opp-160000000 { 606 opp-160000000 {
605 opp-hz = /bits/ 64 <16 607 opp-hz = /bits/ 64 <160000000>;
606 opp-microvolt = <87500 608 opp-microvolt = <875000>;
607 }; 609 };
608 opp-267000000 { 610 opp-267000000 {
609 opp-hz = /bits/ 64 <26 611 opp-hz = /bits/ 64 <267000000>;
610 opp-microvolt = <90000 612 opp-microvolt = <900000>;
611 }; 613 };
612 opp-350000000 { 614 opp-350000000 {
613 opp-hz = /bits/ 64 <35 615 opp-hz = /bits/ 64 <350000000>;
614 opp-microvolt = <95000 616 opp-microvolt = <950000>;
615 }; 617 };
616 opp-440000000 { 618 opp-440000000 {
617 opp-hz = /bits/ 64 <44 619 opp-hz = /bits/ 64 <440000000>;
618 opp-microvolt = <10250 620 opp-microvolt = <1025000>;
619 }; 621 };
620 }; 622 };
621 }; 623 };
622 624
623 &hdmi { 625 &hdmi {
624 compatible = "samsung,exynos4212-hdmi" 626 compatible = "samsung,exynos4212-hdmi";
625 }; 627 };
626 628
627 &jpeg_codec { 629 &jpeg_codec {
628 compatible = "samsung,exynos4212-jpeg" 630 compatible = "samsung,exynos4212-jpeg";
629 }; 631 };
630 632
631 &rotator { 633 &rotator {
632 compatible = "samsung,exynos4212-rotat 634 compatible = "samsung,exynos4212-rotator";
633 }; 635 };
634 636
635 &mixer { 637 &mixer {
636 compatible = "samsung,exynos4212-mixer 638 compatible = "samsung,exynos4212-mixer";
637 clock-names = "mixer", "hdmi", "sclk_h 639 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp";
638 clocks = <&clock CLK_MIXER>, <&clock C 640 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
639 <&clock CLK_SCLK_HDMI>, <&clo 641 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>;
640 interconnects = <&bus_display &bus_dmc 642 interconnects = <&bus_display &bus_dmc>;
641 }; 643 };
642 644
643 &pmu_system_controller { 645 &pmu_system_controller {
644 clock-names = "clkout0", "clkout1", "c 646 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
645 "clkout4", "clkout8", 647 "clkout4", "clkout8", "clkout9";
646 clocks = <&clock CLK_OUT_DMC>, <&clock 648 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
647 <&clock CLK_OUT_LEFTBUS>, <&cl 649 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
648 <&clock CLK_OUT_CPU>, <&clock 650 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
649 #clock-cells = <1>; 651 #clock-cells = <1>;
650 }; 652 };
651 653
652 &tmu { 654 &tmu {
653 compatible = "samsung,exynos4412-tmu"; 655 compatible = "samsung,exynos4412-tmu";
654 interrupt-parent = <&combiner>; 656 interrupt-parent = <&combiner>;
655 interrupts = <2 4>; 657 interrupts = <2 4>;
656 reg = <0x100c0000 0x100>; 658 reg = <0x100c0000 0x100>;
657 clocks = <&clock CLK_TMU_APBIF>; 659 clocks = <&clock CLK_TMU_APBIF>;
658 clock-names = "tmu_apbif"; 660 clock-names = "tmu_apbif";
659 status = "disabled"; 661 status = "disabled";
660 }; 662 };
661 663
662 #include "exynos4x12-pinctrl.dtsi" 664 #include "exynos4x12-pinctrl.dtsi"
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