1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Samsung Exynos5250 SoC device tree source 3 * Samsung Exynos5250 SoC device tree source
4 * 4 *
5 * Copyright (c) 2012 Samsung Electronics Co., 5 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com 6 * http://www.samsung.com
7 * 7 *
8 * Samsung Exynos5250 SoC device nodes are lis 8 * Samsung Exynos5250 SoC device nodes are listed in this file.
9 * Exynos5250 based board files can include th 9 * Exynos5250 based board files can include this file and provide
10 * values for board specific bindings. 10 * values for board specific bindings.
11 * 11 *
12 * Note: This file does not include device nod 12 * Note: This file does not include device nodes for all the controllers in
13 * Exynos5250 SoC. As device tree coverage for 13 * Exynos5250 SoC. As device tree coverage for Exynos5250 increases,
14 * additional nodes can be added to this file. 14 * additional nodes can be added to this file.
15 */ 15 */
16 16
17 #include <dt-bindings/clock/exynos5250.h> 17 #include <dt-bindings/clock/exynos5250.h>
18 #include "exynos5.dtsi" 18 #include "exynos5.dtsi"
19 #include "exynos4-cpu-thermal.dtsi" 19 #include "exynos4-cpu-thermal.dtsi"
20 #include <dt-bindings/clock/exynos-audss-clk.h 20 #include <dt-bindings/clock/exynos-audss-clk.h>
21 21
22 / { 22 / {
23 compatible = "samsung,exynos5250", "sa 23 compatible = "samsung,exynos5250", "samsung,exynos5";
24 24
25 aliases { 25 aliases {
26 spi0 = &spi_0; 26 spi0 = &spi_0;
27 spi1 = &spi_1; 27 spi1 = &spi_1;
28 spi2 = &spi_2; 28 spi2 = &spi_2;
29 gsc0 = &gsc_0; 29 gsc0 = &gsc_0;
30 gsc1 = &gsc_1; 30 gsc1 = &gsc_1;
31 gsc2 = &gsc_2; 31 gsc2 = &gsc_2;
32 gsc3 = &gsc_3; 32 gsc3 = &gsc_3;
33 i2c4 = &i2c_4; 33 i2c4 = &i2c_4;
34 i2c5 = &i2c_5; 34 i2c5 = &i2c_5;
35 i2c6 = &i2c_6; 35 i2c6 = &i2c_6;
36 i2c7 = &i2c_7; 36 i2c7 = &i2c_7;
37 i2c8 = &i2c_8; 37 i2c8 = &i2c_8;
38 i2c9 = &i2c_9; 38 i2c9 = &i2c_9;
39 pinctrl0 = &pinctrl_0; 39 pinctrl0 = &pinctrl_0;
40 pinctrl1 = &pinctrl_1; 40 pinctrl1 = &pinctrl_1;
41 pinctrl2 = &pinctrl_2; 41 pinctrl2 = &pinctrl_2;
42 pinctrl3 = &pinctrl_3; 42 pinctrl3 = &pinctrl_3;
43 }; 43 };
44 44
45 cpus { 45 cpus {
46 #address-cells = <1>; 46 #address-cells = <1>;
47 #size-cells = <0>; 47 #size-cells = <0>;
48 48
49 cpu-map { 49 cpu-map {
50 cluster0 { 50 cluster0 {
51 core0 { 51 core0 {
52 cpu = 52 cpu = <&cpu0>;
53 }; 53 };
54 core1 { 54 core1 {
55 cpu = 55 cpu = <&cpu1>;
56 }; 56 };
57 }; 57 };
58 }; 58 };
59 59
60 cpu0: cpu@0 { 60 cpu0: cpu@0 {
61 device_type = "cpu"; 61 device_type = "cpu";
62 compatible = "arm,cort 62 compatible = "arm,cortex-a15";
63 reg = <0>; 63 reg = <0>;
64 clocks = <&clock CLK_A 64 clocks = <&clock CLK_ARM_CLK>;
65 clock-names = "cpu"; 65 clock-names = "cpu";
66 operating-points-v2 = 66 operating-points-v2 = <&cpu0_opp_table>;
67 #cooling-cells = <2>; 67 #cooling-cells = <2>; /* min followed by max */
68 }; 68 };
69 cpu1: cpu@1 { 69 cpu1: cpu@1 {
70 device_type = "cpu"; 70 device_type = "cpu";
71 compatible = "arm,cort 71 compatible = "arm,cortex-a15";
72 reg = <1>; 72 reg = <1>;
73 clocks = <&clock CLK_A 73 clocks = <&clock CLK_ARM_CLK>;
74 clock-names = "cpu"; 74 clock-names = "cpu";
75 operating-points-v2 = 75 operating-points-v2 = <&cpu0_opp_table>;
76 #cooling-cells = <2>; 76 #cooling-cells = <2>; /* min followed by max */
77 }; 77 };
78 }; 78 };
79 79
80 cpu0_opp_table: opp-table-0 { 80 cpu0_opp_table: opp-table-0 {
81 compatible = "operating-points 81 compatible = "operating-points-v2";
82 opp-shared; 82 opp-shared;
83 83
84 opp-200000000 { 84 opp-200000000 {
85 opp-hz = /bits/ 64 <20 85 opp-hz = /bits/ 64 <200000000>;
86 opp-microvolt = <92500 86 opp-microvolt = <925000>;
87 clock-latency-ns = <14 87 clock-latency-ns = <140000>;
88 }; 88 };
89 opp-300000000 { 89 opp-300000000 {
90 opp-hz = /bits/ 64 <30 90 opp-hz = /bits/ 64 <300000000>;
91 opp-microvolt = <93750 91 opp-microvolt = <937500>;
92 clock-latency-ns = <14 92 clock-latency-ns = <140000>;
93 }; 93 };
94 opp-400000000 { 94 opp-400000000 {
95 opp-hz = /bits/ 64 <40 95 opp-hz = /bits/ 64 <400000000>;
96 opp-microvolt = <95000 96 opp-microvolt = <950000>;
97 clock-latency-ns = <14 97 clock-latency-ns = <140000>;
98 }; 98 };
99 opp-500000000 { 99 opp-500000000 {
100 opp-hz = /bits/ 64 <50 100 opp-hz = /bits/ 64 <500000000>;
101 opp-microvolt = <97500 101 opp-microvolt = <975000>;
102 clock-latency-ns = <14 102 clock-latency-ns = <140000>;
103 }; 103 };
104 opp-600000000 { 104 opp-600000000 {
105 opp-hz = /bits/ 64 <60 105 opp-hz = /bits/ 64 <600000000>;
106 opp-microvolt = <10000 106 opp-microvolt = <1000000>;
107 clock-latency-ns = <14 107 clock-latency-ns = <140000>;
108 }; 108 };
109 opp-700000000 { 109 opp-700000000 {
110 opp-hz = /bits/ 64 <70 110 opp-hz = /bits/ 64 <700000000>;
111 opp-microvolt = <10125 111 opp-microvolt = <1012500>;
112 clock-latency-ns = <14 112 clock-latency-ns = <140000>;
113 }; 113 };
114 opp-800000000 { 114 opp-800000000 {
115 opp-hz = /bits/ 64 <80 115 opp-hz = /bits/ 64 <800000000>;
116 opp-microvolt = <10250 116 opp-microvolt = <1025000>;
117 clock-latency-ns = <14 117 clock-latency-ns = <140000>;
118 }; 118 };
119 opp-900000000 { 119 opp-900000000 {
120 opp-hz = /bits/ 64 <90 120 opp-hz = /bits/ 64 <900000000>;
121 opp-microvolt = <10500 121 opp-microvolt = <1050000>;
122 clock-latency-ns = <14 122 clock-latency-ns = <140000>;
123 }; 123 };
124 opp-1000000000 { 124 opp-1000000000 {
125 opp-hz = /bits/ 64 <10 125 opp-hz = /bits/ 64 <1000000000>;
126 opp-microvolt = <10750 126 opp-microvolt = <1075000>;
127 clock-latency-ns = <14 127 clock-latency-ns = <140000>;
128 opp-suspend; 128 opp-suspend;
129 }; 129 };
130 opp-1100000000 { 130 opp-1100000000 {
131 opp-hz = /bits/ 64 <11 131 opp-hz = /bits/ 64 <1100000000>;
132 opp-microvolt = <11000 132 opp-microvolt = <1100000>;
133 clock-latency-ns = <14 133 clock-latency-ns = <140000>;
134 }; 134 };
135 opp-1200000000 { 135 opp-1200000000 {
136 opp-hz = /bits/ 64 <12 136 opp-hz = /bits/ 64 <1200000000>;
137 opp-microvolt = <11250 137 opp-microvolt = <1125000>;
138 clock-latency-ns = <14 138 clock-latency-ns = <140000>;
139 }; 139 };
140 opp-1300000000 { 140 opp-1300000000 {
141 opp-hz = /bits/ 64 <13 141 opp-hz = /bits/ 64 <1300000000>;
142 opp-microvolt = <11500 142 opp-microvolt = <1150000>;
143 clock-latency-ns = <14 143 clock-latency-ns = <140000>;
144 }; 144 };
145 opp-1400000000 { 145 opp-1400000000 {
146 opp-hz = /bits/ 64 <14 146 opp-hz = /bits/ 64 <1400000000>;
147 opp-microvolt = <12000 147 opp-microvolt = <1200000>;
148 clock-latency-ns = <14 148 clock-latency-ns = <140000>;
149 }; 149 };
150 opp-1500000000 { 150 opp-1500000000 {
151 opp-hz = /bits/ 64 <15 151 opp-hz = /bits/ 64 <1500000000>;
152 opp-microvolt = <12250 152 opp-microvolt = <1225000>;
153 clock-latency-ns = <14 153 clock-latency-ns = <140000>;
154 }; 154 };
155 opp-1600000000 { 155 opp-1600000000 {
156 opp-hz = /bits/ 64 <16 156 opp-hz = /bits/ 64 <1600000000>;
157 opp-microvolt = <12500 157 opp-microvolt = <1250000>;
158 clock-latency-ns = <14 158 clock-latency-ns = <140000>;
159 }; 159 };
160 opp-1700000000 { 160 opp-1700000000 {
161 opp-hz = /bits/ 64 <17 161 opp-hz = /bits/ 64 <1700000000>;
162 opp-microvolt = <13000 162 opp-microvolt = <1300000>;
163 clock-latency-ns = <14 163 clock-latency-ns = <140000>;
164 }; 164 };
165 }; 165 };
166 166
167 pmu { 167 pmu {
168 compatible = "arm,cortex-a15-p 168 compatible = "arm,cortex-a15-pmu";
169 interrupt-parent = <&combiner> 169 interrupt-parent = <&combiner>;
170 interrupts = <1 2>, <22 4>; 170 interrupts = <1 2>, <22 4>;
171 }; 171 };
172 172
173 soc: soc { 173 soc: soc {
174 sram@2020000 { 174 sram@2020000 {
175 compatible = "mmio-sra 175 compatible = "mmio-sram";
176 reg = <0x02020000 0x30 176 reg = <0x02020000 0x30000>;
177 #address-cells = <1>; 177 #address-cells = <1>;
178 #size-cells = <1>; 178 #size-cells = <1>;
179 ranges = <0 0x02020000 179 ranges = <0 0x02020000 0x30000>;
180 180
181 smp-sram@0 { 181 smp-sram@0 {
182 compatible = " 182 compatible = "samsung,exynos4210-sysram";
183 reg = <0x0 0x1 183 reg = <0x0 0x1000>;
184 }; 184 };
185 185
186 smp-sram@2f000 { 186 smp-sram@2f000 {
187 compatible = " 187 compatible = "samsung,exynos4210-sysram-ns";
188 reg = <0x2f000 188 reg = <0x2f000 0x1000>;
189 }; 189 };
190 }; 190 };
191 191
192 pd_gsc: power-domain@10044000 192 pd_gsc: power-domain@10044000 {
193 compatible = "samsung, 193 compatible = "samsung,exynos4210-pd";
194 reg = <0x10044000 0x20 194 reg = <0x10044000 0x20>;
195 #power-domain-cells = 195 #power-domain-cells = <0>;
196 label = "GSC"; 196 label = "GSC";
197 }; 197 };
198 198
199 pd_mfc: power-domain@10044040 199 pd_mfc: power-domain@10044040 {
200 compatible = "samsung, 200 compatible = "samsung,exynos4210-pd";
201 reg = <0x10044040 0x20 201 reg = <0x10044040 0x20>;
202 #power-domain-cells = 202 #power-domain-cells = <0>;
203 label = "MFC"; 203 label = "MFC";
204 }; 204 };
205 205
206 pd_g3d: power-domain@10044060 206 pd_g3d: power-domain@10044060 {
207 compatible = "samsung, 207 compatible = "samsung,exynos4210-pd";
208 reg = <0x10044060 0x20 208 reg = <0x10044060 0x20>;
209 #power-domain-cells = 209 #power-domain-cells = <0>;
210 label = "G3D"; 210 label = "G3D";
211 }; 211 };
212 212
213 pd_disp1: power-domain@100440a 213 pd_disp1: power-domain@100440a0 {
214 compatible = "samsung, 214 compatible = "samsung,exynos4210-pd";
215 reg = <0x100440a0 0x20 215 reg = <0x100440a0 0x20>;
216 #power-domain-cells = 216 #power-domain-cells = <0>;
217 label = "DISP1"; 217 label = "DISP1";
218 }; 218 };
219 219
220 pd_mau: power-domain@100440c0 220 pd_mau: power-domain@100440c0 {
221 compatible = "samsung, 221 compatible = "samsung,exynos4210-pd";
222 reg = <0x100440c0 0x20 222 reg = <0x100440c0 0x20>;
223 #power-domain-cells = 223 #power-domain-cells = <0>;
224 label = "MAU"; 224 label = "MAU";
225 }; 225 };
226 226
227 clock: clock-controller@100100 227 clock: clock-controller@10010000 {
228 compatible = "samsung, 228 compatible = "samsung,exynos5250-clock";
229 reg = <0x10010000 0x30 229 reg = <0x10010000 0x30000>;
230 #clock-cells = <1>; 230 #clock-cells = <1>;
231 }; 231 };
232 232
233 clock_audss: audss-clock-contr 233 clock_audss: audss-clock-controller@3810000 {
234 compatible = "samsung, 234 compatible = "samsung,exynos5250-audss-clock";
235 reg = <0x03810000 0x0c 235 reg = <0x03810000 0x0c>;
236 #clock-cells = <1>; 236 #clock-cells = <1>;
237 clocks = <&clock CLK_F 237 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
238 <&clock CLK_S 238 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
239 clock-names = "pll_ref 239 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
240 power-domains = <&pd_m 240 power-domains = <&pd_mau>;
241 }; 241 };
242 242
243 timer@101c0000 { 243 timer@101c0000 {
244 compatible = "samsung, 244 compatible = "samsung,exynos5250-mct",
245 "samsung, 245 "samsung,exynos4210-mct";
246 reg = <0x101c0000 0x80 246 reg = <0x101c0000 0x800>;
247 clocks = <&clock CLK_F 247 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
248 clock-names = "fin_pll 248 clock-names = "fin_pll", "mct";
249 interrupts-extended = 249 interrupts-extended = <&combiner 23 3>,
250 250 <&combiner 23 4>,
251 251 <&combiner 25 2>,
252 252 <&combiner 25 3>,
253 253 <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
254 254 <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
255 }; 255 };
256 256
257 pinctrl_0: pinctrl@11400000 { 257 pinctrl_0: pinctrl@11400000 {
258 compatible = "samsung, 258 compatible = "samsung,exynos5250-pinctrl";
259 reg = <0x11400000 0x10 259 reg = <0x11400000 0x1000>;
260 interrupts = <GIC_SPI 260 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
261 261
262 wakup_eint: wakeup-int 262 wakup_eint: wakeup-interrupt-controller {
263 compatible = " 263 compatible = "samsung,exynos4210-wakeup-eint";
264 interrupt-pare 264 interrupt-parent = <&gic>;
265 interrupts = < 265 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
266 }; 266 };
267 }; 267 };
268 268
269 pinctrl_1: pinctrl@13400000 { 269 pinctrl_1: pinctrl@13400000 {
270 compatible = "samsung, 270 compatible = "samsung,exynos5250-pinctrl";
271 reg = <0x13400000 0x10 271 reg = <0x13400000 0x1000>;
272 interrupts = <GIC_SPI 272 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
273 }; 273 };
274 274
275 pinctrl_2: pinctrl@10d10000 { 275 pinctrl_2: pinctrl@10d10000 {
276 compatible = "samsung, 276 compatible = "samsung,exynos5250-pinctrl";
277 reg = <0x10d10000 0x10 277 reg = <0x10d10000 0x1000>;
278 interrupts = <GIC_SPI 278 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
279 }; 279 };
280 280
281 pinctrl_3: pinctrl@3860000 { 281 pinctrl_3: pinctrl@3860000 {
282 compatible = "samsung, 282 compatible = "samsung,exynos5250-pinctrl";
283 reg = <0x03860000 0x10 283 reg = <0x03860000 0x1000>;
284 interrupts = <GIC_SPI 284 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
285 power-domains = <&pd_m 285 power-domains = <&pd_mau>;
286 }; 286 };
287 287
288 pmu_system_controller: system- 288 pmu_system_controller: system-controller@10040000 {
289 compatible = "samsung, 289 compatible = "samsung,exynos5250-pmu", "simple-mfd", "syscon";
290 reg = <0x10040000 0x50 290 reg = <0x10040000 0x5000>;
291 clock-names = "clkout1 291 clock-names = "clkout16";
292 clocks = <&clock CLK_F 292 clocks = <&clock CLK_FIN_PLL>;
293 #clock-cells = <1>; 293 #clock-cells = <1>;
294 interrupt-controller; 294 interrupt-controller;
295 #interrupt-cells = <3> 295 #interrupt-cells = <3>;
296 interrupt-parent = <&g 296 interrupt-parent = <&gic>;
297 297
298 dp_phy: dp-phy { 298 dp_phy: dp-phy {
299 compatible = " 299 compatible = "samsung,exynos5250-dp-video-phy";
300 #phy-cells = < 300 #phy-cells = <0>;
301 }; 301 };
302 302
303 mipi_phy: mipi-phy { 303 mipi_phy: mipi-phy {
304 compatible = " 304 compatible = "samsung,s5pv210-mipi-video-phy";
305 #phy-cells = < 305 #phy-cells = <1>;
306 }; 306 };
307 }; 307 };
308 308
309 watchdog@101d0000 { 309 watchdog@101d0000 {
310 compatible = "samsung, 310 compatible = "samsung,exynos5250-wdt";
311 reg = <0x101d0000 0x10 311 reg = <0x101d0000 0x100>;
312 interrupts = <GIC_SPI 312 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&clock CLK_W 313 clocks = <&clock CLK_WDT>;
314 clock-names = "watchdo 314 clock-names = "watchdog";
315 samsung,syscon-phandle 315 samsung,syscon-phandle = <&pmu_system_controller>;
316 }; 316 };
317 317
318 mfc: codec@11000000 { 318 mfc: codec@11000000 {
319 compatible = "samsung, 319 compatible = "samsung,mfc-v6";
320 reg = <0x11000000 0x10 320 reg = <0x11000000 0x10000>;
321 interrupts = <GIC_SPI 321 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
322 power-domains = <&pd_m 322 power-domains = <&pd_mfc>;
323 clocks = <&clock CLK_M 323 clocks = <&clock CLK_MFC>;
324 clock-names = "mfc"; 324 clock-names = "mfc";
325 iommus = <&sysmmu_mfc_ 325 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
326 iommu-names = "left", 326 iommu-names = "left", "right";
327 }; 327 };
328 328
329 rotator: rotator@11c00000 { 329 rotator: rotator@11c00000 {
330 compatible = "samsung, 330 compatible = "samsung,exynos5250-rotator";
331 reg = <0x11c00000 0x64 331 reg = <0x11c00000 0x64>;
332 interrupts = <GIC_SPI 332 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&clock CLK_R 333 clocks = <&clock CLK_ROTATOR>;
334 clock-names = "rotator 334 clock-names = "rotator";
335 iommus = <&sysmmu_rota 335 iommus = <&sysmmu_rotator>;
336 }; 336 };
337 337
338 mali: gpu@11800000 { 338 mali: gpu@11800000 {
339 compatible = "samsung, 339 compatible = "samsung,exynos5250-mali", "arm,mali-t604";
340 reg = <0x11800000 0x50 340 reg = <0x11800000 0x5000>;
341 interrupts = <GIC_SPI 341 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
342 <GIC_SPI 342 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
343 <GIC_SPI 343 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
344 interrupt-names = "job 344 interrupt-names = "job", "mmu", "gpu";
345 clocks = <&clock CLK_G 345 clocks = <&clock CLK_G3D>;
346 clock-names = "core"; 346 clock-names = "core";
347 operating-points-v2 = 347 operating-points-v2 = <&gpu_opp_table>;
348 power-domains = <&pd_g 348 power-domains = <&pd_g3d>;
349 status = "disabled"; 349 status = "disabled";
350 350
351 gpu_opp_table: opp-tab 351 gpu_opp_table: opp-table {
352 compatible = " 352 compatible = "operating-points-v2";
353 353
354 opp-100000000 354 opp-100000000 {
355 opp-hz 355 opp-hz = /bits/ 64 <100000000>;
356 opp-mi 356 opp-microvolt = <925000>;
357 }; 357 };
358 opp-160000000 358 opp-160000000 {
359 opp-hz 359 opp-hz = /bits/ 64 <160000000>;
360 opp-mi 360 opp-microvolt = <925000>;
361 }; 361 };
362 opp-266000000 362 opp-266000000 {
363 opp-hz 363 opp-hz = /bits/ 64 <266000000>;
364 opp-mi 364 opp-microvolt = <1025000>;
365 }; 365 };
366 opp-350000000 366 opp-350000000 {
367 opp-hz 367 opp-hz = /bits/ 64 <350000000>;
368 opp-mi 368 opp-microvolt = <1075000>;
369 }; 369 };
370 opp-400000000 370 opp-400000000 {
371 opp-hz 371 opp-hz = /bits/ 64 <400000000>;
372 opp-mi 372 opp-microvolt = <1125000>;
373 }; 373 };
374 opp-450000000 374 opp-450000000 {
375 opp-hz 375 opp-hz = /bits/ 64 <450000000>;
376 opp-mi 376 opp-microvolt = <1150000>;
377 }; 377 };
378 opp-533000000 378 opp-533000000 {
379 opp-hz 379 opp-hz = /bits/ 64 <533000000>;
380 opp-mi 380 opp-microvolt = <1250000>;
381 }; 381 };
382 }; 382 };
383 }; 383 };
384 384
385 tmu: tmu@10060000 { 385 tmu: tmu@10060000 {
386 compatible = "samsung, 386 compatible = "samsung,exynos5250-tmu";
387 reg = <0x10060000 0x10 387 reg = <0x10060000 0x100>;
388 interrupts = <GIC_SPI 388 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
389 clocks = <&clock CLK_T 389 clocks = <&clock CLK_TMU>;
390 clock-names = "tmu_apb 390 clock-names = "tmu_apbif";
391 #thermal-sensor-cells 391 #thermal-sensor-cells = <0>;
392 }; 392 };
393 393
394 sata: sata@122f0000 { 394 sata: sata@122f0000 {
395 compatible = "snps,dwc 395 compatible = "snps,dwc-ahci";
396 reg = <0x122f0000 0x1f 396 reg = <0x122f0000 0x1ff>;
397 interrupts = <GIC_SPI 397 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&clock CLK_S 398 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
399 clock-names = "sata", 399 clock-names = "sata", "pclk";
400 phys = <&sata_phy>; 400 phys = <&sata_phy>;
401 phy-names = "sata-phy" 401 phy-names = "sata-phy";
402 ports-implemented = <0 402 ports-implemented = <0x1>;
403 status = "disabled"; 403 status = "disabled";
404 }; 404 };
405 405
406 sata_phy: sata-phy@12170000 { 406 sata_phy: sata-phy@12170000 {
407 compatible = "samsung, 407 compatible = "samsung,exynos5250-sata-phy";
408 reg = <0x12170000 0x1f 408 reg = <0x12170000 0x1ff>;
409 clocks = <&clock CLK_S 409 clocks = <&clock CLK_SATA_PHYCTRL>;
410 clock-names = "sata_ph 410 clock-names = "sata_phyctrl";
411 #phy-cells = <0>; 411 #phy-cells = <0>;
412 samsung,syscon-phandle 412 samsung,syscon-phandle = <&pmu_system_controller>;
413 status = "disabled"; 413 status = "disabled";
414 }; 414 };
415 415
416 /* i2c_0-3 are defined in exyn 416 /* i2c_0-3 are defined in exynos5.dtsi */
417 i2c_4: i2c@12ca0000 { 417 i2c_4: i2c@12ca0000 {
418 compatible = "samsung, 418 compatible = "samsung,s3c2440-i2c";
419 reg = <0x12ca0000 0x10 419 reg = <0x12ca0000 0x100>;
420 interrupts = <GIC_SPI 420 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
421 #address-cells = <1>; 421 #address-cells = <1>;
422 #size-cells = <0>; 422 #size-cells = <0>;
423 clocks = <&clock CLK_I 423 clocks = <&clock CLK_I2C4>;
424 clock-names = "i2c"; 424 clock-names = "i2c";
425 pinctrl-names = "defau 425 pinctrl-names = "default";
426 pinctrl-0 = <&i2c4_bus 426 pinctrl-0 = <&i2c4_bus>;
427 status = "disabled"; 427 status = "disabled";
428 }; 428 };
429 429
430 i2c_5: i2c@12cb0000 { 430 i2c_5: i2c@12cb0000 {
431 compatible = "samsung, 431 compatible = "samsung,s3c2440-i2c";
432 reg = <0x12cb0000 0x10 432 reg = <0x12cb0000 0x100>;
433 interrupts = <GIC_SPI 433 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
434 #address-cells = <1>; 434 #address-cells = <1>;
435 #size-cells = <0>; 435 #size-cells = <0>;
436 clocks = <&clock CLK_I 436 clocks = <&clock CLK_I2C5>;
437 clock-names = "i2c"; 437 clock-names = "i2c";
438 pinctrl-names = "defau 438 pinctrl-names = "default";
439 pinctrl-0 = <&i2c5_bus 439 pinctrl-0 = <&i2c5_bus>;
440 status = "disabled"; 440 status = "disabled";
441 }; 441 };
442 442
443 i2c_6: i2c@12cc0000 { 443 i2c_6: i2c@12cc0000 {
444 compatible = "samsung, 444 compatible = "samsung,s3c2440-i2c";
445 reg = <0x12cc0000 0x10 445 reg = <0x12cc0000 0x100>;
446 interrupts = <GIC_SPI 446 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
447 #address-cells = <1>; 447 #address-cells = <1>;
448 #size-cells = <0>; 448 #size-cells = <0>;
449 clocks = <&clock CLK_I 449 clocks = <&clock CLK_I2C6>;
450 clock-names = "i2c"; 450 clock-names = "i2c";
451 pinctrl-names = "defau 451 pinctrl-names = "default";
452 pinctrl-0 = <&i2c6_bus 452 pinctrl-0 = <&i2c6_bus>;
453 status = "disabled"; 453 status = "disabled";
454 }; 454 };
455 455
456 i2c_7: i2c@12cd0000 { 456 i2c_7: i2c@12cd0000 {
457 compatible = "samsung, 457 compatible = "samsung,s3c2440-i2c";
458 reg = <0x12cd0000 0x10 458 reg = <0x12cd0000 0x100>;
459 interrupts = <GIC_SPI 459 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
460 #address-cells = <1>; 460 #address-cells = <1>;
461 #size-cells = <0>; 461 #size-cells = <0>;
462 clocks = <&clock CLK_I 462 clocks = <&clock CLK_I2C7>;
463 clock-names = "i2c"; 463 clock-names = "i2c";
464 pinctrl-names = "defau 464 pinctrl-names = "default";
465 pinctrl-0 = <&i2c7_bus 465 pinctrl-0 = <&i2c7_bus>;
466 status = "disabled"; 466 status = "disabled";
467 }; 467 };
468 468
469 i2c_8: i2c@12ce0000 { 469 i2c_8: i2c@12ce0000 {
470 compatible = "samsung, 470 compatible = "samsung,s3c2440-hdmiphy-i2c";
471 reg = <0x12ce0000 0x10 471 reg = <0x12ce0000 0x1000>;
472 interrupts = <GIC_SPI 472 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
473 #address-cells = <1>; 473 #address-cells = <1>;
474 #size-cells = <0>; 474 #size-cells = <0>;
475 clocks = <&clock CLK_I 475 clocks = <&clock CLK_I2C_HDMI>;
476 clock-names = "i2c"; 476 clock-names = "i2c";
477 status = "disabled"; 477 status = "disabled";
478 478
479 hdmiphy: hdmi-phy@38 { 479 hdmiphy: hdmi-phy@38 {
480 compatible = " 480 compatible = "samsung,exynos4212-hdmiphy";
481 reg = <0x38>; 481 reg = <0x38>;
482 }; 482 };
483 }; 483 };
484 484
485 i2c_9: i2c@121d0000 { 485 i2c_9: i2c@121d0000 {
486 compatible = "samsung, 486 compatible = "samsung,exynos5-sata-phy-i2c";
487 reg = <0x121d0000 0x10 487 reg = <0x121d0000 0x100>;
488 #address-cells = <1>; 488 #address-cells = <1>;
489 #size-cells = <0>; 489 #size-cells = <0>;
490 clocks = <&clock CLK_S 490 clocks = <&clock CLK_SATA_PHYI2C>;
491 clock-names = "i2c"; 491 clock-names = "i2c";
492 status = "disabled"; 492 status = "disabled";
493 493
494 sata_phy_i2c: sata-phy 494 sata_phy_i2c: sata-phy-i2c@38 {
495 compatible = " 495 compatible = "samsung,exynos-sataphy-i2c";
496 reg = <0x38>; 496 reg = <0x38>;
497 status = "disa 497 status = "disabled";
498 }; 498 };
499 }; 499 };
500 500
501 spi_0: spi@12d20000 { 501 spi_0: spi@12d20000 {
502 compatible = "samsung, 502 compatible = "samsung,exynos4210-spi";
503 status = "disabled"; 503 status = "disabled";
504 reg = <0x12d20000 0x10 504 reg = <0x12d20000 0x100>;
505 interrupts = <GIC_SPI 505 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
506 dmas = <&pdma0 5>, <&p 506 dmas = <&pdma0 5>, <&pdma0 4>;
507 dma-names = "tx", "rx" 507 dma-names = "tx", "rx";
508 #address-cells = <1>; 508 #address-cells = <1>;
509 #size-cells = <0>; 509 #size-cells = <0>;
510 clocks = <&clock CLK_S 510 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
511 clock-names = "spi", " 511 clock-names = "spi", "spi_busclk0";
512 pinctrl-names = "defau 512 pinctrl-names = "default";
513 pinctrl-0 = <&spi0_bus 513 pinctrl-0 = <&spi0_bus>;
514 fifo-depth = <256>; 514 fifo-depth = <256>;
515 }; 515 };
516 516
517 spi_1: spi@12d30000 { 517 spi_1: spi@12d30000 {
518 compatible = "samsung, 518 compatible = "samsung,exynos4210-spi";
519 status = "disabled"; 519 status = "disabled";
520 reg = <0x12d30000 0x10 520 reg = <0x12d30000 0x100>;
521 interrupts = <GIC_SPI 521 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
522 dmas = <&pdma1 5>, <&p 522 dmas = <&pdma1 5>, <&pdma1 4>;
523 dma-names = "tx", "rx" 523 dma-names = "tx", "rx";
524 #address-cells = <1>; 524 #address-cells = <1>;
525 #size-cells = <0>; 525 #size-cells = <0>;
526 clocks = <&clock CLK_S 526 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
527 clock-names = "spi", " 527 clock-names = "spi", "spi_busclk0";
528 pinctrl-names = "defau 528 pinctrl-names = "default";
529 pinctrl-0 = <&spi1_bus 529 pinctrl-0 = <&spi1_bus>;
530 fifo-depth = <64>; 530 fifo-depth = <64>;
531 }; 531 };
532 532
533 spi_2: spi@12d40000 { 533 spi_2: spi@12d40000 {
534 compatible = "samsung, 534 compatible = "samsung,exynos4210-spi";
535 status = "disabled"; 535 status = "disabled";
536 reg = <0x12d40000 0x10 536 reg = <0x12d40000 0x100>;
537 interrupts = <GIC_SPI 537 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
538 dmas = <&pdma0 7>, <&p 538 dmas = <&pdma0 7>, <&pdma0 6>;
539 dma-names = "tx", "rx" 539 dma-names = "tx", "rx";
540 #address-cells = <1>; 540 #address-cells = <1>;
541 #size-cells = <0>; 541 #size-cells = <0>;
542 clocks = <&clock CLK_S 542 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
543 clock-names = "spi", " 543 clock-names = "spi", "spi_busclk0";
544 pinctrl-names = "defau 544 pinctrl-names = "default";
545 pinctrl-0 = <&spi2_bus 545 pinctrl-0 = <&spi2_bus>;
546 fifo-depth = <64>; 546 fifo-depth = <64>;
547 }; 547 };
548 548
549 mmc_0: mmc@12200000 { 549 mmc_0: mmc@12200000 {
550 compatible = "samsung, 550 compatible = "samsung,exynos5250-dw-mshc";
551 interrupts = <GIC_SPI 551 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
552 #address-cells = <1>; 552 #address-cells = <1>;
553 #size-cells = <0>; 553 #size-cells = <0>;
554 reg = <0x12200000 0x10 554 reg = <0x12200000 0x1000>;
555 clocks = <&clock CLK_S 555 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
556 clock-names = "biu", " 556 clock-names = "biu", "ciu";
557 fifo-depth = <0x80>; 557 fifo-depth = <0x80>;
558 status = "disabled"; 558 status = "disabled";
559 }; 559 };
560 560
561 mmc_1: mmc@12210000 { 561 mmc_1: mmc@12210000 {
562 compatible = "samsung, 562 compatible = "samsung,exynos5250-dw-mshc";
563 interrupts = <GIC_SPI 563 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
564 #address-cells = <1>; 564 #address-cells = <1>;
565 #size-cells = <0>; 565 #size-cells = <0>;
566 reg = <0x12210000 0x10 566 reg = <0x12210000 0x1000>;
567 clocks = <&clock CLK_S 567 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
568 clock-names = "biu", " 568 clock-names = "biu", "ciu";
569 fifo-depth = <0x80>; 569 fifo-depth = <0x80>;
570 status = "disabled"; 570 status = "disabled";
571 }; 571 };
572 572
573 mmc_2: mmc@12220000 { 573 mmc_2: mmc@12220000 {
574 compatible = "samsung, 574 compatible = "samsung,exynos5250-dw-mshc";
575 interrupts = <GIC_SPI 575 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
576 #address-cells = <1>; 576 #address-cells = <1>;
577 #size-cells = <0>; 577 #size-cells = <0>;
578 reg = <0x12220000 0x10 578 reg = <0x12220000 0x1000>;
579 clocks = <&clock CLK_S 579 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
580 clock-names = "biu", " 580 clock-names = "biu", "ciu";
581 fifo-depth = <0x80>; 581 fifo-depth = <0x80>;
582 status = "disabled"; 582 status = "disabled";
583 }; 583 };
584 584
585 mmc_3: mmc@12230000 { 585 mmc_3: mmc@12230000 {
586 compatible = "samsung, 586 compatible = "samsung,exynos5250-dw-mshc";
587 reg = <0x12230000 0x10 587 reg = <0x12230000 0x1000>;
588 interrupts = <GIC_SPI 588 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
589 #address-cells = <1>; 589 #address-cells = <1>;
590 #size-cells = <0>; 590 #size-cells = <0>;
591 clocks = <&clock CLK_S 591 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
592 clock-names = "biu", " 592 clock-names = "biu", "ciu";
593 fifo-depth = <0x80>; 593 fifo-depth = <0x80>;
594 status = "disabled"; 594 status = "disabled";
595 }; 595 };
596 596
597 i2s0: i2s@3830000 { 597 i2s0: i2s@3830000 {
598 compatible = "samsung, 598 compatible = "samsung,s5pv210-i2s";
599 status = "disabled"; 599 status = "disabled";
600 reg = <0x03830000 0x10 600 reg = <0x03830000 0x100>;
601 dmas = <&pdma0 10>, 601 dmas = <&pdma0 10>,
602 <&pdma0 9>, 602 <&pdma0 9>,
603 <&pdma0 8>; 603 <&pdma0 8>;
604 dma-names = "tx", "rx" 604 dma-names = "tx", "rx", "tx-sec";
605 clocks = <&clock_audss 605 clocks = <&clock_audss EXYNOS_I2S_BUS>,
606 <&clock_audss 606 <&clock_audss EXYNOS_I2S_BUS>,
607 <&clock_audss 607 <&clock_audss EXYNOS_SCLK_I2S>;
608 clock-names = "iis", " 608 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
609 samsung,idma-addr = <0 609 samsung,idma-addr = <0x03000000>;
610 pinctrl-names = "defau 610 pinctrl-names = "default";
611 pinctrl-0 = <&i2s0_bus 611 pinctrl-0 = <&i2s0_bus>;
612 power-domains = <&pd_m 612 power-domains = <&pd_mau>;
613 #clock-cells = <1>; 613 #clock-cells = <1>;
614 #sound-dai-cells = <1> 614 #sound-dai-cells = <1>;
615 }; 615 };
616 616
617 i2s1: i2s@12d60000 { 617 i2s1: i2s@12d60000 {
618 compatible = "samsung, 618 compatible = "samsung,s3c6410-i2s";
619 status = "disabled"; 619 status = "disabled";
620 reg = <0x12d60000 0x10 620 reg = <0x12d60000 0x100>;
621 dmas = <&pdma1 12>, 621 dmas = <&pdma1 12>,
622 <&pdma1 11>; 622 <&pdma1 11>;
623 dma-names = "tx", "rx" 623 dma-names = "tx", "rx";
624 clocks = <&clock CLK_I 624 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
625 clock-names = "iis", " 625 clock-names = "iis", "i2s_opclk0";
626 pinctrl-names = "defau 626 pinctrl-names = "default";
627 pinctrl-0 = <&i2s1_bus 627 pinctrl-0 = <&i2s1_bus>;
628 power-domains = <&pd_m 628 power-domains = <&pd_mau>;
629 #sound-dai-cells = <1> 629 #sound-dai-cells = <1>;
630 }; 630 };
631 631
632 i2s2: i2s@12d70000 { 632 i2s2: i2s@12d70000 {
633 compatible = "samsung, 633 compatible = "samsung,s3c6410-i2s";
634 status = "disabled"; 634 status = "disabled";
635 reg = <0x12d70000 0x10 635 reg = <0x12d70000 0x100>;
636 dmas = <&pdma0 12>, 636 dmas = <&pdma0 12>,
637 <&pdma0 11>; 637 <&pdma0 11>;
638 dma-names = "tx", "rx" 638 dma-names = "tx", "rx";
639 clocks = <&clock CLK_I 639 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
640 clock-names = "iis", " 640 clock-names = "iis", "i2s_opclk0";
641 pinctrl-names = "defau 641 pinctrl-names = "default";
642 pinctrl-0 = <&i2s2_bus 642 pinctrl-0 = <&i2s2_bus>;
643 power-domains = <&pd_m 643 power-domains = <&pd_mau>;
644 #sound-dai-cells = <1> 644 #sound-dai-cells = <1>;
645 }; 645 };
646 646
647 usbdrd: usb@12000000 { 647 usbdrd: usb@12000000 {
648 compatible = "samsung, 648 compatible = "samsung,exynos5250-dwusb3";
649 clocks = <&clock CLK_U 649 clocks = <&clock CLK_USB3>;
650 clock-names = "usbdrd3 650 clock-names = "usbdrd30";
651 #address-cells = <1>; 651 #address-cells = <1>;
652 #size-cells = <1>; 652 #size-cells = <1>;
653 ranges = <0x0 0x120000 653 ranges = <0x0 0x12000000 0x10000>;
654 654
655 usbdrd_dwc3: usb@0 { 655 usbdrd_dwc3: usb@0 {
656 compatible = " 656 compatible = "snps,dwc3";
657 reg = <0x0 0x1 657 reg = <0x0 0x10000>;
658 interrupts = < 658 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
659 phys = <&usbdr 659 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
660 phy-names = "u 660 phy-names = "usb2-phy", "usb3-phy";
661 }; 661 };
662 }; 662 };
663 663
664 usbdrd_phy: phy@12100000 { 664 usbdrd_phy: phy@12100000 {
665 compatible = "samsung, 665 compatible = "samsung,exynos5250-usbdrd-phy";
666 reg = <0x12100000 0x10 666 reg = <0x12100000 0x100>;
667 clocks = <&clock CLK_U 667 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
668 clock-names = "phy", " 668 clock-names = "phy", "ref";
669 samsung,pmu-syscon = < 669 samsung,pmu-syscon = <&pmu_system_controller>;
670 #phy-cells = <1>; 670 #phy-cells = <1>;
671 }; 671 };
672 672
673 ehci: usb@12110000 { 673 ehci: usb@12110000 {
674 compatible = "samsung, 674 compatible = "samsung,exynos4210-ehci";
675 reg = <0x12110000 0x10 675 reg = <0x12110000 0x100>;
676 interrupts = <GIC_SPI 676 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
677 677
678 clocks = <&clock CLK_U 678 clocks = <&clock CLK_USB2>;
679 clock-names = "usbhost 679 clock-names = "usbhost";
680 phys = <&usb2_phy_gen 680 phys = <&usb2_phy_gen 1>;
681 phy-names = "host"; 681 phy-names = "host";
682 }; 682 };
683 683
684 ohci: usb@12120000 { 684 ohci: usb@12120000 {
685 compatible = "samsung, 685 compatible = "samsung,exynos4210-ohci";
686 reg = <0x12120000 0x10 686 reg = <0x12120000 0x100>;
687 interrupts = <GIC_SPI 687 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
688 688
689 clocks = <&clock CLK_U 689 clocks = <&clock CLK_USB2>;
690 clock-names = "usbhost 690 clock-names = "usbhost";
691 phys = <&usb2_phy_gen 691 phys = <&usb2_phy_gen 1>;
692 phy-names = "host"; 692 phy-names = "host";
693 }; 693 };
694 694
695 usb2_phy_gen: phy@12130000 { 695 usb2_phy_gen: phy@12130000 {
696 compatible = "samsung, 696 compatible = "samsung,exynos5250-usb2-phy";
697 reg = <0x12130000 0x10 697 reg = <0x12130000 0x100>;
698 clocks = <&clock CLK_U 698 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
699 clock-names = "phy", " 699 clock-names = "phy", "ref";
700 #phy-cells = <1>; 700 #phy-cells = <1>;
701 samsung,sysreg-phandle 701 samsung,sysreg-phandle = <&sysreg_system_controller>;
702 samsung,pmureg-phandle 702 samsung,pmureg-phandle = <&pmu_system_controller>;
703 }; 703 };
704 704
705 pdma0: dma-controller@121a0000 705 pdma0: dma-controller@121a0000 {
706 compatible = "arm,pl33 706 compatible = "arm,pl330", "arm,primecell";
707 reg = <0x121a0000 0x10 707 reg = <0x121a0000 0x1000>;
708 interrupts = <GIC_SPI 708 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
709 clocks = <&clock CLK_P 709 clocks = <&clock CLK_PDMA0>;
710 clock-names = "apb_pcl 710 clock-names = "apb_pclk";
711 #dma-cells = <1>; 711 #dma-cells = <1>;
712 }; 712 };
713 713
714 pdma1: dma-controller@121b0000 714 pdma1: dma-controller@121b0000 {
715 compatible = "arm,pl33 715 compatible = "arm,pl330", "arm,primecell";
716 reg = <0x121b0000 0x10 716 reg = <0x121b0000 0x1000>;
717 interrupts = <GIC_SPI 717 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
718 clocks = <&clock CLK_P 718 clocks = <&clock CLK_PDMA1>;
719 clock-names = "apb_pcl 719 clock-names = "apb_pclk";
720 #dma-cells = <1>; 720 #dma-cells = <1>;
721 }; 721 };
722 722
723 mdma0: dma-controller@10800000 723 mdma0: dma-controller@10800000 {
724 compatible = "arm,pl33 724 compatible = "arm,pl330", "arm,primecell";
725 reg = <0x10800000 0x10 725 reg = <0x10800000 0x1000>;
726 interrupts = <GIC_SPI 726 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
727 clocks = <&clock CLK_M 727 clocks = <&clock CLK_MDMA0>;
728 clock-names = "apb_pcl 728 clock-names = "apb_pclk";
729 #dma-cells = <1>; 729 #dma-cells = <1>;
730 }; 730 };
731 731
732 mdma1: dma-controller@11c10000 732 mdma1: dma-controller@11c10000 {
733 compatible = "arm,pl33 733 compatible = "arm,pl330", "arm,primecell";
734 reg = <0x11c10000 0x10 734 reg = <0x11c10000 0x1000>;
735 interrupts = <GIC_SPI 735 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
736 clocks = <&clock CLK_M 736 clocks = <&clock CLK_MDMA1>;
737 clock-names = "apb_pcl 737 clock-names = "apb_pclk";
738 #dma-cells = <1>; 738 #dma-cells = <1>;
739 }; 739 };
740 740
741 gsc_0: gsc@13e00000 { 741 gsc_0: gsc@13e00000 {
742 compatible = "samsung, 742 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
743 reg = <0x13e00000 0x10 743 reg = <0x13e00000 0x1000>;
744 interrupts = <GIC_SPI 744 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
745 power-domains = <&pd_g 745 power-domains = <&pd_gsc>;
746 clocks = <&clock CLK_G 746 clocks = <&clock CLK_GSCL0>;
747 clock-names = "gscl"; 747 clock-names = "gscl";
748 iommus = <&sysmmu_gsc0 748 iommus = <&sysmmu_gsc0>;
749 }; 749 };
750 750
751 gsc_1: gsc@13e10000 { 751 gsc_1: gsc@13e10000 {
752 compatible = "samsung, 752 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
753 reg = <0x13e10000 0x10 753 reg = <0x13e10000 0x1000>;
754 interrupts = <GIC_SPI 754 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
755 power-domains = <&pd_g 755 power-domains = <&pd_gsc>;
756 clocks = <&clock CLK_G 756 clocks = <&clock CLK_GSCL1>;
757 clock-names = "gscl"; 757 clock-names = "gscl";
758 iommus = <&sysmmu_gsc1 758 iommus = <&sysmmu_gsc1>;
759 }; 759 };
760 760
761 gsc_2: gsc@13e20000 { 761 gsc_2: gsc@13e20000 {
762 compatible = "samsung, 762 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
763 reg = <0x13e20000 0x10 763 reg = <0x13e20000 0x1000>;
764 interrupts = <GIC_SPI 764 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
765 power-domains = <&pd_g 765 power-domains = <&pd_gsc>;
766 clocks = <&clock CLK_G 766 clocks = <&clock CLK_GSCL2>;
767 clock-names = "gscl"; 767 clock-names = "gscl";
768 iommus = <&sysmmu_gsc2 768 iommus = <&sysmmu_gsc2>;
769 }; 769 };
770 770
771 gsc_3: gsc@13e30000 { 771 gsc_3: gsc@13e30000 {
772 compatible = "samsung, 772 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
773 reg = <0x13e30000 0x10 773 reg = <0x13e30000 0x1000>;
774 interrupts = <GIC_SPI 774 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
775 power-domains = <&pd_g 775 power-domains = <&pd_gsc>;
776 clocks = <&clock CLK_G 776 clocks = <&clock CLK_GSCL3>;
777 clock-names = "gscl"; 777 clock-names = "gscl";
778 iommus = <&sysmmu_gsc3 778 iommus = <&sysmmu_gsc3>;
779 }; 779 };
780 780
781 hdmi: hdmi@14530000 { 781 hdmi: hdmi@14530000 {
782 compatible = "samsung, 782 compatible = "samsung,exynos4212-hdmi";
783 reg = <0x14530000 0x70 783 reg = <0x14530000 0x70000>;
784 power-domains = <&pd_d 784 power-domains = <&pd_disp1>;
785 interrupts = <GIC_SPI 785 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
786 clocks = <&clock CLK_H 786 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
787 <&clock CLK_S 787 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
788 <&clock CLK_M 788 <&clock CLK_MOUT_HDMI>;
789 clock-names = "hdmi", 789 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
790 "sclk_ 790 "sclk_hdmiphy", "mout_hdmi";
791 samsung,syscon-phandle 791 samsung,syscon-phandle = <&pmu_system_controller>;
792 phy = <&hdmiphy>; 792 phy = <&hdmiphy>;
793 #sound-dai-cells = <0> 793 #sound-dai-cells = <0>;
794 status = "disabled"; 794 status = "disabled";
795 }; 795 };
796 796
797 hdmicec: cec@101b0000 { 797 hdmicec: cec@101b0000 {
798 compatible = "samsung, 798 compatible = "samsung,s5p-cec";
799 reg = <0x101b0000 0x20 799 reg = <0x101b0000 0x200>;
800 interrupts = <GIC_SPI 800 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
801 clocks = <&clock CLK_H 801 clocks = <&clock CLK_HDMI_CEC>;
802 clock-names = "hdmicec 802 clock-names = "hdmicec";
803 samsung,syscon-phandle 803 samsung,syscon-phandle = <&pmu_system_controller>;
804 hdmi-phandle = <&hdmi> 804 hdmi-phandle = <&hdmi>;
805 pinctrl-names = "defau 805 pinctrl-names = "default";
806 pinctrl-0 = <&hdmi_cec 806 pinctrl-0 = <&hdmi_cec>;
807 status = "disabled"; 807 status = "disabled";
808 }; 808 };
809 809
810 mixer: mixer@14450000 { 810 mixer: mixer@14450000 {
811 compatible = "samsung, 811 compatible = "samsung,exynos5250-mixer";
812 reg = <0x14450000 0x10 812 reg = <0x14450000 0x10000>;
813 power-domains = <&pd_d 813 power-domains = <&pd_disp1>;
814 interrupts = <GIC_SPI 814 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
815 clocks = <&clock CLK_M 815 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
816 <&clock CLK_S 816 <&clock CLK_SCLK_HDMI>;
817 clock-names = "mixer", 817 clock-names = "mixer", "hdmi", "sclk_hdmi";
818 iommus = <&sysmmu_tv>; 818 iommus = <&sysmmu_tv>;
819 status = "disabled"; 819 status = "disabled";
820 }; 820 };
821 821
822 dsi_0: dsi@14500000 { 822 dsi_0: dsi@14500000 {
823 compatible = "samsung, 823 compatible = "samsung,exynos4210-mipi-dsi";
824 reg = <0x14500000 0x10 824 reg = <0x14500000 0x10000>;
825 interrupts = <GIC_SPI 825 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
826 samsung,power-domain = 826 samsung,power-domain = <&pd_disp1>;
827 phys = <&mipi_phy 3>; 827 phys = <&mipi_phy 3>;
828 phy-names = "dsim"; 828 phy-names = "dsim";
829 clocks = <&clock CLK_D 829 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI1>;
830 clock-names = "bus_clk 830 clock-names = "bus_clk", "sclk_mipi";
831 status = "disabled"; 831 status = "disabled";
832 #address-cells = <1>; 832 #address-cells = <1>;
833 #size-cells = <0>; 833 #size-cells = <0>;
834 }; 834 };
835 835
836 adc: adc@12d10000 { 836 adc: adc@12d10000 {
837 compatible = "samsung, 837 compatible = "samsung,exynos-adc-v1";
838 reg = <0x12d10000 0x10 838 reg = <0x12d10000 0x100>;
839 interrupts = <GIC_SPI 839 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
840 clocks = <&clock CLK_A 840 clocks = <&clock CLK_ADC>;
841 clock-names = "adc"; 841 clock-names = "adc";
842 #io-channel-cells = <1 842 #io-channel-cells = <1>;
843 samsung,syscon-phandle 843 samsung,syscon-phandle = <&pmu_system_controller>;
844 status = "disabled"; 844 status = "disabled";
845 }; 845 };
846 846
847 sysmmu_g2d: sysmmu@10a60000 { 847 sysmmu_g2d: sysmmu@10a60000 {
848 compatible = "samsung, 848 compatible = "samsung,exynos-sysmmu";
849 reg = <0x10a60000 0x10 849 reg = <0x10a60000 0x1000>;
850 interrupt-parent = <&c 850 interrupt-parent = <&combiner>;
851 interrupts = <24 5>; 851 interrupts = <24 5>;
852 clock-names = "sysmmu" 852 clock-names = "sysmmu", "master";
853 clocks = <&clock CLK_S 853 clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
854 #iommu-cells = <0>; 854 #iommu-cells = <0>;
855 }; 855 };
856 856
857 sysmmu_mfc_r: sysmmu@11200000 857 sysmmu_mfc_r: sysmmu@11200000 {
858 compatible = "samsung, 858 compatible = "samsung,exynos-sysmmu";
859 reg = <0x11200000 0x10 859 reg = <0x11200000 0x1000>;
860 interrupt-parent = <&c 860 interrupt-parent = <&combiner>;
861 interrupts = <6 2>; 861 interrupts = <6 2>;
862 power-domains = <&pd_m 862 power-domains = <&pd_mfc>;
863 clock-names = "sysmmu" 863 clock-names = "sysmmu", "master";
864 clocks = <&clock CLK_S 864 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
865 #iommu-cells = <0>; 865 #iommu-cells = <0>;
866 }; 866 };
867 867
868 sysmmu_mfc_l: sysmmu@11210000 868 sysmmu_mfc_l: sysmmu@11210000 {
869 compatible = "samsung, 869 compatible = "samsung,exynos-sysmmu";
870 reg = <0x11210000 0x10 870 reg = <0x11210000 0x1000>;
871 interrupt-parent = <&c 871 interrupt-parent = <&combiner>;
872 interrupts = <8 5>; 872 interrupts = <8 5>;
873 power-domains = <&pd_m 873 power-domains = <&pd_mfc>;
874 clock-names = "sysmmu" 874 clock-names = "sysmmu", "master";
875 clocks = <&clock CLK_S 875 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
876 #iommu-cells = <0>; 876 #iommu-cells = <0>;
877 }; 877 };
878 878
879 sysmmu_rotator: sysmmu@11d4000 879 sysmmu_rotator: sysmmu@11d40000 {
880 compatible = "samsung, 880 compatible = "samsung,exynos-sysmmu";
881 reg = <0x11d40000 0x10 881 reg = <0x11d40000 0x1000>;
882 interrupt-parent = <&c 882 interrupt-parent = <&combiner>;
883 interrupts = <4 0>; 883 interrupts = <4 0>;
884 clock-names = "sysmmu" 884 clock-names = "sysmmu", "master";
885 clocks = <&clock CLK_S 885 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
886 #iommu-cells = <0>; 886 #iommu-cells = <0>;
887 }; 887 };
888 888
889 sysmmu_jpeg: sysmmu@11f20000 { 889 sysmmu_jpeg: sysmmu@11f20000 {
890 compatible = "samsung, 890 compatible = "samsung,exynos-sysmmu";
891 reg = <0x11f20000 0x10 891 reg = <0x11f20000 0x1000>;
892 interrupt-parent = <&c 892 interrupt-parent = <&combiner>;
893 interrupts = <4 2>; 893 interrupts = <4 2>;
894 power-domains = <&pd_g 894 power-domains = <&pd_gsc>;
895 clock-names = "sysmmu" 895 clock-names = "sysmmu", "master";
896 clocks = <&clock CLK_S 896 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
897 #iommu-cells = <0>; 897 #iommu-cells = <0>;
898 }; 898 };
899 899
900 sysmmu_fimc_isp: sysmmu@132600 900 sysmmu_fimc_isp: sysmmu@13260000 {
901 compatible = "samsung, 901 compatible = "samsung,exynos-sysmmu";
902 reg = <0x13260000 0x10 902 reg = <0x13260000 0x1000>;
903 interrupt-parent = <&c 903 interrupt-parent = <&combiner>;
904 interrupts = <10 6>; 904 interrupts = <10 6>;
905 clock-names = "sysmmu" 905 clock-names = "sysmmu";
906 clocks = <&clock CLK_S 906 clocks = <&clock CLK_SMMU_FIMC_ISP>;
907 #iommu-cells = <0>; 907 #iommu-cells = <0>;
908 }; 908 };
909 909
910 sysmmu_fimc_drc: sysmmu@132700 910 sysmmu_fimc_drc: sysmmu@13270000 {
911 compatible = "samsung, 911 compatible = "samsung,exynos-sysmmu";
912 reg = <0x13270000 0x10 912 reg = <0x13270000 0x1000>;
913 interrupt-parent = <&c 913 interrupt-parent = <&combiner>;
914 interrupts = <11 6>; 914 interrupts = <11 6>;
915 clock-names = "sysmmu" 915 clock-names = "sysmmu";
916 clocks = <&clock CLK_S 916 clocks = <&clock CLK_SMMU_FIMC_DRC>;
917 #iommu-cells = <0>; 917 #iommu-cells = <0>;
918 }; 918 };
919 919
920 sysmmu_fimc_fd: sysmmu@132a000 920 sysmmu_fimc_fd: sysmmu@132a0000 {
921 compatible = "samsung, 921 compatible = "samsung,exynos-sysmmu";
922 reg = <0x132a0000 0x10 922 reg = <0x132a0000 0x1000>;
923 interrupt-parent = <&c 923 interrupt-parent = <&combiner>;
924 interrupts = <5 0>; 924 interrupts = <5 0>;
925 clock-names = "sysmmu" 925 clock-names = "sysmmu";
926 clocks = <&clock CLK_S 926 clocks = <&clock CLK_SMMU_FIMC_FD>;
927 #iommu-cells = <0>; 927 #iommu-cells = <0>;
928 }; 928 };
929 929
930 sysmmu_fimc_scc: sysmmu@132800 930 sysmmu_fimc_scc: sysmmu@13280000 {
931 compatible = "samsung, 931 compatible = "samsung,exynos-sysmmu";
932 reg = <0x13280000 0x10 932 reg = <0x13280000 0x1000>;
933 interrupt-parent = <&c 933 interrupt-parent = <&combiner>;
934 interrupts = <5 2>; 934 interrupts = <5 2>;
935 clock-names = "sysmmu" 935 clock-names = "sysmmu";
936 clocks = <&clock CLK_S 936 clocks = <&clock CLK_SMMU_FIMC_SCC>;
937 #iommu-cells = <0>; 937 #iommu-cells = <0>;
938 }; 938 };
939 939
940 sysmmu_fimc_scp: sysmmu@132900 940 sysmmu_fimc_scp: sysmmu@13290000 {
941 compatible = "samsung, 941 compatible = "samsung,exynos-sysmmu";
942 reg = <0x13290000 0x10 942 reg = <0x13290000 0x1000>;
943 interrupt-parent = <&c 943 interrupt-parent = <&combiner>;
944 interrupts = <3 6>; 944 interrupts = <3 6>;
945 clock-names = "sysmmu" 945 clock-names = "sysmmu";
946 clocks = <&clock CLK_S 946 clocks = <&clock CLK_SMMU_FIMC_SCP>;
947 #iommu-cells = <0>; 947 #iommu-cells = <0>;
948 }; 948 };
949 949
950 sysmmu_fimc_mcuctl: sysmmu@132 950 sysmmu_fimc_mcuctl: sysmmu@132b0000 {
951 compatible = "samsung, 951 compatible = "samsung,exynos-sysmmu";
952 reg = <0x132b0000 0x10 952 reg = <0x132b0000 0x1000>;
953 interrupt-parent = <&c 953 interrupt-parent = <&combiner>;
954 interrupts = <5 4>; 954 interrupts = <5 4>;
955 clock-names = "sysmmu" 955 clock-names = "sysmmu";
956 clocks = <&clock CLK_S 956 clocks = <&clock CLK_SMMU_FIMC_MCU>;
957 #iommu-cells = <0>; 957 #iommu-cells = <0>;
958 }; 958 };
959 959
960 sysmmu_fimc_odc: sysmmu@132c00 960 sysmmu_fimc_odc: sysmmu@132c0000 {
961 compatible = "samsung, 961 compatible = "samsung,exynos-sysmmu";
962 reg = <0x132c0000 0x10 962 reg = <0x132c0000 0x1000>;
963 interrupt-parent = <&c 963 interrupt-parent = <&combiner>;
964 interrupts = <11 0>; 964 interrupts = <11 0>;
965 clock-names = "sysmmu" 965 clock-names = "sysmmu";
966 clocks = <&clock CLK_S 966 clocks = <&clock CLK_SMMU_FIMC_ODC>;
967 #iommu-cells = <0>; 967 #iommu-cells = <0>;
968 }; 968 };
969 969
970 sysmmu_fimc_dis0: sysmmu@132d0 970 sysmmu_fimc_dis0: sysmmu@132d0000 {
971 compatible = "samsung, 971 compatible = "samsung,exynos-sysmmu";
972 reg = <0x132d0000 0x10 972 reg = <0x132d0000 0x1000>;
973 interrupt-parent = <&c 973 interrupt-parent = <&combiner>;
974 interrupts = <10 4>; 974 interrupts = <10 4>;
975 clock-names = "sysmmu" 975 clock-names = "sysmmu";
976 clocks = <&clock CLK_S 976 clocks = <&clock CLK_SMMU_FIMC_DIS0>;
977 #iommu-cells = <0>; 977 #iommu-cells = <0>;
978 }; 978 };
979 979
980 sysmmu_fimc_dis1: sysmmu@132e0 980 sysmmu_fimc_dis1: sysmmu@132e0000 {
981 compatible = "samsung, 981 compatible = "samsung,exynos-sysmmu";
982 reg = <0x132e0000 0x10 982 reg = <0x132e0000 0x1000>;
983 interrupt-parent = <&c 983 interrupt-parent = <&combiner>;
984 interrupts = <9 4>; 984 interrupts = <9 4>;
985 clock-names = "sysmmu" 985 clock-names = "sysmmu";
986 clocks = <&clock CLK_S 986 clocks = <&clock CLK_SMMU_FIMC_DIS1>;
987 #iommu-cells = <0>; 987 #iommu-cells = <0>;
988 }; 988 };
989 989
990 sysmmu_fimc_3dnr: sysmmu@132f0 990 sysmmu_fimc_3dnr: sysmmu@132f0000 {
991 compatible = "samsung, 991 compatible = "samsung,exynos-sysmmu";
992 reg = <0x132f0000 0x10 992 reg = <0x132f0000 0x1000>;
993 interrupt-parent = <&c 993 interrupt-parent = <&combiner>;
994 interrupts = <5 6>; 994 interrupts = <5 6>;
995 clock-names = "sysmmu" 995 clock-names = "sysmmu";
996 clocks = <&clock CLK_S 996 clocks = <&clock CLK_SMMU_FIMC_3DNR>;
997 #iommu-cells = <0>; 997 #iommu-cells = <0>;
998 }; 998 };
999 999
1000 sysmmu_fimc_lite0: sysmmu@13c 1000 sysmmu_fimc_lite0: sysmmu@13c40000 {
1001 compatible = "samsung 1001 compatible = "samsung,exynos-sysmmu";
1002 reg = <0x13c40000 0x1 1002 reg = <0x13c40000 0x1000>;
1003 interrupt-parent = <& 1003 interrupt-parent = <&combiner>;
1004 interrupts = <3 4>; 1004 interrupts = <3 4>;
1005 power-domains = <&pd_ 1005 power-domains = <&pd_gsc>;
1006 clock-names = "sysmmu 1006 clock-names = "sysmmu", "master";
1007 clocks = <&clock CLK_ 1007 clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
1008 #iommu-cells = <0>; 1008 #iommu-cells = <0>;
1009 }; 1009 };
1010 1010
1011 sysmmu_fimc_lite1: sysmmu@13c 1011 sysmmu_fimc_lite1: sysmmu@13c50000 {
1012 compatible = "samsung 1012 compatible = "samsung,exynos-sysmmu";
1013 reg = <0x13c50000 0x1 1013 reg = <0x13c50000 0x1000>;
1014 interrupt-parent = <& 1014 interrupt-parent = <&combiner>;
1015 interrupts = <24 1>; 1015 interrupts = <24 1>;
1016 power-domains = <&pd_ 1016 power-domains = <&pd_gsc>;
1017 clock-names = "sysmmu 1017 clock-names = "sysmmu", "master";
1018 clocks = <&clock CLK_ 1018 clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
1019 #iommu-cells = <0>; 1019 #iommu-cells = <0>;
1020 }; 1020 };
1021 1021
1022 sysmmu_gsc0: sysmmu@13e80000 1022 sysmmu_gsc0: sysmmu@13e80000 {
1023 compatible = "samsung 1023 compatible = "samsung,exynos-sysmmu";
1024 reg = <0x13e80000 0x1 1024 reg = <0x13e80000 0x1000>;
1025 interrupt-parent = <& 1025 interrupt-parent = <&combiner>;
1026 interrupts = <2 0>; 1026 interrupts = <2 0>;
1027 power-domains = <&pd_ 1027 power-domains = <&pd_gsc>;
1028 clock-names = "sysmmu 1028 clock-names = "sysmmu", "master";
1029 clocks = <&clock CLK_ 1029 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
1030 #iommu-cells = <0>; 1030 #iommu-cells = <0>;
1031 }; 1031 };
1032 1032
1033 sysmmu_gsc1: sysmmu@13e90000 1033 sysmmu_gsc1: sysmmu@13e90000 {
1034 compatible = "samsung 1034 compatible = "samsung,exynos-sysmmu";
1035 reg = <0x13e90000 0x1 1035 reg = <0x13e90000 0x1000>;
1036 interrupt-parent = <& 1036 interrupt-parent = <&combiner>;
1037 interrupts = <2 2>; 1037 interrupts = <2 2>;
1038 power-domains = <&pd_ 1038 power-domains = <&pd_gsc>;
1039 clock-names = "sysmmu 1039 clock-names = "sysmmu", "master";
1040 clocks = <&clock CLK_ 1040 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
1041 #iommu-cells = <0>; 1041 #iommu-cells = <0>;
1042 }; 1042 };
1043 1043
1044 sysmmu_gsc2: sysmmu@13ea0000 1044 sysmmu_gsc2: sysmmu@13ea0000 {
1045 compatible = "samsung 1045 compatible = "samsung,exynos-sysmmu";
1046 reg = <0x13ea0000 0x1 1046 reg = <0x13ea0000 0x1000>;
1047 interrupt-parent = <& 1047 interrupt-parent = <&combiner>;
1048 interrupts = <2 4>; 1048 interrupts = <2 4>;
1049 power-domains = <&pd_ 1049 power-domains = <&pd_gsc>;
1050 clock-names = "sysmmu 1050 clock-names = "sysmmu", "master";
1051 clocks = <&clock CLK_ 1051 clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
1052 #iommu-cells = <0>; 1052 #iommu-cells = <0>;
1053 }; 1053 };
1054 1054
1055 sysmmu_gsc3: sysmmu@13eb0000 1055 sysmmu_gsc3: sysmmu@13eb0000 {
1056 compatible = "samsung 1056 compatible = "samsung,exynos-sysmmu";
1057 reg = <0x13eb0000 0x1 1057 reg = <0x13eb0000 0x1000>;
1058 interrupt-parent = <& 1058 interrupt-parent = <&combiner>;
1059 interrupts = <2 6>; 1059 interrupts = <2 6>;
1060 power-domains = <&pd_ 1060 power-domains = <&pd_gsc>;
1061 clock-names = "sysmmu 1061 clock-names = "sysmmu", "master";
1062 clocks = <&clock CLK_ 1062 clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
1063 #iommu-cells = <0>; 1063 #iommu-cells = <0>;
1064 }; 1064 };
1065 1065
1066 sysmmu_fimd1: sysmmu@14640000 1066 sysmmu_fimd1: sysmmu@14640000 {
1067 compatible = "samsung 1067 compatible = "samsung,exynos-sysmmu";
1068 reg = <0x14640000 0x1 1068 reg = <0x14640000 0x1000>;
1069 interrupt-parent = <& 1069 interrupt-parent = <&combiner>;
1070 interrupts = <3 2>; 1070 interrupts = <3 2>;
1071 power-domains = <&pd_ 1071 power-domains = <&pd_disp1>;
1072 clock-names = "sysmmu 1072 clock-names = "sysmmu", "master";
1073 clocks = <&clock CLK_ 1073 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
1074 #iommu-cells = <0>; 1074 #iommu-cells = <0>;
1075 }; 1075 };
1076 1076
1077 sysmmu_tv: sysmmu@14650000 { 1077 sysmmu_tv: sysmmu@14650000 {
1078 compatible = "samsung 1078 compatible = "samsung,exynos-sysmmu";
1079 reg = <0x14650000 0x1 1079 reg = <0x14650000 0x1000>;
1080 interrupt-parent = <& 1080 interrupt-parent = <&combiner>;
1081 interrupts = <7 4>; 1081 interrupts = <7 4>;
1082 power-domains = <&pd_ 1082 power-domains = <&pd_disp1>;
1083 clock-names = "sysmmu 1083 clock-names = "sysmmu", "master";
1084 clocks = <&clock CLK_ 1084 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
1085 #iommu-cells = <0>; 1085 #iommu-cells = <0>;
1086 }; 1086 };
1087 }; 1087 };
1088 1088
1089 timer { 1089 timer {
1090 compatible = "arm,armv7-timer 1090 compatible = "arm,armv7-timer";
1091 interrupts = <GIC_PPI 13 (GIC 1091 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1092 <GIC_PPI 14 (GIC 1092 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1093 <GIC_PPI 11 (GIC 1093 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1094 <GIC_PPI 10 (GIC 1094 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1095 /* 1095 /*
1096 * Unfortunately we need this 1096 * Unfortunately we need this since some versions
1097 * of U-Boot on Exynos don't 1097 * of U-Boot on Exynos don't set the CNTFRQ register,
1098 * so we need the value from 1098 * so we need the value from DT.
1099 */ 1099 */
1100 clock-frequency = <24000000>; 1100 clock-frequency = <24000000>;
1101 }; 1101 };
1102 }; 1102 };
1103 1103
1104 &cpu_thermal { 1104 &cpu_thermal {
1105 polling-delay-passive = <0>; 1105 polling-delay-passive = <0>;
1106 polling-delay = <0>; 1106 polling-delay = <0>;
1107 thermal-sensors = <&tmu>; 1107 thermal-sensors = <&tmu>;
1108 1108
1109 cooling-maps { 1109 cooling-maps {
1110 map0 { 1110 map0 {
1111 /* Corresponds to 800 1111 /* Corresponds to 800MHz at freq_table */
1112 cooling-device = <&cp 1112 cooling-device = <&cpu0 9 9>, <&cpu1 9 9>;
1113 }; 1113 };
1114 map1 { 1114 map1 {
1115 /* Corresponds to 200 1115 /* Corresponds to 200MHz at freq_table */
1116 cooling-device = <&cp 1116 cooling-device = <&cpu0 15 15>,
1117 <&cp 1117 <&cpu1 15 15>;
1118 }; 1118 };
1119 }; 1119 };
1120 }; 1120 };
1121 1121
1122 &dp { 1122 &dp {
1123 power-domains = <&pd_disp1>; 1123 power-domains = <&pd_disp1>;
1124 clocks = <&clock CLK_DP>; 1124 clocks = <&clock CLK_DP>;
1125 clock-names = "dp"; 1125 clock-names = "dp";
1126 phys = <&dp_phy>; 1126 phys = <&dp_phy>;
1127 phy-names = "dp"; 1127 phy-names = "dp";
1128 }; 1128 };
1129 1129
1130 &fimd { 1130 &fimd {
1131 power-domains = <&pd_disp1>; 1131 power-domains = <&pd_disp1>;
1132 clocks = <&clock CLK_SCLK_FIMD1>, <&c 1132 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1133 clock-names = "sclk_fimd", "fimd"; 1133 clock-names = "sclk_fimd", "fimd";
1134 iommus = <&sysmmu_fimd1>; 1134 iommus = <&sysmmu_fimd1>;
1135 }; 1135 };
1136 1136
1137 &g2d { 1137 &g2d {
1138 iommus = <&sysmmu_g2d>; 1138 iommus = <&sysmmu_g2d>;
1139 clocks = <&clock CLK_G2D>; 1139 clocks = <&clock CLK_G2D>;
1140 clock-names = "fimg2d"; 1140 clock-names = "fimg2d";
1141 status = "okay"; 1141 status = "okay";
1142 }; 1142 };
1143 1143
1144 &i2c_0 { 1144 &i2c_0 {
1145 clocks = <&clock CLK_I2C0>; 1145 clocks = <&clock CLK_I2C0>;
1146 clock-names = "i2c"; 1146 clock-names = "i2c";
1147 pinctrl-names = "default"; 1147 pinctrl-names = "default";
1148 pinctrl-0 = <&i2c0_bus>; 1148 pinctrl-0 = <&i2c0_bus>;
1149 }; 1149 };
1150 1150
1151 &i2c_1 { 1151 &i2c_1 {
1152 clocks = <&clock CLK_I2C1>; 1152 clocks = <&clock CLK_I2C1>;
1153 clock-names = "i2c"; 1153 clock-names = "i2c";
1154 pinctrl-names = "default"; 1154 pinctrl-names = "default";
1155 pinctrl-0 = <&i2c1_bus>; 1155 pinctrl-0 = <&i2c1_bus>;
1156 }; 1156 };
1157 1157
1158 &i2c_2 { 1158 &i2c_2 {
1159 clocks = <&clock CLK_I2C2>; 1159 clocks = <&clock CLK_I2C2>;
1160 clock-names = "i2c"; 1160 clock-names = "i2c";
1161 pinctrl-names = "default"; 1161 pinctrl-names = "default";
1162 pinctrl-0 = <&i2c2_bus>; 1162 pinctrl-0 = <&i2c2_bus>;
1163 }; 1163 };
1164 1164
1165 &i2c_3 { 1165 &i2c_3 {
1166 clocks = <&clock CLK_I2C3>; 1166 clocks = <&clock CLK_I2C3>;
1167 clock-names = "i2c"; 1167 clock-names = "i2c";
1168 pinctrl-names = "default"; 1168 pinctrl-names = "default";
1169 pinctrl-0 = <&i2c3_bus>; 1169 pinctrl-0 = <&i2c3_bus>;
1170 }; 1170 };
1171 1171
1172 &prng { 1172 &prng {
1173 clocks = <&clock CLK_SSS>; 1173 clocks = <&clock CLK_SSS>;
1174 clock-names = "secss"; 1174 clock-names = "secss";
1175 }; 1175 };
1176 1176
1177 &pwm { 1177 &pwm {
1178 clocks = <&clock CLK_PWM>; 1178 clocks = <&clock CLK_PWM>;
1179 clock-names = "timers"; 1179 clock-names = "timers";
1180 }; 1180 };
1181 1181
1182 &rtc { 1182 &rtc {
1183 clocks = <&clock CLK_RTC>; 1183 clocks = <&clock CLK_RTC>;
1184 clock-names = "rtc"; 1184 clock-names = "rtc";
1185 interrupt-parent = <&pmu_system_contr 1185 interrupt-parent = <&pmu_system_controller>;
1186 status = "disabled"; 1186 status = "disabled";
1187 }; 1187 };
1188 1188
1189 &serial_0 { 1189 &serial_0 {
1190 clocks = <&clock CLK_UART0>, <&clock 1190 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1191 clock-names = "uart", "clk_uart_baud0 1191 clock-names = "uart", "clk_uart_baud0";
1192 dmas = <&pdma0 13>, <&pdma0 14>; 1192 dmas = <&pdma0 13>, <&pdma0 14>;
1193 dma-names = "rx", "tx"; 1193 dma-names = "rx", "tx";
1194 }; 1194 };
1195 1195
1196 &serial_1 { 1196 &serial_1 {
1197 clocks = <&clock CLK_UART1>, <&clock 1197 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1198 clock-names = "uart", "clk_uart_baud0 1198 clock-names = "uart", "clk_uart_baud0";
1199 dmas = <&pdma1 15>, <&pdma1 16>; 1199 dmas = <&pdma1 15>, <&pdma1 16>;
1200 dma-names = "rx", "tx"; 1200 dma-names = "rx", "tx";
1201 }; 1201 };
1202 1202
1203 &serial_2 { 1203 &serial_2 {
1204 clocks = <&clock CLK_UART2>, <&clock 1204 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1205 clock-names = "uart", "clk_uart_baud0 1205 clock-names = "uart", "clk_uart_baud0";
1206 dmas = <&pdma0 15>, <&pdma0 16>; 1206 dmas = <&pdma0 15>, <&pdma0 16>;
1207 dma-names = "rx", "tx"; 1207 dma-names = "rx", "tx";
1208 }; 1208 };
1209 1209
1210 &serial_3 { 1210 &serial_3 {
1211 clocks = <&clock CLK_UART3>, <&clock 1211 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1212 clock-names = "uart", "clk_uart_baud0 1212 clock-names = "uart", "clk_uart_baud0";
1213 dmas = <&pdma1 17>, <&pdma1 18>; 1213 dmas = <&pdma1 17>, <&pdma1 18>;
1214 dma-names = "rx", "tx"; 1214 dma-names = "rx", "tx";
1215 }; 1215 };
1216 1216
1217 &sss { 1217 &sss {
1218 clocks = <&clock CLK_SSS>; 1218 clocks = <&clock CLK_SSS>;
1219 clock-names = "secss"; 1219 clock-names = "secss";
1220 }; 1220 };
1221 1221
1222 &trng { 1222 &trng {
1223 clocks = <&clock CLK_SSS>; 1223 clocks = <&clock CLK_SSS>;
1224 clock-names = "secss"; 1224 clock-names = "secss";
1225 }; 1225 };
1226 1226
1227 #include "exynos5250-pinctrl.dtsi" 1227 #include "exynos5250-pinctrl.dtsi"
1228 #include "exynos-syscon-restart.dtsi" 1228 #include "exynos-syscon-restart.dtsi"
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