1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Samsung Exynos5250 SoC device tree source
4 *
5 * Copyright (c) 2012 Samsung Electronics Co.,
6 * http://www.samsung.com
7 *
8 * Samsung Exynos5250 SoC device nodes are lis
9 * Exynos5250 based board files can include th
10 * values for board specific bindings.
11 *
12 * Note: This file does not include device nod
13 * Exynos5250 SoC. As device tree coverage for
14 * additional nodes can be added to this file.
15 */
16
17 #include <dt-bindings/clock/exynos5250.h>
18 #include "exynos5.dtsi"
19 #include "exynos4-cpu-thermal.dtsi"
20 #include <dt-bindings/clock/exynos-audss-clk.h
21
22 / {
23 compatible = "samsung,exynos5250", "sa
24
25 aliases {
26 spi0 = &spi_0;
27 spi1 = &spi_1;
28 spi2 = &spi_2;
29 gsc0 = &gsc_0;
30 gsc1 = &gsc_1;
31 gsc2 = &gsc_2;
32 gsc3 = &gsc_3;
33 i2c4 = &i2c_4;
34 i2c5 = &i2c_5;
35 i2c6 = &i2c_6;
36 i2c7 = &i2c_7;
37 i2c8 = &i2c_8;
38 i2c9 = &i2c_9;
39 pinctrl0 = &pinctrl_0;
40 pinctrl1 = &pinctrl_1;
41 pinctrl2 = &pinctrl_2;
42 pinctrl3 = &pinctrl_3;
43 };
44
45 cpus {
46 #address-cells = <1>;
47 #size-cells = <0>;
48
49 cpu-map {
50 cluster0 {
51 core0 {
52 cpu =
53 };
54 core1 {
55 cpu =
56 };
57 };
58 };
59
60 cpu0: cpu@0 {
61 device_type = "cpu";
62 compatible = "arm,cort
63 reg = <0>;
64 clocks = <&clock CLK_A
65 clock-names = "cpu";
66 operating-points-v2 =
67 #cooling-cells = <2>;
68 };
69 cpu1: cpu@1 {
70 device_type = "cpu";
71 compatible = "arm,cort
72 reg = <1>;
73 clocks = <&clock CLK_A
74 clock-names = "cpu";
75 operating-points-v2 =
76 #cooling-cells = <2>;
77 };
78 };
79
80 cpu0_opp_table: opp-table-0 {
81 compatible = "operating-points
82 opp-shared;
83
84 opp-200000000 {
85 opp-hz = /bits/ 64 <20
86 opp-microvolt = <92500
87 clock-latency-ns = <14
88 };
89 opp-300000000 {
90 opp-hz = /bits/ 64 <30
91 opp-microvolt = <93750
92 clock-latency-ns = <14
93 };
94 opp-400000000 {
95 opp-hz = /bits/ 64 <40
96 opp-microvolt = <95000
97 clock-latency-ns = <14
98 };
99 opp-500000000 {
100 opp-hz = /bits/ 64 <50
101 opp-microvolt = <97500
102 clock-latency-ns = <14
103 };
104 opp-600000000 {
105 opp-hz = /bits/ 64 <60
106 opp-microvolt = <10000
107 clock-latency-ns = <14
108 };
109 opp-700000000 {
110 opp-hz = /bits/ 64 <70
111 opp-microvolt = <10125
112 clock-latency-ns = <14
113 };
114 opp-800000000 {
115 opp-hz = /bits/ 64 <80
116 opp-microvolt = <10250
117 clock-latency-ns = <14
118 };
119 opp-900000000 {
120 opp-hz = /bits/ 64 <90
121 opp-microvolt = <10500
122 clock-latency-ns = <14
123 };
124 opp-1000000000 {
125 opp-hz = /bits/ 64 <10
126 opp-microvolt = <10750
127 clock-latency-ns = <14
128 opp-suspend;
129 };
130 opp-1100000000 {
131 opp-hz = /bits/ 64 <11
132 opp-microvolt = <11000
133 clock-latency-ns = <14
134 };
135 opp-1200000000 {
136 opp-hz = /bits/ 64 <12
137 opp-microvolt = <11250
138 clock-latency-ns = <14
139 };
140 opp-1300000000 {
141 opp-hz = /bits/ 64 <13
142 opp-microvolt = <11500
143 clock-latency-ns = <14
144 };
145 opp-1400000000 {
146 opp-hz = /bits/ 64 <14
147 opp-microvolt = <12000
148 clock-latency-ns = <14
149 };
150 opp-1500000000 {
151 opp-hz = /bits/ 64 <15
152 opp-microvolt = <12250
153 clock-latency-ns = <14
154 };
155 opp-1600000000 {
156 opp-hz = /bits/ 64 <16
157 opp-microvolt = <12500
158 clock-latency-ns = <14
159 };
160 opp-1700000000 {
161 opp-hz = /bits/ 64 <17
162 opp-microvolt = <13000
163 clock-latency-ns = <14
164 };
165 };
166
167 pmu {
168 compatible = "arm,cortex-a15-p
169 interrupt-parent = <&combiner>
170 interrupts = <1 2>, <22 4>;
171 };
172
173 soc: soc {
174 sram@2020000 {
175 compatible = "mmio-sra
176 reg = <0x02020000 0x30
177 #address-cells = <1>;
178 #size-cells = <1>;
179 ranges = <0 0x02020000
180
181 smp-sram@0 {
182 compatible = "
183 reg = <0x0 0x1
184 };
185
186 smp-sram@2f000 {
187 compatible = "
188 reg = <0x2f000
189 };
190 };
191
192 pd_gsc: power-domain@10044000
193 compatible = "samsung,
194 reg = <0x10044000 0x20
195 #power-domain-cells =
196 label = "GSC";
197 };
198
199 pd_mfc: power-domain@10044040
200 compatible = "samsung,
201 reg = <0x10044040 0x20
202 #power-domain-cells =
203 label = "MFC";
204 };
205
206 pd_g3d: power-domain@10044060
207 compatible = "samsung,
208 reg = <0x10044060 0x20
209 #power-domain-cells =
210 label = "G3D";
211 };
212
213 pd_disp1: power-domain@100440a
214 compatible = "samsung,
215 reg = <0x100440a0 0x20
216 #power-domain-cells =
217 label = "DISP1";
218 };
219
220 pd_mau: power-domain@100440c0
221 compatible = "samsung,
222 reg = <0x100440c0 0x20
223 #power-domain-cells =
224 label = "MAU";
225 };
226
227 clock: clock-controller@100100
228 compatible = "samsung,
229 reg = <0x10010000 0x30
230 #clock-cells = <1>;
231 };
232
233 clock_audss: audss-clock-contr
234 compatible = "samsung,
235 reg = <0x03810000 0x0c
236 #clock-cells = <1>;
237 clocks = <&clock CLK_F
238 <&clock CLK_S
239 clock-names = "pll_ref
240 power-domains = <&pd_m
241 };
242
243 timer@101c0000 {
244 compatible = "samsung,
245 "samsung,
246 reg = <0x101c0000 0x80
247 clocks = <&clock CLK_F
248 clock-names = "fin_pll
249 interrupts-extended =
250
251
252
253
254
255 };
256
257 pinctrl_0: pinctrl@11400000 {
258 compatible = "samsung,
259 reg = <0x11400000 0x10
260 interrupts = <GIC_SPI
261
262 wakup_eint: wakeup-int
263 compatible = "
264 interrupt-pare
265 interrupts = <
266 };
267 };
268
269 pinctrl_1: pinctrl@13400000 {
270 compatible = "samsung,
271 reg = <0x13400000 0x10
272 interrupts = <GIC_SPI
273 };
274
275 pinctrl_2: pinctrl@10d10000 {
276 compatible = "samsung,
277 reg = <0x10d10000 0x10
278 interrupts = <GIC_SPI
279 };
280
281 pinctrl_3: pinctrl@3860000 {
282 compatible = "samsung,
283 reg = <0x03860000 0x10
284 interrupts = <GIC_SPI
285 power-domains = <&pd_m
286 };
287
288 pmu_system_controller: system-
289 compatible = "samsung,
290 reg = <0x10040000 0x50
291 clock-names = "clkout1
292 clocks = <&clock CLK_F
293 #clock-cells = <1>;
294 interrupt-controller;
295 #interrupt-cells = <3>
296 interrupt-parent = <&g
297
298 dp_phy: dp-phy {
299 compatible = "
300 #phy-cells = <
301 };
302
303 mipi_phy: mipi-phy {
304 compatible = "
305 #phy-cells = <
306 };
307 };
308
309 watchdog@101d0000 {
310 compatible = "samsung,
311 reg = <0x101d0000 0x10
312 interrupts = <GIC_SPI
313 clocks = <&clock CLK_W
314 clock-names = "watchdo
315 samsung,syscon-phandle
316 };
317
318 mfc: codec@11000000 {
319 compatible = "samsung,
320 reg = <0x11000000 0x10
321 interrupts = <GIC_SPI
322 power-domains = <&pd_m
323 clocks = <&clock CLK_M
324 clock-names = "mfc";
325 iommus = <&sysmmu_mfc_
326 iommu-names = "left",
327 };
328
329 rotator: rotator@11c00000 {
330 compatible = "samsung,
331 reg = <0x11c00000 0x64
332 interrupts = <GIC_SPI
333 clocks = <&clock CLK_R
334 clock-names = "rotator
335 iommus = <&sysmmu_rota
336 };
337
338 mali: gpu@11800000 {
339 compatible = "samsung,
340 reg = <0x11800000 0x50
341 interrupts = <GIC_SPI
342 <GIC_SPI
343 <GIC_SPI
344 interrupt-names = "job
345 clocks = <&clock CLK_G
346 clock-names = "core";
347 operating-points-v2 =
348 power-domains = <&pd_g
349 status = "disabled";
350
351 gpu_opp_table: opp-tab
352 compatible = "
353
354 opp-100000000
355 opp-hz
356 opp-mi
357 };
358 opp-160000000
359 opp-hz
360 opp-mi
361 };
362 opp-266000000
363 opp-hz
364 opp-mi
365 };
366 opp-350000000
367 opp-hz
368 opp-mi
369 };
370 opp-400000000
371 opp-hz
372 opp-mi
373 };
374 opp-450000000
375 opp-hz
376 opp-mi
377 };
378 opp-533000000
379 opp-hz
380 opp-mi
381 };
382 };
383 };
384
385 tmu: tmu@10060000 {
386 compatible = "samsung,
387 reg = <0x10060000 0x10
388 interrupts = <GIC_SPI
389 clocks = <&clock CLK_T
390 clock-names = "tmu_apb
391 #thermal-sensor-cells
392 };
393
394 sata: sata@122f0000 {
395 compatible = "snps,dwc
396 reg = <0x122f0000 0x1f
397 interrupts = <GIC_SPI
398 clocks = <&clock CLK_S
399 clock-names = "sata",
400 phys = <&sata_phy>;
401 phy-names = "sata-phy"
402 ports-implemented = <0
403 status = "disabled";
404 };
405
406 sata_phy: sata-phy@12170000 {
407 compatible = "samsung,
408 reg = <0x12170000 0x1f
409 clocks = <&clock CLK_S
410 clock-names = "sata_ph
411 #phy-cells = <0>;
412 samsung,syscon-phandle
413 status = "disabled";
414 };
415
416 /* i2c_0-3 are defined in exyn
417 i2c_4: i2c@12ca0000 {
418 compatible = "samsung,
419 reg = <0x12ca0000 0x10
420 interrupts = <GIC_SPI
421 #address-cells = <1>;
422 #size-cells = <0>;
423 clocks = <&clock CLK_I
424 clock-names = "i2c";
425 pinctrl-names = "defau
426 pinctrl-0 = <&i2c4_bus
427 status = "disabled";
428 };
429
430 i2c_5: i2c@12cb0000 {
431 compatible = "samsung,
432 reg = <0x12cb0000 0x10
433 interrupts = <GIC_SPI
434 #address-cells = <1>;
435 #size-cells = <0>;
436 clocks = <&clock CLK_I
437 clock-names = "i2c";
438 pinctrl-names = "defau
439 pinctrl-0 = <&i2c5_bus
440 status = "disabled";
441 };
442
443 i2c_6: i2c@12cc0000 {
444 compatible = "samsung,
445 reg = <0x12cc0000 0x10
446 interrupts = <GIC_SPI
447 #address-cells = <1>;
448 #size-cells = <0>;
449 clocks = <&clock CLK_I
450 clock-names = "i2c";
451 pinctrl-names = "defau
452 pinctrl-0 = <&i2c6_bus
453 status = "disabled";
454 };
455
456 i2c_7: i2c@12cd0000 {
457 compatible = "samsung,
458 reg = <0x12cd0000 0x10
459 interrupts = <GIC_SPI
460 #address-cells = <1>;
461 #size-cells = <0>;
462 clocks = <&clock CLK_I
463 clock-names = "i2c";
464 pinctrl-names = "defau
465 pinctrl-0 = <&i2c7_bus
466 status = "disabled";
467 };
468
469 i2c_8: i2c@12ce0000 {
470 compatible = "samsung,
471 reg = <0x12ce0000 0x10
472 interrupts = <GIC_SPI
473 #address-cells = <1>;
474 #size-cells = <0>;
475 clocks = <&clock CLK_I
476 clock-names = "i2c";
477 status = "disabled";
478
479 hdmiphy: hdmi-phy@38 {
480 compatible = "
481 reg = <0x38>;
482 };
483 };
484
485 i2c_9: i2c@121d0000 {
486 compatible = "samsung,
487 reg = <0x121d0000 0x10
488 #address-cells = <1>;
489 #size-cells = <0>;
490 clocks = <&clock CLK_S
491 clock-names = "i2c";
492 status = "disabled";
493
494 sata_phy_i2c: sata-phy
495 compatible = "
496 reg = <0x38>;
497 status = "disa
498 };
499 };
500
501 spi_0: spi@12d20000 {
502 compatible = "samsung,
503 status = "disabled";
504 reg = <0x12d20000 0x10
505 interrupts = <GIC_SPI
506 dmas = <&pdma0 5>, <&p
507 dma-names = "tx", "rx"
508 #address-cells = <1>;
509 #size-cells = <0>;
510 clocks = <&clock CLK_S
511 clock-names = "spi", "
512 pinctrl-names = "defau
513 pinctrl-0 = <&spi0_bus
514 fifo-depth = <256>;
515 };
516
517 spi_1: spi@12d30000 {
518 compatible = "samsung,
519 status = "disabled";
520 reg = <0x12d30000 0x10
521 interrupts = <GIC_SPI
522 dmas = <&pdma1 5>, <&p
523 dma-names = "tx", "rx"
524 #address-cells = <1>;
525 #size-cells = <0>;
526 clocks = <&clock CLK_S
527 clock-names = "spi", "
528 pinctrl-names = "defau
529 pinctrl-0 = <&spi1_bus
530 fifo-depth = <64>;
531 };
532
533 spi_2: spi@12d40000 {
534 compatible = "samsung,
535 status = "disabled";
536 reg = <0x12d40000 0x10
537 interrupts = <GIC_SPI
538 dmas = <&pdma0 7>, <&p
539 dma-names = "tx", "rx"
540 #address-cells = <1>;
541 #size-cells = <0>;
542 clocks = <&clock CLK_S
543 clock-names = "spi", "
544 pinctrl-names = "defau
545 pinctrl-0 = <&spi2_bus
546 fifo-depth = <64>;
547 };
548
549 mmc_0: mmc@12200000 {
550 compatible = "samsung,
551 interrupts = <GIC_SPI
552 #address-cells = <1>;
553 #size-cells = <0>;
554 reg = <0x12200000 0x10
555 clocks = <&clock CLK_S
556 clock-names = "biu", "
557 fifo-depth = <0x80>;
558 status = "disabled";
559 };
560
561 mmc_1: mmc@12210000 {
562 compatible = "samsung,
563 interrupts = <GIC_SPI
564 #address-cells = <1>;
565 #size-cells = <0>;
566 reg = <0x12210000 0x10
567 clocks = <&clock CLK_S
568 clock-names = "biu", "
569 fifo-depth = <0x80>;
570 status = "disabled";
571 };
572
573 mmc_2: mmc@12220000 {
574 compatible = "samsung,
575 interrupts = <GIC_SPI
576 #address-cells = <1>;
577 #size-cells = <0>;
578 reg = <0x12220000 0x10
579 clocks = <&clock CLK_S
580 clock-names = "biu", "
581 fifo-depth = <0x80>;
582 status = "disabled";
583 };
584
585 mmc_3: mmc@12230000 {
586 compatible = "samsung,
587 reg = <0x12230000 0x10
588 interrupts = <GIC_SPI
589 #address-cells = <1>;
590 #size-cells = <0>;
591 clocks = <&clock CLK_S
592 clock-names = "biu", "
593 fifo-depth = <0x80>;
594 status = "disabled";
595 };
596
597 i2s0: i2s@3830000 {
598 compatible = "samsung,
599 status = "disabled";
600 reg = <0x03830000 0x10
601 dmas = <&pdma0 10>,
602 <&pdma0 9>,
603 <&pdma0 8>;
604 dma-names = "tx", "rx"
605 clocks = <&clock_audss
606 <&clock_audss
607 <&clock_audss
608 clock-names = "iis", "
609 samsung,idma-addr = <0
610 pinctrl-names = "defau
611 pinctrl-0 = <&i2s0_bus
612 power-domains = <&pd_m
613 #clock-cells = <1>;
614 #sound-dai-cells = <1>
615 };
616
617 i2s1: i2s@12d60000 {
618 compatible = "samsung,
619 status = "disabled";
620 reg = <0x12d60000 0x10
621 dmas = <&pdma1 12>,
622 <&pdma1 11>;
623 dma-names = "tx", "rx"
624 clocks = <&clock CLK_I
625 clock-names = "iis", "
626 pinctrl-names = "defau
627 pinctrl-0 = <&i2s1_bus
628 power-domains = <&pd_m
629 #sound-dai-cells = <1>
630 };
631
632 i2s2: i2s@12d70000 {
633 compatible = "samsung,
634 status = "disabled";
635 reg = <0x12d70000 0x10
636 dmas = <&pdma0 12>,
637 <&pdma0 11>;
638 dma-names = "tx", "rx"
639 clocks = <&clock CLK_I
640 clock-names = "iis", "
641 pinctrl-names = "defau
642 pinctrl-0 = <&i2s2_bus
643 power-domains = <&pd_m
644 #sound-dai-cells = <1>
645 };
646
647 usbdrd: usb@12000000 {
648 compatible = "samsung,
649 clocks = <&clock CLK_U
650 clock-names = "usbdrd3
651 #address-cells = <1>;
652 #size-cells = <1>;
653 ranges = <0x0 0x120000
654
655 usbdrd_dwc3: usb@0 {
656 compatible = "
657 reg = <0x0 0x1
658 interrupts = <
659 phys = <&usbdr
660 phy-names = "u
661 };
662 };
663
664 usbdrd_phy: phy@12100000 {
665 compatible = "samsung,
666 reg = <0x12100000 0x10
667 clocks = <&clock CLK_U
668 clock-names = "phy", "
669 samsung,pmu-syscon = <
670 #phy-cells = <1>;
671 };
672
673 ehci: usb@12110000 {
674 compatible = "samsung,
675 reg = <0x12110000 0x10
676 interrupts = <GIC_SPI
677
678 clocks = <&clock CLK_U
679 clock-names = "usbhost
680 phys = <&usb2_phy_gen
681 phy-names = "host";
682 };
683
684 ohci: usb@12120000 {
685 compatible = "samsung,
686 reg = <0x12120000 0x10
687 interrupts = <GIC_SPI
688
689 clocks = <&clock CLK_U
690 clock-names = "usbhost
691 phys = <&usb2_phy_gen
692 phy-names = "host";
693 };
694
695 usb2_phy_gen: phy@12130000 {
696 compatible = "samsung,
697 reg = <0x12130000 0x10
698 clocks = <&clock CLK_U
699 clock-names = "phy", "
700 #phy-cells = <1>;
701 samsung,sysreg-phandle
702 samsung,pmureg-phandle
703 };
704
705 pdma0: dma-controller@121a0000
706 compatible = "arm,pl33
707 reg = <0x121a0000 0x10
708 interrupts = <GIC_SPI
709 clocks = <&clock CLK_P
710 clock-names = "apb_pcl
711 #dma-cells = <1>;
712 };
713
714 pdma1: dma-controller@121b0000
715 compatible = "arm,pl33
716 reg = <0x121b0000 0x10
717 interrupts = <GIC_SPI
718 clocks = <&clock CLK_P
719 clock-names = "apb_pcl
720 #dma-cells = <1>;
721 };
722
723 mdma0: dma-controller@10800000
724 compatible = "arm,pl33
725 reg = <0x10800000 0x10
726 interrupts = <GIC_SPI
727 clocks = <&clock CLK_M
728 clock-names = "apb_pcl
729 #dma-cells = <1>;
730 };
731
732 mdma1: dma-controller@11c10000
733 compatible = "arm,pl33
734 reg = <0x11c10000 0x10
735 interrupts = <GIC_SPI
736 clocks = <&clock CLK_M
737 clock-names = "apb_pcl
738 #dma-cells = <1>;
739 };
740
741 gsc_0: gsc@13e00000 {
742 compatible = "samsung,
743 reg = <0x13e00000 0x10
744 interrupts = <GIC_SPI
745 power-domains = <&pd_g
746 clocks = <&clock CLK_G
747 clock-names = "gscl";
748 iommus = <&sysmmu_gsc0
749 };
750
751 gsc_1: gsc@13e10000 {
752 compatible = "samsung,
753 reg = <0x13e10000 0x10
754 interrupts = <GIC_SPI
755 power-domains = <&pd_g
756 clocks = <&clock CLK_G
757 clock-names = "gscl";
758 iommus = <&sysmmu_gsc1
759 };
760
761 gsc_2: gsc@13e20000 {
762 compatible = "samsung,
763 reg = <0x13e20000 0x10
764 interrupts = <GIC_SPI
765 power-domains = <&pd_g
766 clocks = <&clock CLK_G
767 clock-names = "gscl";
768 iommus = <&sysmmu_gsc2
769 };
770
771 gsc_3: gsc@13e30000 {
772 compatible = "samsung,
773 reg = <0x13e30000 0x10
774 interrupts = <GIC_SPI
775 power-domains = <&pd_g
776 clocks = <&clock CLK_G
777 clock-names = "gscl";
778 iommus = <&sysmmu_gsc3
779 };
780
781 hdmi: hdmi@14530000 {
782 compatible = "samsung,
783 reg = <0x14530000 0x70
784 power-domains = <&pd_d
785 interrupts = <GIC_SPI
786 clocks = <&clock CLK_H
787 <&clock CLK_S
788 <&clock CLK_M
789 clock-names = "hdmi",
790 "sclk_
791 samsung,syscon-phandle
792 phy = <&hdmiphy>;
793 #sound-dai-cells = <0>
794 status = "disabled";
795 };
796
797 hdmicec: cec@101b0000 {
798 compatible = "samsung,
799 reg = <0x101b0000 0x20
800 interrupts = <GIC_SPI
801 clocks = <&clock CLK_H
802 clock-names = "hdmicec
803 samsung,syscon-phandle
804 hdmi-phandle = <&hdmi>
805 pinctrl-names = "defau
806 pinctrl-0 = <&hdmi_cec
807 status = "disabled";
808 };
809
810 mixer: mixer@14450000 {
811 compatible = "samsung,
812 reg = <0x14450000 0x10
813 power-domains = <&pd_d
814 interrupts = <GIC_SPI
815 clocks = <&clock CLK_M
816 <&clock CLK_S
817 clock-names = "mixer",
818 iommus = <&sysmmu_tv>;
819 status = "disabled";
820 };
821
822 dsi_0: dsi@14500000 {
823 compatible = "samsung,
824 reg = <0x14500000 0x10
825 interrupts = <GIC_SPI
826 samsung,power-domain =
827 phys = <&mipi_phy 3>;
828 phy-names = "dsim";
829 clocks = <&clock CLK_D
830 clock-names = "bus_clk
831 status = "disabled";
832 #address-cells = <1>;
833 #size-cells = <0>;
834 };
835
836 adc: adc@12d10000 {
837 compatible = "samsung,
838 reg = <0x12d10000 0x10
839 interrupts = <GIC_SPI
840 clocks = <&clock CLK_A
841 clock-names = "adc";
842 #io-channel-cells = <1
843 samsung,syscon-phandle
844 status = "disabled";
845 };
846
847 sysmmu_g2d: sysmmu@10a60000 {
848 compatible = "samsung,
849 reg = <0x10a60000 0x10
850 interrupt-parent = <&c
851 interrupts = <24 5>;
852 clock-names = "sysmmu"
853 clocks = <&clock CLK_S
854 #iommu-cells = <0>;
855 };
856
857 sysmmu_mfc_r: sysmmu@11200000
858 compatible = "samsung,
859 reg = <0x11200000 0x10
860 interrupt-parent = <&c
861 interrupts = <6 2>;
862 power-domains = <&pd_m
863 clock-names = "sysmmu"
864 clocks = <&clock CLK_S
865 #iommu-cells = <0>;
866 };
867
868 sysmmu_mfc_l: sysmmu@11210000
869 compatible = "samsung,
870 reg = <0x11210000 0x10
871 interrupt-parent = <&c
872 interrupts = <8 5>;
873 power-domains = <&pd_m
874 clock-names = "sysmmu"
875 clocks = <&clock CLK_S
876 #iommu-cells = <0>;
877 };
878
879 sysmmu_rotator: sysmmu@11d4000
880 compatible = "samsung,
881 reg = <0x11d40000 0x10
882 interrupt-parent = <&c
883 interrupts = <4 0>;
884 clock-names = "sysmmu"
885 clocks = <&clock CLK_S
886 #iommu-cells = <0>;
887 };
888
889 sysmmu_jpeg: sysmmu@11f20000 {
890 compatible = "samsung,
891 reg = <0x11f20000 0x10
892 interrupt-parent = <&c
893 interrupts = <4 2>;
894 power-domains = <&pd_g
895 clock-names = "sysmmu"
896 clocks = <&clock CLK_S
897 #iommu-cells = <0>;
898 };
899
900 sysmmu_fimc_isp: sysmmu@132600
901 compatible = "samsung,
902 reg = <0x13260000 0x10
903 interrupt-parent = <&c
904 interrupts = <10 6>;
905 clock-names = "sysmmu"
906 clocks = <&clock CLK_S
907 #iommu-cells = <0>;
908 };
909
910 sysmmu_fimc_drc: sysmmu@132700
911 compatible = "samsung,
912 reg = <0x13270000 0x10
913 interrupt-parent = <&c
914 interrupts = <11 6>;
915 clock-names = "sysmmu"
916 clocks = <&clock CLK_S
917 #iommu-cells = <0>;
918 };
919
920 sysmmu_fimc_fd: sysmmu@132a000
921 compatible = "samsung,
922 reg = <0x132a0000 0x10
923 interrupt-parent = <&c
924 interrupts = <5 0>;
925 clock-names = "sysmmu"
926 clocks = <&clock CLK_S
927 #iommu-cells = <0>;
928 };
929
930 sysmmu_fimc_scc: sysmmu@132800
931 compatible = "samsung,
932 reg = <0x13280000 0x10
933 interrupt-parent = <&c
934 interrupts = <5 2>;
935 clock-names = "sysmmu"
936 clocks = <&clock CLK_S
937 #iommu-cells = <0>;
938 };
939
940 sysmmu_fimc_scp: sysmmu@132900
941 compatible = "samsung,
942 reg = <0x13290000 0x10
943 interrupt-parent = <&c
944 interrupts = <3 6>;
945 clock-names = "sysmmu"
946 clocks = <&clock CLK_S
947 #iommu-cells = <0>;
948 };
949
950 sysmmu_fimc_mcuctl: sysmmu@132
951 compatible = "samsung,
952 reg = <0x132b0000 0x10
953 interrupt-parent = <&c
954 interrupts = <5 4>;
955 clock-names = "sysmmu"
956 clocks = <&clock CLK_S
957 #iommu-cells = <0>;
958 };
959
960 sysmmu_fimc_odc: sysmmu@132c00
961 compatible = "samsung,
962 reg = <0x132c0000 0x10
963 interrupt-parent = <&c
964 interrupts = <11 0>;
965 clock-names = "sysmmu"
966 clocks = <&clock CLK_S
967 #iommu-cells = <0>;
968 };
969
970 sysmmu_fimc_dis0: sysmmu@132d0
971 compatible = "samsung,
972 reg = <0x132d0000 0x10
973 interrupt-parent = <&c
974 interrupts = <10 4>;
975 clock-names = "sysmmu"
976 clocks = <&clock CLK_S
977 #iommu-cells = <0>;
978 };
979
980 sysmmu_fimc_dis1: sysmmu@132e0
981 compatible = "samsung,
982 reg = <0x132e0000 0x10
983 interrupt-parent = <&c
984 interrupts = <9 4>;
985 clock-names = "sysmmu"
986 clocks = <&clock CLK_S
987 #iommu-cells = <0>;
988 };
989
990 sysmmu_fimc_3dnr: sysmmu@132f0
991 compatible = "samsung,
992 reg = <0x132f0000 0x10
993 interrupt-parent = <&c
994 interrupts = <5 6>;
995 clock-names = "sysmmu"
996 clocks = <&clock CLK_S
997 #iommu-cells = <0>;
998 };
999
1000 sysmmu_fimc_lite0: sysmmu@13c
1001 compatible = "samsung
1002 reg = <0x13c40000 0x1
1003 interrupt-parent = <&
1004 interrupts = <3 4>;
1005 power-domains = <&pd_
1006 clock-names = "sysmmu
1007 clocks = <&clock CLK_
1008 #iommu-cells = <0>;
1009 };
1010
1011 sysmmu_fimc_lite1: sysmmu@13c
1012 compatible = "samsung
1013 reg = <0x13c50000 0x1
1014 interrupt-parent = <&
1015 interrupts = <24 1>;
1016 power-domains = <&pd_
1017 clock-names = "sysmmu
1018 clocks = <&clock CLK_
1019 #iommu-cells = <0>;
1020 };
1021
1022 sysmmu_gsc0: sysmmu@13e80000
1023 compatible = "samsung
1024 reg = <0x13e80000 0x1
1025 interrupt-parent = <&
1026 interrupts = <2 0>;
1027 power-domains = <&pd_
1028 clock-names = "sysmmu
1029 clocks = <&clock CLK_
1030 #iommu-cells = <0>;
1031 };
1032
1033 sysmmu_gsc1: sysmmu@13e90000
1034 compatible = "samsung
1035 reg = <0x13e90000 0x1
1036 interrupt-parent = <&
1037 interrupts = <2 2>;
1038 power-domains = <&pd_
1039 clock-names = "sysmmu
1040 clocks = <&clock CLK_
1041 #iommu-cells = <0>;
1042 };
1043
1044 sysmmu_gsc2: sysmmu@13ea0000
1045 compatible = "samsung
1046 reg = <0x13ea0000 0x1
1047 interrupt-parent = <&
1048 interrupts = <2 4>;
1049 power-domains = <&pd_
1050 clock-names = "sysmmu
1051 clocks = <&clock CLK_
1052 #iommu-cells = <0>;
1053 };
1054
1055 sysmmu_gsc3: sysmmu@13eb0000
1056 compatible = "samsung
1057 reg = <0x13eb0000 0x1
1058 interrupt-parent = <&
1059 interrupts = <2 6>;
1060 power-domains = <&pd_
1061 clock-names = "sysmmu
1062 clocks = <&clock CLK_
1063 #iommu-cells = <0>;
1064 };
1065
1066 sysmmu_fimd1: sysmmu@14640000
1067 compatible = "samsung
1068 reg = <0x14640000 0x1
1069 interrupt-parent = <&
1070 interrupts = <3 2>;
1071 power-domains = <&pd_
1072 clock-names = "sysmmu
1073 clocks = <&clock CLK_
1074 #iommu-cells = <0>;
1075 };
1076
1077 sysmmu_tv: sysmmu@14650000 {
1078 compatible = "samsung
1079 reg = <0x14650000 0x1
1080 interrupt-parent = <&
1081 interrupts = <7 4>;
1082 power-domains = <&pd_
1083 clock-names = "sysmmu
1084 clocks = <&clock CLK_
1085 #iommu-cells = <0>;
1086 };
1087 };
1088
1089 timer {
1090 compatible = "arm,armv7-timer
1091 interrupts = <GIC_PPI 13 (GIC
1092 <GIC_PPI 14 (GIC
1093 <GIC_PPI 11 (GIC
1094 <GIC_PPI 10 (GIC
1095 /*
1096 * Unfortunately we need this
1097 * of U-Boot on Exynos don't
1098 * so we need the value from
1099 */
1100 clock-frequency = <24000000>;
1101 };
1102 };
1103
1104 &cpu_thermal {
1105 polling-delay-passive = <0>;
1106 polling-delay = <0>;
1107 thermal-sensors = <&tmu>;
1108
1109 cooling-maps {
1110 map0 {
1111 /* Corresponds to 800
1112 cooling-device = <&cp
1113 };
1114 map1 {
1115 /* Corresponds to 200
1116 cooling-device = <&cp
1117 <&cp
1118 };
1119 };
1120 };
1121
1122 &dp {
1123 power-domains = <&pd_disp1>;
1124 clocks = <&clock CLK_DP>;
1125 clock-names = "dp";
1126 phys = <&dp_phy>;
1127 phy-names = "dp";
1128 };
1129
1130 &fimd {
1131 power-domains = <&pd_disp1>;
1132 clocks = <&clock CLK_SCLK_FIMD1>, <&c
1133 clock-names = "sclk_fimd", "fimd";
1134 iommus = <&sysmmu_fimd1>;
1135 };
1136
1137 &g2d {
1138 iommus = <&sysmmu_g2d>;
1139 clocks = <&clock CLK_G2D>;
1140 clock-names = "fimg2d";
1141 status = "okay";
1142 };
1143
1144 &i2c_0 {
1145 clocks = <&clock CLK_I2C0>;
1146 clock-names = "i2c";
1147 pinctrl-names = "default";
1148 pinctrl-0 = <&i2c0_bus>;
1149 };
1150
1151 &i2c_1 {
1152 clocks = <&clock CLK_I2C1>;
1153 clock-names = "i2c";
1154 pinctrl-names = "default";
1155 pinctrl-0 = <&i2c1_bus>;
1156 };
1157
1158 &i2c_2 {
1159 clocks = <&clock CLK_I2C2>;
1160 clock-names = "i2c";
1161 pinctrl-names = "default";
1162 pinctrl-0 = <&i2c2_bus>;
1163 };
1164
1165 &i2c_3 {
1166 clocks = <&clock CLK_I2C3>;
1167 clock-names = "i2c";
1168 pinctrl-names = "default";
1169 pinctrl-0 = <&i2c3_bus>;
1170 };
1171
1172 &prng {
1173 clocks = <&clock CLK_SSS>;
1174 clock-names = "secss";
1175 };
1176
1177 &pwm {
1178 clocks = <&clock CLK_PWM>;
1179 clock-names = "timers";
1180 };
1181
1182 &rtc {
1183 clocks = <&clock CLK_RTC>;
1184 clock-names = "rtc";
1185 interrupt-parent = <&pmu_system_contr
1186 status = "disabled";
1187 };
1188
1189 &serial_0 {
1190 clocks = <&clock CLK_UART0>, <&clock
1191 clock-names = "uart", "clk_uart_baud0
1192 dmas = <&pdma0 13>, <&pdma0 14>;
1193 dma-names = "rx", "tx";
1194 };
1195
1196 &serial_1 {
1197 clocks = <&clock CLK_UART1>, <&clock
1198 clock-names = "uart", "clk_uart_baud0
1199 dmas = <&pdma1 15>, <&pdma1 16>;
1200 dma-names = "rx", "tx";
1201 };
1202
1203 &serial_2 {
1204 clocks = <&clock CLK_UART2>, <&clock
1205 clock-names = "uart", "clk_uart_baud0
1206 dmas = <&pdma0 15>, <&pdma0 16>;
1207 dma-names = "rx", "tx";
1208 };
1209
1210 &serial_3 {
1211 clocks = <&clock CLK_UART3>, <&clock
1212 clock-names = "uart", "clk_uart_baud0
1213 dmas = <&pdma1 17>, <&pdma1 18>;
1214 dma-names = "rx", "tx";
1215 };
1216
1217 &sss {
1218 clocks = <&clock CLK_SSS>;
1219 clock-names = "secss";
1220 };
1221
1222 &trng {
1223 clocks = <&clock CLK_SSS>;
1224 clock-names = "secss";
1225 };
1226
1227 #include "exynos5250-pinctrl.dtsi"
1228 #include "exynos-syscon-restart.dtsi"
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