1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Samsung Exynos5422 SoC cpu device tree sour 3 * Samsung Exynos5422 SoC cpu device tree source
4 * 4 *
5 * Copyright (c) 2015 Samsung Electronics Co., 5 * Copyright (c) 2015 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com 6 * http://www.samsung.com
7 * 7 *
8 * This file provides desired ordering for Exy 8 * This file provides desired ordering for Exynos5422: CPU[0123] being the A7.
9 * 9 *
10 * The Exynos5420, 5422 and 5800 actually shar 10 * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
11 * but particular boards choose different boot 11 * but particular boards choose different booting order.
12 * 12 *
13 * Exynos5420 and Exynos5800 always boot from 13 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
14 * booting cluster (big or LITTLE) is chosen b 14 * booting cluster (big or LITTLE) is chosen by IROM code by reading
15 * the gpg2-1 GPIO. By default all Exynos5422 15 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
16 * from the LITTLE: Cortex-A7. 16 * from the LITTLE: Cortex-A7.
17 */ 17 */
18 18
19 / { 19 / {
20 cpus { 20 cpus {
21 #address-cells = <1>; 21 #address-cells = <1>;
22 #size-cells = <0>; 22 #size-cells = <0>;
23 23
24 cpu-map { 24 cpu-map {
25 cluster0 { 25 cluster0 {
26 core0 { 26 core0 {
27 cpu = 27 cpu = <&cpu0>;
28 }; 28 };
29 core1 { 29 core1 {
30 cpu = 30 cpu = <&cpu1>;
31 }; 31 };
32 core2 { 32 core2 {
33 cpu = 33 cpu = <&cpu2>;
34 }; 34 };
35 core3 { 35 core3 {
36 cpu = 36 cpu = <&cpu3>;
37 }; 37 };
38 }; 38 };
39 39
40 cluster1 { 40 cluster1 {
41 core0 { 41 core0 {
42 cpu = 42 cpu = <&cpu4>;
43 }; 43 };
44 core1 { 44 core1 {
45 cpu = 45 cpu = <&cpu5>;
46 }; 46 };
47 core2 { 47 core2 {
48 cpu = 48 cpu = <&cpu6>;
49 }; 49 };
50 core3 { 50 core3 {
51 cpu = 51 cpu = <&cpu7>;
52 }; 52 };
53 }; 53 };
54 }; 54 };
55 55
56 cpu0: cpu@100 { 56 cpu0: cpu@100 {
57 device_type = "cpu"; 57 device_type = "cpu";
58 compatible = "arm,cort 58 compatible = "arm,cortex-a7";
59 reg = <0x100>; 59 reg = <0x100>;
60 clocks = <&clock CLK_K 60 clocks = <&clock CLK_KFC_CLK>;
61 clock-frequency = <100 61 clock-frequency = <1000000000>;
62 cci-control-port = <&c 62 cci-control-port = <&cci_control0>;
63 operating-points-v2 = 63 operating-points-v2 = <&cluster_a7_opp_table>;
64 #cooling-cells = <2>; 64 #cooling-cells = <2>; /* min followed by max */
65 capacity-dmips-mhz = < 65 capacity-dmips-mhz = <539>;
66 dynamic-power-coeffici 66 dynamic-power-coefficient = <90>;
67 }; 67 };
68 68
69 cpu1: cpu@101 { 69 cpu1: cpu@101 {
70 device_type = "cpu"; 70 device_type = "cpu";
71 compatible = "arm,cort 71 compatible = "arm,cortex-a7";
72 reg = <0x101>; 72 reg = <0x101>;
73 clocks = <&clock CLK_K 73 clocks = <&clock CLK_KFC_CLK>;
74 clock-frequency = <100 74 clock-frequency = <1000000000>;
75 cci-control-port = <&c 75 cci-control-port = <&cci_control0>;
76 operating-points-v2 = 76 operating-points-v2 = <&cluster_a7_opp_table>;
77 #cooling-cells = <2>; 77 #cooling-cells = <2>; /* min followed by max */
78 capacity-dmips-mhz = < 78 capacity-dmips-mhz = <539>;
79 dynamic-power-coeffici 79 dynamic-power-coefficient = <90>;
80 }; 80 };
81 81
82 cpu2: cpu@102 { 82 cpu2: cpu@102 {
83 device_type = "cpu"; 83 device_type = "cpu";
84 compatible = "arm,cort 84 compatible = "arm,cortex-a7";
85 reg = <0x102>; 85 reg = <0x102>;
86 clocks = <&clock CLK_K 86 clocks = <&clock CLK_KFC_CLK>;
87 clock-frequency = <100 87 clock-frequency = <1000000000>;
88 cci-control-port = <&c 88 cci-control-port = <&cci_control0>;
89 operating-points-v2 = 89 operating-points-v2 = <&cluster_a7_opp_table>;
90 #cooling-cells = <2>; 90 #cooling-cells = <2>; /* min followed by max */
91 capacity-dmips-mhz = < 91 capacity-dmips-mhz = <539>;
92 dynamic-power-coeffici 92 dynamic-power-coefficient = <90>;
93 }; 93 };
94 94
95 cpu3: cpu@103 { 95 cpu3: cpu@103 {
96 device_type = "cpu"; 96 device_type = "cpu";
97 compatible = "arm,cort 97 compatible = "arm,cortex-a7";
98 reg = <0x103>; 98 reg = <0x103>;
99 clocks = <&clock CLK_K 99 clocks = <&clock CLK_KFC_CLK>;
100 clock-frequency = <100 100 clock-frequency = <1000000000>;
101 cci-control-port = <&c 101 cci-control-port = <&cci_control0>;
102 operating-points-v2 = 102 operating-points-v2 = <&cluster_a7_opp_table>;
103 #cooling-cells = <2>; 103 #cooling-cells = <2>; /* min followed by max */
104 capacity-dmips-mhz = < 104 capacity-dmips-mhz = <539>;
105 dynamic-power-coeffici 105 dynamic-power-coefficient = <90>;
106 }; 106 };
107 107
108 cpu4: cpu@0 { 108 cpu4: cpu@0 {
109 device_type = "cpu"; 109 device_type = "cpu";
110 compatible = "arm,cort 110 compatible = "arm,cortex-a15";
111 reg = <0x0>; 111 reg = <0x0>;
112 clocks = <&clock CLK_A 112 clocks = <&clock CLK_ARM_CLK>;
113 clock-frequency = <180 113 clock-frequency = <1800000000>;
114 cci-control-port = <&c 114 cci-control-port = <&cci_control1>;
115 operating-points-v2 = 115 operating-points-v2 = <&cluster_a15_opp_table>;
116 #cooling-cells = <2>; 116 #cooling-cells = <2>; /* min followed by max */
117 capacity-dmips-mhz = < 117 capacity-dmips-mhz = <1024>;
118 dynamic-power-coeffici 118 dynamic-power-coefficient = <310>;
119 }; 119 };
120 120
121 cpu5: cpu@1 { 121 cpu5: cpu@1 {
122 device_type = "cpu"; 122 device_type = "cpu";
123 compatible = "arm,cort 123 compatible = "arm,cortex-a15";
124 reg = <0x1>; 124 reg = <0x1>;
125 clocks = <&clock CLK_A 125 clocks = <&clock CLK_ARM_CLK>;
126 clock-frequency = <180 126 clock-frequency = <1800000000>;
127 cci-control-port = <&c 127 cci-control-port = <&cci_control1>;
128 operating-points-v2 = 128 operating-points-v2 = <&cluster_a15_opp_table>;
129 #cooling-cells = <2>; 129 #cooling-cells = <2>; /* min followed by max */
130 capacity-dmips-mhz = < 130 capacity-dmips-mhz = <1024>;
131 dynamic-power-coeffici 131 dynamic-power-coefficient = <310>;
132 }; 132 };
133 133
134 cpu6: cpu@2 { 134 cpu6: cpu@2 {
135 device_type = "cpu"; 135 device_type = "cpu";
136 compatible = "arm,cort 136 compatible = "arm,cortex-a15";
137 reg = <0x2>; 137 reg = <0x2>;
138 clocks = <&clock CLK_A 138 clocks = <&clock CLK_ARM_CLK>;
139 clock-frequency = <180 139 clock-frequency = <1800000000>;
140 cci-control-port = <&c 140 cci-control-port = <&cci_control1>;
141 operating-points-v2 = 141 operating-points-v2 = <&cluster_a15_opp_table>;
142 #cooling-cells = <2>; 142 #cooling-cells = <2>; /* min followed by max */
143 capacity-dmips-mhz = < 143 capacity-dmips-mhz = <1024>;
144 dynamic-power-coeffici 144 dynamic-power-coefficient = <310>;
145 }; 145 };
146 146
147 cpu7: cpu@3 { 147 cpu7: cpu@3 {
148 device_type = "cpu"; 148 device_type = "cpu";
149 compatible = "arm,cort 149 compatible = "arm,cortex-a15";
150 reg = <0x3>; 150 reg = <0x3>;
151 clocks = <&clock CLK_A 151 clocks = <&clock CLK_ARM_CLK>;
152 clock-frequency = <180 152 clock-frequency = <1800000000>;
153 cci-control-port = <&c 153 cci-control-port = <&cci_control1>;
154 operating-points-v2 = 154 operating-points-v2 = <&cluster_a15_opp_table>;
155 #cooling-cells = <2>; 155 #cooling-cells = <2>; /* min followed by max */
156 capacity-dmips-mhz = < 156 capacity-dmips-mhz = <1024>;
157 dynamic-power-coeffici 157 dynamic-power-coefficient = <310>;
158 }; 158 };
159 }; 159 };
160 }; 160 };
161 161
162 &arm_a7_pmu { 162 &arm_a7_pmu {
163 interrupt-affinity = <&cpu0>, <&cpu1>, 163 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
164 status = "okay"; 164 status = "okay";
165 }; 165 };
166 166
167 &arm_a15_pmu { 167 &arm_a15_pmu {
168 interrupt-affinity = <&cpu4>, <&cpu5>, 168 interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
169 status = "okay"; 169 status = "okay";
170 }; 170 };
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