1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Samsung's S3C64xx SoC series common device 3 * Samsung's S3C64xx SoC series common device tree source
4 * 4 *
5 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@ 5 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
6 * 6 *
7 * Samsung's S3C64xx SoC series device nodes a 7 * Samsung's S3C64xx SoC series device nodes are listed in this file.
8 * Particular SoCs from S3C64xx series can inc 8 * Particular SoCs from S3C64xx series can include this file and provide
9 * values for SoCs specific bindings. 9 * values for SoCs specific bindings.
10 * 10 *
11 * Note: This file does not include device nod 11 * Note: This file does not include device nodes for all the controllers in
12 * S3C64xx SoCs. As device tree coverage for S 12 * S3C64xx SoCs. As device tree coverage for S3C64xx increases, additional
13 * nodes can be added to this file. 13 * nodes can be added to this file.
14 */ 14 */
15 15
16 #include <dt-bindings/clock/samsung,s3c64xx-cl 16 #include <dt-bindings/clock/samsung,s3c64xx-clock.h>
17 17
18 / { 18 / {
19 #address-cells = <1>; 19 #address-cells = <1>;
20 #size-cells = <1>; 20 #size-cells = <1>;
21 21
22 aliases { 22 aliases {
23 i2c0 = &i2c0; 23 i2c0 = &i2c0;
24 pinctrl0 = &pinctrl0; 24 pinctrl0 = &pinctrl0;
25 serial0 = &uart0; 25 serial0 = &uart0;
26 serial1 = &uart1; 26 serial1 = &uart1;
27 serial2 = &uart2; 27 serial2 = &uart2;
28 serial3 = &uart3; 28 serial3 = &uart3;
29 }; 29 };
30 30
31 cpus { 31 cpus {
32 #address-cells = <1>; 32 #address-cells = <1>;
33 #size-cells = <0>; 33 #size-cells = <0>;
34 34
35 cpu@0 { 35 cpu@0 {
36 device_type = "cpu"; 36 device_type = "cpu";
37 compatible = "arm,arm1 37 compatible = "arm,arm1176jzf-s";
38 reg = <0x0>; 38 reg = <0x0>;
39 }; 39 };
40 }; 40 };
41 41
42 soc: soc { 42 soc: soc {
43 compatible = "simple-bus"; 43 compatible = "simple-bus";
44 #address-cells = <1>; 44 #address-cells = <1>;
45 #size-cells = <1>; 45 #size-cells = <1>;
46 ranges; 46 ranges;
47 47
48 vic0: interrupt-controller@712 48 vic0: interrupt-controller@71200000 {
49 compatible = "arm,pl19 49 compatible = "arm,pl192-vic";
50 interrupt-controller; 50 interrupt-controller;
51 reg = <0x71200000 0x10 51 reg = <0x71200000 0x1000>;
52 #interrupt-cells = <1> 52 #interrupt-cells = <1>;
53 }; 53 };
54 54
55 vic1: interrupt-controller@713 55 vic1: interrupt-controller@71300000 {
56 compatible = "arm,pl19 56 compatible = "arm,pl192-vic";
57 interrupt-controller; 57 interrupt-controller;
58 reg = <0x71300000 0x10 58 reg = <0x71300000 0x1000>;
59 #interrupt-cells = <1> 59 #interrupt-cells = <1>;
60 }; 60 };
61 61
62 sdhci0: mmc@7c200000 { 62 sdhci0: mmc@7c200000 {
63 compatible = "samsung, 63 compatible = "samsung,s3c6410-sdhci";
64 reg = <0x7c200000 0x10 64 reg = <0x7c200000 0x100>;
65 interrupt-parent = <&v 65 interrupt-parent = <&vic1>;
66 interrupts = <24>; 66 interrupts = <24>;
67 clock-names = "hsmmc", 67 clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
68 clocks = <&clocks HCLK 68 clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>,
69 <&cloc 69 <&clocks SCLK_MMC0>;
70 status = "disabled"; 70 status = "disabled";
71 }; 71 };
72 72
73 sdhci1: mmc@7c300000 { 73 sdhci1: mmc@7c300000 {
74 compatible = "samsung, 74 compatible = "samsung,s3c6410-sdhci";
75 reg = <0x7c300000 0x10 75 reg = <0x7c300000 0x100>;
76 interrupt-parent = <&v 76 interrupt-parent = <&vic1>;
77 interrupts = <25>; 77 interrupts = <25>;
78 clock-names = "hsmmc", 78 clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
79 clocks = <&clocks HCLK 79 clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>,
80 <&cloc 80 <&clocks SCLK_MMC1>;
81 status = "disabled"; 81 status = "disabled";
82 }; 82 };
83 83
84 sdhci2: mmc@7c400000 { 84 sdhci2: mmc@7c400000 {
85 compatible = "samsung, 85 compatible = "samsung,s3c6410-sdhci";
86 reg = <0x7c400000 0x10 86 reg = <0x7c400000 0x100>;
87 interrupt-parent = <&v 87 interrupt-parent = <&vic1>;
88 interrupts = <17>; 88 interrupts = <17>;
89 clock-names = "hsmmc", 89 clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
90 clocks = <&clocks HCLK 90 clocks = <&clocks HCLK_HSMMC2>, <&clocks HCLK_HSMMC2>,
91 <&cloc 91 <&clocks SCLK_MMC2>;
92 status = "disabled"; 92 status = "disabled";
93 }; 93 };
94 94
95 watchdog: watchdog@7e004000 { 95 watchdog: watchdog@7e004000 {
96 compatible = "samsung, 96 compatible = "samsung,s3c6410-wdt";
97 reg = <0x7e004000 0x10 97 reg = <0x7e004000 0x1000>;
98 interrupt-parent = <&v 98 interrupt-parent = <&vic0>;
99 interrupts = <26>; 99 interrupts = <26>;
100 clock-names = "watchdo 100 clock-names = "watchdog";
101 clocks = <&clocks PCLK 101 clocks = <&clocks PCLK_WDT>;
102 }; 102 };
103 103
104 i2c0: i2c@7f004000 { 104 i2c0: i2c@7f004000 {
105 compatible = "samsung, 105 compatible = "samsung,s3c2440-i2c";
106 reg = <0x7f004000 0x10 106 reg = <0x7f004000 0x1000>;
107 interrupt-parent = <&v 107 interrupt-parent = <&vic1>;
108 interrupts = <18>; 108 interrupts = <18>;
109 clock-names = "i2c"; 109 clock-names = "i2c";
110 clocks = <&clocks PCLK 110 clocks = <&clocks PCLK_IIC0>;
111 status = "disabled"; 111 status = "disabled";
112 #address-cells = <1>; 112 #address-cells = <1>;
113 #size-cells = <0>; 113 #size-cells = <0>;
114 }; 114 };
115 115
116 uart0: serial@7f005000 { 116 uart0: serial@7f005000 {
117 compatible = "samsung, 117 compatible = "samsung,s3c6400-uart";
118 reg = <0x7f005000 0x10 118 reg = <0x7f005000 0x100>;
119 interrupt-parent = <&v 119 interrupt-parent = <&vic1>;
120 interrupts = <5>; 120 interrupts = <5>;
121 clock-names = "uart", 121 clock-names = "uart", "clk_uart_baud2",
122 "clk_u 122 "clk_uart_baud3";
123 clocks = <&clocks PCLK 123 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
124 <&cloc 124 <&clocks SCLK_UART>;
125 status = "disabled"; 125 status = "disabled";
126 }; 126 };
127 127
128 uart1: serial@7f005400 { 128 uart1: serial@7f005400 {
129 compatible = "samsung, 129 compatible = "samsung,s3c6400-uart";
130 reg = <0x7f005400 0x10 130 reg = <0x7f005400 0x100>;
131 interrupt-parent = <&v 131 interrupt-parent = <&vic1>;
132 interrupts = <6>; 132 interrupts = <6>;
133 clock-names = "uart", 133 clock-names = "uart", "clk_uart_baud2",
134 "clk_u 134 "clk_uart_baud3";
135 clocks = <&clocks PCLK 135 clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
136 <&cloc 136 <&clocks SCLK_UART>;
137 status = "disabled"; 137 status = "disabled";
138 }; 138 };
139 139
140 uart2: serial@7f005800 { 140 uart2: serial@7f005800 {
141 compatible = "samsung, 141 compatible = "samsung,s3c6400-uart";
142 reg = <0x7f005800 0x10 142 reg = <0x7f005800 0x100>;
143 interrupt-parent = <&v 143 interrupt-parent = <&vic1>;
144 interrupts = <7>; 144 interrupts = <7>;
145 clock-names = "uart", 145 clock-names = "uart", "clk_uart_baud2",
146 "clk_u 146 "clk_uart_baud3";
147 clocks = <&clocks PCLK 147 clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>,
148 <&cloc 148 <&clocks SCLK_UART>;
149 status = "disabled"; 149 status = "disabled";
150 }; 150 };
151 151
152 uart3: serial@7f005c00 { 152 uart3: serial@7f005c00 {
153 compatible = "samsung, 153 compatible = "samsung,s3c6400-uart";
154 reg = <0x7f005c00 0x10 154 reg = <0x7f005c00 0x100>;
155 interrupt-parent = <&v 155 interrupt-parent = <&vic1>;
156 interrupts = <8>; 156 interrupts = <8>;
157 clock-names = "uart", 157 clock-names = "uart", "clk_uart_baud2",
158 "clk_u 158 "clk_uart_baud3";
159 clocks = <&clocks PCLK 159 clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>,
160 <&cloc 160 <&clocks SCLK_UART>;
161 status = "disabled"; 161 status = "disabled";
162 }; 162 };
163 163
164 pwm: pwm@7f006000 { 164 pwm: pwm@7f006000 {
165 compatible = "samsung, 165 compatible = "samsung,s3c6400-pwm";
166 reg = <0x7f006000 0x10 166 reg = <0x7f006000 0x1000>;
167 interrupt-parent = <&v 167 interrupt-parent = <&vic0>;
168 interrupts = <23>, <24 168 interrupts = <23>, <24>, <25>, <27>, <28>;
169 clock-names = "timers" 169 clock-names = "timers";
170 clocks = <&clocks PCLK 170 clocks = <&clocks PCLK_PWM>;
171 samsung,pwm-outputs = 171 samsung,pwm-outputs = <0>, <1>;
172 #pwm-cells = <3>; 172 #pwm-cells = <3>;
173 }; 173 };
174 174
175 pinctrl0: pinctrl@7f008000 { 175 pinctrl0: pinctrl@7f008000 {
176 compatible = "samsung, 176 compatible = "samsung,s3c64xx-pinctrl";
177 reg = <0x7f008000 0x10 177 reg = <0x7f008000 0x1000>;
178 interrupt-parent = <&v 178 interrupt-parent = <&vic1>;
179 interrupts = <21>; 179 interrupts = <21>;
180 180
181 wakeup-interrupt-contr 181 wakeup-interrupt-controller {
182 compatible = " 182 compatible = "samsung,s3c64xx-wakeup-eint";
183 interrupts-ext 183 interrupts-extended = <&vic0 0>,
184 184 <&vic0 1>,
185 185 <&vic1 0>,
186 186 <&vic1 1>;
187 }; 187 };
188 }; 188 };
189 }; 189 };
190 }; 190 };
191 191
192 #include "s3c64xx-pinctrl.dtsi" 192 #include "s3c64xx-pinctrl.dtsi"
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