1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
2 //
3 // Device Tree Source for UniPhier Pro4 SoC
4 //
5 // Copyright (C) 2015-2016 Socionext Inc.
6 // Author: Masahiro Yamada <yamada.masahiro@s
7
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/interrupt-controller/arm
10
11 / {
12 compatible = "socionext,uniphier-pro4"
13 #address-cells = <1>;
14 #size-cells = <1>;
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 cpu@0 {
21 device_type = "cpu";
22 compatible = "arm,cort
23 reg = <0>;
24 enable-method = "psci"
25 next-level-cache = <&l
26 };
27
28 cpu@1 {
29 device_type = "cpu";
30 compatible = "arm,cort
31 reg = <1>;
32 enable-method = "psci"
33 next-level-cache = <&l
34 };
35 };
36
37 psci {
38 compatible = "arm,psci-0.2";
39 method = "smc";
40 };
41
42 clocks {
43 refclk: ref {
44 compatible = "fixed-cl
45 #clock-cells = <0>;
46 clock-frequency = <250
47 };
48
49 arm_timer_clk: arm-timer {
50 #clock-cells = <0>;
51 compatible = "fixed-cl
52 clock-frequency = <500
53 };
54 };
55
56 soc {
57 compatible = "simple-bus";
58 #address-cells = <1>;
59 #size-cells = <1>;
60 ranges;
61 interrupt-parent = <&intc>;
62
63 l2: cache-controller@500c0000
64 compatible = "socionex
65 reg = <0x500c0000 0x20
66 <0x506c0000 0x40
67 interrupts = <GIC_SPI
68 <GIC_SPI
69 cache-unified;
70 cache-size = <(768 * 1
71 cache-sets = <256>;
72 cache-line-size = <128
73 cache-level = <2>;
74 };
75
76 spi0: spi@54006000 {
77 compatible = "socionex
78 status = "disabled";
79 reg = <0x54006000 0x10
80 #address-cells = <1>;
81 #size-cells = <0>;
82 interrupts = <GIC_SPI
83 pinctrl-names = "defau
84 pinctrl-0 = <&pinctrl_
85 clocks = <&peri_clk 11
86 resets = <&peri_rst 11
87 };
88
89 serial0: serial@54006800 {
90 compatible = "socionex
91 status = "disabled";
92 reg = <0x54006800 0x40
93 interrupts = <GIC_SPI
94 pinctrl-names = "defau
95 pinctrl-0 = <&pinctrl_
96 clocks = <&peri_clk 0>
97 resets = <&peri_rst 0>
98 };
99
100 serial1: serial@54006900 {
101 compatible = "socionex
102 status = "disabled";
103 reg = <0x54006900 0x40
104 interrupts = <GIC_SPI
105 pinctrl-names = "defau
106 pinctrl-0 = <&pinctrl_
107 clocks = <&peri_clk 1>
108 resets = <&peri_rst 1>
109 };
110
111 serial2: serial@54006a00 {
112 compatible = "socionex
113 status = "disabled";
114 reg = <0x54006a00 0x40
115 interrupts = <GIC_SPI
116 pinctrl-names = "defau
117 pinctrl-0 = <&pinctrl_
118 clocks = <&peri_clk 2>
119 resets = <&peri_rst 2>
120 };
121
122 serial3: serial@54006b00 {
123 compatible = "socionex
124 status = "disabled";
125 reg = <0x54006b00 0x40
126 interrupts = <GIC_SPI
127 pinctrl-names = "defau
128 pinctrl-0 = <&pinctrl_
129 clocks = <&peri_clk 3>
130 resets = <&peri_rst 3>
131 };
132
133 gpio: gpio@55000000 {
134 compatible = "socionex
135 reg = <0x55000000 0x20
136 interrupt-parent = <&a
137 interrupt-controller;
138 #interrupt-cells = <2>
139 gpio-controller;
140 #gpio-cells = <2>;
141 gpio-ranges = <&pinctr
142 gpio-ranges-group-name
143 ngpios = <248>;
144 socionext,interrupt-ra
145 };
146
147 i2c0: i2c@58780000 {
148 compatible = "socionex
149 status = "disabled";
150 reg = <0x58780000 0x80
151 #address-cells = <1>;
152 #size-cells = <0>;
153 interrupts = <GIC_SPI
154 pinctrl-names = "defau
155 pinctrl-0 = <&pinctrl_
156 clocks = <&peri_clk 4>
157 resets = <&peri_rst 4>
158 clock-frequency = <100
159 };
160
161 i2c1: i2c@58781000 {
162 compatible = "socionex
163 status = "disabled";
164 reg = <0x58781000 0x80
165 #address-cells = <1>;
166 #size-cells = <0>;
167 interrupts = <GIC_SPI
168 pinctrl-names = "defau
169 pinctrl-0 = <&pinctrl_
170 clocks = <&peri_clk 5>
171 resets = <&peri_rst 5>
172 clock-frequency = <100
173 };
174
175 i2c2: i2c@58782000 {
176 compatible = "socionex
177 status = "disabled";
178 reg = <0x58782000 0x80
179 #address-cells = <1>;
180 #size-cells = <0>;
181 interrupts = <GIC_SPI
182 pinctrl-names = "defau
183 pinctrl-0 = <&pinctrl_
184 clocks = <&peri_clk 6>
185 resets = <&peri_rst 6>
186 clock-frequency = <100
187 };
188
189 i2c3: i2c@58783000 {
190 compatible = "socionex
191 status = "disabled";
192 reg = <0x58783000 0x80
193 #address-cells = <1>;
194 #size-cells = <0>;
195 interrupts = <GIC_SPI
196 pinctrl-names = "defau
197 pinctrl-0 = <&pinctrl_
198 clocks = <&peri_clk 7>
199 resets = <&peri_rst 7>
200 clock-frequency = <100
201 };
202
203 /* i2c4 does not exist */
204
205 /* chip-internal connection fo
206 i2c5: i2c@58785000 {
207 compatible = "socionex
208 reg = <0x58785000 0x80
209 #address-cells = <1>;
210 #size-cells = <0>;
211 interrupts = <GIC_SPI
212 clocks = <&peri_clk 9>
213 resets = <&peri_rst 9>
214 clock-frequency = <400
215 };
216
217 /* chip-internal connection fo
218 i2c6: i2c@58786000 {
219 compatible = "socionex
220 reg = <0x58786000 0x80
221 #address-cells = <1>;
222 #size-cells = <0>;
223 interrupts = <GIC_SPI
224 clocks = <&peri_clk 10
225 resets = <&peri_rst 10
226 clock-frequency = <400
227 };
228
229 system_bus: system-bus@58c0000
230 compatible = "socionex
231 status = "disabled";
232 reg = <0x58c00000 0x40
233 #address-cells = <2>;
234 #size-cells = <1>;
235 pinctrl-names = "defau
236 pinctrl-0 = <&pinctrl_
237 };
238
239 smpctrl@59801000 {
240 compatible = "socionex
241 reg = <0x59801000 0x40
242 };
243
244 mioctrl: syscon@59810000 {
245 compatible = "socionex
246 "simple-m
247 reg = <0x59810000 0x80
248
249 mio_clk: clock-control
250 compatible = "
251 #clock-cells =
252 };
253
254 mio_rst: reset-control
255 compatible = "
256 #reset-cells =
257 };
258 };
259
260 syscon@59820000 {
261 compatible = "socionex
262 "simple-m
263 reg = <0x59820000 0x20
264
265 peri_clk: clock-contro
266 compatible = "
267 #clock-cells =
268 };
269
270 peri_rst: reset-contro
271 compatible = "
272 #reset-cells =
273 };
274 };
275
276 dmac: dma-controller@5a000000
277 compatible = "socionex
278 reg = <0x5a000000 0x10
279 interrupts = <GIC_SPI
280 <GIC_SPI
281 <GIC_SPI
282 <GIC_SPI
283 <GIC_SPI
284 <GIC_SPI
285 <GIC_SPI
286 <GIC_SPI
287 clocks = <&mio_clk 7>;
288 resets = <&mio_rst 7>;
289 #dma-cells = <1>;
290 };
291
292 sd: mmc@5a400000 {
293 compatible = "socionex
294 status = "disabled";
295 reg = <0x5a400000 0x20
296 interrupts = <GIC_SPI
297 pinctrl-names = "defau
298 pinctrl-0 = <&pinctrl_
299 pinctrl-1 = <&pinctrl_
300 clocks = <&mio_clk 0>;
301 reset-names = "host",
302 resets = <&mio_rst 0>,
303 dma-names = "rx-tx";
304 dmas = <&dmac 4>;
305 bus-width = <4>;
306 cap-sd-highspeed;
307 sd-uhs-sdr12;
308 sd-uhs-sdr25;
309 sd-uhs-sdr50;
310 socionext,syscon-uhs-m
311 };
312
313 emmc: mmc@5a500000 {
314 compatible = "socionex
315 status = "disabled";
316 reg = <0x5a500000 0x20
317 interrupts = <GIC_SPI
318 pinctrl-names = "defau
319 pinctrl-0 = <&pinctrl_
320 clocks = <&mio_clk 1>;
321 reset-names = "host",
322 resets = <&mio_rst 1>,
323 dma-names = "rx-tx";
324 dmas = <&dmac 5>;
325 bus-width = <8>;
326 cap-mmc-highspeed;
327 cap-mmc-hw-reset;
328 non-removable;
329 };
330
331 sd1: mmc@5a600000 {
332 compatible = "socionex
333 status = "disabled";
334 reg = <0x5a600000 0x20
335 interrupts = <GIC_SPI
336 pinctrl-names = "defau
337 pinctrl-0 = <&pinctrl_
338 clocks = <&mio_clk 2>;
339 reset-names = "host",
340 resets = <&mio_rst 2>,
341 dma-names = "rx-tx";
342 dmas = <&dmac 6>;
343 bus-width = <4>;
344 cap-sd-highspeed;
345 };
346
347 usb2: usb@5a800100 {
348 compatible = "socionex
349 status = "disabled";
350 reg = <0x5a800100 0x10
351 interrupts = <GIC_SPI
352 pinctrl-names = "defau
353 pinctrl-0 = <&pinctrl_
354 clocks = <&sys_clk 8>,
355 <&mio_clk 12>
356 resets = <&sys_rst 8>,
357 <&mio_rst 12>
358 phy-names = "usb";
359 phys = <&usb_phy0>;
360 has-transaction-transl
361 };
362
363 usb3: usb@5a810100 {
364 compatible = "socionex
365 status = "disabled";
366 reg = <0x5a810100 0x10
367 interrupts = <GIC_SPI
368 pinctrl-names = "defau
369 pinctrl-0 = <&pinctrl_
370 clocks = <&sys_clk 8>,
371 <&mio_clk 13>
372 resets = <&sys_rst 8>,
373 <&mio_rst 13>
374 phy-names = "usb";
375 phys = <&usb_phy1>;
376 has-transaction-transl
377 };
378
379 soc_glue: syscon@5f800000 {
380 compatible = "socionex
381 "simple-m
382 reg = <0x5f800000 0x20
383
384 pinctrl: pinctrl {
385 compatible = "
386 };
387
388 usb-hub {
389 compatible = "
390 #address-cells
391 #size-cells =
392
393 usb_phy0: phy@
394 reg =
395 #phy-c
396 };
397
398 usb_phy1: phy@
399 reg =
400 #phy-c
401 };
402
403 usb_phy2: phy@
404 reg =
405 #phy-c
406 vbus-s
407 };
408
409 usb_phy3: phy@
410 reg =
411 #phy-c
412 vbus-s
413 };
414 };
415
416 sg_clk: clock-controll
417 compatible = "
418 #clock-cells =
419 };
420 };
421
422 syscon@5f900000 {
423 compatible = "socionex
424 "simple-m
425 reg = <0x5f900000 0x20
426 #address-cells = <1>;
427 #size-cells = <1>;
428 ranges = <0 0x5f900000
429
430 efuse@100 {
431 compatible = "
432 reg = <0x100 0
433 };
434
435 efuse@130 {
436 compatible = "
437 reg = <0x130 0
438 };
439
440 efuse@200 {
441 compatible = "
442 reg = <0x200 0
443 };
444 };
445
446 xdmac: dma-controller@5fc10000
447 compatible = "socionex
448 reg = <0x5fc10000 0x53
449 interrupts = <GIC_SPI
450 dma-channels = <16>;
451 #dma-cells = <2>;
452 };
453
454 aidet: interrupt-controller@5f
455 compatible = "socionex
456 reg = <0x5fc20000 0x20
457 interrupt-controller;
458 #interrupt-cells = <2>
459 };
460
461 timer@60000200 {
462 compatible = "arm,cort
463 reg = <0x60000200 0x20
464 interrupts = <GIC_PPI
465 (GIC_CPU_MASK_
466 clocks = <&arm_timer_c
467 };
468
469 timer@60000600 {
470 compatible = "arm,cort
471 reg = <0x60000600 0x20
472 interrupts = <GIC_PPI
473 (GIC_CPU_MASK_
474 clocks = <&arm_timer_c
475 };
476
477 intc: interrupt-controller@600
478 compatible = "arm,cort
479 reg = <0x60001000 0x10
480 <0x60000100 0x10
481 #interrupt-cells = <3>
482 interrupt-controller;
483 };
484
485 syscon@61840000 {
486 compatible = "socionex
487 "simple-m
488 reg = <0x61840000 0x10
489
490 sys_clk: clock-control
491 compatible = "
492 #clock-cells =
493 };
494
495 sys_rst: reset-control
496 compatible = "
497 #reset-cells =
498 };
499 };
500
501 eth: ethernet@65000000 {
502 compatible = "socionex
503 status = "disabled";
504 reg = <0x65000000 0x85
505 interrupts = <GIC_SPI
506 pinctrl-names = "defau
507 pinctrl-0 = <&pinctrl_
508 clock-names = "gio", "
509 clocks = <&sys_clk 12>
510 <&sys_clk 10>
511 reset-names = "gio", "
512 resets = <&sys_rst 12>
513 phy-mode = "rgmii";
514 local-mac-address = [0
515 socionext,syscon-phy-m
516
517 mdio: mdio {
518 #address-cells
519 #size-cells =
520 };
521 };
522
523 ahci0: sata@65600000 {
524 compatible = "socionex
525 "generic-
526 status = "disabled";
527 reg = <0x65600000 0x10
528 interrupts = <GIC_SPI
529 clocks = <&sys_clk 12>
530 resets = <&sys_rst 12>
531 ports-implemented = <1
532 phys = <&ahci0_phy>;
533 assigned-clocks = <&sg
534 assigned-clock-rates =
535 };
536
537 sata-controller@65700000 {
538 compatible = "socionex
539 "simple-m
540 reg = <0x65700000 0x10
541 #address-cells = <1>;
542 #size-cells = <1>;
543 ranges = <0 0x65700000
544
545 ahci0_rst: reset-contr
546 compatible = "
547 reg = <0x0 0x4
548 clock-names =
549 clocks = <&sys
550 reset-names =
551 resets = <&sys
552 #reset-cells =
553 };
554
555 ahci0_phy: phy@10 {
556 compatible = "
557 reg = <0x10 0x
558 clock-names =
559 clocks = <&sys
560 reset-names =
561
562 resets = <&sys
563 <&sys
564 <&ahc
565 <&ahc
566 #phy-cells = <
567 };
568 };
569
570 ahci1: sata@65800000 {
571 compatible = "socionex
572 "generic-
573 status = "disabled";
574 reg = <0x65800000 0x10
575 interrupts = <GIC_SPI
576 clocks = <&sys_clk 12>
577 resets = <&sys_rst 12>
578 ports-implemented = <1
579 phys = <&ahci1_phy>;
580 assigned-clocks = <&sg
581 assigned-clock-rates =
582 };
583
584 sata-controller@65900000 {
585 compatible = "socionex
586 "simple-m
587 reg = <0x65900000 0x10
588 #address-cells = <1>;
589 #size-cells = <1>;
590 ranges = <0 0x65900000
591
592 ahci1_rst: reset-contr
593 compatible = "
594 reg = <0x0 0x4
595 clock-names =
596 clocks = <&sys
597 reset-names =
598 resets = <&sys
599 #reset-cells =
600 };
601
602 ahci1_phy: phy@10 {
603 compatible = "
604 reg = <0x10 0x
605 clock-names =
606 clocks = <&sys
607 reset-names =
608
609 resets = <&sys
610 <&sys
611 <&ahc
612 <&ahc
613 #phy-cells = <
614 };
615 };
616
617 usb0: usb@65a00000 {
618 compatible = "socionex
619 status = "disabled";
620 reg = <0x65a00000 0xcd
621 interrupt-names = "hos
622 interrupts = <GIC_SPI
623 <GIC_SPI
624 pinctrl-names = "defau
625 pinctrl-0 = <&pinctrl_
626 clock-names = "ref", "
627 clocks = <&sys_clk 12>
628 resets = <&usb0_rst 4>
629 phys = <&usb_phy2>, <&
630 dr_mode = "host";
631 };
632
633 usb-controller@65b00000 {
634 compatible = "socionex
635 "simple-m
636 reg = <0x65b00000 0x10
637 #address-cells = <1>;
638 #size-cells = <1>;
639 ranges = <0 0x65b00000
640
641 usb0_vbus: regulator@0
642 compatible = "
643 reg = <0 0x10>
644 clock-names =
645 clocks = <&sys
646 reset-names =
647 resets = <&sys
648 };
649
650 usb0_ssphy: phy@10 {
651 compatible = "
652 reg = <0x10 0x
653 #phy-cells = <
654 clock-names =
655 clocks = <&sys
656 reset-names =
657 resets = <&sys
658 vbus-supply =
659 };
660
661 usb0_rst: reset-contro
662 compatible = "
663 reg = <0x40 0x
664 #reset-cells =
665 clock-names =
666 clocks = <&sys
667 reset-names =
668 resets = <&sys
669 };
670 };
671
672 usb1: usb@65c00000 {
673 compatible = "socionex
674 status = "disabled";
675 reg = <0x65c00000 0xcd
676 interrupt-names = "hos
677 interrupts = <GIC_SPI
678 <GIC_SPI
679 pinctrl-names = "defau
680 pinctrl-0 = <&pinctrl_
681 clock-names = "ref", "
682 clocks = <&sys_clk 12>
683 resets = <&usb1_rst 4>
684 phys = <&usb_phy3>;
685 dr_mode = "host";
686 };
687
688 usb-controller@65d00000 {
689 compatible = "socionex
690 "simple-m
691 reg = <0x65d00000 0x10
692 #address-cells = <1>;
693 #size-cells = <1>;
694 ranges = <0 0x65d00000
695
696 usb1_vbus: regulator@0
697 compatible = "
698 reg = <0 0x10>
699 clock-names =
700 clocks = <&sys
701 reset-names =
702 resets = <&sys
703 };
704
705 usb1_rst: reset-contro
706 compatible = "
707 reg = <0x40 0x
708 #reset-cells =
709 clock-names =
710 clocks = <&sys
711 reset-names =
712 resets = <&sys
713 };
714 };
715
716 nand: nand-controller@68000000
717 compatible = "socionex
718 status = "disabled";
719 reg-names = "nand_data
720 reg = <0x68000000 0x20
721 #address-cells = <1>;
722 #size-cells = <0>;
723 interrupts = <GIC_SPI
724 pinctrl-names = "defau
725 pinctrl-0 = <&pinctrl_
726 clock-names = "nand",
727 clocks = <&sys_clk 2>,
728 reset-names = "nand",
729 resets = <&sys_rst 2>,
730 };
731 };
732 };
733
734 #include "uniphier-pinctrl.dtsi"
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