1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
2 // 2 //
3 // Device Tree Source for UniPhier Pro4 SoC 3 // Device Tree Source for UniPhier Pro4 SoC
4 // 4 //
5 // Copyright (C) 2015-2016 Socionext Inc. 5 // Copyright (C) 2015-2016 Socionext Inc.
6 // Author: Masahiro Yamada <yamada.masahiro@s 6 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 7
8 #include <dt-bindings/gpio/uniphier-gpio.h> 8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 10
11 / { 11 / {
12 compatible = "socionext,uniphier-pro4" 12 compatible = "socionext,uniphier-pro4";
13 #address-cells = <1>; 13 #address-cells = <1>;
14 #size-cells = <1>; 14 #size-cells = <1>;
15 15
16 cpus { 16 cpus {
17 #address-cells = <1>; 17 #address-cells = <1>;
18 #size-cells = <0>; 18 #size-cells = <0>;
19 19
20 cpu@0 { 20 cpu@0 {
21 device_type = "cpu"; 21 device_type = "cpu";
22 compatible = "arm,cort 22 compatible = "arm,cortex-a9";
23 reg = <0>; 23 reg = <0>;
24 enable-method = "psci" 24 enable-method = "psci";
25 next-level-cache = <&l 25 next-level-cache = <&l2>;
26 }; 26 };
27 27
28 cpu@1 { 28 cpu@1 {
29 device_type = "cpu"; 29 device_type = "cpu";
30 compatible = "arm,cort 30 compatible = "arm,cortex-a9";
31 reg = <1>; 31 reg = <1>;
32 enable-method = "psci" 32 enable-method = "psci";
33 next-level-cache = <&l 33 next-level-cache = <&l2>;
34 }; 34 };
35 }; 35 };
36 36
37 psci { 37 psci {
38 compatible = "arm,psci-0.2"; 38 compatible = "arm,psci-0.2";
39 method = "smc"; 39 method = "smc";
40 }; 40 };
41 41
42 clocks { 42 clocks {
43 refclk: ref { 43 refclk: ref {
44 compatible = "fixed-cl 44 compatible = "fixed-clock";
45 #clock-cells = <0>; 45 #clock-cells = <0>;
46 clock-frequency = <250 46 clock-frequency = <25000000>;
47 }; 47 };
48 48
49 arm_timer_clk: arm-timer { 49 arm_timer_clk: arm-timer {
50 #clock-cells = <0>; 50 #clock-cells = <0>;
51 compatible = "fixed-cl 51 compatible = "fixed-clock";
52 clock-frequency = <500 52 clock-frequency = <50000000>;
53 }; 53 };
54 }; 54 };
55 55
56 soc { 56 soc {
57 compatible = "simple-bus"; 57 compatible = "simple-bus";
58 #address-cells = <1>; 58 #address-cells = <1>;
59 #size-cells = <1>; 59 #size-cells = <1>;
60 ranges; 60 ranges;
61 interrupt-parent = <&intc>; 61 interrupt-parent = <&intc>;
62 62
63 l2: cache-controller@500c0000 63 l2: cache-controller@500c0000 {
64 compatible = "socionex 64 compatible = "socionext,uniphier-system-cache";
65 reg = <0x500c0000 0x20 65 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
66 <0x506c0000 0x40 66 <0x506c0000 0x400>;
67 interrupts = <GIC_SPI 67 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
68 <GIC_SPI 68 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
69 cache-unified; 69 cache-unified;
70 cache-size = <(768 * 1 70 cache-size = <(768 * 1024)>;
71 cache-sets = <256>; 71 cache-sets = <256>;
72 cache-line-size = <128 72 cache-line-size = <128>;
73 cache-level = <2>; 73 cache-level = <2>;
74 }; 74 };
75 75
76 spi0: spi@54006000 { 76 spi0: spi@54006000 {
77 compatible = "socionex 77 compatible = "socionext,uniphier-scssi";
78 status = "disabled"; 78 status = "disabled";
79 reg = <0x54006000 0x10 79 reg = <0x54006000 0x100>;
80 #address-cells = <1>; 80 #address-cells = <1>;
81 #size-cells = <0>; 81 #size-cells = <0>;
82 interrupts = <GIC_SPI 82 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
83 pinctrl-names = "defau 83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_ 84 pinctrl-0 = <&pinctrl_spi0>;
85 clocks = <&peri_clk 11 85 clocks = <&peri_clk 11>;
86 resets = <&peri_rst 11 86 resets = <&peri_rst 11>;
87 }; 87 };
88 88
89 serial0: serial@54006800 { 89 serial0: serial@54006800 {
90 compatible = "socionex 90 compatible = "socionext,uniphier-uart";
91 status = "disabled"; 91 status = "disabled";
92 reg = <0x54006800 0x40 92 reg = <0x54006800 0x40>;
93 interrupts = <GIC_SPI 93 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
94 pinctrl-names = "defau 94 pinctrl-names = "default";
95 pinctrl-0 = <&pinctrl_ 95 pinctrl-0 = <&pinctrl_uart0>;
96 clocks = <&peri_clk 0> 96 clocks = <&peri_clk 0>;
97 resets = <&peri_rst 0> 97 resets = <&peri_rst 0>;
98 }; 98 };
99 99
100 serial1: serial@54006900 { 100 serial1: serial@54006900 {
101 compatible = "socionex 101 compatible = "socionext,uniphier-uart";
102 status = "disabled"; 102 status = "disabled";
103 reg = <0x54006900 0x40 103 reg = <0x54006900 0x40>;
104 interrupts = <GIC_SPI 104 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
105 pinctrl-names = "defau 105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_ 106 pinctrl-0 = <&pinctrl_uart1>;
107 clocks = <&peri_clk 1> 107 clocks = <&peri_clk 1>;
108 resets = <&peri_rst 1> 108 resets = <&peri_rst 1>;
109 }; 109 };
110 110
111 serial2: serial@54006a00 { 111 serial2: serial@54006a00 {
112 compatible = "socionex 112 compatible = "socionext,uniphier-uart";
113 status = "disabled"; 113 status = "disabled";
114 reg = <0x54006a00 0x40 114 reg = <0x54006a00 0x40>;
115 interrupts = <GIC_SPI 115 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
116 pinctrl-names = "defau 116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_ 117 pinctrl-0 = <&pinctrl_uart2>;
118 clocks = <&peri_clk 2> 118 clocks = <&peri_clk 2>;
119 resets = <&peri_rst 2> 119 resets = <&peri_rst 2>;
120 }; 120 };
121 121
122 serial3: serial@54006b00 { 122 serial3: serial@54006b00 {
123 compatible = "socionex 123 compatible = "socionext,uniphier-uart";
124 status = "disabled"; 124 status = "disabled";
125 reg = <0x54006b00 0x40 125 reg = <0x54006b00 0x40>;
126 interrupts = <GIC_SPI 126 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
127 pinctrl-names = "defau 127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_ 128 pinctrl-0 = <&pinctrl_uart3>;
129 clocks = <&peri_clk 3> 129 clocks = <&peri_clk 3>;
130 resets = <&peri_rst 3> 130 resets = <&peri_rst 3>;
131 }; 131 };
132 132
133 gpio: gpio@55000000 { 133 gpio: gpio@55000000 {
134 compatible = "socionex 134 compatible = "socionext,uniphier-gpio";
135 reg = <0x55000000 0x20 135 reg = <0x55000000 0x200>;
136 interrupt-parent = <&a 136 interrupt-parent = <&aidet>;
137 interrupt-controller; 137 interrupt-controller;
138 #interrupt-cells = <2> 138 #interrupt-cells = <2>;
139 gpio-controller; 139 gpio-controller;
140 #gpio-cells = <2>; 140 #gpio-cells = <2>;
141 gpio-ranges = <&pinctr 141 gpio-ranges = <&pinctrl 0 0 0>;
142 gpio-ranges-group-name 142 gpio-ranges-group-names = "gpio_range";
143 ngpios = <248>; 143 ngpios = <248>;
144 socionext,interrupt-ra 144 socionext,interrupt-ranges = <0 48 16>, <16 154 5>;
145 }; 145 };
146 146
147 i2c0: i2c@58780000 { 147 i2c0: i2c@58780000 {
148 compatible = "socionex 148 compatible = "socionext,uniphier-fi2c";
149 status = "disabled"; 149 status = "disabled";
150 reg = <0x58780000 0x80 150 reg = <0x58780000 0x80>;
151 #address-cells = <1>; 151 #address-cells = <1>;
152 #size-cells = <0>; 152 #size-cells = <0>;
153 interrupts = <GIC_SPI 153 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
154 pinctrl-names = "defau 154 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_ 155 pinctrl-0 = <&pinctrl_i2c0>;
156 clocks = <&peri_clk 4> 156 clocks = <&peri_clk 4>;
157 resets = <&peri_rst 4> 157 resets = <&peri_rst 4>;
158 clock-frequency = <100 158 clock-frequency = <100000>;
159 }; 159 };
160 160
161 i2c1: i2c@58781000 { 161 i2c1: i2c@58781000 {
162 compatible = "socionex 162 compatible = "socionext,uniphier-fi2c";
163 status = "disabled"; 163 status = "disabled";
164 reg = <0x58781000 0x80 164 reg = <0x58781000 0x80>;
165 #address-cells = <1>; 165 #address-cells = <1>;
166 #size-cells = <0>; 166 #size-cells = <0>;
167 interrupts = <GIC_SPI 167 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
168 pinctrl-names = "defau 168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_ 169 pinctrl-0 = <&pinctrl_i2c1>;
170 clocks = <&peri_clk 5> 170 clocks = <&peri_clk 5>;
171 resets = <&peri_rst 5> 171 resets = <&peri_rst 5>;
172 clock-frequency = <100 172 clock-frequency = <100000>;
173 }; 173 };
174 174
175 i2c2: i2c@58782000 { 175 i2c2: i2c@58782000 {
176 compatible = "socionex 176 compatible = "socionext,uniphier-fi2c";
177 status = "disabled"; 177 status = "disabled";
178 reg = <0x58782000 0x80 178 reg = <0x58782000 0x80>;
179 #address-cells = <1>; 179 #address-cells = <1>;
180 #size-cells = <0>; 180 #size-cells = <0>;
181 interrupts = <GIC_SPI 181 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
182 pinctrl-names = "defau 182 pinctrl-names = "default";
183 pinctrl-0 = <&pinctrl_ 183 pinctrl-0 = <&pinctrl_i2c2>;
184 clocks = <&peri_clk 6> 184 clocks = <&peri_clk 6>;
185 resets = <&peri_rst 6> 185 resets = <&peri_rst 6>;
186 clock-frequency = <100 186 clock-frequency = <100000>;
187 }; 187 };
188 188
189 i2c3: i2c@58783000 { 189 i2c3: i2c@58783000 {
190 compatible = "socionex 190 compatible = "socionext,uniphier-fi2c";
191 status = "disabled"; 191 status = "disabled";
192 reg = <0x58783000 0x80 192 reg = <0x58783000 0x80>;
193 #address-cells = <1>; 193 #address-cells = <1>;
194 #size-cells = <0>; 194 #size-cells = <0>;
195 interrupts = <GIC_SPI 195 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
196 pinctrl-names = "defau 196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_ 197 pinctrl-0 = <&pinctrl_i2c3>;
198 clocks = <&peri_clk 7> 198 clocks = <&peri_clk 7>;
199 resets = <&peri_rst 7> 199 resets = <&peri_rst 7>;
200 clock-frequency = <100 200 clock-frequency = <100000>;
201 }; 201 };
202 202
203 /* i2c4 does not exist */ 203 /* i2c4 does not exist */
204 204
205 /* chip-internal connection fo 205 /* chip-internal connection for DMD */
206 i2c5: i2c@58785000 { 206 i2c5: i2c@58785000 {
207 compatible = "socionex 207 compatible = "socionext,uniphier-fi2c";
208 reg = <0x58785000 0x80 208 reg = <0x58785000 0x80>;
209 #address-cells = <1>; 209 #address-cells = <1>;
210 #size-cells = <0>; 210 #size-cells = <0>;
211 interrupts = <GIC_SPI 211 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&peri_clk 9> 212 clocks = <&peri_clk 9>;
213 resets = <&peri_rst 9> 213 resets = <&peri_rst 9>;
214 clock-frequency = <400 214 clock-frequency = <400000>;
215 }; 215 };
216 216
217 /* chip-internal connection fo 217 /* chip-internal connection for HDMI */
218 i2c6: i2c@58786000 { 218 i2c6: i2c@58786000 {
219 compatible = "socionex 219 compatible = "socionext,uniphier-fi2c";
220 reg = <0x58786000 0x80 220 reg = <0x58786000 0x80>;
221 #address-cells = <1>; 221 #address-cells = <1>;
222 #size-cells = <0>; 222 #size-cells = <0>;
223 interrupts = <GIC_SPI 223 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&peri_clk 10 224 clocks = <&peri_clk 10>;
225 resets = <&peri_rst 10 225 resets = <&peri_rst 10>;
226 clock-frequency = <400 226 clock-frequency = <400000>;
227 }; 227 };
228 228
229 system_bus: system-bus@58c0000 229 system_bus: system-bus@58c00000 {
230 compatible = "socionex 230 compatible = "socionext,uniphier-system-bus";
231 status = "disabled"; 231 status = "disabled";
232 reg = <0x58c00000 0x40 232 reg = <0x58c00000 0x400>;
233 #address-cells = <2>; 233 #address-cells = <2>;
234 #size-cells = <1>; 234 #size-cells = <1>;
235 pinctrl-names = "defau 235 pinctrl-names = "default";
236 pinctrl-0 = <&pinctrl_ 236 pinctrl-0 = <&pinctrl_system_bus>;
237 }; 237 };
238 238
239 smpctrl@59801000 { 239 smpctrl@59801000 {
240 compatible = "socionex 240 compatible = "socionext,uniphier-smpctrl";
241 reg = <0x59801000 0x40 241 reg = <0x59801000 0x400>;
242 }; 242 };
243 243
244 mioctrl: syscon@59810000 { 244 mioctrl: syscon@59810000 {
245 compatible = "socionex 245 compatible = "socionext,uniphier-pro4-mioctrl",
246 "simple-m 246 "simple-mfd", "syscon";
247 reg = <0x59810000 0x80 247 reg = <0x59810000 0x800>;
248 248
249 mio_clk: clock-control 249 mio_clk: clock-controller {
250 compatible = " 250 compatible = "socionext,uniphier-pro4-mio-clock";
251 #clock-cells = 251 #clock-cells = <1>;
252 }; 252 };
253 253
254 mio_rst: reset-control 254 mio_rst: reset-controller {
255 compatible = " 255 compatible = "socionext,uniphier-pro4-mio-reset";
256 #reset-cells = 256 #reset-cells = <1>;
257 }; 257 };
258 }; 258 };
259 259
260 syscon@59820000 { 260 syscon@59820000 {
261 compatible = "socionex 261 compatible = "socionext,uniphier-pro4-perictrl",
262 "simple-m 262 "simple-mfd", "syscon";
263 reg = <0x59820000 0x20 263 reg = <0x59820000 0x200>;
264 264
265 peri_clk: clock-contro 265 peri_clk: clock-controller {
266 compatible = " 266 compatible = "socionext,uniphier-pro4-peri-clock";
267 #clock-cells = 267 #clock-cells = <1>;
268 }; 268 };
269 269
270 peri_rst: reset-contro 270 peri_rst: reset-controller {
271 compatible = " 271 compatible = "socionext,uniphier-pro4-peri-reset";
272 #reset-cells = 272 #reset-cells = <1>;
273 }; 273 };
274 }; 274 };
275 275
276 dmac: dma-controller@5a000000 276 dmac: dma-controller@5a000000 {
277 compatible = "socionex 277 compatible = "socionext,uniphier-mio-dmac";
278 reg = <0x5a000000 0x10 278 reg = <0x5a000000 0x1000>;
279 interrupts = <GIC_SPI 279 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 280 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 281 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 282 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 283 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 284 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 285 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 286 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
287 clocks = <&mio_clk 7>; 287 clocks = <&mio_clk 7>;
288 resets = <&mio_rst 7>; 288 resets = <&mio_rst 7>;
289 #dma-cells = <1>; 289 #dma-cells = <1>;
290 }; 290 };
291 291
292 sd: mmc@5a400000 { 292 sd: mmc@5a400000 {
293 compatible = "socionex 293 compatible = "socionext,uniphier-sd-v2.91";
294 status = "disabled"; 294 status = "disabled";
295 reg = <0x5a400000 0x20 295 reg = <0x5a400000 0x200>;
296 interrupts = <GIC_SPI 296 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
297 pinctrl-names = "defau 297 pinctrl-names = "default", "uhs";
298 pinctrl-0 = <&pinctrl_ 298 pinctrl-0 = <&pinctrl_sd>;
299 pinctrl-1 = <&pinctrl_ 299 pinctrl-1 = <&pinctrl_sd_uhs>;
300 clocks = <&mio_clk 0>; 300 clocks = <&mio_clk 0>;
301 reset-names = "host", 301 reset-names = "host", "bridge";
302 resets = <&mio_rst 0>, 302 resets = <&mio_rst 0>, <&mio_rst 3>;
303 dma-names = "rx-tx"; 303 dma-names = "rx-tx";
304 dmas = <&dmac 4>; 304 dmas = <&dmac 4>;
305 bus-width = <4>; 305 bus-width = <4>;
306 cap-sd-highspeed; 306 cap-sd-highspeed;
307 sd-uhs-sdr12; 307 sd-uhs-sdr12;
308 sd-uhs-sdr25; 308 sd-uhs-sdr25;
309 sd-uhs-sdr50; 309 sd-uhs-sdr50;
310 socionext,syscon-uhs-m 310 socionext,syscon-uhs-mode = <&mioctrl 0>;
311 }; 311 };
312 312
313 emmc: mmc@5a500000 { 313 emmc: mmc@5a500000 {
314 compatible = "socionex 314 compatible = "socionext,uniphier-sd-v2.91";
315 status = "disabled"; 315 status = "disabled";
316 reg = <0x5a500000 0x20 316 reg = <0x5a500000 0x200>;
317 interrupts = <GIC_SPI 317 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
318 pinctrl-names = "defau 318 pinctrl-names = "default";
319 pinctrl-0 = <&pinctrl_ 319 pinctrl-0 = <&pinctrl_emmc>;
320 clocks = <&mio_clk 1>; 320 clocks = <&mio_clk 1>;
321 reset-names = "host", 321 reset-names = "host", "bridge", "hw";
322 resets = <&mio_rst 1>, 322 resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
323 dma-names = "rx-tx"; 323 dma-names = "rx-tx";
324 dmas = <&dmac 5>; 324 dmas = <&dmac 5>;
325 bus-width = <8>; 325 bus-width = <8>;
326 cap-mmc-highspeed; 326 cap-mmc-highspeed;
327 cap-mmc-hw-reset; 327 cap-mmc-hw-reset;
328 non-removable; 328 non-removable;
329 }; 329 };
330 330
331 sd1: mmc@5a600000 { 331 sd1: mmc@5a600000 {
332 compatible = "socionex 332 compatible = "socionext,uniphier-sd-v2.91";
333 status = "disabled"; 333 status = "disabled";
334 reg = <0x5a600000 0x20 334 reg = <0x5a600000 0x200>;
335 interrupts = <GIC_SPI 335 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
336 pinctrl-names = "defau 336 pinctrl-names = "default";
337 pinctrl-0 = <&pinctrl_ 337 pinctrl-0 = <&pinctrl_sd1>;
338 clocks = <&mio_clk 2>; 338 clocks = <&mio_clk 2>;
339 reset-names = "host", 339 reset-names = "host", "bridge";
340 resets = <&mio_rst 2>, 340 resets = <&mio_rst 2>, <&mio_rst 5>;
341 dma-names = "rx-tx"; 341 dma-names = "rx-tx";
342 dmas = <&dmac 6>; 342 dmas = <&dmac 6>;
343 bus-width = <4>; 343 bus-width = <4>;
344 cap-sd-highspeed; 344 cap-sd-highspeed;
345 }; 345 };
346 346
347 usb2: usb@5a800100 { 347 usb2: usb@5a800100 {
348 compatible = "socionex 348 compatible = "socionext,uniphier-ehci", "generic-ehci";
349 status = "disabled"; 349 status = "disabled";
350 reg = <0x5a800100 0x10 350 reg = <0x5a800100 0x100>;
351 interrupts = <GIC_SPI 351 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
352 pinctrl-names = "defau 352 pinctrl-names = "default";
353 pinctrl-0 = <&pinctrl_ 353 pinctrl-0 = <&pinctrl_usb2>;
354 clocks = <&sys_clk 8>, 354 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
355 <&mio_clk 12> 355 <&mio_clk 12>;
356 resets = <&sys_rst 8>, 356 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
357 <&mio_rst 12> 357 <&mio_rst 12>;
358 phy-names = "usb"; 358 phy-names = "usb";
359 phys = <&usb_phy0>; 359 phys = <&usb_phy0>;
360 has-transaction-transl 360 has-transaction-translator;
361 }; 361 };
362 362
363 usb3: usb@5a810100 { 363 usb3: usb@5a810100 {
364 compatible = "socionex 364 compatible = "socionext,uniphier-ehci", "generic-ehci";
365 status = "disabled"; 365 status = "disabled";
366 reg = <0x5a810100 0x10 366 reg = <0x5a810100 0x100>;
367 interrupts = <GIC_SPI 367 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
368 pinctrl-names = "defau 368 pinctrl-names = "default";
369 pinctrl-0 = <&pinctrl_ 369 pinctrl-0 = <&pinctrl_usb3>;
370 clocks = <&sys_clk 8>, 370 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
371 <&mio_clk 13> 371 <&mio_clk 13>;
372 resets = <&sys_rst 8>, 372 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
373 <&mio_rst 13> 373 <&mio_rst 13>;
374 phy-names = "usb"; 374 phy-names = "usb";
375 phys = <&usb_phy1>; 375 phys = <&usb_phy1>;
376 has-transaction-transl 376 has-transaction-translator;
377 }; 377 };
378 378
379 soc_glue: syscon@5f800000 { 379 soc_glue: syscon@5f800000 {
380 compatible = "socionex 380 compatible = "socionext,uniphier-pro4-soc-glue",
381 "simple-m 381 "simple-mfd", "syscon";
382 reg = <0x5f800000 0x20 382 reg = <0x5f800000 0x2000>;
383 383
384 pinctrl: pinctrl { 384 pinctrl: pinctrl {
385 compatible = " 385 compatible = "socionext,uniphier-pro4-pinctrl";
386 }; 386 };
387 387
388 usb-hub { 388 usb-hub {
389 compatible = " 389 compatible = "socionext,uniphier-pro4-usb2-phy";
390 #address-cells 390 #address-cells = <1>;
391 #size-cells = 391 #size-cells = <0>;
392 392
393 usb_phy0: phy@ 393 usb_phy0: phy@0 {
394 reg = 394 reg = <0>;
395 #phy-c 395 #phy-cells = <0>;
396 }; 396 };
397 397
398 usb_phy1: phy@ 398 usb_phy1: phy@1 {
399 reg = 399 reg = <1>;
400 #phy-c 400 #phy-cells = <0>;
401 }; 401 };
402 402
403 usb_phy2: phy@ 403 usb_phy2: phy@2 {
404 reg = 404 reg = <2>;
405 #phy-c 405 #phy-cells = <0>;
406 vbus-s 406 vbus-supply = <&usb0_vbus>;
407 }; 407 };
408 408
409 usb_phy3: phy@ 409 usb_phy3: phy@3 {
410 reg = 410 reg = <3>;
411 #phy-c 411 #phy-cells = <0>;
412 vbus-s 412 vbus-supply = <&usb1_vbus>;
413 }; 413 };
414 }; 414 };
415 415
416 sg_clk: clock-controll 416 sg_clk: clock-controller {
417 compatible = " 417 compatible = "socionext,uniphier-pro4-sg-clock";
418 #clock-cells = 418 #clock-cells = <1>;
419 }; 419 };
420 }; 420 };
421 421
422 syscon@5f900000 { 422 syscon@5f900000 {
423 compatible = "socionex 423 compatible = "socionext,uniphier-pro4-soc-glue-debug",
424 "simple-m 424 "simple-mfd", "syscon";
425 reg = <0x5f900000 0x20 425 reg = <0x5f900000 0x2000>;
426 #address-cells = <1>; 426 #address-cells = <1>;
427 #size-cells = <1>; 427 #size-cells = <1>;
428 ranges = <0 0x5f900000 428 ranges = <0 0x5f900000 0x2000>;
429 429
430 efuse@100 { 430 efuse@100 {
431 compatible = " 431 compatible = "socionext,uniphier-efuse";
432 reg = <0x100 0 432 reg = <0x100 0x28>;
433 }; 433 };
434 434
435 efuse@130 { 435 efuse@130 {
436 compatible = " 436 compatible = "socionext,uniphier-efuse";
437 reg = <0x130 0 437 reg = <0x130 0x8>;
438 }; 438 };
439 439
440 efuse@200 { 440 efuse@200 {
441 compatible = " 441 compatible = "socionext,uniphier-efuse";
442 reg = <0x200 0 442 reg = <0x200 0x14>;
443 }; 443 };
444 }; 444 };
445 445
446 xdmac: dma-controller@5fc10000 446 xdmac: dma-controller@5fc10000 {
447 compatible = "socionex 447 compatible = "socionext,uniphier-xdmac";
448 reg = <0x5fc10000 0x53 448 reg = <0x5fc10000 0x5300>;
449 interrupts = <GIC_SPI 449 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
450 dma-channels = <16>; 450 dma-channels = <16>;
451 #dma-cells = <2>; 451 #dma-cells = <2>;
452 }; 452 };
453 453
454 aidet: interrupt-controller@5f 454 aidet: interrupt-controller@5fc20000 {
455 compatible = "socionex 455 compatible = "socionext,uniphier-pro4-aidet";
456 reg = <0x5fc20000 0x20 456 reg = <0x5fc20000 0x200>;
457 interrupt-controller; 457 interrupt-controller;
458 #interrupt-cells = <2> 458 #interrupt-cells = <2>;
459 }; 459 };
460 460
461 timer@60000200 { 461 timer@60000200 {
462 compatible = "arm,cort 462 compatible = "arm,cortex-a9-global-timer";
463 reg = <0x60000200 0x20 463 reg = <0x60000200 0x20>;
464 interrupts = <GIC_PPI 464 interrupts = <GIC_PPI 11
465 (GIC_CPU_MASK_ 465 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
466 clocks = <&arm_timer_c 466 clocks = <&arm_timer_clk>;
467 }; 467 };
468 468
469 timer@60000600 { 469 timer@60000600 {
470 compatible = "arm,cort 470 compatible = "arm,cortex-a9-twd-timer";
471 reg = <0x60000600 0x20 471 reg = <0x60000600 0x20>;
472 interrupts = <GIC_PPI 472 interrupts = <GIC_PPI 13
473 (GIC_CPU_MASK_ 473 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
474 clocks = <&arm_timer_c 474 clocks = <&arm_timer_clk>;
475 }; 475 };
476 476
477 intc: interrupt-controller@600 477 intc: interrupt-controller@60001000 {
478 compatible = "arm,cort 478 compatible = "arm,cortex-a9-gic";
479 reg = <0x60001000 0x10 479 reg = <0x60001000 0x1000>,
480 <0x60000100 0x10 480 <0x60000100 0x100>;
481 #interrupt-cells = <3> 481 #interrupt-cells = <3>;
482 interrupt-controller; 482 interrupt-controller;
483 }; 483 };
484 484
485 syscon@61840000 { 485 syscon@61840000 {
486 compatible = "socionex 486 compatible = "socionext,uniphier-pro4-sysctrl",
487 "simple-m 487 "simple-mfd", "syscon";
488 reg = <0x61840000 0x10 488 reg = <0x61840000 0x10000>;
489 489
490 sys_clk: clock-control 490 sys_clk: clock-controller {
491 compatible = " 491 compatible = "socionext,uniphier-pro4-clock";
492 #clock-cells = 492 #clock-cells = <1>;
493 }; 493 };
494 494
495 sys_rst: reset-control 495 sys_rst: reset-controller {
496 compatible = " 496 compatible = "socionext,uniphier-pro4-reset";
497 #reset-cells = 497 #reset-cells = <1>;
498 }; 498 };
499 }; 499 };
500 500
501 eth: ethernet@65000000 { 501 eth: ethernet@65000000 {
502 compatible = "socionex 502 compatible = "socionext,uniphier-pro4-ave4";
503 status = "disabled"; 503 status = "disabled";
504 reg = <0x65000000 0x85 504 reg = <0x65000000 0x8500>;
505 interrupts = <GIC_SPI 505 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
506 pinctrl-names = "defau 506 pinctrl-names = "default";
507 pinctrl-0 = <&pinctrl_ 507 pinctrl-0 = <&pinctrl_ether_rgmii>;
508 clock-names = "gio", " 508 clock-names = "gio", "ether", "ether-gb", "ether-phy";
509 clocks = <&sys_clk 12> 509 clocks = <&sys_clk 12>, <&sys_clk 6>, <&sys_clk 7>,
510 <&sys_clk 10> 510 <&sys_clk 10>;
511 reset-names = "gio", " 511 reset-names = "gio", "ether";
512 resets = <&sys_rst 12> 512 resets = <&sys_rst 12>, <&sys_rst 6>;
513 phy-mode = "rgmii"; 513 phy-mode = "rgmii";
514 local-mac-address = [0 514 local-mac-address = [00 00 00 00 00 00];
515 socionext,syscon-phy-m 515 socionext,syscon-phy-mode = <&soc_glue 0>;
516 516
517 mdio: mdio { 517 mdio: mdio {
518 #address-cells 518 #address-cells = <1>;
519 #size-cells = 519 #size-cells = <0>;
520 }; 520 };
521 }; 521 };
522 522
523 ahci0: sata@65600000 { 523 ahci0: sata@65600000 {
524 compatible = "socionex 524 compatible = "socionext,uniphier-pro4-ahci",
525 "generic- 525 "generic-ahci";
526 status = "disabled"; 526 status = "disabled";
527 reg = <0x65600000 0x10 527 reg = <0x65600000 0x10000>;
528 interrupts = <GIC_SPI 528 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
529 clocks = <&sys_clk 12> 529 clocks = <&sys_clk 12>, <&sys_clk 28>;
530 resets = <&sys_rst 12> 530 resets = <&sys_rst 12>, <&sys_rst 28>, <&ahci0_rst 3>;
531 ports-implemented = <1 531 ports-implemented = <1>;
532 phys = <&ahci0_phy>; 532 phys = <&ahci0_phy>;
533 assigned-clocks = <&sg 533 assigned-clocks = <&sg_clk 0>;
534 assigned-clock-rates = 534 assigned-clock-rates = <25000000>;
535 }; 535 };
536 536
537 sata-controller@65700000 { 537 sata-controller@65700000 {
538 compatible = "socionex 538 compatible = "socionext,uniphier-pxs2-ahci-glue",
539 "simple-m 539 "simple-mfd";
540 reg = <0x65700000 0x10 540 reg = <0x65700000 0x100>;
541 #address-cells = <1>; 541 #address-cells = <1>;
542 #size-cells = <1>; 542 #size-cells = <1>;
543 ranges = <0 0x65700000 543 ranges = <0 0x65700000 0x100>;
544 544
545 ahci0_rst: reset-contr 545 ahci0_rst: reset-controller@0 {
546 compatible = " 546 compatible = "socionext,uniphier-pro4-ahci-reset";
547 reg = <0x0 0x4 547 reg = <0x0 0x4>;
548 clock-names = 548 clock-names = "gio", "link";
549 clocks = <&sys 549 clocks = <&sys_clk 12>, <&sys_clk 28>;
550 reset-names = 550 reset-names = "gio", "link";
551 resets = <&sys 551 resets = <&sys_rst 12>, <&sys_rst 28>;
552 #reset-cells = 552 #reset-cells = <1>;
553 }; 553 };
554 554
555 ahci0_phy: phy@10 { 555 ahci0_phy: phy@10 {
556 compatible = " 556 compatible = "socionext,uniphier-pro4-ahci-phy";
557 reg = <0x10 0x 557 reg = <0x10 0x40>;
558 clock-names = 558 clock-names = "link", "gio";
559 clocks = <&sys 559 clocks = <&sys_clk 28>, <&sys_clk 12>;
560 reset-names = 560 reset-names = "link", "gio", "phy",
561 561 "pm", "tx", "rx";
562 resets = <&sys 562 resets = <&sys_rst 28>, <&sys_rst 12>,
563 <&sys 563 <&sys_rst 30>,
564 <&ahc 564 <&ahci0_rst 0>, <&ahci0_rst 1>,
565 <&ahc 565 <&ahci0_rst 2>;
566 #phy-cells = < 566 #phy-cells = <0>;
567 }; 567 };
568 }; 568 };
569 569
570 ahci1: sata@65800000 { 570 ahci1: sata@65800000 {
571 compatible = "socionex 571 compatible = "socionext,uniphier-pro4-ahci",
572 "generic- 572 "generic-ahci";
573 status = "disabled"; 573 status = "disabled";
574 reg = <0x65800000 0x10 574 reg = <0x65800000 0x10000>;
575 interrupts = <GIC_SPI 575 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
576 clocks = <&sys_clk 12> 576 clocks = <&sys_clk 12>, <&sys_clk 29>;
577 resets = <&sys_rst 12> 577 resets = <&sys_rst 12>, <&sys_rst 29>, <&ahci1_rst 3>;
578 ports-implemented = <1 578 ports-implemented = <1>;
579 phys = <&ahci1_phy>; 579 phys = <&ahci1_phy>;
580 assigned-clocks = <&sg 580 assigned-clocks = <&sg_clk 0>;
581 assigned-clock-rates = 581 assigned-clock-rates = <25000000>;
582 }; 582 };
583 583
584 sata-controller@65900000 { 584 sata-controller@65900000 {
585 compatible = "socionex 585 compatible = "socionext,uniphier-pro4-ahci-glue",
586 "simple-m 586 "simple-mfd";
587 reg = <0x65900000 0x10 587 reg = <0x65900000 0x100>;
588 #address-cells = <1>; 588 #address-cells = <1>;
589 #size-cells = <1>; 589 #size-cells = <1>;
590 ranges = <0 0x65900000 590 ranges = <0 0x65900000 0x100>;
591 591
592 ahci1_rst: reset-contr 592 ahci1_rst: reset-controller@0 {
593 compatible = " 593 compatible = "socionext,uniphier-pro4-ahci-reset";
594 reg = <0x0 0x4 594 reg = <0x0 0x4>;
595 clock-names = 595 clock-names = "gio", "link";
596 clocks = <&sys 596 clocks = <&sys_clk 12>, <&sys_clk 29>;
597 reset-names = 597 reset-names = "gio", "link";
598 resets = <&sys 598 resets = <&sys_rst 12>, <&sys_rst 29>;
599 #reset-cells = 599 #reset-cells = <1>;
600 }; 600 };
601 601
602 ahci1_phy: phy@10 { 602 ahci1_phy: phy@10 {
603 compatible = " 603 compatible = "socionext,uniphier-pro4-ahci-phy";
604 reg = <0x10 0x 604 reg = <0x10 0x40>;
605 clock-names = 605 clock-names = "link", "gio";
606 clocks = <&sys 606 clocks = <&sys_clk 29>, <&sys_clk 12>;
607 reset-names = 607 reset-names = "link", "gio", "phy",
608 608 "pm", "tx", "rx";
609 resets = <&sys 609 resets = <&sys_rst 29>, <&sys_rst 12>,
610 <&sys 610 <&sys_rst 30>,
611 <&ahc 611 <&ahci1_rst 0>, <&ahci1_rst 1>,
612 <&ahc 612 <&ahci1_rst 2>;
613 #phy-cells = < 613 #phy-cells = <0>;
614 }; 614 };
615 }; 615 };
616 616
617 usb0: usb@65a00000 { 617 usb0: usb@65a00000 {
618 compatible = "socionex 618 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
619 status = "disabled"; 619 status = "disabled";
620 reg = <0x65a00000 0xcd 620 reg = <0x65a00000 0xcd00>;
621 interrupt-names = "hos 621 interrupt-names = "host", "peripheral";
622 interrupts = <GIC_SPI 622 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
623 <GIC_SPI 623 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
624 pinctrl-names = "defau 624 pinctrl-names = "default";
625 pinctrl-0 = <&pinctrl_ 625 pinctrl-0 = <&pinctrl_usb0>;
626 clock-names = "ref", " 626 clock-names = "ref", "bus_early", "suspend";
627 clocks = <&sys_clk 12> 627 clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
628 resets = <&usb0_rst 4> 628 resets = <&usb0_rst 4>;
629 phys = <&usb_phy2>, <& 629 phys = <&usb_phy2>, <&usb0_ssphy>;
630 dr_mode = "host"; 630 dr_mode = "host";
631 }; 631 };
632 632
633 usb-controller@65b00000 { 633 usb-controller@65b00000 {
634 compatible = "socionex 634 compatible = "socionext,uniphier-pro4-dwc3-glue",
635 "simple-m 635 "simple-mfd";
636 reg = <0x65b00000 0x10 636 reg = <0x65b00000 0x100>;
637 #address-cells = <1>; 637 #address-cells = <1>;
638 #size-cells = <1>; 638 #size-cells = <1>;
639 ranges = <0 0x65b00000 639 ranges = <0 0x65b00000 0x100>;
640 640
641 usb0_vbus: regulator@0 641 usb0_vbus: regulator@0 {
642 compatible = " 642 compatible = "socionext,uniphier-pro4-usb3-regulator";
643 reg = <0 0x10> 643 reg = <0 0x10>;
644 clock-names = 644 clock-names = "gio", "link";
645 clocks = <&sys 645 clocks = <&sys_clk 12>, <&sys_clk 14>;
646 reset-names = 646 reset-names = "gio", "link";
647 resets = <&sys 647 resets = <&sys_rst 12>, <&sys_rst 14>;
648 }; 648 };
649 649
650 usb0_ssphy: phy@10 { 650 usb0_ssphy: phy@10 {
651 compatible = " 651 compatible = "socionext,uniphier-pro4-usb3-ssphy";
652 reg = <0x10 0x 652 reg = <0x10 0x10>;
653 #phy-cells = < 653 #phy-cells = <0>;
654 clock-names = 654 clock-names = "gio", "link";
655 clocks = <&sys 655 clocks = <&sys_clk 12>, <&sys_clk 14>;
656 reset-names = 656 reset-names = "gio", "link";
657 resets = <&sys 657 resets = <&sys_rst 12>, <&sys_rst 14>;
658 vbus-supply = 658 vbus-supply = <&usb0_vbus>;
659 }; 659 };
660 660
661 usb0_rst: reset-contro 661 usb0_rst: reset-controller@40 {
662 compatible = " 662 compatible = "socionext,uniphier-pro4-usb3-reset";
663 reg = <0x40 0x 663 reg = <0x40 0x4>;
664 #reset-cells = 664 #reset-cells = <1>;
665 clock-names = 665 clock-names = "gio", "link";
666 clocks = <&sys 666 clocks = <&sys_clk 12>, <&sys_clk 14>;
667 reset-names = 667 reset-names = "gio", "link";
668 resets = <&sys 668 resets = <&sys_rst 12>, <&sys_rst 14>;
669 }; 669 };
670 }; 670 };
671 671
672 usb1: usb@65c00000 { 672 usb1: usb@65c00000 {
673 compatible = "socionex 673 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
674 status = "disabled"; 674 status = "disabled";
675 reg = <0x65c00000 0xcd 675 reg = <0x65c00000 0xcd00>;
676 interrupt-names = "hos 676 interrupt-names = "host", "peripheral";
677 interrupts = <GIC_SPI 677 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
678 <GIC_SPI 678 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
679 pinctrl-names = "defau 679 pinctrl-names = "default";
680 pinctrl-0 = <&pinctrl_ 680 pinctrl-0 = <&pinctrl_usb1>;
681 clock-names = "ref", " 681 clock-names = "ref", "bus_early", "suspend";
682 clocks = <&sys_clk 12> 682 clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
683 resets = <&usb1_rst 4> 683 resets = <&usb1_rst 4>;
684 phys = <&usb_phy3>; 684 phys = <&usb_phy3>;
685 dr_mode = "host"; 685 dr_mode = "host";
686 }; 686 };
687 687
688 usb-controller@65d00000 { 688 usb-controller@65d00000 {
689 compatible = "socionex 689 compatible = "socionext,uniphier-pro4-dwc3-glue",
690 "simple-m 690 "simple-mfd";
691 reg = <0x65d00000 0x10 691 reg = <0x65d00000 0x100>;
692 #address-cells = <1>; 692 #address-cells = <1>;
693 #size-cells = <1>; 693 #size-cells = <1>;
694 ranges = <0 0x65d00000 694 ranges = <0 0x65d00000 0x100>;
695 695
696 usb1_vbus: regulator@0 696 usb1_vbus: regulator@0 {
697 compatible = " 697 compatible = "socionext,uniphier-pro4-usb3-regulator";
698 reg = <0 0x10> 698 reg = <0 0x10>;
699 clock-names = 699 clock-names = "gio", "link";
700 clocks = <&sys 700 clocks = <&sys_clk 12>, <&sys_clk 15>;
701 reset-names = 701 reset-names = "gio", "link";
702 resets = <&sys 702 resets = <&sys_rst 12>, <&sys_rst 15>;
703 }; 703 };
704 704
705 usb1_rst: reset-contro 705 usb1_rst: reset-controller@40 {
706 compatible = " 706 compatible = "socionext,uniphier-pro4-usb3-reset";
707 reg = <0x40 0x 707 reg = <0x40 0x4>;
708 #reset-cells = 708 #reset-cells = <1>;
709 clock-names = 709 clock-names = "gio", "link";
710 clocks = <&sys 710 clocks = <&sys_clk 12>, <&sys_clk 15>;
711 reset-names = 711 reset-names = "gio", "link";
712 resets = <&sys 712 resets = <&sys_rst 12>, <&sys_rst 15>;
713 }; 713 };
714 }; 714 };
715 715
716 nand: nand-controller@68000000 716 nand: nand-controller@68000000 {
717 compatible = "socionex 717 compatible = "socionext,uniphier-denali-nand-v5a";
718 status = "disabled"; 718 status = "disabled";
719 reg-names = "nand_data 719 reg-names = "nand_data", "denali_reg";
720 reg = <0x68000000 0x20 720 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
721 #address-cells = <1>; 721 #address-cells = <1>;
722 #size-cells = <0>; 722 #size-cells = <0>;
723 interrupts = <GIC_SPI 723 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
724 pinctrl-names = "defau 724 pinctrl-names = "default";
725 pinctrl-0 = <&pinctrl_ 725 pinctrl-0 = <&pinctrl_nand>;
726 clock-names = "nand", 726 clock-names = "nand", "nand_x", "ecc";
727 clocks = <&sys_clk 2>, 727 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
728 reset-names = "nand", 728 reset-names = "nand", "reg";
729 resets = <&sys_rst 2>, 729 resets = <&sys_rst 2>, <&sys_rst 2>;
730 }; 730 };
731 }; 731 };
732 }; 732 };
733 733
734 #include "uniphier-pinctrl.dtsi" 734 #include "uniphier-pinctrl.dtsi"
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