1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
2 //
3 // Device Tree Source for UniPhier PXs2 SoC
4 //
5 // Copyright (C) 2015-2016 Socionext Inc.
6 // Author: Masahiro Yamada <yamada.masahiro@s
7
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/interrupt-controller/arm
10 #include <dt-bindings/thermal/thermal.h>
11
12 / {
13 compatible = "socionext,uniphier-pxs2"
14 #address-cells = <1>;
15 #size-cells = <1>;
16
17 cpus {
18 #address-cells = <1>;
19 #size-cells = <0>;
20
21 cpu0: cpu@0 {
22 device_type = "cpu";
23 compatible = "arm,cort
24 reg = <0>;
25 clocks = <&sys_clk 32>
26 enable-method = "psci"
27 next-level-cache = <&l
28 operating-points-v2 =
29 #cooling-cells = <2>;
30 };
31
32 cpu1: cpu@1 {
33 device_type = "cpu";
34 compatible = "arm,cort
35 reg = <1>;
36 clocks = <&sys_clk 32>
37 enable-method = "psci"
38 next-level-cache = <&l
39 operating-points-v2 =
40 #cooling-cells = <2>;
41 };
42
43 cpu2: cpu@2 {
44 device_type = "cpu";
45 compatible = "arm,cort
46 reg = <2>;
47 clocks = <&sys_clk 32>
48 enable-method = "psci"
49 next-level-cache = <&l
50 operating-points-v2 =
51 #cooling-cells = <2>;
52 };
53
54 cpu3: cpu@3 {
55 device_type = "cpu";
56 compatible = "arm,cort
57 reg = <3>;
58 clocks = <&sys_clk 32>
59 enable-method = "psci"
60 next-level-cache = <&l
61 operating-points-v2 =
62 #cooling-cells = <2>;
63 };
64 };
65
66 cpu_opp: opp-table {
67 compatible = "operating-points
68 opp-shared;
69
70 opp-100000000 {
71 opp-hz = /bits/ 64 <10
72 clock-latency-ns = <30
73 };
74 opp-150000000 {
75 opp-hz = /bits/ 64 <15
76 clock-latency-ns = <30
77 };
78 opp-200000000 {
79 opp-hz = /bits/ 64 <20
80 clock-latency-ns = <30
81 };
82 opp-300000000 {
83 opp-hz = /bits/ 64 <30
84 clock-latency-ns = <30
85 };
86 opp-400000000 {
87 opp-hz = /bits/ 64 <40
88 clock-latency-ns = <30
89 };
90 opp-600000000 {
91 opp-hz = /bits/ 64 <60
92 clock-latency-ns = <30
93 };
94 opp-800000000 {
95 opp-hz = /bits/ 64 <80
96 clock-latency-ns = <30
97 };
98 opp-1200000000 {
99 opp-hz = /bits/ 64 <12
100 clock-latency-ns = <30
101 };
102 };
103
104 psci {
105 compatible = "arm,psci-0.2";
106 method = "smc";
107 };
108
109 clocks {
110 refclk: ref {
111 compatible = "fixed-cl
112 #clock-cells = <0>;
113 clock-frequency = <250
114 };
115
116 arm_timer_clk: arm-timer {
117 #clock-cells = <0>;
118 compatible = "fixed-cl
119 clock-frequency = <500
120 };
121 };
122
123 thermal-zones {
124 cpu-thermal {
125 polling-delay-passive
126 polling-delay = <1000>
127 thermal-sensors = <&pv
128
129 trips {
130 cpu_crit: cpu-
131 temper
132 hyster
133 type =
134 };
135 cpu_alert: cpu
136 temper
137 hyster
138 type =
139 };
140 };
141
142 cooling-maps {
143 map {
144 trip =
145 coolin
146
147
148
149 };
150 };
151 };
152 };
153
154 soc {
155 compatible = "simple-bus";
156 #address-cells = <1>;
157 #size-cells = <1>;
158 ranges;
159 interrupt-parent = <&intc>;
160
161 l2: cache-controller@500c0000
162 compatible = "socionex
163 reg = <0x500c0000 0x20
164 <0x506c0000 0x40
165 interrupts = <GIC_SPI
166 <GIC_SPI
167 <GIC_SPI
168 <GIC_SPI
169 cache-unified;
170 cache-size = <(1280 *
171 cache-sets = <512>;
172 cache-line-size = <128
173 cache-level = <2>;
174 };
175
176 spi0: spi@54006000 {
177 compatible = "socionex
178 status = "disabled";
179 reg = <0x54006000 0x10
180 #address-cells = <1>;
181 #size-cells = <0>;
182 interrupts = <GIC_SPI
183 pinctrl-names = "defau
184 pinctrl-0 = <&pinctrl_
185 clocks = <&peri_clk 11
186 resets = <&peri_rst 11
187 };
188
189 spi1: spi@54006100 {
190 compatible = "socionex
191 status = "disabled";
192 reg = <0x54006100 0x10
193 #address-cells = <1>;
194 #size-cells = <0>;
195 interrupts = <GIC_SPI
196 pinctrl-names = "defau
197 pinctrl-0 = <&pinctrl_
198 clocks = <&peri_clk 12
199 resets = <&peri_rst 12
200 };
201
202 serial0: serial@54006800 {
203 compatible = "socionex
204 status = "disabled";
205 reg = <0x54006800 0x40
206 interrupts = <GIC_SPI
207 pinctrl-names = "defau
208 pinctrl-0 = <&pinctrl_
209 clocks = <&peri_clk 0>
210 resets = <&peri_rst 0>
211 };
212
213 serial1: serial@54006900 {
214 compatible = "socionex
215 status = "disabled";
216 reg = <0x54006900 0x40
217 interrupts = <GIC_SPI
218 pinctrl-names = "defau
219 pinctrl-0 = <&pinctrl_
220 clocks = <&peri_clk 1>
221 resets = <&peri_rst 1>
222 };
223
224 serial2: serial@54006a00 {
225 compatible = "socionex
226 status = "disabled";
227 reg = <0x54006a00 0x40
228 interrupts = <GIC_SPI
229 pinctrl-names = "defau
230 pinctrl-0 = <&pinctrl_
231 clocks = <&peri_clk 2>
232 resets = <&peri_rst 2>
233 };
234
235 serial3: serial@54006b00 {
236 compatible = "socionex
237 status = "disabled";
238 reg = <0x54006b00 0x40
239 interrupts = <GIC_SPI
240 pinctrl-names = "defau
241 pinctrl-0 = <&pinctrl_
242 clocks = <&peri_clk 3>
243 resets = <&peri_rst 3>
244 };
245
246 gpio: gpio@55000000 {
247 compatible = "socionex
248 reg = <0x55000000 0x20
249 interrupt-parent = <&a
250 interrupt-controller;
251 #interrupt-cells = <2>
252 gpio-controller;
253 #gpio-cells = <2>;
254 gpio-ranges = <&pinctr
255 <&pinctr
256 gpio-ranges-group-name
257
258 ngpios = <232>;
259 socionext,interrupt-ra
260
261 };
262
263 audio@56000000 {
264 compatible = "socionex
265 reg = <0x56000000 0x80
266 interrupts = <GIC_SPI
267 pinctrl-names = "defau
268 pinctrl-0 = <&pinctrl_
269 <&pinctrl_
270 <&pinctrl_
271 <&pinctrl_
272 <&pinctrl_
273 <&pinctrl_
274 <&pinctrl_
275 clock-names = "aio";
276 clocks = <&sys_clk 40>
277 reset-names = "aio";
278 resets = <&sys_rst 40>
279 #sound-dai-cells = <1>
280 socionext,syscon = <&s
281
282 i2s_port0: port@0 {
283 i2s_hdmi: endp
284 };
285 };
286
287 i2s_port1: port@1 {
288 i2s_line: endp
289 };
290 };
291
292 i2s_port2: port@2 {
293 i2s_aux: endpo
294 };
295 };
296
297 spdif_port0: port@3 {
298 spdif_hiecout1
299 };
300 };
301
302 spdif_port1: port@4 {
303 spdif_iecout1:
304 };
305 };
306
307 comp_spdif_port0: port
308 comp_spdif_hie
309 };
310 };
311
312 comp_spdif_port1: port
313 comp_spdif_iec
314 };
315 };
316 };
317
318 i2c0: i2c@58780000 {
319 compatible = "socionex
320 status = "disabled";
321 reg = <0x58780000 0x80
322 #address-cells = <1>;
323 #size-cells = <0>;
324 interrupts = <GIC_SPI
325 pinctrl-names = "defau
326 pinctrl-0 = <&pinctrl_
327 clocks = <&peri_clk 4>
328 resets = <&peri_rst 4>
329 clock-frequency = <100
330 };
331
332 i2c1: i2c@58781000 {
333 compatible = "socionex
334 status = "disabled";
335 reg = <0x58781000 0x80
336 #address-cells = <1>;
337 #size-cells = <0>;
338 interrupts = <GIC_SPI
339 pinctrl-names = "defau
340 pinctrl-0 = <&pinctrl_
341 clocks = <&peri_clk 5>
342 resets = <&peri_rst 5>
343 clock-frequency = <100
344 };
345
346 i2c2: i2c@58782000 {
347 compatible = "socionex
348 status = "disabled";
349 reg = <0x58782000 0x80
350 #address-cells = <1>;
351 #size-cells = <0>;
352 interrupts = <GIC_SPI
353 pinctrl-names = "defau
354 pinctrl-0 = <&pinctrl_
355 clocks = <&peri_clk 6>
356 resets = <&peri_rst 6>
357 clock-frequency = <100
358 };
359
360 i2c3: i2c@58783000 {
361 compatible = "socionex
362 status = "disabled";
363 reg = <0x58783000 0x80
364 #address-cells = <1>;
365 #size-cells = <0>;
366 interrupts = <GIC_SPI
367 pinctrl-names = "defau
368 pinctrl-0 = <&pinctrl_
369 clocks = <&peri_clk 7>
370 resets = <&peri_rst 7>
371 clock-frequency = <100
372 };
373
374 /* chip-internal connection fo
375 i2c4: i2c@58784000 {
376 compatible = "socionex
377 reg = <0x58784000 0x80
378 #address-cells = <1>;
379 #size-cells = <0>;
380 interrupts = <GIC_SPI
381 clocks = <&peri_clk 8>
382 resets = <&peri_rst 8>
383 clock-frequency = <400
384 };
385
386 /* chip-internal connection fo
387 i2c5: i2c@58785000 {
388 compatible = "socionex
389 reg = <0x58785000 0x80
390 #address-cells = <1>;
391 #size-cells = <0>;
392 interrupts = <GIC_SPI
393 clocks = <&peri_clk 9>
394 resets = <&peri_rst 9>
395 clock-frequency = <400
396 };
397
398 /* chip-internal connection fo
399 i2c6: i2c@58786000 {
400 compatible = "socionex
401 reg = <0x58786000 0x80
402 #address-cells = <1>;
403 #size-cells = <0>;
404 interrupts = <GIC_SPI
405 clocks = <&peri_clk 10
406 resets = <&peri_rst 10
407 clock-frequency = <400
408 };
409
410 system_bus: system-bus@58c0000
411 compatible = "socionex
412 status = "disabled";
413 reg = <0x58c00000 0x40
414 #address-cells = <2>;
415 #size-cells = <1>;
416 pinctrl-names = "defau
417 pinctrl-0 = <&pinctrl_
418 };
419
420 smpctrl@59801000 {
421 compatible = "socionex
422 reg = <0x59801000 0x40
423 };
424
425 sdctrl: syscon@59810000 {
426 compatible = "socionex
427 "simple-m
428 reg = <0x59810000 0x40
429
430 sd_clk: clock-controll
431 compatible = "
432 #clock-cells =
433 };
434
435 sd_rst: reset-controll
436 compatible = "
437 #reset-cells =
438 };
439 };
440
441 syscon@59820000 {
442 compatible = "socionex
443 "simple-m
444 reg = <0x59820000 0x20
445
446 peri_clk: clock-contro
447 compatible = "
448 #clock-cells =
449 };
450
451 peri_rst: reset-contro
452 compatible = "
453 #reset-cells =
454 };
455 };
456
457 emmc: mmc@5a000000 {
458 compatible = "socionex
459 status = "disabled";
460 reg = <0x5a000000 0x80
461 interrupts = <GIC_SPI
462 pinctrl-names = "defau
463 pinctrl-0 = <&pinctrl_
464 clocks = <&sd_clk 1>;
465 reset-names = "host",
466 resets = <&sd_rst 1>,
467 bus-width = <8>;
468 cap-mmc-highspeed;
469 cap-mmc-hw-reset;
470 non-removable;
471 };
472
473 sd: mmc@5a400000 {
474 compatible = "socionex
475 status = "disabled";
476 reg = <0x5a400000 0x80
477 interrupts = <GIC_SPI
478 pinctrl-names = "defau
479 pinctrl-0 = <&pinctrl_
480 pinctrl-1 = <&pinctrl_
481 clocks = <&sd_clk 0>;
482 reset-names = "host";
483 resets = <&sd_rst 0>;
484 bus-width = <4>;
485 cap-sd-highspeed;
486 sd-uhs-sdr12;
487 sd-uhs-sdr25;
488 sd-uhs-sdr50;
489 socionext,syscon-uhs-m
490 };
491
492 soc_glue: syscon@5f800000 {
493 compatible = "socionex
494 "simple-m
495 reg = <0x5f800000 0x20
496
497 pinctrl: pinctrl {
498 compatible = "
499 };
500 };
501
502 syscon@5f900000 {
503 compatible = "socionex
504 "simple-m
505 reg = <0x5f900000 0x20
506 #address-cells = <1>;
507 #size-cells = <1>;
508 ranges = <0 0x5f900000
509
510 efuse@100 {
511 compatible = "
512 reg = <0x100 0
513 };
514
515 efuse@200 {
516 compatible = "
517 reg = <0x200 0
518 };
519 };
520
521 xdmac: dma-controller@5fc10000
522 compatible = "socionex
523 reg = <0x5fc10000 0x53
524 interrupts = <GIC_SPI
525 dma-channels = <16>;
526 #dma-cells = <2>;
527 };
528
529 aidet: interrupt-controller@5f
530 compatible = "socionex
531 reg = <0x5fc20000 0x20
532 interrupt-controller;
533 #interrupt-cells = <2>
534 };
535
536 timer@60000200 {
537 compatible = "arm,cort
538 reg = <0x60000200 0x20
539 interrupts = <GIC_PPI
540 (GIC_CPU_MASK_
541 clocks = <&arm_timer_c
542 };
543
544 timer@60000600 {
545 compatible = "arm,cort
546 reg = <0x60000600 0x20
547 interrupts = <GIC_PPI
548 (GIC_CPU_MASK_
549 clocks = <&arm_timer_c
550 };
551
552 intc: interrupt-controller@600
553 compatible = "arm,cort
554 reg = <0x60001000 0x10
555 <0x60000100 0x10
556 #interrupt-cells = <3>
557 interrupt-controller;
558 };
559
560 syscon@61840000 {
561 compatible = "socionex
562 "simple-m
563 reg = <0x61840000 0x10
564
565 sys_clk: clock-control
566 compatible = "
567 #clock-cells =
568 };
569
570 sys_rst: reset-control
571 compatible = "
572 #reset-cells =
573 };
574
575 pvtctl: thermal-sensor
576 compatible = "
577 interrupts = <
578 #thermal-senso
579 socionext,tmod
580 };
581 };
582
583 eth: ethernet@65000000 {
584 compatible = "socionex
585 status = "disabled";
586 reg = <0x65000000 0x85
587 interrupts = <GIC_SPI
588 pinctrl-names = "defau
589 pinctrl-0 = <&pinctrl_
590 clock-names = "ether";
591 clocks = <&sys_clk 6>;
592 reset-names = "ether";
593 resets = <&sys_rst 6>;
594 phy-mode = "rgmii-id";
595 local-mac-address = [0
596 socionext,syscon-phy-m
597
598 mdio: mdio {
599 #address-cells
600 #size-cells =
601 };
602 };
603
604 ahci: sata@65600000 {
605 compatible = "socionex
606 "generic-
607 status = "disabled";
608 reg = <0x65600000 0x10
609 interrupts = <GIC_SPI
610 clocks = <&sys_clk 28>
611 resets = <&sys_rst 28>
612 ports-implemented = <1
613 phys = <&ahci_phy>;
614 };
615
616 sata-controller@65700000 {
617 compatible = "socionex
618 "simple-m
619 reg = <0x65700000 0x10
620 #address-cells = <1>;
621 #size-cells = <1>;
622 ranges = <0 0x65700000
623
624 ahci_rst: reset-contro
625 compatible = "
626 reg = <0x0 0x4
627 clock-names =
628 clocks = <&sys
629 reset-names =
630 resets = <&sys
631 #reset-cells =
632 };
633
634 ahci_phy: phy@10 {
635 compatible = "
636 reg = <0x10 0x
637 clock-names =
638 clocks = <&sys
639 reset-names =
640 resets = <&sys
641 #phy-cells = <
642 };
643 };
644
645 usb0: usb@65a00000 {
646 compatible = "socionex
647 status = "disabled";
648 reg = <0x65a00000 0xcd
649 interrupt-names = "dwc
650 interrupts = <GIC_SPI
651 pinctrl-names = "defau
652 pinctrl-0 = <&pinctrl_
653 clock-names = "ref", "
654 clocks = <&sys_clk 14>
655 resets = <&usb0_rst 15
656 phys = <&usb0_hsphy0>,
657 <&usb0_ssphy0>,
658 dr_mode = "host";
659 };
660
661 usb-controller@65b00000 {
662 compatible = "socionex
663 "simple-m
664 reg = <0x65b00000 0x40
665 #address-cells = <1>;
666 #size-cells = <1>;
667 ranges = <0 0x65b00000
668
669 usb0_rst: reset-contro
670 compatible = "
671 reg = <0x0 0x4
672 #reset-cells =
673 clock-names =
674 clocks = <&sys
675 reset-names =
676 resets = <&sys
677 };
678
679 usb0_vbus0: regulator@
680 compatible = "
681 reg = <0x100 0
682 clock-names =
683 clocks = <&sys
684 reset-names =
685 resets = <&sys
686 };
687
688 usb0_vbus1: regulator@
689 compatible = "
690 reg = <0x110 0
691 clock-names =
692 clocks = <&sys
693 reset-names =
694 resets = <&sys
695 };
696
697 usb0_hsphy0: phy@200 {
698 compatible = "
699 reg = <0x200 0
700 #phy-cells = <
701 clock-names =
702 clocks = <&sys
703 reset-names =
704 resets = <&sys
705 vbus-supply =
706 };
707
708 usb0_hsphy1: phy@210 {
709 compatible = "
710 reg = <0x210 0
711 #phy-cells = <
712 clock-names =
713 clocks = <&sys
714 reset-names =
715 resets = <&sys
716 vbus-supply =
717 };
718
719 usb0_ssphy0: phy@300 {
720 compatible = "
721 reg = <0x300 0
722 #phy-cells = <
723 clock-names =
724 clocks = <&sys
725 reset-names =
726 resets = <&sys
727 vbus-supply =
728 };
729
730 usb0_ssphy1: phy@310 {
731 compatible = "
732 reg = <0x310 0
733 #phy-cells = <
734 clock-names =
735 clocks = <&sys
736 reset-names =
737 resets = <&sys
738 vbus-supply =
739 };
740 };
741
742 usb1: usb@65c00000 {
743 compatible = "socionex
744 status = "disabled";
745 reg = <0x65c00000 0xcd
746 interrupt-names = "dwc
747 interrupts = <GIC_SPI
748 pinctrl-names = "defau
749 pinctrl-0 = <&pinctrl_
750 clock-names = "ref", "
751 clocks = <&sys_clk 15>
752 resets = <&usb1_rst 15
753 phys = <&usb1_hsphy0>,
754 dr_mode = "host";
755 };
756
757 usb-controller@65d00000 {
758 compatible = "socionex
759 "simple-m
760 reg = <0x65d00000 0x40
761 #address-cells = <1>;
762 #size-cells = <1>;
763 ranges = <0 0x65d00000
764
765 usb1_rst: reset-contro
766 compatible = "
767 reg = <0x0 0x4
768 #reset-cells =
769 clock-names =
770 clocks = <&sys
771 reset-names =
772 resets = <&sys
773 };
774
775 usb1_vbus0: regulator@
776 compatible = "
777 reg = <0x100 0
778 clock-names =
779 clocks = <&sys
780 reset-names =
781 resets = <&sys
782 };
783
784 usb1_vbus1: regulator@
785 compatible = "
786 reg = <0x110 0
787 clock-names =
788 clocks = <&sys
789 reset-names =
790 resets = <&sys
791 };
792
793 usb1_hsphy0: phy@200 {
794 compatible = "
795 reg = <0x200 0
796 #phy-cells = <
797 clock-names =
798 clocks = <&sys
799 reset-names =
800 resets = <&sys
801 vbus-supply =
802 };
803
804 usb1_hsphy1: phy@210 {
805 compatible = "
806 reg = <0x210 0
807 #phy-cells = <
808 clock-names =
809 clocks = <&sys
810 reset-names =
811 resets = <&sys
812 vbus-supply =
813 };
814
815 usb1_ssphy0: phy@300 {
816 compatible = "
817 reg = <0x300 0
818 #phy-cells = <
819 clock-names =
820 clocks = <&sys
821 reset-names =
822 resets = <&sys
823 vbus-supply =
824 };
825 };
826
827 nand: nand-controller@68000000
828 compatible = "socionex
829 status = "disabled";
830 reg-names = "nand_data
831 reg = <0x68000000 0x20
832 #address-cells = <1>;
833 #size-cells = <0>;
834 interrupts = <GIC_SPI
835 pinctrl-names = "defau
836 pinctrl-0 = <&pinctrl_
837 clock-names = "nand",
838 clocks = <&sys_clk 2>,
839 reset-names = "nand",
840 resets = <&sys_rst 2>,
841 };
842 };
843 };
844
845 #include "uniphier-pinctrl.dtsi"
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