1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
2 // 2 //
3 // Device Tree Source for UniPhier PXs2 SoC 3 // Device Tree Source for UniPhier PXs2 SoC
4 // 4 //
5 // Copyright (C) 2015-2016 Socionext Inc. 5 // Copyright (C) 2015-2016 Socionext Inc.
6 // Author: Masahiro Yamada <yamada.masahiro@s 6 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 7
8 #include <dt-bindings/gpio/uniphier-gpio.h> 8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h> 10 #include <dt-bindings/thermal/thermal.h>
11 11
12 / { 12 / {
13 compatible = "socionext,uniphier-pxs2" 13 compatible = "socionext,uniphier-pxs2";
14 #address-cells = <1>; 14 #address-cells = <1>;
15 #size-cells = <1>; 15 #size-cells = <1>;
16 16
17 cpus { 17 cpus {
18 #address-cells = <1>; 18 #address-cells = <1>;
19 #size-cells = <0>; 19 #size-cells = <0>;
20 20
21 cpu0: cpu@0 { 21 cpu0: cpu@0 {
22 device_type = "cpu"; 22 device_type = "cpu";
23 compatible = "arm,cort 23 compatible = "arm,cortex-a9";
24 reg = <0>; 24 reg = <0>;
25 clocks = <&sys_clk 32> 25 clocks = <&sys_clk 32>;
26 enable-method = "psci" 26 enable-method = "psci";
27 next-level-cache = <&l 27 next-level-cache = <&l2>;
28 operating-points-v2 = 28 operating-points-v2 = <&cpu_opp>;
29 #cooling-cells = <2>; 29 #cooling-cells = <2>;
30 }; 30 };
31 31
32 cpu1: cpu@1 { 32 cpu1: cpu@1 {
33 device_type = "cpu"; 33 device_type = "cpu";
34 compatible = "arm,cort 34 compatible = "arm,cortex-a9";
35 reg = <1>; 35 reg = <1>;
36 clocks = <&sys_clk 32> 36 clocks = <&sys_clk 32>;
37 enable-method = "psci" 37 enable-method = "psci";
38 next-level-cache = <&l 38 next-level-cache = <&l2>;
39 operating-points-v2 = 39 operating-points-v2 = <&cpu_opp>;
40 #cooling-cells = <2>; 40 #cooling-cells = <2>;
41 }; 41 };
42 42
43 cpu2: cpu@2 { 43 cpu2: cpu@2 {
44 device_type = "cpu"; 44 device_type = "cpu";
45 compatible = "arm,cort 45 compatible = "arm,cortex-a9";
46 reg = <2>; 46 reg = <2>;
47 clocks = <&sys_clk 32> 47 clocks = <&sys_clk 32>;
48 enable-method = "psci" 48 enable-method = "psci";
49 next-level-cache = <&l 49 next-level-cache = <&l2>;
50 operating-points-v2 = 50 operating-points-v2 = <&cpu_opp>;
51 #cooling-cells = <2>; 51 #cooling-cells = <2>;
52 }; 52 };
53 53
54 cpu3: cpu@3 { 54 cpu3: cpu@3 {
55 device_type = "cpu"; 55 device_type = "cpu";
56 compatible = "arm,cort 56 compatible = "arm,cortex-a9";
57 reg = <3>; 57 reg = <3>;
58 clocks = <&sys_clk 32> 58 clocks = <&sys_clk 32>;
59 enable-method = "psci" 59 enable-method = "psci";
60 next-level-cache = <&l 60 next-level-cache = <&l2>;
61 operating-points-v2 = 61 operating-points-v2 = <&cpu_opp>;
62 #cooling-cells = <2>; 62 #cooling-cells = <2>;
63 }; 63 };
64 }; 64 };
65 65
66 cpu_opp: opp-table { 66 cpu_opp: opp-table {
67 compatible = "operating-points 67 compatible = "operating-points-v2";
68 opp-shared; 68 opp-shared;
69 69
70 opp-100000000 { 70 opp-100000000 {
71 opp-hz = /bits/ 64 <10 71 opp-hz = /bits/ 64 <100000000>;
72 clock-latency-ns = <30 72 clock-latency-ns = <300>;
73 }; 73 };
74 opp-150000000 { 74 opp-150000000 {
75 opp-hz = /bits/ 64 <15 75 opp-hz = /bits/ 64 <150000000>;
76 clock-latency-ns = <30 76 clock-latency-ns = <300>;
77 }; 77 };
78 opp-200000000 { 78 opp-200000000 {
79 opp-hz = /bits/ 64 <20 79 opp-hz = /bits/ 64 <200000000>;
80 clock-latency-ns = <30 80 clock-latency-ns = <300>;
81 }; 81 };
82 opp-300000000 { 82 opp-300000000 {
83 opp-hz = /bits/ 64 <30 83 opp-hz = /bits/ 64 <300000000>;
84 clock-latency-ns = <30 84 clock-latency-ns = <300>;
85 }; 85 };
86 opp-400000000 { 86 opp-400000000 {
87 opp-hz = /bits/ 64 <40 87 opp-hz = /bits/ 64 <400000000>;
88 clock-latency-ns = <30 88 clock-latency-ns = <300>;
89 }; 89 };
90 opp-600000000 { 90 opp-600000000 {
91 opp-hz = /bits/ 64 <60 91 opp-hz = /bits/ 64 <600000000>;
92 clock-latency-ns = <30 92 clock-latency-ns = <300>;
93 }; 93 };
94 opp-800000000 { 94 opp-800000000 {
95 opp-hz = /bits/ 64 <80 95 opp-hz = /bits/ 64 <800000000>;
96 clock-latency-ns = <30 96 clock-latency-ns = <300>;
97 }; 97 };
98 opp-1200000000 { 98 opp-1200000000 {
99 opp-hz = /bits/ 64 <12 99 opp-hz = /bits/ 64 <1200000000>;
100 clock-latency-ns = <30 100 clock-latency-ns = <300>;
101 }; 101 };
102 }; 102 };
103 103
104 psci { 104 psci {
105 compatible = "arm,psci-0.2"; 105 compatible = "arm,psci-0.2";
106 method = "smc"; 106 method = "smc";
107 }; 107 };
108 108
109 clocks { 109 clocks {
110 refclk: ref { 110 refclk: ref {
111 compatible = "fixed-cl 111 compatible = "fixed-clock";
112 #clock-cells = <0>; 112 #clock-cells = <0>;
113 clock-frequency = <250 113 clock-frequency = <25000000>;
114 }; 114 };
115 115
116 arm_timer_clk: arm-timer { 116 arm_timer_clk: arm-timer {
117 #clock-cells = <0>; 117 #clock-cells = <0>;
118 compatible = "fixed-cl 118 compatible = "fixed-clock";
119 clock-frequency = <500 119 clock-frequency = <50000000>;
120 }; 120 };
121 }; 121 };
122 122
123 thermal-zones { 123 thermal-zones {
124 cpu-thermal { 124 cpu-thermal {
125 polling-delay-passive 125 polling-delay-passive = <250>; /* 250ms */
126 polling-delay = <1000> 126 polling-delay = <1000>; /* 1000ms */
127 thermal-sensors = <&pv 127 thermal-sensors = <&pvtctl>;
128 128
129 trips { 129 trips {
130 cpu_crit: cpu- 130 cpu_crit: cpu-crit {
131 temper 131 temperature = <95000>; /* 95C */
132 hyster 132 hysteresis = <2000>;
133 type = 133 type = "critical";
134 }; 134 };
135 cpu_alert: cpu 135 cpu_alert: cpu-alert {
136 temper 136 temperature = <85000>; /* 85C */
137 hyster 137 hysteresis = <2000>;
138 type = 138 type = "passive";
139 }; 139 };
140 }; 140 };
141 141
142 cooling-maps { 142 cooling-maps {
143 map { 143 map {
144 trip = 144 trip = <&cpu_alert>;
145 coolin 145 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
146 146 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
147 147 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
148 148 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
149 }; 149 };
150 }; 150 };
151 }; 151 };
152 }; 152 };
153 153
154 soc { 154 soc {
155 compatible = "simple-bus"; 155 compatible = "simple-bus";
156 #address-cells = <1>; 156 #address-cells = <1>;
157 #size-cells = <1>; 157 #size-cells = <1>;
158 ranges; 158 ranges;
159 interrupt-parent = <&intc>; 159 interrupt-parent = <&intc>;
160 160
161 l2: cache-controller@500c0000 161 l2: cache-controller@500c0000 {
162 compatible = "socionex 162 compatible = "socionext,uniphier-system-cache";
163 reg = <0x500c0000 0x20 163 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
164 <0x506c0000 0x40 164 <0x506c0000 0x400>;
165 interrupts = <GIC_SPI 165 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 166 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 167 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
168 <GIC_SPI 168 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
169 cache-unified; 169 cache-unified;
170 cache-size = <(1280 * 170 cache-size = <(1280 * 1024)>;
171 cache-sets = <512>; 171 cache-sets = <512>;
172 cache-line-size = <128 172 cache-line-size = <128>;
173 cache-level = <2>; 173 cache-level = <2>;
174 }; 174 };
175 175
176 spi0: spi@54006000 { 176 spi0: spi@54006000 {
177 compatible = "socionex 177 compatible = "socionext,uniphier-scssi";
178 status = "disabled"; 178 status = "disabled";
179 reg = <0x54006000 0x10 179 reg = <0x54006000 0x100>;
180 #address-cells = <1>; 180 #address-cells = <1>;
181 #size-cells = <0>; 181 #size-cells = <0>;
182 interrupts = <GIC_SPI 182 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
183 pinctrl-names = "defau 183 pinctrl-names = "default";
184 pinctrl-0 = <&pinctrl_ 184 pinctrl-0 = <&pinctrl_spi0>;
185 clocks = <&peri_clk 11 185 clocks = <&peri_clk 11>;
186 resets = <&peri_rst 11 186 resets = <&peri_rst 11>;
187 }; 187 };
188 188
189 spi1: spi@54006100 { 189 spi1: spi@54006100 {
190 compatible = "socionex 190 compatible = "socionext,uniphier-scssi";
191 status = "disabled"; 191 status = "disabled";
192 reg = <0x54006100 0x10 192 reg = <0x54006100 0x100>;
193 #address-cells = <1>; 193 #address-cells = <1>;
194 #size-cells = <0>; 194 #size-cells = <0>;
195 interrupts = <GIC_SPI 195 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
196 pinctrl-names = "defau 196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_ 197 pinctrl-0 = <&pinctrl_spi1>;
198 clocks = <&peri_clk 12 198 clocks = <&peri_clk 12>;
199 resets = <&peri_rst 12 199 resets = <&peri_rst 12>;
200 }; 200 };
201 201
202 serial0: serial@54006800 { 202 serial0: serial@54006800 {
203 compatible = "socionex 203 compatible = "socionext,uniphier-uart";
204 status = "disabled"; 204 status = "disabled";
205 reg = <0x54006800 0x40 205 reg = <0x54006800 0x40>;
206 interrupts = <GIC_SPI 206 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
207 pinctrl-names = "defau 207 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_ 208 pinctrl-0 = <&pinctrl_uart0>;
209 clocks = <&peri_clk 0> 209 clocks = <&peri_clk 0>;
210 resets = <&peri_rst 0> 210 resets = <&peri_rst 0>;
211 }; 211 };
212 212
213 serial1: serial@54006900 { 213 serial1: serial@54006900 {
214 compatible = "socionex 214 compatible = "socionext,uniphier-uart";
215 status = "disabled"; 215 status = "disabled";
216 reg = <0x54006900 0x40 216 reg = <0x54006900 0x40>;
217 interrupts = <GIC_SPI 217 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
218 pinctrl-names = "defau 218 pinctrl-names = "default";
219 pinctrl-0 = <&pinctrl_ 219 pinctrl-0 = <&pinctrl_uart1>;
220 clocks = <&peri_clk 1> 220 clocks = <&peri_clk 1>;
221 resets = <&peri_rst 1> 221 resets = <&peri_rst 1>;
222 }; 222 };
223 223
224 serial2: serial@54006a00 { 224 serial2: serial@54006a00 {
225 compatible = "socionex 225 compatible = "socionext,uniphier-uart";
226 status = "disabled"; 226 status = "disabled";
227 reg = <0x54006a00 0x40 227 reg = <0x54006a00 0x40>;
228 interrupts = <GIC_SPI 228 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
229 pinctrl-names = "defau 229 pinctrl-names = "default";
230 pinctrl-0 = <&pinctrl_ 230 pinctrl-0 = <&pinctrl_uart2>;
231 clocks = <&peri_clk 2> 231 clocks = <&peri_clk 2>;
232 resets = <&peri_rst 2> 232 resets = <&peri_rst 2>;
233 }; 233 };
234 234
235 serial3: serial@54006b00 { 235 serial3: serial@54006b00 {
236 compatible = "socionex 236 compatible = "socionext,uniphier-uart";
237 status = "disabled"; 237 status = "disabled";
238 reg = <0x54006b00 0x40 238 reg = <0x54006b00 0x40>;
239 interrupts = <GIC_SPI 239 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
240 pinctrl-names = "defau 240 pinctrl-names = "default";
241 pinctrl-0 = <&pinctrl_ 241 pinctrl-0 = <&pinctrl_uart3>;
242 clocks = <&peri_clk 3> 242 clocks = <&peri_clk 3>;
243 resets = <&peri_rst 3> 243 resets = <&peri_rst 3>;
244 }; 244 };
245 245
246 gpio: gpio@55000000 { 246 gpio: gpio@55000000 {
247 compatible = "socionex 247 compatible = "socionext,uniphier-gpio";
248 reg = <0x55000000 0x20 248 reg = <0x55000000 0x200>;
249 interrupt-parent = <&a 249 interrupt-parent = <&aidet>;
250 interrupt-controller; 250 interrupt-controller;
251 #interrupt-cells = <2> 251 #interrupt-cells = <2>;
252 gpio-controller; 252 gpio-controller;
253 #gpio-cells = <2>; 253 #gpio-cells = <2>;
254 gpio-ranges = <&pinctr 254 gpio-ranges = <&pinctrl 0 0 0>,
255 <&pinctr 255 <&pinctrl 96 0 0>;
256 gpio-ranges-group-name 256 gpio-ranges-group-names = "gpio_range0",
257 257 "gpio_range1";
258 ngpios = <232>; 258 ngpios = <232>;
259 socionext,interrupt-ra 259 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
260 260 <21 217 3>;
261 }; 261 };
262 262
263 audio@56000000 { 263 audio@56000000 {
264 compatible = "socionex 264 compatible = "socionext,uniphier-pxs2-aio";
265 reg = <0x56000000 0x80 265 reg = <0x56000000 0x80000>;
266 interrupts = <GIC_SPI 266 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
267 pinctrl-names = "defau 267 pinctrl-names = "default";
268 pinctrl-0 = <&pinctrl_ 268 pinctrl-0 = <&pinctrl_ain1>,
269 <&pinctrl_ 269 <&pinctrl_ain2>,
270 <&pinctrl_ 270 <&pinctrl_ainiec1>,
271 <&pinctrl_ 271 <&pinctrl_aout2>,
272 <&pinctrl_ 272 <&pinctrl_aout3>,
273 <&pinctrl_ 273 <&pinctrl_aoutiec1>,
274 <&pinctrl_ 274 <&pinctrl_aoutiec2>;
275 clock-names = "aio"; 275 clock-names = "aio";
276 clocks = <&sys_clk 40> 276 clocks = <&sys_clk 40>;
277 reset-names = "aio"; 277 reset-names = "aio";
278 resets = <&sys_rst 40> 278 resets = <&sys_rst 40>;
279 #sound-dai-cells = <1> 279 #sound-dai-cells = <1>;
280 socionext,syscon = <&s 280 socionext,syscon = <&soc_glue>;
281 281
282 i2s_port0: port@0 { 282 i2s_port0: port@0 {
283 i2s_hdmi: endp 283 i2s_hdmi: endpoint {
284 }; 284 };
285 }; 285 };
286 286
287 i2s_port1: port@1 { 287 i2s_port1: port@1 {
288 i2s_line: endp 288 i2s_line: endpoint {
289 }; 289 };
290 }; 290 };
291 291
292 i2s_port2: port@2 { 292 i2s_port2: port@2 {
293 i2s_aux: endpo 293 i2s_aux: endpoint {
294 }; 294 };
295 }; 295 };
296 296
297 spdif_port0: port@3 { 297 spdif_port0: port@3 {
298 spdif_hiecout1 298 spdif_hiecout1: endpoint {
299 }; 299 };
300 }; 300 };
301 301
302 spdif_port1: port@4 { 302 spdif_port1: port@4 {
303 spdif_iecout1: 303 spdif_iecout1: endpoint {
304 }; 304 };
305 }; 305 };
306 306
307 comp_spdif_port0: port 307 comp_spdif_port0: port@5 {
308 comp_spdif_hie 308 comp_spdif_hiecout1: endpoint {
309 }; 309 };
310 }; 310 };
311 311
312 comp_spdif_port1: port 312 comp_spdif_port1: port@6 {
313 comp_spdif_iec 313 comp_spdif_iecout1: endpoint {
314 }; 314 };
315 }; 315 };
316 }; 316 };
317 317
318 i2c0: i2c@58780000 { 318 i2c0: i2c@58780000 {
319 compatible = "socionex 319 compatible = "socionext,uniphier-fi2c";
320 status = "disabled"; 320 status = "disabled";
321 reg = <0x58780000 0x80 321 reg = <0x58780000 0x80>;
322 #address-cells = <1>; 322 #address-cells = <1>;
323 #size-cells = <0>; 323 #size-cells = <0>;
324 interrupts = <GIC_SPI 324 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
325 pinctrl-names = "defau 325 pinctrl-names = "default";
326 pinctrl-0 = <&pinctrl_ 326 pinctrl-0 = <&pinctrl_i2c0>;
327 clocks = <&peri_clk 4> 327 clocks = <&peri_clk 4>;
328 resets = <&peri_rst 4> 328 resets = <&peri_rst 4>;
329 clock-frequency = <100 329 clock-frequency = <100000>;
330 }; 330 };
331 331
332 i2c1: i2c@58781000 { 332 i2c1: i2c@58781000 {
333 compatible = "socionex 333 compatible = "socionext,uniphier-fi2c";
334 status = "disabled"; 334 status = "disabled";
335 reg = <0x58781000 0x80 335 reg = <0x58781000 0x80>;
336 #address-cells = <1>; 336 #address-cells = <1>;
337 #size-cells = <0>; 337 #size-cells = <0>;
338 interrupts = <GIC_SPI 338 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
339 pinctrl-names = "defau 339 pinctrl-names = "default";
340 pinctrl-0 = <&pinctrl_ 340 pinctrl-0 = <&pinctrl_i2c1>;
341 clocks = <&peri_clk 5> 341 clocks = <&peri_clk 5>;
342 resets = <&peri_rst 5> 342 resets = <&peri_rst 5>;
343 clock-frequency = <100 343 clock-frequency = <100000>;
344 }; 344 };
345 345
346 i2c2: i2c@58782000 { 346 i2c2: i2c@58782000 {
347 compatible = "socionex 347 compatible = "socionext,uniphier-fi2c";
348 status = "disabled"; 348 status = "disabled";
349 reg = <0x58782000 0x80 349 reg = <0x58782000 0x80>;
350 #address-cells = <1>; 350 #address-cells = <1>;
351 #size-cells = <0>; 351 #size-cells = <0>;
352 interrupts = <GIC_SPI 352 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
353 pinctrl-names = "defau 353 pinctrl-names = "default";
354 pinctrl-0 = <&pinctrl_ 354 pinctrl-0 = <&pinctrl_i2c2>;
355 clocks = <&peri_clk 6> 355 clocks = <&peri_clk 6>;
356 resets = <&peri_rst 6> 356 resets = <&peri_rst 6>;
357 clock-frequency = <100 357 clock-frequency = <100000>;
358 }; 358 };
359 359
360 i2c3: i2c@58783000 { 360 i2c3: i2c@58783000 {
361 compatible = "socionex 361 compatible = "socionext,uniphier-fi2c";
362 status = "disabled"; 362 status = "disabled";
363 reg = <0x58783000 0x80 363 reg = <0x58783000 0x80>;
364 #address-cells = <1>; 364 #address-cells = <1>;
365 #size-cells = <0>; 365 #size-cells = <0>;
366 interrupts = <GIC_SPI 366 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
367 pinctrl-names = "defau 367 pinctrl-names = "default";
368 pinctrl-0 = <&pinctrl_ 368 pinctrl-0 = <&pinctrl_i2c3>;
369 clocks = <&peri_clk 7> 369 clocks = <&peri_clk 7>;
370 resets = <&peri_rst 7> 370 resets = <&peri_rst 7>;
371 clock-frequency = <100 371 clock-frequency = <100000>;
372 }; 372 };
373 373
374 /* chip-internal connection fo 374 /* chip-internal connection for DMD */
375 i2c4: i2c@58784000 { 375 i2c4: i2c@58784000 {
376 compatible = "socionex 376 compatible = "socionext,uniphier-fi2c";
377 reg = <0x58784000 0x80 377 reg = <0x58784000 0x80>;
378 #address-cells = <1>; 378 #address-cells = <1>;
379 #size-cells = <0>; 379 #size-cells = <0>;
380 interrupts = <GIC_SPI 380 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&peri_clk 8> 381 clocks = <&peri_clk 8>;
382 resets = <&peri_rst 8> 382 resets = <&peri_rst 8>;
383 clock-frequency = <400 383 clock-frequency = <400000>;
384 }; 384 };
385 385
386 /* chip-internal connection fo 386 /* chip-internal connection for STM */
387 i2c5: i2c@58785000 { 387 i2c5: i2c@58785000 {
388 compatible = "socionex 388 compatible = "socionext,uniphier-fi2c";
389 reg = <0x58785000 0x80 389 reg = <0x58785000 0x80>;
390 #address-cells = <1>; 390 #address-cells = <1>;
391 #size-cells = <0>; 391 #size-cells = <0>;
392 interrupts = <GIC_SPI 392 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&peri_clk 9> 393 clocks = <&peri_clk 9>;
394 resets = <&peri_rst 9> 394 resets = <&peri_rst 9>;
395 clock-frequency = <400 395 clock-frequency = <400000>;
396 }; 396 };
397 397
398 /* chip-internal connection fo 398 /* chip-internal connection for HDMI */
399 i2c6: i2c@58786000 { 399 i2c6: i2c@58786000 {
400 compatible = "socionex 400 compatible = "socionext,uniphier-fi2c";
401 reg = <0x58786000 0x80 401 reg = <0x58786000 0x80>;
402 #address-cells = <1>; 402 #address-cells = <1>;
403 #size-cells = <0>; 403 #size-cells = <0>;
404 interrupts = <GIC_SPI 404 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&peri_clk 10 405 clocks = <&peri_clk 10>;
406 resets = <&peri_rst 10 406 resets = <&peri_rst 10>;
407 clock-frequency = <400 407 clock-frequency = <400000>;
408 }; 408 };
409 409
410 system_bus: system-bus@58c0000 410 system_bus: system-bus@58c00000 {
411 compatible = "socionex 411 compatible = "socionext,uniphier-system-bus";
412 status = "disabled"; 412 status = "disabled";
413 reg = <0x58c00000 0x40 413 reg = <0x58c00000 0x400>;
414 #address-cells = <2>; 414 #address-cells = <2>;
415 #size-cells = <1>; 415 #size-cells = <1>;
416 pinctrl-names = "defau 416 pinctrl-names = "default";
417 pinctrl-0 = <&pinctrl_ 417 pinctrl-0 = <&pinctrl_system_bus>;
418 }; 418 };
419 419
420 smpctrl@59801000 { 420 smpctrl@59801000 {
421 compatible = "socionex 421 compatible = "socionext,uniphier-smpctrl";
422 reg = <0x59801000 0x40 422 reg = <0x59801000 0x400>;
423 }; 423 };
424 424
425 sdctrl: syscon@59810000 { 425 sdctrl: syscon@59810000 {
426 compatible = "socionex 426 compatible = "socionext,uniphier-pxs2-sdctrl",
427 "simple-m 427 "simple-mfd", "syscon";
428 reg = <0x59810000 0x40 428 reg = <0x59810000 0x400>;
429 429
430 sd_clk: clock-controll 430 sd_clk: clock-controller {
431 compatible = " 431 compatible = "socionext,uniphier-pxs2-sd-clock";
432 #clock-cells = 432 #clock-cells = <1>;
433 }; 433 };
434 434
435 sd_rst: reset-controll 435 sd_rst: reset-controller {
436 compatible = " 436 compatible = "socionext,uniphier-pxs2-sd-reset";
437 #reset-cells = 437 #reset-cells = <1>;
438 }; 438 };
439 }; 439 };
440 440
441 syscon@59820000 { 441 syscon@59820000 {
442 compatible = "socionex 442 compatible = "socionext,uniphier-pxs2-perictrl",
443 "simple-m 443 "simple-mfd", "syscon";
444 reg = <0x59820000 0x20 444 reg = <0x59820000 0x200>;
445 445
446 peri_clk: clock-contro 446 peri_clk: clock-controller {
447 compatible = " 447 compatible = "socionext,uniphier-pxs2-peri-clock";
448 #clock-cells = 448 #clock-cells = <1>;
449 }; 449 };
450 450
451 peri_rst: reset-contro 451 peri_rst: reset-controller {
452 compatible = " 452 compatible = "socionext,uniphier-pxs2-peri-reset";
453 #reset-cells = 453 #reset-cells = <1>;
454 }; 454 };
455 }; 455 };
456 456
457 emmc: mmc@5a000000 { 457 emmc: mmc@5a000000 {
458 compatible = "socionex 458 compatible = "socionext,uniphier-sd-v3.1.1";
459 status = "disabled"; 459 status = "disabled";
460 reg = <0x5a000000 0x80 460 reg = <0x5a000000 0x800>;
461 interrupts = <GIC_SPI 461 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
462 pinctrl-names = "defau 462 pinctrl-names = "default";
463 pinctrl-0 = <&pinctrl_ 463 pinctrl-0 = <&pinctrl_emmc>;
464 clocks = <&sd_clk 1>; 464 clocks = <&sd_clk 1>;
465 reset-names = "host", 465 reset-names = "host", "hw";
466 resets = <&sd_rst 1>, 466 resets = <&sd_rst 1>, <&sd_rst 6>;
467 bus-width = <8>; 467 bus-width = <8>;
468 cap-mmc-highspeed; 468 cap-mmc-highspeed;
469 cap-mmc-hw-reset; 469 cap-mmc-hw-reset;
470 non-removable; 470 non-removable;
471 }; 471 };
472 472
473 sd: mmc@5a400000 { 473 sd: mmc@5a400000 {
474 compatible = "socionex 474 compatible = "socionext,uniphier-sd-v3.1.1";
475 status = "disabled"; 475 status = "disabled";
476 reg = <0x5a400000 0x80 476 reg = <0x5a400000 0x800>;
477 interrupts = <GIC_SPI 477 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
478 pinctrl-names = "defau 478 pinctrl-names = "default", "uhs";
479 pinctrl-0 = <&pinctrl_ 479 pinctrl-0 = <&pinctrl_sd>;
480 pinctrl-1 = <&pinctrl_ 480 pinctrl-1 = <&pinctrl_sd_uhs>;
481 clocks = <&sd_clk 0>; 481 clocks = <&sd_clk 0>;
482 reset-names = "host"; 482 reset-names = "host";
483 resets = <&sd_rst 0>; 483 resets = <&sd_rst 0>;
484 bus-width = <4>; 484 bus-width = <4>;
485 cap-sd-highspeed; 485 cap-sd-highspeed;
486 sd-uhs-sdr12; 486 sd-uhs-sdr12;
487 sd-uhs-sdr25; 487 sd-uhs-sdr25;
488 sd-uhs-sdr50; 488 sd-uhs-sdr50;
489 socionext,syscon-uhs-m 489 socionext,syscon-uhs-mode = <&sdctrl 0>;
490 }; 490 };
491 491
492 soc_glue: syscon@5f800000 { 492 soc_glue: syscon@5f800000 {
493 compatible = "socionex 493 compatible = "socionext,uniphier-pxs2-soc-glue",
494 "simple-m 494 "simple-mfd", "syscon";
495 reg = <0x5f800000 0x20 495 reg = <0x5f800000 0x2000>;
496 496
497 pinctrl: pinctrl { 497 pinctrl: pinctrl {
498 compatible = " 498 compatible = "socionext,uniphier-pxs2-pinctrl";
499 }; 499 };
500 }; 500 };
501 501
502 syscon@5f900000 { 502 syscon@5f900000 {
503 compatible = "socionex 503 compatible = "socionext,uniphier-pxs2-soc-glue-debug",
504 "simple-m 504 "simple-mfd", "syscon";
505 reg = <0x5f900000 0x20 505 reg = <0x5f900000 0x2000>;
506 #address-cells = <1>; 506 #address-cells = <1>;
507 #size-cells = <1>; 507 #size-cells = <1>;
508 ranges = <0 0x5f900000 508 ranges = <0 0x5f900000 0x2000>;
509 509
510 efuse@100 { 510 efuse@100 {
511 compatible = " 511 compatible = "socionext,uniphier-efuse";
512 reg = <0x100 0 512 reg = <0x100 0x28>;
513 }; 513 };
514 514
515 efuse@200 { 515 efuse@200 {
516 compatible = " 516 compatible = "socionext,uniphier-efuse";
517 reg = <0x200 0 517 reg = <0x200 0x58>;
518 }; 518 };
519 }; 519 };
520 520
521 xdmac: dma-controller@5fc10000 521 xdmac: dma-controller@5fc10000 {
522 compatible = "socionex 522 compatible = "socionext,uniphier-xdmac";
523 reg = <0x5fc10000 0x53 523 reg = <0x5fc10000 0x5300>;
524 interrupts = <GIC_SPI 524 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
525 dma-channels = <16>; 525 dma-channels = <16>;
526 #dma-cells = <2>; 526 #dma-cells = <2>;
527 }; 527 };
528 528
529 aidet: interrupt-controller@5f 529 aidet: interrupt-controller@5fc20000 {
530 compatible = "socionex 530 compatible = "socionext,uniphier-pxs2-aidet";
531 reg = <0x5fc20000 0x20 531 reg = <0x5fc20000 0x200>;
532 interrupt-controller; 532 interrupt-controller;
533 #interrupt-cells = <2> 533 #interrupt-cells = <2>;
534 }; 534 };
535 535
536 timer@60000200 { 536 timer@60000200 {
537 compatible = "arm,cort 537 compatible = "arm,cortex-a9-global-timer";
538 reg = <0x60000200 0x20 538 reg = <0x60000200 0x20>;
539 interrupts = <GIC_PPI 539 interrupts = <GIC_PPI 11
540 (GIC_CPU_MASK_ 540 (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_HIGH)>;
541 clocks = <&arm_timer_c 541 clocks = <&arm_timer_clk>;
542 }; 542 };
543 543
544 timer@60000600 { 544 timer@60000600 {
545 compatible = "arm,cort 545 compatible = "arm,cortex-a9-twd-timer";
546 reg = <0x60000600 0x20 546 reg = <0x60000600 0x20>;
547 interrupts = <GIC_PPI 547 interrupts = <GIC_PPI 13
548 (GIC_CPU_MASK_ 548 (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_HIGH)>;
549 clocks = <&arm_timer_c 549 clocks = <&arm_timer_clk>;
550 }; 550 };
551 551
552 intc: interrupt-controller@600 552 intc: interrupt-controller@60001000 {
553 compatible = "arm,cort 553 compatible = "arm,cortex-a9-gic";
554 reg = <0x60001000 0x10 554 reg = <0x60001000 0x1000>,
555 <0x60000100 0x10 555 <0x60000100 0x100>;
556 #interrupt-cells = <3> 556 #interrupt-cells = <3>;
557 interrupt-controller; 557 interrupt-controller;
558 }; 558 };
559 559
560 syscon@61840000 { 560 syscon@61840000 {
561 compatible = "socionex 561 compatible = "socionext,uniphier-pxs2-sysctrl",
562 "simple-m 562 "simple-mfd", "syscon";
563 reg = <0x61840000 0x10 563 reg = <0x61840000 0x10000>;
564 564
565 sys_clk: clock-control 565 sys_clk: clock-controller {
566 compatible = " 566 compatible = "socionext,uniphier-pxs2-clock";
567 #clock-cells = 567 #clock-cells = <1>;
568 }; 568 };
569 569
570 sys_rst: reset-control 570 sys_rst: reset-controller {
571 compatible = " 571 compatible = "socionext,uniphier-pxs2-reset";
572 #reset-cells = 572 #reset-cells = <1>;
573 }; 573 };
574 574
575 pvtctl: thermal-sensor 575 pvtctl: thermal-sensor {
576 compatible = " 576 compatible = "socionext,uniphier-pxs2-thermal";
577 interrupts = < 577 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
578 #thermal-senso 578 #thermal-sensor-cells = <0>;
579 socionext,tmod 579 socionext,tmod-calibration = <0x0f86 0x6844>;
580 }; 580 };
581 }; 581 };
582 582
583 eth: ethernet@65000000 { 583 eth: ethernet@65000000 {
584 compatible = "socionex 584 compatible = "socionext,uniphier-pxs2-ave4";
585 status = "disabled"; 585 status = "disabled";
586 reg = <0x65000000 0x85 586 reg = <0x65000000 0x8500>;
587 interrupts = <GIC_SPI 587 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
588 pinctrl-names = "defau 588 pinctrl-names = "default";
589 pinctrl-0 = <&pinctrl_ 589 pinctrl-0 = <&pinctrl_ether_rgmii>;
590 clock-names = "ether"; 590 clock-names = "ether";
591 clocks = <&sys_clk 6>; 591 clocks = <&sys_clk 6>;
592 reset-names = "ether"; 592 reset-names = "ether";
593 resets = <&sys_rst 6>; 593 resets = <&sys_rst 6>;
594 phy-mode = "rgmii-id"; 594 phy-mode = "rgmii-id";
595 local-mac-address = [0 595 local-mac-address = [00 00 00 00 00 00];
596 socionext,syscon-phy-m 596 socionext,syscon-phy-mode = <&soc_glue 0>;
597 597
598 mdio: mdio { 598 mdio: mdio {
599 #address-cells 599 #address-cells = <1>;
600 #size-cells = 600 #size-cells = <0>;
601 }; 601 };
602 }; 602 };
603 603
604 ahci: sata@65600000 { 604 ahci: sata@65600000 {
605 compatible = "socionex 605 compatible = "socionext,uniphier-pxs2-ahci",
606 "generic- 606 "generic-ahci";
607 status = "disabled"; 607 status = "disabled";
608 reg = <0x65600000 0x10 608 reg = <0x65600000 0x10000>;
609 interrupts = <GIC_SPI 609 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
610 clocks = <&sys_clk 28> 610 clocks = <&sys_clk 28>;
611 resets = <&sys_rst 28> 611 resets = <&sys_rst 28>, <&ahci_rst 0>;
612 ports-implemented = <1 612 ports-implemented = <1>;
613 phys = <&ahci_phy>; 613 phys = <&ahci_phy>;
614 }; 614 };
615 615
616 sata-controller@65700000 { 616 sata-controller@65700000 {
617 compatible = "socionex 617 compatible = "socionext,uniphier-pxs2-ahci-glue",
618 "simple-m 618 "simple-mfd";
619 reg = <0x65700000 0x10 619 reg = <0x65700000 0x100>;
620 #address-cells = <1>; 620 #address-cells = <1>;
621 #size-cells = <1>; 621 #size-cells = <1>;
622 ranges = <0 0x65700000 622 ranges = <0 0x65700000 0x100>;
623 623
624 ahci_rst: reset-contro 624 ahci_rst: reset-controller@0 {
625 compatible = " 625 compatible = "socionext,uniphier-pxs2-ahci-reset";
626 reg = <0x0 0x4 626 reg = <0x0 0x4>;
627 clock-names = 627 clock-names = "link";
628 clocks = <&sys 628 clocks = <&sys_clk 28>;
629 reset-names = 629 reset-names = "link";
630 resets = <&sys 630 resets = <&sys_rst 28>;
631 #reset-cells = 631 #reset-cells = <1>;
632 }; 632 };
633 633
634 ahci_phy: phy@10 { 634 ahci_phy: phy@10 {
635 compatible = " 635 compatible = "socionext,uniphier-pxs2-ahci-phy";
636 reg = <0x10 0x 636 reg = <0x10 0x10>;
637 clock-names = 637 clock-names = "link";
638 clocks = <&sys 638 clocks = <&sys_clk 28>;
639 reset-names = 639 reset-names = "link", "phy";
640 resets = <&sys 640 resets = <&sys_rst 28>, <&sys_rst 30>;
641 #phy-cells = < 641 #phy-cells = <0>;
642 }; 642 };
643 }; 643 };
644 644
645 usb0: usb@65a00000 { 645 usb0: usb@65a00000 {
646 compatible = "socionex 646 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
647 status = "disabled"; 647 status = "disabled";
648 reg = <0x65a00000 0xcd 648 reg = <0x65a00000 0xcd00>;
649 interrupt-names = "dwc 649 interrupt-names = "dwc_usb3";
650 interrupts = <GIC_SPI 650 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
651 pinctrl-names = "defau 651 pinctrl-names = "default";
652 pinctrl-0 = <&pinctrl_ 652 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
653 clock-names = "ref", " 653 clock-names = "ref", "bus_early", "suspend";
654 clocks = <&sys_clk 14> 654 clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>;
655 resets = <&usb0_rst 15 655 resets = <&usb0_rst 15>;
656 phys = <&usb0_hsphy0>, 656 phys = <&usb0_hsphy0>, <&usb0_hsphy1>,
657 <&usb0_ssphy0>, 657 <&usb0_ssphy0>, <&usb0_ssphy1>;
658 dr_mode = "host"; 658 dr_mode = "host";
659 }; 659 };
660 660
661 usb-controller@65b00000 { 661 usb-controller@65b00000 {
662 compatible = "socionex 662 compatible = "socionext,uniphier-pxs2-dwc3-glue",
663 "simple-m 663 "simple-mfd";
664 reg = <0x65b00000 0x40 664 reg = <0x65b00000 0x400>;
665 #address-cells = <1>; 665 #address-cells = <1>;
666 #size-cells = <1>; 666 #size-cells = <1>;
667 ranges = <0 0x65b00000 667 ranges = <0 0x65b00000 0x400>;
668 668
669 usb0_rst: reset-contro 669 usb0_rst: reset-controller@0 {
670 compatible = " 670 compatible = "socionext,uniphier-pxs2-usb3-reset";
671 reg = <0x0 0x4 671 reg = <0x0 0x4>;
672 #reset-cells = 672 #reset-cells = <1>;
673 clock-names = 673 clock-names = "link";
674 clocks = <&sys 674 clocks = <&sys_clk 14>;
675 reset-names = 675 reset-names = "link";
676 resets = <&sys 676 resets = <&sys_rst 14>;
677 }; 677 };
678 678
679 usb0_vbus0: regulator@ 679 usb0_vbus0: regulator@100 {
680 compatible = " 680 compatible = "socionext,uniphier-pxs2-usb3-regulator";
681 reg = <0x100 0 681 reg = <0x100 0x10>;
682 clock-names = 682 clock-names = "link";
683 clocks = <&sys 683 clocks = <&sys_clk 14>;
684 reset-names = 684 reset-names = "link";
685 resets = <&sys 685 resets = <&sys_rst 14>;
686 }; 686 };
687 687
688 usb0_vbus1: regulator@ 688 usb0_vbus1: regulator@110 {
689 compatible = " 689 compatible = "socionext,uniphier-pxs2-usb3-regulator";
690 reg = <0x110 0 690 reg = <0x110 0x10>;
691 clock-names = 691 clock-names = "link";
692 clocks = <&sys 692 clocks = <&sys_clk 14>;
693 reset-names = 693 reset-names = "link";
694 resets = <&sys 694 resets = <&sys_rst 14>;
695 }; 695 };
696 696
697 usb0_hsphy0: phy@200 { 697 usb0_hsphy0: phy@200 {
698 compatible = " 698 compatible = "socionext,uniphier-pxs2-usb3-hsphy";
699 reg = <0x200 0 699 reg = <0x200 0x10>;
700 #phy-cells = < 700 #phy-cells = <0>;
701 clock-names = 701 clock-names = "link", "phy";
702 clocks = <&sys 702 clocks = <&sys_clk 14>, <&sys_clk 16>;
703 reset-names = 703 reset-names = "link", "phy";
704 resets = <&sys 704 resets = <&sys_rst 14>, <&sys_rst 16>;
705 vbus-supply = 705 vbus-supply = <&usb0_vbus0>;
706 }; 706 };
707 707
708 usb0_hsphy1: phy@210 { 708 usb0_hsphy1: phy@210 {
709 compatible = " 709 compatible = "socionext,uniphier-pxs2-usb3-hsphy";
710 reg = <0x210 0 710 reg = <0x210 0x10>;
711 #phy-cells = < 711 #phy-cells = <0>;
712 clock-names = 712 clock-names = "link", "phy";
713 clocks = <&sys 713 clocks = <&sys_clk 14>, <&sys_clk 16>;
714 reset-names = 714 reset-names = "link", "phy";
715 resets = <&sys 715 resets = <&sys_rst 14>, <&sys_rst 16>;
716 vbus-supply = 716 vbus-supply = <&usb0_vbus1>;
717 }; 717 };
718 718
719 usb0_ssphy0: phy@300 { 719 usb0_ssphy0: phy@300 {
720 compatible = " 720 compatible = "socionext,uniphier-pxs2-usb3-ssphy";
721 reg = <0x300 0 721 reg = <0x300 0x10>;
722 #phy-cells = < 722 #phy-cells = <0>;
723 clock-names = 723 clock-names = "link", "phy";
724 clocks = <&sys 724 clocks = <&sys_clk 14>, <&sys_clk 17>;
725 reset-names = 725 reset-names = "link", "phy";
726 resets = <&sys 726 resets = <&sys_rst 14>, <&sys_rst 17>;
727 vbus-supply = 727 vbus-supply = <&usb0_vbus0>;
728 }; 728 };
729 729
730 usb0_ssphy1: phy@310 { 730 usb0_ssphy1: phy@310 {
731 compatible = " 731 compatible = "socionext,uniphier-pxs2-usb3-ssphy";
732 reg = <0x310 0 732 reg = <0x310 0x10>;
733 #phy-cells = < 733 #phy-cells = <0>;
734 clock-names = 734 clock-names = "link", "phy";
735 clocks = <&sys 735 clocks = <&sys_clk 14>, <&sys_clk 18>;
736 reset-names = 736 reset-names = "link", "phy";
737 resets = <&sys 737 resets = <&sys_rst 14>, <&sys_rst 18>;
738 vbus-supply = 738 vbus-supply = <&usb0_vbus1>;
739 }; 739 };
740 }; 740 };
741 741
742 usb1: usb@65c00000 { 742 usb1: usb@65c00000 {
743 compatible = "socionex 743 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
744 status = "disabled"; 744 status = "disabled";
745 reg = <0x65c00000 0xcd 745 reg = <0x65c00000 0xcd00>;
746 interrupt-names = "dwc 746 interrupt-names = "dwc_usb3";
747 interrupts = <GIC_SPI 747 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
748 pinctrl-names = "defau 748 pinctrl-names = "default";
749 pinctrl-0 = <&pinctrl_ 749 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
750 clock-names = "ref", " 750 clock-names = "ref", "bus_early", "suspend";
751 clocks = <&sys_clk 15> 751 clocks = <&sys_clk 15>, <&sys_clk 15>, <&sys_clk 15>;
752 resets = <&usb1_rst 15 752 resets = <&usb1_rst 15>;
753 phys = <&usb1_hsphy0>, 753 phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>;
754 dr_mode = "host"; 754 dr_mode = "host";
755 }; 755 };
756 756
757 usb-controller@65d00000 { 757 usb-controller@65d00000 {
758 compatible = "socionex 758 compatible = "socionext,uniphier-pxs2-dwc3-glue",
759 "simple-m 759 "simple-mfd";
760 reg = <0x65d00000 0x40 760 reg = <0x65d00000 0x400>;
761 #address-cells = <1>; 761 #address-cells = <1>;
762 #size-cells = <1>; 762 #size-cells = <1>;
763 ranges = <0 0x65d00000 763 ranges = <0 0x65d00000 0x400>;
764 764
765 usb1_rst: reset-contro 765 usb1_rst: reset-controller@0 {
766 compatible = " 766 compatible = "socionext,uniphier-pxs2-usb3-reset";
767 reg = <0x0 0x4 767 reg = <0x0 0x4>;
768 #reset-cells = 768 #reset-cells = <1>;
769 clock-names = 769 clock-names = "link";
770 clocks = <&sys 770 clocks = <&sys_clk 15>;
771 reset-names = 771 reset-names = "link";
772 resets = <&sys 772 resets = <&sys_rst 15>;
773 }; 773 };
774 774
775 usb1_vbus0: regulator@ 775 usb1_vbus0: regulator@100 {
776 compatible = " 776 compatible = "socionext,uniphier-pxs2-usb3-regulator";
777 reg = <0x100 0 777 reg = <0x100 0x10>;
778 clock-names = 778 clock-names = "link";
779 clocks = <&sys 779 clocks = <&sys_clk 15>;
780 reset-names = 780 reset-names = "link";
781 resets = <&sys 781 resets = <&sys_rst 15>;
782 }; 782 };
783 783
784 usb1_vbus1: regulator@ 784 usb1_vbus1: regulator@110 {
785 compatible = " 785 compatible = "socionext,uniphier-pxs2-usb3-regulator";
786 reg = <0x110 0 786 reg = <0x110 0x10>;
787 clock-names = 787 clock-names = "link";
788 clocks = <&sys 788 clocks = <&sys_clk 15>;
789 reset-names = 789 reset-names = "link";
790 resets = <&sys 790 resets = <&sys_rst 15>;
791 }; 791 };
792 792
793 usb1_hsphy0: phy@200 { 793 usb1_hsphy0: phy@200 {
794 compatible = " 794 compatible = "socionext,uniphier-pxs2-usb3-hsphy";
795 reg = <0x200 0 795 reg = <0x200 0x10>;
796 #phy-cells = < 796 #phy-cells = <0>;
797 clock-names = 797 clock-names = "link", "phy";
798 clocks = <&sys 798 clocks = <&sys_clk 15>, <&sys_clk 20>;
799 reset-names = 799 reset-names = "link", "phy";
800 resets = <&sys 800 resets = <&sys_rst 15>, <&sys_rst 20>;
801 vbus-supply = 801 vbus-supply = <&usb1_vbus0>;
802 }; 802 };
803 803
804 usb1_hsphy1: phy@210 { 804 usb1_hsphy1: phy@210 {
805 compatible = " 805 compatible = "socionext,uniphier-pxs2-usb3-hsphy";
806 reg = <0x210 0 806 reg = <0x210 0x10>;
807 #phy-cells = < 807 #phy-cells = <0>;
808 clock-names = 808 clock-names = "link", "phy";
809 clocks = <&sys 809 clocks = <&sys_clk 15>, <&sys_clk 20>;
810 reset-names = 810 reset-names = "link", "phy";
811 resets = <&sys 811 resets = <&sys_rst 15>, <&sys_rst 20>;
812 vbus-supply = 812 vbus-supply = <&usb1_vbus1>;
813 }; 813 };
814 814
815 usb1_ssphy0: phy@300 { 815 usb1_ssphy0: phy@300 {
816 compatible = " 816 compatible = "socionext,uniphier-pxs2-usb3-ssphy";
817 reg = <0x300 0 817 reg = <0x300 0x10>;
818 #phy-cells = < 818 #phy-cells = <0>;
819 clock-names = 819 clock-names = "link", "phy";
820 clocks = <&sys 820 clocks = <&sys_clk 15>, <&sys_clk 21>;
821 reset-names = 821 reset-names = "link", "phy";
822 resets = <&sys 822 resets = <&sys_rst 15>, <&sys_rst 21>;
823 vbus-supply = 823 vbus-supply = <&usb1_vbus0>;
824 }; 824 };
825 }; 825 };
826 826
827 nand: nand-controller@68000000 827 nand: nand-controller@68000000 {
828 compatible = "socionex 828 compatible = "socionext,uniphier-denali-nand-v5b";
829 status = "disabled"; 829 status = "disabled";
830 reg-names = "nand_data 830 reg-names = "nand_data", "denali_reg";
831 reg = <0x68000000 0x20 831 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
832 #address-cells = <1>; 832 #address-cells = <1>;
833 #size-cells = <0>; 833 #size-cells = <0>;
834 interrupts = <GIC_SPI 834 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
835 pinctrl-names = "defau 835 pinctrl-names = "default";
836 pinctrl-0 = <&pinctrl_ 836 pinctrl-0 = <&pinctrl_nand>;
837 clock-names = "nand", 837 clock-names = "nand", "nand_x", "ecc";
838 clocks = <&sys_clk 2>, 838 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
839 reset-names = "nand", 839 reset-names = "nand", "reg";
840 resets = <&sys_rst 2>, 840 resets = <&sys_rst 2>, <&sys_rst 2>;
841 }; 841 };
842 }; 842 };
843 }; 843 };
844 844
845 #include "uniphier-pinctrl.dtsi" 845 #include "uniphier-pinctrl.dtsi"
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