1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
2 //
3 // Device Tree Source for UniPhier sLD8 SoC
4 //
5 // Copyright (C) 2015-2016 Socionext Inc.
6 // Author: Masahiro Yamada <yamada.masahiro@s
7
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/interrupt-controller/arm
10
11 / {
12 compatible = "socionext,uniphier-sld8"
13 #address-cells = <1>;
14 #size-cells = <1>;
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 cpu@0 {
21 device_type = "cpu";
22 compatible = "arm,cort
23 reg = <0>;
24 enable-method = "psci"
25 next-level-cache = <&l
26 };
27 };
28
29 psci {
30 compatible = "arm,psci-0.2";
31 method = "smc";
32 };
33
34 clocks {
35 refclk: ref {
36 compatible = "fixed-cl
37 #clock-cells = <0>;
38 clock-frequency = <250
39 };
40
41 arm_timer_clk: arm-timer {
42 #clock-cells = <0>;
43 compatible = "fixed-cl
44 clock-frequency = <500
45 };
46 };
47
48 soc {
49 compatible = "simple-bus";
50 #address-cells = <1>;
51 #size-cells = <1>;
52 ranges;
53 interrupt-parent = <&intc>;
54
55 l2: cache-controller@500c0000
56 compatible = "socionex
57 reg = <0x500c0000 0x20
58 <0x506c0000 0x40
59 interrupts = <GIC_SPI
60 <GIC_SPI
61 cache-unified;
62 cache-size = <(256 * 1
63 cache-sets = <256>;
64 cache-line-size = <128
65 cache-level = <2>;
66 };
67
68 spi: spi@54006000 {
69 compatible = "socionex
70 status = "disabled";
71 reg = <0x54006000 0x10
72 #address-cells = <1>;
73 #size-cells = <0>;
74 interrupts = <GIC_SPI
75 pinctrl-names = "defau
76 pinctrl-0 = <&pinctrl_
77 clocks = <&peri_clk 11
78 resets = <&peri_rst 11
79 };
80
81 serial0: serial@54006800 {
82 compatible = "socionex
83 status = "disabled";
84 reg = <0x54006800 0x40
85 interrupts = <GIC_SPI
86 pinctrl-names = "defau
87 pinctrl-0 = <&pinctrl_
88 clocks = <&peri_clk 0>
89 resets = <&peri_rst 0>
90 };
91
92 serial1: serial@54006900 {
93 compatible = "socionex
94 status = "disabled";
95 reg = <0x54006900 0x40
96 interrupts = <GIC_SPI
97 pinctrl-names = "defau
98 pinctrl-0 = <&pinctrl_
99 clocks = <&peri_clk 1>
100 resets = <&peri_rst 1>
101 };
102
103 serial2: serial@54006a00 {
104 compatible = "socionex
105 status = "disabled";
106 reg = <0x54006a00 0x40
107 interrupts = <GIC_SPI
108 pinctrl-names = "defau
109 pinctrl-0 = <&pinctrl_
110 clocks = <&peri_clk 2>
111 resets = <&peri_rst 2>
112 };
113
114 serial3: serial@54006b00 {
115 compatible = "socionex
116 status = "disabled";
117 reg = <0x54006b00 0x40
118 interrupts = <GIC_SPI
119 pinctrl-names = "defau
120 pinctrl-0 = <&pinctrl_
121 clocks = <&peri_clk 3>
122 resets = <&peri_rst 3>
123 };
124
125 gpio: gpio@55000000 {
126 compatible = "socionex
127 reg = <0x55000000 0x20
128 interrupt-parent = <&a
129 interrupt-controller;
130 #interrupt-cells = <2>
131 gpio-controller;
132 #gpio-cells = <2>;
133 gpio-ranges = <&pinctr
134 <&pinctr
135 <&pinctr
136 gpio-ranges-group-name
137
138
139 ngpios = <136>;
140 socionext,interrupt-ra
141 };
142
143 i2c0: i2c@58400000 {
144 compatible = "socionex
145 status = "disabled";
146 reg = <0x58400000 0x40
147 #address-cells = <1>;
148 #size-cells = <0>;
149 interrupts = <GIC_SPI
150 pinctrl-names = "defau
151 pinctrl-0 = <&pinctrl_
152 clocks = <&peri_clk 4>
153 resets = <&peri_rst 4>
154 clock-frequency = <100
155 };
156
157 i2c1: i2c@58480000 {
158 compatible = "socionex
159 status = "disabled";
160 reg = <0x58480000 0x40
161 #address-cells = <1>;
162 #size-cells = <0>;
163 interrupts = <GIC_SPI
164 pinctrl-names = "defau
165 pinctrl-0 = <&pinctrl_
166 clocks = <&peri_clk 5>
167 resets = <&peri_rst 5>
168 clock-frequency = <100
169 };
170
171 /* chip-internal connection fo
172 i2c2: i2c@58500000 {
173 compatible = "socionex
174 reg = <0x58500000 0x40
175 #address-cells = <1>;
176 #size-cells = <0>;
177 interrupts = <GIC_SPI
178 pinctrl-names = "defau
179 pinctrl-0 = <&pinctrl_
180 clocks = <&peri_clk 6>
181 resets = <&peri_rst 6>
182 clock-frequency = <400
183 };
184
185 i2c3: i2c@58580000 {
186 compatible = "socionex
187 status = "disabled";
188 reg = <0x58580000 0x40
189 #address-cells = <1>;
190 #size-cells = <0>;
191 interrupts = <GIC_SPI
192 pinctrl-names = "defau
193 pinctrl-0 = <&pinctrl_
194 clocks = <&peri_clk 7>
195 resets = <&peri_rst 7>
196 clock-frequency = <100
197 };
198
199 system_bus: system-bus@58c0000
200 compatible = "socionex
201 status = "disabled";
202 reg = <0x58c00000 0x40
203 #address-cells = <2>;
204 #size-cells = <1>;
205 pinctrl-names = "defau
206 pinctrl-0 = <&pinctrl_
207 };
208
209 smpctrl@59801000 {
210 compatible = "socionex
211 reg = <0x59801000 0x40
212 };
213
214 mioctrl: syscon@59810000 {
215 compatible = "socionex
216 "simple-m
217 reg = <0x59810000 0x80
218
219 mio_clk: clock-control
220 compatible = "
221 #clock-cells =
222 };
223
224 mio_rst: reset-control
225 compatible = "
226 #reset-cells =
227 };
228 };
229
230 syscon@59820000 {
231 compatible = "socionex
232 "simple-m
233 reg = <0x59820000 0x20
234
235 peri_clk: clock-contro
236 compatible = "
237 #clock-cells =
238 };
239
240 peri_rst: reset-contro
241 compatible = "
242 #reset-cells =
243 };
244 };
245
246 dmac: dma-controller@5a000000
247 compatible = "socionex
248 reg = <0x5a000000 0x10
249 interrupts = <GIC_SPI
250 <GIC_SPI
251 <GIC_SPI
252 <GIC_SPI
253 <GIC_SPI
254 <GIC_SPI
255 <GIC_SPI
256 clocks = <&mio_clk 7>;
257 resets = <&mio_rst 7>;
258 #dma-cells = <1>;
259 };
260
261 sd: mmc@5a400000 {
262 compatible = "socionex
263 status = "disabled";
264 reg = <0x5a400000 0x20
265 interrupts = <GIC_SPI
266 pinctrl-names = "defau
267 pinctrl-0 = <&pinctrl_
268 pinctrl-1 = <&pinctrl_
269 clocks = <&mio_clk 0>;
270 reset-names = "host",
271 resets = <&mio_rst 0>,
272 dma-names = "rx-tx";
273 dmas = <&dmac 4>;
274 bus-width = <4>;
275 cap-sd-highspeed;
276 sd-uhs-sdr12;
277 sd-uhs-sdr25;
278 sd-uhs-sdr50;
279 socionext,syscon-uhs-m
280 };
281
282 emmc: mmc@5a500000 {
283 compatible = "socionex
284 status = "disabled";
285 reg = <0x5a500000 0x20
286 interrupts = <GIC_SPI
287 pinctrl-names = "defau
288 pinctrl-0 = <&pinctrl_
289 clocks = <&mio_clk 1>;
290 reset-names = "host",
291 resets = <&mio_rst 1>,
292 dma-names = "rx-tx";
293 dmas = <&dmac 6>;
294 bus-width = <8>;
295 cap-mmc-highspeed;
296 cap-mmc-hw-reset;
297 non-removable;
298 };
299
300 usb0: usb@5a800100 {
301 compatible = "socionex
302 status = "disabled";
303 reg = <0x5a800100 0x10
304 interrupts = <GIC_SPI
305 pinctrl-names = "defau
306 pinctrl-0 = <&pinctrl_
307 clocks = <&sys_clk 8>,
308 <&mio_clk 12>
309 resets = <&sys_rst 8>,
310 <&mio_rst 12>
311 has-transaction-transl
312 };
313
314 usb1: usb@5a810100 {
315 compatible = "socionex
316 status = "disabled";
317 reg = <0x5a810100 0x10
318 interrupts = <GIC_SPI
319 pinctrl-names = "defau
320 pinctrl-0 = <&pinctrl_
321 clocks = <&sys_clk 8>,
322 <&mio_clk 13>
323 resets = <&sys_rst 8>,
324 <&mio_rst 13>
325 has-transaction-transl
326 };
327
328 usb2: usb@5a820100 {
329 compatible = "socionex
330 status = "disabled";
331 reg = <0x5a820100 0x10
332 interrupts = <GIC_SPI
333 pinctrl-names = "defau
334 pinctrl-0 = <&pinctrl_
335 clocks = <&sys_clk 8>,
336 <&mio_clk 14>
337 resets = <&sys_rst 8>,
338 <&mio_rst 14>
339 has-transaction-transl
340 };
341
342 syscon@5f800000 {
343 compatible = "socionex
344 "simple-m
345 reg = <0x5f800000 0x20
346
347 pinctrl: pinctrl {
348 compatible = "
349 };
350 };
351
352 syscon@5f900000 {
353 compatible = "socionex
354 "simple-m
355 reg = <0x5f900000 0x20
356 #address-cells = <1>;
357 #size-cells = <1>;
358 ranges = <0 0x5f900000
359
360 efuse@100 {
361 compatible = "
362 reg = <0x100 0
363 };
364
365 efuse@200 {
366 compatible = "
367 reg = <0x200 0
368 };
369 };
370
371 timer@60000200 {
372 compatible = "arm,cort
373 reg = <0x60000200 0x20
374 interrupts = <GIC_PPI
375 (GIC_CPU_MASK_
376 clocks = <&arm_timer_c
377 };
378
379 timer@60000600 {
380 compatible = "arm,cort
381 reg = <0x60000600 0x20
382 interrupts = <GIC_PPI
383 (GIC_CPU_MASK_
384 clocks = <&arm_timer_c
385 };
386
387 intc: interrupt-controller@600
388 compatible = "arm,cort
389 reg = <0x60001000 0x10
390 <0x60000100 0x10
391 #interrupt-cells = <3>
392 interrupt-controller;
393 };
394
395 aidet: interrupt-controller@61
396 compatible = "socionex
397 reg = <0x61830000 0x20
398 interrupt-controller;
399 #interrupt-cells = <2>
400 };
401
402 syscon@61840000 {
403 compatible = "socionex
404 "simple-m
405 reg = <0x61840000 0x10
406
407 sys_clk: clock-control
408 compatible = "
409 #clock-cells =
410 };
411
412 sys_rst: reset-control
413 compatible = "
414 #reset-cells =
415 };
416 };
417
418 nand: nand-controller@68000000
419 compatible = "socionex
420 status = "disabled";
421 reg-names = "nand_data
422 reg = <0x68000000 0x20
423 #address-cells = <1>;
424 #size-cells = <0>;
425 interrupts = <GIC_SPI
426 pinctrl-names = "defau
427 pinctrl-0 = <&pinctrl_
428 clock-names = "nand",
429 clocks = <&sys_clk 2>,
430 reset-names = "nand",
431 resets = <&sys_rst 2>,
432 };
433 };
434 };
435
436 #include "uniphier-pinctrl.dtsi"
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