1 // SPDX-License-Identifier: GPL-2.0-or-later 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* 2 /*
3 * Copyright 2012 Stefan Roese <sr@denx.de> 3 * Copyright 2012 Stefan Roese <sr@denx.de>
4 */ 4 */
5 5
6 / { 6 / {
7 #address-cells = <1>; 7 #address-cells = <1>;
8 #size-cells = <1>; 8 #size-cells = <1>;
9 compatible = "st,spear600"; 9 compatible = "st,spear600";
10 10
11 cpus { 11 cpus {
12 #address-cells = <0>; 12 #address-cells = <0>;
13 #size-cells = <0>; 13 #size-cells = <0>;
14 14
15 cpu { 15 cpu {
16 compatible = "arm,arm9 16 compatible = "arm,arm926ej-s";
17 device_type = "cpu"; 17 device_type = "cpu";
18 }; 18 };
19 }; 19 };
20 20
21 memory { 21 memory {
22 device_type = "memory"; 22 device_type = "memory";
23 reg = <0 0x40000000>; 23 reg = <0 0x40000000>;
24 }; 24 };
25 25
26 ahb { 26 ahb {
27 #address-cells = <1>; 27 #address-cells = <1>;
28 #size-cells = <1>; 28 #size-cells = <1>;
29 compatible = "simple-bus"; 29 compatible = "simple-bus";
30 ranges = <0xd0000000 0xd000000 30 ranges = <0xd0000000 0xd0000000 0x30000000>;
31 31
32 vic0: interrupt-controller@f11 32 vic0: interrupt-controller@f1100000 {
33 compatible = "arm,pl19 33 compatible = "arm,pl190-vic";
34 interrupt-controller; 34 interrupt-controller;
35 reg = <0xf1100000 0x10 35 reg = <0xf1100000 0x1000>;
36 #interrupt-cells = <1> 36 #interrupt-cells = <1>;
37 }; 37 };
38 38
39 vic1: interrupt-controller@f10 39 vic1: interrupt-controller@f1000000 {
40 compatible = "arm,pl19 40 compatible = "arm,pl190-vic";
41 interrupt-controller; 41 interrupt-controller;
42 reg = <0xf1000000 0x10 42 reg = <0xf1000000 0x1000>;
43 #interrupt-cells = <1> 43 #interrupt-cells = <1>;
44 }; 44 };
45 45
46 clcd: clcd@fc200000 { 46 clcd: clcd@fc200000 {
47 compatible = "arm,pl11 47 compatible = "arm,pl110", "arm,primecell";
48 reg = <0xfc200000 0x10 48 reg = <0xfc200000 0x1000>;
49 interrupt-parent = <&v 49 interrupt-parent = <&vic1>;
50 interrupts = <13>; 50 interrupts = <13>;
51 status = "disabled"; 51 status = "disabled";
52 }; 52 };
53 53
54 dmac: dma@fc400000 { 54 dmac: dma@fc400000 {
55 compatible = "arm,pl08 55 compatible = "arm,pl080", "arm,primecell";
56 reg = <0xfc400000 0x10 56 reg = <0xfc400000 0x1000>;
57 interrupt-parent = <&v 57 interrupt-parent = <&vic1>;
58 interrupts = <10>; 58 interrupts = <10>;
59 status = "disabled"; 59 status = "disabled";
60 }; 60 };
61 61
62 gmac: ethernet@e0800000 { 62 gmac: ethernet@e0800000 {
63 compatible = "st,spear 63 compatible = "st,spear600-gmac";
64 reg = <0xe0800000 0x80 64 reg = <0xe0800000 0x8000>;
65 interrupt-parent = <&v 65 interrupt-parent = <&vic1>;
66 interrupts = <24 23>; 66 interrupts = <24 23>;
67 interrupt-names = "mac 67 interrupt-names = "macirq", "eth_wake_irq";
68 phy-mode = "gmii"; 68 phy-mode = "gmii";
69 status = "disabled"; 69 status = "disabled";
70 }; 70 };
71 71
72 fsmc: flash@d1800000 { 72 fsmc: flash@d1800000 {
73 compatible = "st,spear 73 compatible = "st,spear600-fsmc-nand";
74 #address-cells = <1>; 74 #address-cells = <1>;
75 #size-cells = <1>; 75 #size-cells = <1>;
76 reg = <0xd1800000 0x10 76 reg = <0xd1800000 0x1000 /* FSMC Register */
77 0xd2000000 0x00 77 0xd2000000 0x0010 /* NAND Base DATA */
78 0xd2020000 0x00 78 0xd2020000 0x0010 /* NAND Base ADDR */
79 0xd2010000 0x00 79 0xd2010000 0x0010>; /* NAND Base CMD */
80 reg-names = "fsmc_regs 80 reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
81 status = "disabled"; 81 status = "disabled";
82 }; 82 };
83 83
84 smi: flash@fc000000 { 84 smi: flash@fc000000 {
85 compatible = "st,spear 85 compatible = "st,spear600-smi";
86 #address-cells = <1>; 86 #address-cells = <1>;
87 #size-cells = <1>; 87 #size-cells = <1>;
88 reg = <0xfc000000 0x10 88 reg = <0xfc000000 0x1000>;
89 interrupt-parent = <&v 89 interrupt-parent = <&vic1>;
90 interrupts = <12>; 90 interrupts = <12>;
91 status = "disabled"; 91 status = "disabled";
92 }; 92 };
93 93
94 ehci_usb0: ehci@e1800000 { 94 ehci_usb0: ehci@e1800000 {
95 compatible = "st,spear 95 compatible = "st,spear600-ehci", "usb-ehci";
96 reg = <0xe1800000 0x10 96 reg = <0xe1800000 0x1000>;
97 interrupt-parent = <&v 97 interrupt-parent = <&vic1>;
98 interrupts = <27>; 98 interrupts = <27>;
99 status = "disabled"; 99 status = "disabled";
100 }; 100 };
101 101
102 ehci_usb1: ehci@e2000000 { 102 ehci_usb1: ehci@e2000000 {
103 compatible = "st,spear 103 compatible = "st,spear600-ehci", "usb-ehci";
104 reg = <0xe2000000 0x10 104 reg = <0xe2000000 0x1000>;
105 interrupt-parent = <&v 105 interrupt-parent = <&vic1>;
106 interrupts = <29>; 106 interrupts = <29>;
107 status = "disabled"; 107 status = "disabled";
108 }; 108 };
109 109
110 ohci_usb0: ohci@e1900000 { 110 ohci_usb0: ohci@e1900000 {
111 compatible = "st,spear 111 compatible = "st,spear600-ohci", "usb-ohci";
112 reg = <0xe1900000 0x10 112 reg = <0xe1900000 0x1000>;
113 interrupt-parent = <&v 113 interrupt-parent = <&vic1>;
114 interrupts = <26>; 114 interrupts = <26>;
115 status = "disabled"; 115 status = "disabled";
116 }; 116 };
117 117
118 ohci_usb1: ohci@e2100000 { 118 ohci_usb1: ohci@e2100000 {
119 compatible = "st,spear 119 compatible = "st,spear600-ohci", "usb-ohci";
120 reg = <0xe2100000 0x10 120 reg = <0xe2100000 0x1000>;
121 interrupt-parent = <&v 121 interrupt-parent = <&vic1>;
122 interrupts = <28>; 122 interrupts = <28>;
123 status = "disabled"; 123 status = "disabled";
124 }; 124 };
125 125
126 apb { 126 apb {
127 #address-cells = <1>; 127 #address-cells = <1>;
128 #size-cells = <1>; 128 #size-cells = <1>;
129 compatible = "simple-b 129 compatible = "simple-bus";
130 ranges = <0xd0000000 0 130 ranges = <0xd0000000 0xd0000000 0x30000000>;
131 131
132 uart0: serial@d0000000 132 uart0: serial@d0000000 {
133 compatible = " 133 compatible = "arm,pl011", "arm,primecell";
134 reg = <0xd0000 134 reg = <0xd0000000 0x1000>;
135 interrupt-pare 135 interrupt-parent = <&vic0>;
136 interrupts = < 136 interrupts = <24>;
137 status = "disa 137 status = "disabled";
138 }; 138 };
139 139
140 uart1: serial@d0080000 140 uart1: serial@d0080000 {
141 compatible = " 141 compatible = "arm,pl011", "arm,primecell";
142 reg = <0xd0080 142 reg = <0xd0080000 0x1000>;
143 interrupt-pare 143 interrupt-parent = <&vic0>;
144 interrupts = < 144 interrupts = <25>;
145 status = "disa 145 status = "disabled";
146 }; 146 };
147 147
148 /* local/cpu GPIO */ 148 /* local/cpu GPIO */
149 gpio0: gpio@f0100000 { 149 gpio0: gpio@f0100000 {
150 #gpio-cells = 150 #gpio-cells = <2>;
151 compatible = " 151 compatible = "arm,pl061", "arm,primecell";
152 gpio-controlle 152 gpio-controller;
153 reg = <0xf0100 153 reg = <0xf0100000 0x1000>;
154 interrupt-pare 154 interrupt-parent = <&vic0>;
155 interrupts = < 155 interrupts = <18>;
156 }; 156 };
157 157
158 /* basic GPIO */ 158 /* basic GPIO */
159 gpio1: gpio@fc980000 { 159 gpio1: gpio@fc980000 {
160 #gpio-cells = 160 #gpio-cells = <2>;
161 compatible = " 161 compatible = "arm,pl061", "arm,primecell";
162 gpio-controlle 162 gpio-controller;
163 reg = <0xfc980 163 reg = <0xfc980000 0x1000>;
164 interrupt-pare 164 interrupt-parent = <&vic1>;
165 interrupts = < 165 interrupts = <19>;
166 }; 166 };
167 167
168 /* appl GPIO */ 168 /* appl GPIO */
169 gpio2: gpio@d8100000 { 169 gpio2: gpio@d8100000 {
170 #gpio-cells = 170 #gpio-cells = <2>;
171 compatible = " 171 compatible = "arm,pl061", "arm,primecell";
172 gpio-controlle 172 gpio-controller;
173 reg = <0xd8100 173 reg = <0xd8100000 0x1000>;
174 interrupt-pare 174 interrupt-parent = <&vic1>;
175 interrupts = < 175 interrupts = <4>;
176 }; 176 };
177 177
178 i2c: i2c@d0200000 { 178 i2c: i2c@d0200000 {
179 #address-cells 179 #address-cells = <1>;
180 #size-cells = 180 #size-cells = <0>;
181 compatible = " 181 compatible = "snps,designware-i2c";
182 reg = <0xd0200 182 reg = <0xd0200000 0x1000>;
183 interrupt-pare 183 interrupt-parent = <&vic0>;
184 interrupts = < 184 interrupts = <28>;
185 status = "disa 185 status = "disabled";
186 }; 186 };
187 187
188 rtc: rtc@fc900000 { 188 rtc: rtc@fc900000 {
189 compatible = " 189 compatible = "st,spear600-rtc";
190 reg = <0xfc900 190 reg = <0xfc900000 0x1000>;
191 interrupt-pare 191 interrupt-parent = <&vic0>;
192 interrupts = < 192 interrupts = <10>;
193 status = "disa 193 status = "disabled";
194 }; 194 };
195 195
196 timer@f0000000 { 196 timer@f0000000 {
197 compatible = " 197 compatible = "st,spear-timer";
198 reg = <0xf0000 198 reg = <0xf0000000 0x400>;
199 interrupt-pare 199 interrupt-parent = <&vic0>;
200 interrupts = < 200 interrupts = <16>;
201 }; 201 };
202 202
203 adc: adc@d820b000 { 203 adc: adc@d820b000 {
204 compatible = " 204 compatible = "st,spear600-adc";
205 reg = <0xd820b 205 reg = <0xd820b000 0x1000>;
206 interrupt-pare 206 interrupt-parent = <&vic1>;
207 interrupts = < 207 interrupts = <6>;
208 status = "disa 208 status = "disabled";
209 }; 209 };
210 210
211 ssp1: spi@d0100000 { 211 ssp1: spi@d0100000 {
212 compatible = " 212 compatible = "arm,pl022", "arm,primecell";
213 reg = <0xd0100 213 reg = <0xd0100000 0x1000>;
214 #address-cells 214 #address-cells = <1>;
215 #size-cells = 215 #size-cells = <0>;
216 interrupt-pare 216 interrupt-parent = <&vic0>;
217 interrupts = < 217 interrupts = <26>;
218 status = "disa 218 status = "disabled";
219 }; 219 };
220 220
221 ssp2: spi@d0180000 { 221 ssp2: spi@d0180000 {
222 compatible = " 222 compatible = "arm,pl022", "arm,primecell";
223 reg = <0xd0180 223 reg = <0xd0180000 0x1000>;
224 #address-cells 224 #address-cells = <1>;
225 #size-cells = 225 #size-cells = <0>;
226 interrupt-pare 226 interrupt-parent = <&vic0>;
227 interrupts = < 227 interrupts = <27>;
228 status = "disa 228 status = "disabled";
229 }; 229 };
230 230
231 ssp3: spi@d8180000 { 231 ssp3: spi@d8180000 {
232 compatible = " 232 compatible = "arm,pl022", "arm,primecell";
233 reg = <0xd8180 233 reg = <0xd8180000 0x1000>;
234 #address-cells 234 #address-cells = <1>;
235 #size-cells = 235 #size-cells = <0>;
236 interrupt-pare 236 interrupt-parent = <&vic1>;
237 interrupts = < 237 interrupts = <5>;
238 status = "disa 238 status = "disabled";
239 }; 239 };
240 }; 240 };
241 }; 241 };
242 }; 242 };
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