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Linux/scripts/dtc/include-prefixes/arm/st/stih410-clock.dtsi

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Diff markup

Differences between /scripts/dtc/include-prefixes/arm/st/stih410-clock.dtsi (Version linux-6.12-rc7) and /scripts/dtc/include-prefixes/arm/st/stih410-clock.dtsi (Version linux-5.9.16)


  1 // SPDX-License-Identifier: GPL-2.0-only          
  2 /*                                                
  3  * Copyright (C) 2014 STMicroelectronics R&D L    
  4  */                                               
  5 #include <dt-bindings/clock/stih410-clks.h>       
  6 / {                                               
  7         /*                                        
  8          * Fixed 30MHz oscillator inputs to So    
  9          */                                       
 10         clk_sysin: clk-sysin {                    
 11                 #clock-cells = <0>;               
 12                 compatible = "fixed-clock";       
 13                 clock-frequency = <30000000>;     
 14                 clock-output-names = "CLK_SYSI    
 15         };                                        
 16                                                   
 17         clk_tmdsout_hdmi: clk-tmdsout-hdmi {      
 18                 #clock-cells = <0>;               
 19                 compatible = "fixed-clock";       
 20                 clock-frequency = <0>;            
 21         };                                        
 22                                                   
 23         clocks {                                  
 24                 #address-cells = <1>;             
 25                 #size-cells = <1>;                
 26                 ranges;                           
 27                                                   
 28                 compatible = "st,stih410-clk",    
 29                                                   
 30                 /*                                
 31                  * A9 PLL.                        
 32                  */                               
 33                 clockgen-a9@92b0000 {             
 34                         compatible = "st,clkge    
 35                         reg = <0x92b0000 0x100    
 36                                                   
 37                         clockgen_a9_pll: clock    
 38                                 #clock-cells =    
 39                                 compatible = "    
 40                                                   
 41                                 clocks = <&clk    
 42                         };                        
 43                                                   
 44                         /*                        
 45                          * ARM CPU related clo    
 46                          */                       
 47                         clk_m_a9: clk-m-a9 {      
 48                                 #clock-cells =    
 49                                 compatible = "    
 50                                                   
 51                                 clocks = <&clo    
 52                                          <&clo    
 53                                          <&clk    
 54                                          <&clk    
 55                                                   
 56                                 /*                
 57                                  * ARM Periphe    
 58                                  */               
 59                                 arm_periph_clk    
 60                                         #clock    
 61                                         compat    
 62                                         clocks    
 63                                         clock-    
 64                                         clock-    
 65                                 };                
 66                         };                        
 67                 };                                
 68                                                   
 69                 clockgen-a@90ff000 {              
 70                         compatible = "st,clkge    
 71                         reg = <0x90ff000 0x100    
 72                                                   
 73                         clk_s_a0_pll: clk-s-a0    
 74                                 #clock-cells =    
 75                                 compatible = "    
 76                                                   
 77                                 clocks = <&clk    
 78                         };                        
 79                                                   
 80                         clk_s_a0_flexgen: clk-    
 81                                 compatible = "    
 82                                                   
 83                                 #clock-cells =    
 84                                                   
 85                                 clocks = <&clk    
 86                                          <&clk    
 87                         };                        
 88                 };                                
 89                                                   
 90                 clk_s_c0: clockgen-c@9103000 {    
 91                         compatible = "st,clkge    
 92                         reg = <0x9103000 0x100    
 93                                                   
 94                         clk_s_c0_pll0: clk-s-c    
 95                                 #clock-cells =    
 96                                 compatible = "    
 97                                                   
 98                                 clocks = <&clk    
 99                         };                        
100                                                   
101                         clk_s_c0_pll1: clk-s-c    
102                                 #clock-cells =    
103                                 compatible = "    
104                                                   
105                                 clocks = <&clk    
106                         };                        
107                                                   
108                         clk_s_c0_quadfs: clk-s    
109                                 #clock-cells =    
110                                 compatible = "    
111                                                   
112                                 clocks = <&clk    
113                         };                        
114                                                   
115                         clk_s_c0_flexgen: clk-    
116                                 #clock-cells =    
117                                 compatible = "    
118                                                   
119                                 clocks = <&clk    
120                                          <&clk    
121                                          <&clk    
122                                          <&clk    
123                                          <&clk    
124                                          <&clk    
125                                          <&clk    
126                                                   
127                                 /*                
128                                  * ARM Periphe    
129                                  */               
130                                 clk_m_a9_ext2f    
131                                         #clock    
132                                         compat    
133                                                   
134                                         clocks    
135                                                   
136                                         clock-    
137                                                   
138                                         clock-    
139                                         clock-    
140                                 };                
141                         };                        
142                 };                                
143                                                   
144                 clockgen-d0@9104000 {             
145                         compatible = "st,clkge    
146                         reg = <0x9104000 0x100    
147                                                   
148                         clk_s_d0_quadfs: clk-s    
149                                 #clock-cells =    
150                                 compatible = "    
151                                                   
152                                 clocks = <&clk    
153                         };                        
154                                                   
155                         clk_s_d0_flexgen: clk-    
156                                 #clock-cells =    
157                                 compatible = "    
158                                                   
159                                 clocks = <&clk    
160                                          <&clk    
161                                          <&clk    
162                                          <&clk    
163                                          <&clk    
164                         };                        
165                 };                                
166                                                   
167                 clockgen-d2@9106000 {             
168                         compatible = "st,clkge    
169                         reg = <0x9106000 0x100    
170                                                   
171                         clk_s_d2_quadfs: clk-s    
172                                 #clock-cells =    
173                                 compatible = "    
174                                                   
175                                 clocks = <&clk    
176                         };                        
177                                                   
178                         clk_s_d2_flexgen: clk-    
179                                 #clock-cells =    
180                                 compatible = "    
181                                                   
182                                 clocks = <&clk    
183                                          <&clk    
184                                          <&clk    
185                                          <&clk    
186                                          <&clk    
187                                          <&clk    
188                                          <&clk    
189                         };                        
190                 };                                
191                                                   
192                 clockgen-d3@9107000 {             
193                         compatible = "st,clkge    
194                         reg = <0x9107000 0x100    
195                                                   
196                         clk_s_d3_quadfs: clk-s    
197                                 #clock-cells =    
198                                 compatible = "    
199                                                   
200                                 clocks = <&clk    
201                         };                        
202                                                   
203                         clk_s_d3_flexgen: clk-    
204                                 #clock-cells =    
205                                 compatible = "    
206                                                   
207                                 clocks = <&clk    
208                                          <&clk    
209                                          <&clk    
210                                          <&clk    
211                                          <&clk    
212                         };                        
213                 };                                
214         };                                        
215 };                                                
                                                      

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