1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * Copyright (C) 2014 STMicroelectronics R&D L 3 * Copyright (C) 2014 STMicroelectronics R&D Limited
4 */ 4 */
5 #include <dt-bindings/clock/stih410-clks.h> 5 #include <dt-bindings/clock/stih410-clks.h>
6 / { 6 / {
7 /* 7 /*
8 * Fixed 30MHz oscillator inputs to So 8 * Fixed 30MHz oscillator inputs to SoC
9 */ 9 */
10 clk_sysin: clk-sysin { 10 clk_sysin: clk-sysin {
11 #clock-cells = <0>; 11 #clock-cells = <0>;
12 compatible = "fixed-clock"; 12 compatible = "fixed-clock";
13 clock-frequency = <30000000>; 13 clock-frequency = <30000000>;
14 clock-output-names = "CLK_SYSI 14 clock-output-names = "CLK_SYSIN";
15 }; 15 };
16 16
17 clk_tmdsout_hdmi: clk-tmdsout-hdmi { 17 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
18 #clock-cells = <0>; 18 #clock-cells = <0>;
19 compatible = "fixed-clock"; 19 compatible = "fixed-clock";
20 clock-frequency = <0>; 20 clock-frequency = <0>;
21 }; 21 };
22 22
23 clocks { 23 clocks {
24 #address-cells = <1>; 24 #address-cells = <1>;
25 #size-cells = <1>; 25 #size-cells = <1>;
26 ranges; 26 ranges;
27 27
28 compatible = "st,stih410-clk", 28 compatible = "st,stih410-clk", "simple-bus";
29 29
30 /* 30 /*
31 * A9 PLL. 31 * A9 PLL.
32 */ 32 */
33 clockgen-a9@92b0000 { 33 clockgen-a9@92b0000 {
34 compatible = "st,clkge 34 compatible = "st,clkgen-c32";
35 reg = <0x92b0000 0x100 35 reg = <0x92b0000 0x10000>;
36 36
37 clockgen_a9_pll: clock 37 clockgen_a9_pll: clockgen-a9-pll {
38 #clock-cells = 38 #clock-cells = <1>;
39 compatible = " 39 compatible = "st,stih407-clkgen-plla9";
40 40
41 clocks = <&clk 41 clocks = <&clk_sysin>;
42 }; 42 };
43 43
44 /* 44 /*
45 * ARM CPU related clo 45 * ARM CPU related clocks.
46 */ 46 */
47 clk_m_a9: clk-m-a9 { 47 clk_m_a9: clk-m-a9 {
48 #clock-cells = 48 #clock-cells = <0>;
49 compatible = " 49 compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
50 50
51 clocks = <&clo 51 clocks = <&clockgen_a9_pll 0>,
52 <&clo 52 <&clockgen_a9_pll 0>,
53 <&clk 53 <&clk_s_c0_flexgen 13>,
54 <&clk 54 <&clk_m_a9_ext2f_div2>;
55 55
56 /* 56 /*
57 * ARM Periphe 57 * ARM Peripheral clock for timers
58 */ 58 */
59 arm_periph_clk 59 arm_periph_clk: clk-m-a9-periphs {
60 #clock 60 #clock-cells = <0>;
61 compat 61 compatible = "fixed-factor-clock";
62 clocks 62 clocks = <&clk_m_a9>;
63 clock- 63 clock-div = <2>;
64 clock- 64 clock-mult = <1>;
65 }; 65 };
66 }; 66 };
67 }; 67 };
68 68
69 clockgen-a@90ff000 { 69 clockgen-a@90ff000 {
70 compatible = "st,clkge 70 compatible = "st,clkgen-c32";
71 reg = <0x90ff000 0x100 71 reg = <0x90ff000 0x1000>;
72 72
73 clk_s_a0_pll: clk-s-a0 73 clk_s_a0_pll: clk-s-a0-pll {
74 #clock-cells = 74 #clock-cells = <1>;
75 compatible = " 75 compatible = "st,clkgen-pll0-a0";
76 76
77 clocks = <&clk 77 clocks = <&clk_sysin>;
78 }; 78 };
79 79
80 clk_s_a0_flexgen: clk- 80 clk_s_a0_flexgen: clk-s-a0-flexgen {
81 compatible = " 81 compatible = "st,flexgen", "st,flexgen-stih410-a0";
82 82
83 #clock-cells = 83 #clock-cells = <1>;
84 84
85 clocks = <&clk 85 clocks = <&clk_s_a0_pll 0>,
86 <&clk 86 <&clk_sysin>;
87 }; 87 };
88 }; 88 };
89 89
90 clk_s_c0: clockgen-c@9103000 { 90 clk_s_c0: clockgen-c@9103000 {
91 compatible = "st,clkge 91 compatible = "st,clkgen-c32";
92 reg = <0x9103000 0x100 92 reg = <0x9103000 0x1000>;
93 93
94 clk_s_c0_pll0: clk-s-c 94 clk_s_c0_pll0: clk-s-c0-pll0 {
95 #clock-cells = 95 #clock-cells = <1>;
96 compatible = " 96 compatible = "st,clkgen-pll0-c0";
97 97
98 clocks = <&clk 98 clocks = <&clk_sysin>;
99 }; 99 };
100 100
101 clk_s_c0_pll1: clk-s-c 101 clk_s_c0_pll1: clk-s-c0-pll1 {
102 #clock-cells = 102 #clock-cells = <1>;
103 compatible = " 103 compatible = "st,clkgen-pll1-c0";
104 104
105 clocks = <&clk 105 clocks = <&clk_sysin>;
106 }; 106 };
107 107
108 clk_s_c0_quadfs: clk-s 108 clk_s_c0_quadfs: clk-s-c0-quadfs {
109 #clock-cells = 109 #clock-cells = <1>;
110 compatible = " 110 compatible = "st,quadfs-pll";
111 111
112 clocks = <&clk 112 clocks = <&clk_sysin>;
113 }; 113 };
114 114
115 clk_s_c0_flexgen: clk- 115 clk_s_c0_flexgen: clk-s-c0-flexgen {
116 #clock-cells = 116 #clock-cells = <1>;
117 compatible = " 117 compatible = "st,flexgen", "st,flexgen-stih410-c0";
118 118
119 clocks = <&clk 119 clocks = <&clk_s_c0_pll0 0>,
120 <&clk 120 <&clk_s_c0_pll1 0>,
121 <&clk 121 <&clk_s_c0_quadfs 0>,
122 <&clk 122 <&clk_s_c0_quadfs 1>,
123 <&clk 123 <&clk_s_c0_quadfs 2>,
124 <&clk 124 <&clk_s_c0_quadfs 3>,
125 <&clk 125 <&clk_sysin>;
126 126
127 /* 127 /*
128 * ARM Periphe 128 * ARM Peripheral clock for timers
129 */ 129 */
130 clk_m_a9_ext2f 130 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
131 #clock 131 #clock-cells = <0>;
132 compat 132 compatible = "fixed-factor-clock";
133 133
134 clocks 134 clocks = <&clk_s_c0_flexgen 13>;
135 135
136 clock- 136 clock-output-names = "clk-m-a9-ext2f-div2";
137 137
138 clock- 138 clock-div = <2>;
139 clock- 139 clock-mult = <1>;
140 }; 140 };
141 }; 141 };
142 }; 142 };
143 143
144 clockgen-d0@9104000 { 144 clockgen-d0@9104000 {
145 compatible = "st,clkge 145 compatible = "st,clkgen-c32";
146 reg = <0x9104000 0x100 146 reg = <0x9104000 0x1000>;
147 147
148 clk_s_d0_quadfs: clk-s 148 clk_s_d0_quadfs: clk-s-d0-quadfs {
149 #clock-cells = 149 #clock-cells = <1>;
150 compatible = " 150 compatible = "st,quadfs-d0";
151 151
152 clocks = <&clk 152 clocks = <&clk_sysin>;
153 }; 153 };
154 154
155 clk_s_d0_flexgen: clk- 155 clk_s_d0_flexgen: clk-s-d0-flexgen {
156 #clock-cells = 156 #clock-cells = <1>;
157 compatible = " 157 compatible = "st,flexgen", "st,flexgen-stih410-d0";
158 158
159 clocks = <&clk 159 clocks = <&clk_s_d0_quadfs 0>,
160 <&clk 160 <&clk_s_d0_quadfs 1>,
161 <&clk 161 <&clk_s_d0_quadfs 2>,
162 <&clk 162 <&clk_s_d0_quadfs 3>,
163 <&clk 163 <&clk_sysin>;
164 }; 164 };
165 }; 165 };
166 166
167 clockgen-d2@9106000 { 167 clockgen-d2@9106000 {
168 compatible = "st,clkge 168 compatible = "st,clkgen-c32";
169 reg = <0x9106000 0x100 169 reg = <0x9106000 0x1000>;
170 170
171 clk_s_d2_quadfs: clk-s 171 clk_s_d2_quadfs: clk-s-d2-quadfs {
172 #clock-cells = 172 #clock-cells = <1>;
173 compatible = " 173 compatible = "st,quadfs-d2";
174 174
175 clocks = <&clk 175 clocks = <&clk_sysin>;
176 }; 176 };
177 177
178 clk_s_d2_flexgen: clk- 178 clk_s_d2_flexgen: clk-s-d2-flexgen {
179 #clock-cells = 179 #clock-cells = <1>;
180 compatible = " 180 compatible = "st,flexgen", "st,flexgen-stih407-d2";
181 181
182 clocks = <&clk 182 clocks = <&clk_s_d2_quadfs 0>,
183 <&clk 183 <&clk_s_d2_quadfs 1>,
184 <&clk 184 <&clk_s_d2_quadfs 2>,
185 <&clk 185 <&clk_s_d2_quadfs 3>,
186 <&clk 186 <&clk_sysin>,
187 <&clk 187 <&clk_sysin>,
188 <&clk 188 <&clk_tmdsout_hdmi>;
189 }; 189 };
190 }; 190 };
191 191
192 clockgen-d3@9107000 { 192 clockgen-d3@9107000 {
193 compatible = "st,clkge 193 compatible = "st,clkgen-c32";
194 reg = <0x9107000 0x100 194 reg = <0x9107000 0x1000>;
195 195
196 clk_s_d3_quadfs: clk-s 196 clk_s_d3_quadfs: clk-s-d3-quadfs {
197 #clock-cells = 197 #clock-cells = <1>;
198 compatible = " 198 compatible = "st,quadfs-d3";
199 199
200 clocks = <&clk 200 clocks = <&clk_sysin>;
201 }; 201 };
202 202
203 clk_s_d3_flexgen: clk- 203 clk_s_d3_flexgen: clk-s-d3-flexgen {
204 #clock-cells = 204 #clock-cells = <1>;
205 compatible = " 205 compatible = "st,flexgen", "st,flexgen-stih407-d3";
206 206
207 clocks = <&clk 207 clocks = <&clk_s_d3_quadfs 0>,
208 <&clk 208 <&clk_s_d3_quadfs 1>,
209 <&clk 209 <&clk_s_d3_quadfs 2>,
210 <&clk 210 <&clk_s_d3_quadfs 3>,
211 <&clk 211 <&clk_sysin>;
212 }; 212 };
213 }; 213 };
214 }; 214 };
215 }; 215 };
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