1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Copyright (c) 2023 Dario Binacchi <dario.bin 3 * Copyright (c) 2023 Dario Binacchi <dario.binacchi@amarulasolutions.com>
4 */ 4 */
5 5
6 #include "stm32f746.dtsi" 6 #include "stm32f746.dtsi"
7 7
8 / { 8 / {
9 soc { 9 soc {
10 can3: can@40003400 { 10 can3: can@40003400 {
11 compatible = "st,stm32 11 compatible = "st,stm32f4-bxcan";
12 reg = <0x40003400 0x20 12 reg = <0x40003400 0x200>;
13 interrupts = <104>, <1 13 interrupts = <104>, <105>, <106>, <107>;
14 interrupt-names = "tx" 14 interrupt-names = "tx", "rx0", "rx1", "sce";
15 resets = <&rcc STM32F7 15 resets = <&rcc STM32F7_APB1_RESET(CAN3)>;
16 clocks = <&rcc 0 STM32 16 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
17 st,gcan = <&gcan3>; 17 st,gcan = <&gcan3>;
18 status = "disabled"; 18 status = "disabled";
19 }; 19 };
20 20
21 gcan3: gcan@40003600 { 21 gcan3: gcan@40003600 {
22 compatible = "st,stm32 22 compatible = "st,stm32f4-gcan", "syscon";
23 reg = <0x40003600 0x20 23 reg = <0x40003600 0x200>;
24 clocks = <&rcc 0 STM32 24 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
25 }; 25 };
26 26
27 dsi: dsi@40016c00 { 27 dsi: dsi@40016c00 {
28 compatible = "st,stm32 28 compatible = "st,stm32-dsi";
29 reg = <0x40016c00 0x80 29 reg = <0x40016c00 0x800>;
30 clocks = <&rcc 1 CLK_F 30 clocks = <&rcc 1 CLK_F769_DSI>, <&clk_hse>;
31 clock-names = "pclk", 31 clock-names = "pclk", "ref";
32 resets = <&rcc STM32F7 32 resets = <&rcc STM32F7_APB2_RESET(DSI)>;
33 reset-names = "apb"; 33 reset-names = "apb";
34 status = "disabled"; 34 status = "disabled";
35 }; 35 };
36 }; 36 };
37 }; 37 };
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