1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3
2 /*
3 * Copyright (C) STMicroelectronics 2021 - All
4 * Author: Alexandre Torgue <alexandre.torgue@f
5 */
6 #include <dt-bindings/interrupt-controller/arm
7 #include <dt-bindings/clock/stm32mp13-clks.h>
8 #include <dt-bindings/reset/stm32mp13-resets.h
9
10 / {
11 #address-cells = <1>;
12 #size-cells = <1>;
13
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 cpu0: cpu@0 {
19 compatible = "arm,cort
20 device_type = "cpu";
21 reg = <0>;
22 };
23 };
24
25 arm-pmu {
26 compatible = "arm,cortex-a7-pm
27 interrupts = <GIC_SPI 133 IRQ_
28 interrupt-affinity = <&cpu0>;
29 interrupt-parent = <&intc>;
30 };
31
32 firmware {
33 optee {
34 method = "smc";
35 compatible = "linaro,o
36 interrupt-parent = <&i
37 interrupts = <GIC_PPI
38 };
39
40 scmi: scmi {
41 compatible = "linaro,s
42 #address-cells = <1>;
43 #size-cells = <0>;
44 linaro,optee-channel-i
45
46 scmi_clk: protocol@14
47 reg = <0x14>;
48 #clock-cells =
49 };
50
51 scmi_reset: protocol@1
52 reg = <0x16>;
53 #reset-cells =
54 };
55
56 scmi_voltd: protocol@1
57 reg = <0x17>;
58
59 scmi_regu: reg
60 #addre
61 #size-
62
63 scmi_r
64
65
66 };
67 scmi_r
68
69
70 };
71 scmi_u
72
73
74 };
75 };
76 };
77 };
78 };
79
80 intc: interrupt-controller@a0021000 {
81 compatible = "arm,cortex-a7-gi
82 #interrupt-cells = <3>;
83 interrupt-controller;
84 reg = <0xa0021000 0x1000>,
85 <0xa0022000 0x2000>;
86 };
87
88 psci {
89 compatible = "arm,psci-1.0";
90 method = "smc";
91 };
92
93 timer {
94 compatible = "arm,armv7-timer"
95 interrupts = <GIC_PPI 13 (GIC_
96 <GIC_PPI 14 (GIC_
97 <GIC_PPI 11 (GIC_
98 <GIC_PPI 10 (GIC_
99 interrupt-parent = <&intc>;
100 always-on;
101 };
102
103 soc {
104 compatible = "simple-bus";
105 #address-cells = <1>;
106 #size-cells = <1>;
107 interrupt-parent = <&intc>;
108 ranges;
109
110 timers2: timer@40000000 {
111 #address-cells = <1>;
112 #size-cells = <0>;
113 compatible = "st,stm32
114 reg = <0x40000000 0x40
115 interrupts = <GIC_SPI
116 interrupt-names = "glo
117 clocks = <&rcc TIM2_K>
118 clock-names = "int";
119 dmas = <&dmamux1 18 0x
120 <&dmamux1 19 0x
121 <&dmamux1 20 0x
122 <&dmamux1 21 0x
123 <&dmamux1 22 0x
124 dma-names = "ch1", "ch
125 status = "disabled";
126
127 pwm {
128 compatible = "
129 #pwm-cells = <
130 status = "disa
131 };
132
133 timer@1 {
134 compatible = "
135 reg = <1>;
136 status = "disa
137 };
138
139 counter {
140 compatible = "
141 status = "disa
142 };
143 };
144
145 timers3: timer@40001000 {
146 #address-cells = <1>;
147 #size-cells = <0>;
148 compatible = "st,stm32
149 reg = <0x40001000 0x40
150 interrupts = <GIC_SPI
151 interrupt-names = "glo
152 clocks = <&rcc TIM3_K>
153 clock-names = "int";
154 dmas = <&dmamux1 23 0x
155 <&dmamux1 24 0x
156 <&dmamux1 25 0x
157 <&dmamux1 26 0x
158 <&dmamux1 27 0x
159 <&dmamux1 28 0x
160 dma-names = "ch1", "ch
161 status = "disabled";
162
163 pwm {
164 compatible = "
165 #pwm-cells = <
166 status = "disa
167 };
168
169 timer@2 {
170 compatible = "
171 reg = <2>;
172 status = "disa
173 };
174
175 counter {
176 compatible = "
177 status = "disa
178 };
179 };
180
181 timers4: timer@40002000 {
182 #address-cells = <1>;
183 #size-cells = <0>;
184 compatible = "st,stm32
185 reg = <0x40002000 0x40
186 interrupts = <GIC_SPI
187 interrupt-names = "glo
188 clocks = <&rcc TIM4_K>
189 clock-names = "int";
190 dmas = <&dmamux1 29 0x
191 <&dmamux1 30 0x
192 <&dmamux1 31 0x
193 <&dmamux1 32 0x
194 dma-names = "ch1", "ch
195 status = "disabled";
196
197 pwm {
198 compatible = "
199 #pwm-cells = <
200 status = "disa
201 };
202
203 timer@3 {
204 compatible = "
205 reg = <3>;
206 status = "disa
207 };
208
209 counter {
210 compatible = "
211 status = "disa
212 };
213 };
214
215 timers5: timer@40003000 {
216 #address-cells = <1>;
217 #size-cells = <0>;
218 compatible = "st,stm32
219 reg = <0x40003000 0x40
220 interrupts = <GIC_SPI
221 interrupt-names = "glo
222 clocks = <&rcc TIM5_K>
223 clock-names = "int";
224 dmas = <&dmamux1 55 0x
225 <&dmamux1 56 0x
226 <&dmamux1 57 0x
227 <&dmamux1 58 0x
228 <&dmamux1 59 0x
229 <&dmamux1 60 0x
230 dma-names = "ch1", "ch
231 status = "disabled";
232
233 pwm {
234 compatible = "
235 #pwm-cells = <
236 status = "disa
237 };
238
239 timer@4 {
240 compatible = "
241 reg = <4>;
242 status = "disa
243 };
244
245 counter {
246 compatible = "
247 status = "disa
248 };
249 };
250
251 timers6: timer@40004000 {
252 #address-cells = <1>;
253 #size-cells = <0>;
254 compatible = "st,stm32
255 reg = <0x40004000 0x40
256 interrupts = <GIC_SPI
257 interrupt-names = "glo
258 clocks = <&rcc TIM6_K>
259 clock-names = "int";
260 dmas = <&dmamux1 69 0x
261 dma-names = "up";
262 status = "disabled";
263
264 timer@5 {
265 compatible = "
266 reg = <5>;
267 status = "disa
268 };
269 };
270
271 timers7: timer@40005000 {
272 #address-cells = <1>;
273 #size-cells = <0>;
274 compatible = "st,stm32
275 reg = <0x40005000 0x40
276 interrupts = <GIC_SPI
277 interrupt-names = "glo
278 clocks = <&rcc TIM7_K>
279 clock-names = "int";
280 dmas = <&dmamux1 70 0x
281 dma-names = "up";
282 status = "disabled";
283
284 timer@6 {
285 compatible = "
286 reg = <6>;
287 status = "disa
288 };
289 };
290
291 lptimer1: timer@40009000 {
292 #address-cells = <1>;
293 #size-cells = <0>;
294 compatible = "st,stm32
295 reg = <0x40009000 0x40
296 interrupts-extended =
297 clocks = <&rcc LPTIM1_
298 clock-names = "mux";
299 wakeup-source;
300 status = "disabled";
301
302 pwm {
303 compatible = "
304 #pwm-cells = <
305 status = "disa
306 };
307
308 trigger@0 {
309 compatible = "
310 reg = <0>;
311 status = "disa
312 };
313
314 counter {
315 compatible = "
316 status = "disa
317 };
318
319 timer {
320 compatible = "
321 status = "disa
322 };
323 };
324
325 i2s2: audio-controller@4000b00
326 compatible = "st,stm32
327 reg = <0x4000b000 0x40
328 #sound-dai-cells = <0>
329 interrupts = <GIC_SPI
330 dmas = <&dmamux1 39 0x
331 <&dmamux1 40 0x
332 dma-names = "rx", "tx"
333 status = "disabled";
334 };
335
336 spi2: spi@4000b000 {
337 compatible = "st,stm32
338 reg = <0x4000b000 0x40
339 interrupts = <GIC_SPI
340 clocks = <&rcc SPI2_K>
341 resets = <&rcc SPI2_R>
342 #address-cells = <1>;
343 #size-cells = <0>;
344 dmas = <&dmamux1 39 0x
345 <&dmamux1 40 0x
346 dma-names = "rx", "tx"
347 status = "disabled";
348 };
349
350 i2s3: audio-controller@4000c00
351 compatible = "st,stm32
352 reg = <0x4000c000 0x40
353 #sound-dai-cells = <0>
354 interrupts = <GIC_SPI
355 dmas = <&dmamux1 61 0x
356 <&dmamux1 62 0x
357 dma-names = "rx", "tx"
358 status = "disabled";
359 };
360
361 spi3: spi@4000c000 {
362 compatible = "st,stm32
363 reg = <0x4000c000 0x40
364 interrupts = <GIC_SPI
365 clocks = <&rcc SPI3_K>
366 resets = <&rcc SPI3_R>
367 #address-cells = <1>;
368 #size-cells = <0>;
369 dmas = <&dmamux1 61 0x
370 <&dmamux1 62 0x
371 dma-names = "rx", "tx"
372 status = "disabled";
373 };
374
375 spdifrx: audio-controller@4000
376 compatible = "st,stm32
377 reg = <0x4000d000 0x40
378 #sound-dai-cells = <0>
379 clocks = <&rcc SPDIF_K
380 clock-names = "kclk";
381 interrupts = <GIC_SPI
382 dmas = <&dmamux1 93 0x
383 <&dmamux1 94 0x
384 dma-names = "rx", "rx-
385 status = "disabled";
386 };
387
388 usart3: serial@4000f000 {
389 compatible = "st,stm32
390 reg = <0x4000f000 0x40
391 interrupts-extended =
392 clocks = <&rcc USART3_
393 resets = <&rcc USART3_
394 wakeup-source;
395 dmas = <&dmamux1 45 0x
396 <&dmamux1 46 0x
397 dma-names = "rx", "tx"
398 status = "disabled";
399 };
400
401 uart4: serial@40010000 {
402 compatible = "st,stm32
403 reg = <0x40010000 0x40
404 interrupts-extended =
405 clocks = <&rcc UART4_K
406 resets = <&rcc UART4_R
407 wakeup-source;
408 dmas = <&dmamux1 63 0x
409 <&dmamux1 64 0x
410 dma-names = "rx", "tx"
411 status = "disabled";
412 };
413
414 uart5: serial@40011000 {
415 compatible = "st,stm32
416 reg = <0x40011000 0x40
417 interrupts-extended =
418 clocks = <&rcc UART5_K
419 resets = <&rcc UART5_R
420 wakeup-source;
421 dmas = <&dmamux1 65 0x
422 <&dmamux1 66 0x
423 dma-names = "rx", "tx"
424 status = "disabled";
425 };
426
427 i2c1: i2c@40012000 {
428 compatible = "st,stm32
429 reg = <0x40012000 0x40
430 interrupt-names = "eve
431 interrupts = <GIC_SPI
432 <GIC_SPI
433 clocks = <&rcc I2C1_K>
434 resets = <&rcc I2C1_R>
435 #address-cells = <1>;
436 #size-cells = <0>;
437 dmas = <&dmamux1 33 0x
438 <&dmamux1 34 0x
439 dma-names = "rx", "tx"
440 st,syscfg-fmp = <&sysc
441 i2c-analog-filter;
442 status = "disabled";
443 };
444
445 i2c2: i2c@40013000 {
446 compatible = "st,stm32
447 reg = <0x40013000 0x40
448 interrupt-names = "eve
449 interrupts = <GIC_SPI
450 <GIC_SPI
451 clocks = <&rcc I2C2_K>
452 resets = <&rcc I2C2_R>
453 #address-cells = <1>;
454 #size-cells = <0>;
455 dmas = <&dmamux1 35 0x
456 <&dmamux1 36 0x
457 dma-names = "rx", "tx"
458 st,syscfg-fmp = <&sysc
459 i2c-analog-filter;
460 status = "disabled";
461 };
462
463 uart7: serial@40018000 {
464 compatible = "st,stm32
465 reg = <0x40018000 0x40
466 interrupts-extended =
467 clocks = <&rcc UART7_K
468 resets = <&rcc UART7_R
469 wakeup-source;
470 dmas = <&dmamux1 79 0x
471 <&dmamux1 80 0x
472 dma-names = "rx", "tx"
473 status = "disabled";
474 };
475
476 uart8: serial@40019000 {
477 compatible = "st,stm32
478 reg = <0x40019000 0x40
479 interrupts-extended =
480 clocks = <&rcc UART8_K
481 resets = <&rcc UART8_R
482 wakeup-source;
483 dmas = <&dmamux1 81 0x
484 <&dmamux1 82 0x
485 dma-names = "rx", "tx"
486 status = "disabled";
487 };
488
489 timers1: timer@44000000 {
490 #address-cells = <1>;
491 #size-cells = <0>;
492 compatible = "st,stm32
493 reg = <0x44000000 0x40
494 interrupts = <GIC_SPI
495 <GIC_SPI
496 <GIC_SPI
497 <GIC_SPI
498 interrupt-names = "brk
499 clocks = <&rcc TIM1_K>
500 clock-names = "int";
501 dmas = <&dmamux1 11 0x
502 <&dmamux1 12 0x
503 <&dmamux1 13 0x
504 <&dmamux1 14 0x
505 <&dmamux1 15 0x
506 <&dmamux1 16 0x
507 <&dmamux1 17 0x
508 dma-names = "ch1", "ch
509 "up", "tri
510 status = "disabled";
511
512 pwm {
513 compatible = "
514 #pwm-cells = <
515 status = "disa
516 };
517
518 timer@0 {
519 compatible = "
520 reg = <0>;
521 status = "disa
522 };
523
524 counter {
525 compatible = "
526 status = "disa
527 };
528 };
529
530 timers8: timer@44001000 {
531 #address-cells = <1>;
532 #size-cells = <0>;
533 compatible = "st,stm32
534 reg = <0x44001000 0x40
535 interrupts = <GIC_SPI
536 <GIC_SPI
537 <GIC_SPI
538 <GIC_SPI
539 interrupt-names = "brk
540 clocks = <&rcc TIM8_K>
541 clock-names = "int";
542 dmas = <&dmamux1 47 0x
543 <&dmamux1 48 0x
544 <&dmamux1 49 0x
545 <&dmamux1 50 0x
546 <&dmamux1 51 0x
547 <&dmamux1 52 0x
548 <&dmamux1 53 0x
549 dma-names = "ch1", "ch
550 "up", "tri
551 status = "disabled";
552
553 pwm {
554 compatible = "
555 #pwm-cells = <
556 status = "disa
557 };
558
559 timer@7 {
560 compatible = "
561 reg = <7>;
562 status = "disa
563 };
564
565 counter {
566 compatible = "
567 status = "disa
568 };
569 };
570
571 usart6: serial@44003000 {
572 compatible = "st,stm32
573 reg = <0x44003000 0x40
574 interrupts-extended =
575 clocks = <&rcc USART6_
576 resets = <&rcc USART6_
577 wakeup-source;
578 dmas = <&dmamux1 71 0x
579 <&dmamux1 72 0x
580 dma-names = "rx", "tx"
581 status = "disabled";
582 };
583
584 i2s1: audio-controller@4400400
585 compatible = "st,stm32
586 reg = <0x44004000 0x40
587 #sound-dai-cells = <0>
588 interrupts = <GIC_SPI
589 dmas = <&dmamux1 37 0x
590 <&dmamux1 38 0x
591 dma-names = "rx", "tx"
592 status = "disabled";
593 };
594
595 spi1: spi@44004000 {
596 compatible = "st,stm32
597 reg = <0x44004000 0x40
598 interrupts = <GIC_SPI
599 clocks = <&rcc SPI1_K>
600 resets = <&rcc SPI1_R>
601 #address-cells = <1>;
602 #size-cells = <0>;
603 dmas = <&dmamux1 37 0x
604 <&dmamux1 38 0x
605 dma-names = "rx", "tx"
606 status = "disabled";
607 };
608
609 sai1: sai@4400a000 {
610 compatible = "st,stm32
611 reg = <0x4400a000 0x4>
612 ranges = <0 0x4400a000
613 #address-cells = <1>;
614 #size-cells = <1>;
615 interrupts = <GIC_SPI
616 resets = <&rcc SAI1_R>
617 status = "disabled";
618
619 sai1a: audio-controlle
620 compatible = "
621 reg = <0x4 0x2
622 #sound-dai-cel
623 clocks = <&rcc
624 clock-names =
625 dmas = <&dmamu
626 status = "disa
627 };
628
629 sai1b: audio-controlle
630 compatible = "
631 reg = <0x24 0x
632 #sound-dai-cel
633 clocks = <&rcc
634 clock-names =
635 dmas = <&dmamu
636 status = "disa
637 };
638 };
639
640 sai2: sai@4400b000 {
641 compatible = "st,stm32
642 reg = <0x4400b000 0x4>
643 ranges = <0 0x4400b000
644 #address-cells = <1>;
645 #size-cells = <1>;
646 interrupts = <GIC_SPI
647 resets = <&rcc SAI2_R>
648 status = "disabled";
649
650 sai2a: audio-controlle
651 compatible = "
652 reg = <0x4 0x2
653 #sound-dai-cel
654 clocks = <&rcc
655 clock-names =
656 dmas = <&dmamu
657 status = "disa
658 };
659
660 sai2b: audio-controlle
661 compatible = "
662 reg = <0x24 0x
663 #sound-dai-cel
664 clocks = <&rcc
665 clock-names =
666 dmas = <&dmamu
667 status = "disa
668 };
669 };
670
671 dfsdm: dfsdm@4400d000 {
672 compatible = "st,stm32
673 reg = <0x4400d000 0x80
674 clocks = <&rcc DFSDM_K
675 clock-names = "dfsdm";
676 #address-cells = <1>;
677 #size-cells = <0>;
678 status = "disabled";
679
680 dfsdm0: filter@0 {
681 compatible = "
682 reg = <0>;
683 #io-channel-ce
684 interrupts = <
685 dmas = <&dmamu
686 dma-names = "r
687 status = "disa
688 };
689
690 dfsdm1: filter@1 {
691 compatible = "
692 reg = <1>;
693 #io-channel-ce
694 interrupts = <
695 dmas = <&dmamu
696 dma-names = "r
697 status = "disa
698 };
699 };
700
701 dma1: dma-controller@48000000
702 compatible = "st,stm32
703 reg = <0x48000000 0x40
704 interrupts = <GIC_SPI
705 <GIC_SPI
706 <GIC_SPI
707 <GIC_SPI
708 <GIC_SPI
709 <GIC_SPI
710 <GIC_SPI
711 <GIC_SPI
712 clocks = <&rcc DMA1>;
713 resets = <&rcc DMA1_R>
714 #dma-cells = <4>;
715 st,mem2mem;
716 dma-requests = <8>;
717 };
718
719 dma2: dma-controller@48001000
720 compatible = "st,stm32
721 reg = <0x48001000 0x40
722 interrupts = <GIC_SPI
723 <GIC_SPI
724 <GIC_SPI
725 <GIC_SPI
726 <GIC_SPI
727 <GIC_SPI
728 <GIC_SPI
729 <GIC_SPI
730 clocks = <&rcc DMA2>;
731 resets = <&rcc DMA2_R>
732 #dma-cells = <4>;
733 st,mem2mem;
734 dma-requests = <8>;
735 };
736
737 dmamux1: dma-router@48002000 {
738 compatible = "st,stm32
739 reg = <0x48002000 0x40
740 clocks = <&rcc DMAMUX1
741 resets = <&rcc DMAMUX1
742 #dma-cells = <3>;
743 dma-masters = <&dma1 &
744 dma-requests = <128>;
745 dma-channels = <16>;
746 };
747
748 rcc: rcc@50000000 {
749 compatible = "st,stm32
750 reg = <0x50000000 0x10
751 #clock-cells = <1>;
752 #reset-cells = <1>;
753 clock-names = "hse", "
754 clocks = <&scmi_clk CK
755 <&scmi_clk CK
756 <&scmi_clk CK
757 <&scmi_clk CK
758 <&scmi_clk CK
759 };
760
761 pwr_regulators: pwr@50001000 {
762 compatible = "st,stm32
763 reg = <0x50001000 0x10
764 status = "disabled";
765
766 reg11: reg11 {
767 regulator-name
768 regulator-min-
769 regulator-max-
770 };
771
772 reg18: reg18 {
773 regulator-name
774 regulator-min-
775 regulator-max-
776 };
777
778 usb33: usb33 {
779 regulator-name
780 regulator-min-
781 regulator-max-
782 };
783 };
784
785 exti: interrupt-controller@500
786 compatible = "st,stm32
787 interrupt-controller;
788 #interrupt-cells = <2>
789 reg = <0x5000d000 0x40
790 interrupts-extended =
791 <&intc GIC_SPI
792 <&intc GIC_SPI
793 <&intc GIC_SPI
794 <&intc GIC_SPI
795 <&intc GIC_SPI
796 <&intc GIC_SPI
797 <&intc GIC_SPI
798 <&intc GIC_SPI
799 <&intc GIC_SPI
800 <&intc GIC_SPI
801 <&intc GIC_SPI
802 <&intc GIC_SPI
803 <&intc GIC_SPI
804 <&intc GIC_SPI
805 <&intc GIC_SPI
806 <&intc GIC_SPI
807 <&intc GIC_SPI
808 <0>,
809 <0>,
810 <&intc GIC_SPI
811 <0>,
812 <&intc GIC_SPI
813 <&intc GIC_SPI
814 <&intc GIC_SPI
815 <&intc GIC_SPI
816 <&intc GIC_SPI
817 <&intc GIC_SPI
818 <&intc GIC_SPI
819 <&intc GIC_SPI
820 <&intc GIC_SPI
821 <&intc GIC_SPI
822 <&intc GIC_SPI
823 <&intc GIC_SPI
824 <&intc GIC_SPI
825 <0>,
826 <0>,
827 <0>,
828 <0>,
829 <0>,
830 <0>,
831 <0>,
832 <0>,
833 <0>,
834 <0>,
835 <&intc GIC_SPI
836 <0>,
837 <0>,
838 <&intc GIC_SPI
839 <&intc GIC_SPI
840 <0>,
841 <&intc GIC_SPI
842 <0>,
843 <&intc GIC_SPI
844 <&intc GIC_SPI
845 <0>,
846 <0>,
847 <0>,
848 <0>,
849 <0>,
850 <0>,
851 <0>,
852 <0>,
853 <0>,
854 <0>,
855 <0>,
856 <0>,
857 <0>,
858 <0>,
859 <&intc GIC_SPI
860 <0>,
861 <&intc GIC_SPI
862 };
863
864 syscfg: syscon@50020000 {
865 compatible = "st,stm32
866 reg = <0x50020000 0x40
867 clocks = <&rcc SYSCFG>
868 };
869
870 lptimer4: timer@50023000 {
871 compatible = "st,stm32
872 reg = <0x50023000 0x40
873 interrupts-extended =
874 clocks = <&rcc LPTIM4_
875 clock-names = "mux";
876 wakeup-source;
877 status = "disabled";
878
879 pwm {
880 compatible = "
881 #pwm-cells = <
882 status = "disa
883 };
884
885 timer {
886 compatible = "
887 status = "disa
888 };
889 };
890
891 lptimer5: timer@50024000 {
892 compatible = "st,stm32
893 reg = <0x50024000 0x40
894 interrupts-extended =
895 clocks = <&rcc LPTIM5_
896 clock-names = "mux";
897 wakeup-source;
898 status = "disabled";
899
900 pwm {
901 compatible = "
902 #pwm-cells = <
903 status = "disa
904 };
905
906 timer {
907 compatible = "
908 status = "disa
909 };
910 };
911
912 mdma: dma-controller@58000000
913 compatible = "st,stm32
914 reg = <0x58000000 0x10
915 interrupts = <GIC_SPI
916 clocks = <&rcc MDMA>;
917 #dma-cells = <5>;
918 dma-channels = <32>;
919 dma-requests = <48>;
920 };
921
922 crc1: crc@58009000 {
923 compatible = "st,stm32
924 reg = <0x58009000 0x40
925 clocks = <&rcc CRC1>;
926 status = "disabled";
927 };
928
929 usbh_ohci: usb@5800c000 {
930 compatible = "generic-
931 reg = <0x5800c000 0x10
932 clocks = <&usbphyc>, <
933 resets = <&rcc USBH_R>
934 interrupts = <GIC_SPI
935 status = "disabled";
936 };
937
938 usbh_ehci: usb@5800d000 {
939 compatible = "generic-
940 reg = <0x5800d000 0x10
941 clocks = <&usbphyc>, <
942 resets = <&rcc USBH_R>
943 interrupts = <GIC_SPI
944 companion = <&usbh_ohc
945 status = "disabled";
946 };
947
948 iwdg2: watchdog@5a002000 {
949 compatible = "st,stm32
950 reg = <0x5a002000 0x40
951 clocks = <&rcc IWDG2>,
952 clock-names = "pclk",
953 status = "disabled";
954 };
955
956 rtc: rtc@5c004000 {
957 compatible = "st,stm32
958 reg = <0x5c004000 0x40
959 interrupts-extended =
960 clocks = <&scmi_clk CK
961 <&scmi_clk CK
962 clock-names = "pclk",
963 status = "disabled";
964 };
965
966 bsec: efuse@5c005000 {
967 compatible = "st,stm32
968 reg = <0x5c005000 0x40
969 #address-cells = <1>;
970 #size-cells = <1>;
971
972 part_number_otp: part_
973 reg = <0x4 0x2
974 bits = <0 12>;
975 };
976 ts_cal1: calib@5c {
977 reg = <0x5c 0x
978 };
979 ts_cal2: calib@5e {
980 reg = <0x5e 0x
981 };
982 ethernet_mac1_address:
983 reg = <0xe4 0x
984 };
985 ethernet_mac2_address:
986 reg = <0xea 0x
987 };
988 };
989
990 etzpc: bus@5c007000 {
991 compatible = "st,stm32
992 reg = <0x5c007000 0x40
993 #address-cells = <1>;
994 #size-cells = <1>;
995 #access-controller-cel
996 ranges;
997
998 adc_2: adc@48004000 {
999 compatible = "
1000 reg = <0x4800
1001 interrupts =
1002 clocks = <&rc
1003 clock-names =
1004 interrupt-con
1005 #interrupt-ce
1006 #address-cell
1007 #size-cells =
1008 access-contro
1009 status = "dis
1010
1011 adc2: adc@0 {
1012 compa
1013 #io-c
1014 #addr
1015 #size
1016 reg =
1017 inter
1018 inter
1019 dmas
1020 dma-n
1021 statu
1022
1023 chann
1024
1025
1026 };
1027 chann
1028
1029
1030 };
1031 chann
1032
1033
1034 };
1035 chann
1036
1037
1038 };
1039 };
1040 };
1041
1042 usbotg_hs: usb@490000
1043 compatible =
1044 reg = <0x4900
1045 clocks = <&rc
1046 clock-names =
1047 resets = <&rc
1048 reset-names =
1049 interrupts =
1050 g-rx-fifo-siz
1051 g-np-tx-fifo-
1052 g-tx-fifo-siz
1053 dr_mode = "ot
1054 otg-rev = <0x
1055 usb33d-supply
1056 access-contro
1057 status = "dis
1058 };
1059
1060 usart1: serial@4c0000
1061 compatible =
1062 reg = <0x4c00
1063 interrupts-ex
1064 clocks = <&rc
1065 resets = <&rc
1066 wakeup-source
1067 dmas = <&dmam
1068 <&dmamux1 42
1069 dma-names = "
1070 access-contro
1071 status = "dis
1072 };
1073
1074 usart2: serial@4c0010
1075 compatible =
1076 reg = <0x4c00
1077 interrupts-ex
1078 clocks = <&rc
1079 resets = <&rc
1080 wakeup-source
1081 dmas = <&dmam
1082 <&dmamux1 44
1083 dma-names = "
1084 access-contro
1085 status = "dis
1086 };
1087
1088 i2s4: audio-controlle
1089 compatible =
1090 reg = <0x4c00
1091 #sound-dai-ce
1092 interrupts =
1093 dmas = <&dmam
1094 <&dmamux1 84
1095 dma-names = "
1096 access-contro
1097 status = "dis
1098 };
1099
1100 spi4: spi@4c002000 {
1101 compatible =
1102 reg = <0x4c00
1103 interrupts =
1104 clocks = <&rc
1105 resets = <&rc
1106 #address-cell
1107 #size-cells =
1108 dmas = <&dmam
1109 <&dmam
1110 dma-names = "
1111 access-contro
1112 status = "dis
1113 };
1114
1115 spi5: spi@4c003000 {
1116 compatible =
1117 reg = <0x4c00
1118 interrupts =
1119 clocks = <&rc
1120 resets = <&rc
1121 #address-cell
1122 #size-cells =
1123 dmas = <&dmam
1124 <&dmam
1125 dma-names = "
1126 access-contro
1127 status = "dis
1128 };
1129
1130 i2c3: i2c@4c004000 {
1131 compatible =
1132 reg = <0x4c00
1133 interrupt-nam
1134 interrupts =
1135
1136 clocks = <&rc
1137 resets = <&rc
1138 #address-cell
1139 #size-cells =
1140 dmas = <&dmam
1141 <&dmam
1142 dma-names = "
1143 st,syscfg-fmp
1144 i2c-analog-fi
1145 access-contro
1146 status = "dis
1147 };
1148
1149 i2c4: i2c@4c005000 {
1150 compatible =
1151 reg = <0x4c00
1152 interrupt-nam
1153 interrupts =
1154
1155 clocks = <&rc
1156 resets = <&rc
1157 #address-cell
1158 #size-cells =
1159 dmas = <&dmam
1160 <&dmam
1161 dma-names = "
1162 st,syscfg-fmp
1163 i2c-analog-fi
1164 access-contro
1165 status = "dis
1166 };
1167
1168 i2c5: i2c@4c006000 {
1169 compatible =
1170 reg = <0x4c00
1171 interrupt-nam
1172 interrupts =
1173
1174 clocks = <&rc
1175 resets = <&rc
1176 #address-cell
1177 #size-cells =
1178 dmas = <&dmam
1179 <&dmam
1180 dma-names = "
1181 st,syscfg-fmp
1182 i2c-analog-fi
1183 access-contro
1184 status = "dis
1185 };
1186
1187 timers12: timer@4c007
1188 #address-cell
1189 #size-cells =
1190 compatible =
1191 reg = <0x4c00
1192 interrupts =
1193 interrupt-nam
1194 clocks = <&rc
1195 clock-names =
1196 access-contro
1197 status = "dis
1198
1199 pwm {
1200 compa
1201 #pwm-
1202 statu
1203 };
1204
1205 timer@11 {
1206 compa
1207 reg =
1208 statu
1209 };
1210 };
1211
1212 timers13: timer@4c008
1213 #address-cell
1214 #size-cells =
1215 compatible =
1216 reg = <0x4c00
1217 interrupts =
1218 interrupt-nam
1219 clocks = <&rc
1220 clock-names =
1221 access-contro
1222 status = "dis
1223
1224 pwm {
1225 compa
1226 #pwm-
1227 statu
1228 };
1229
1230 timer@12 {
1231 compa
1232 reg =
1233 statu
1234 };
1235 };
1236
1237 timers14: timer@4c009
1238 #address-cell
1239 #size-cells =
1240 compatible =
1241 reg = <0x4c00
1242 interrupts =
1243 interrupt-nam
1244 clocks = <&rc
1245 clock-names =
1246 access-contro
1247 status = "dis
1248
1249 pwm {
1250 compa
1251 #pwm-
1252 statu
1253 };
1254
1255 timer@13 {
1256 compa
1257 reg =
1258 statu
1259 };
1260 };
1261
1262 timers15: timer@4c00a
1263 #address-cell
1264 #size-cells =
1265 compatible =
1266 reg = <0x4c00
1267 interrupts =
1268 interrupt-nam
1269 clocks = <&rc
1270 clock-names =
1271 dmas = <&dmam
1272 <&dmamux1 106
1273 <&dmamux1 107
1274 <&dmamux1 108
1275 dma-names = "
1276 access-contro
1277 status = "dis
1278
1279 pwm {
1280 compa
1281 #pwm-
1282 statu
1283 };
1284
1285 timer@14 {
1286 compa
1287 reg =
1288 statu
1289 };
1290 };
1291
1292 timers16: timer@4c00b
1293 #address-cell
1294 #size-cells =
1295 compatible =
1296 reg = <0x4c00
1297 interrupts =
1298 interrupt-nam
1299 clocks = <&rc
1300 clock-names =
1301 dmas = <&dmam
1302 <&dmamux1 110
1303 dma-names = "
1304 access-contro
1305 status = "dis
1306
1307 pwm {
1308 compa
1309 #pwm-
1310 statu
1311 };
1312
1313 timer@15 {
1314 compa
1315 reg =
1316 statu
1317 };
1318 };
1319
1320 timers17: timer@4c00c
1321 #address-cell
1322 #size-cells =
1323 compatible =
1324 reg = <0x4c00
1325 interrupts =
1326 interrupt-nam
1327 clocks = <&rc
1328 clock-names =
1329 dmas = <&dmam
1330 <&dmam
1331 dma-names = "
1332 access-contro
1333 status = "dis
1334
1335 pwm {
1336 compa
1337 #pwm-
1338 statu
1339 };
1340
1341 timer@16 {
1342 compa
1343 reg =
1344 statu
1345 };
1346 };
1347
1348 lptimer2: timer@50021
1349 #address-cell
1350 #size-cells =
1351 compatible =
1352 reg = <0x5002
1353 interrupts-ex
1354 clocks = <&rc
1355 clock-names =
1356 wakeup-source
1357 access-contro
1358 status = "dis
1359
1360 pwm {
1361 compa
1362 #pwm-
1363 statu
1364 };
1365
1366 trigger@1 {
1367 compa
1368 reg =
1369 statu
1370 };
1371
1372 counter {
1373 compa
1374 statu
1375 };
1376
1377 timer {
1378 compa
1379 statu
1380 };
1381 };
1382
1383 lptimer3: timer@50022
1384 #address-cell
1385 #size-cells =
1386 compatible =
1387 reg = <0x5002
1388 interrupts-ex
1389 clocks = <&rc
1390 clock-names =
1391 wakeup-source
1392 access-contro
1393 status = "dis
1394
1395 pwm {
1396 compa
1397 #pwm-
1398 statu
1399 };
1400
1401 trigger@2 {
1402 compa
1403 reg =
1404 statu
1405 };
1406
1407 timer {
1408 compa
1409 statu
1410 };
1411 };
1412
1413 hash: hash@54003000 {
1414 compatible =
1415 reg = <0x5400
1416 interrupts =
1417 clocks = <&rc
1418 resets = <&rc
1419 dmas = <&mdma
1420 dma-names = "
1421 access-contro
1422 status = "dis
1423 };
1424
1425 rng: rng@54004000 {
1426 compatible =
1427 reg = <0x5400
1428 clocks = <&rc
1429 resets = <&rc
1430 access-contro
1431 status = "dis
1432 };
1433
1434 fmc: memory-controlle
1435 compatible =
1436 reg = <0x5800
1437 ranges = <0 0
1438 <1 0
1439 <2 0
1440 <3 0
1441 <4 0
1442 #address-cell
1443 #size-cells =
1444 clocks = <&rc
1445 resets = <&rc
1446 access-contro
1447 status = "dis
1448
1449 nand-controll
1450 compa
1451 reg =
1452
1453
1454
1455
1456
1457 #addr
1458 #size
1459 inter
1460 dmas
1461
1462
1463 dma-n
1464 statu
1465 };
1466 };
1467
1468 qspi: spi@58003000 {
1469 compatible =
1470 reg = <0x5800
1471 reg-names = "
1472 #address-cell
1473 #size-cells =
1474 interrupts =
1475 dmas = <&mdma
1476 <&mdma
1477 dma-names = "
1478 clocks = <&rc
1479 resets = <&rc
1480 access-contro
1481 status = "dis
1482 };
1483
1484 sdmmc1: mmc@58005000
1485 compatible =
1486 arm,primecell
1487 reg = <0x5800
1488 interrupts =
1489 clocks = <&rc
1490 clock-names =
1491 resets = <&rc
1492 cap-sd-highsp
1493 cap-mmc-highs
1494 max-frequency
1495 access-contro
1496 status = "dis
1497 };
1498
1499 sdmmc2: mmc@58007000
1500 compatible =
1501 arm,primecell
1502 reg = <0x5800
1503 interrupts =
1504 clocks = <&rc
1505 clock-names =
1506 resets = <&rc
1507 cap-sd-highsp
1508 cap-mmc-highs
1509 max-frequency
1510 access-contro
1511 status = "dis
1512 };
1513
1514 ethernet1: ethernet@5
1515 compatible =
1516 reg = <0x5800
1517 reg-names = "
1518 interrupts-ex
1519
1520 interrupt-nam
1521 clock-names =
1522
1523
1524
1525
1526 clocks = <&rc
1527 <&rc
1528 <&rc
1529 <&rc
1530 <&rc
1531 st,syscon = <
1532 snps,mixed-bu
1533 snps,pbl = <2
1534 snps,axi-conf
1535 snps,tso;
1536 access-contro
1537 status = "dis
1538
1539 stmmac_axi_co
1540 snps,
1541 snps,
1542 snps,
1543 };
1544 };
1545
1546 usbphyc: usbphyc@5a00
1547 #address-cell
1548 #size-cells =
1549 #clock-cells
1550 compatible =
1551 reg = <0x5a00
1552 clocks = <&rc
1553 resets = <&rc
1554 vdda1v1-suppl
1555 vdda1v8-suppl
1556 access-contro
1557 status = "dis
1558
1559 usbphyc_port0
1560 #phy-
1561 reg =
1562 };
1563
1564 usbphyc_port1
1565 #phy-
1566 reg =
1567 };
1568 };
1569 };
1570
1571 /*
1572 * Break node order to solve
1573 * pinctrl and exti.
1574 */
1575 pinctrl: pinctrl@50002000 {
1576 #address-cells = <1>;
1577 #size-cells = <1>;
1578 compatible = "st,stm3
1579 ranges = <0 0x5000200
1580 interrupt-parent = <&
1581 st,syscfg = <&exti 0x
1582
1583 gpioa: gpio@50002000
1584 gpio-controll
1585 #gpio-cells =
1586 interrupt-con
1587 #interrupt-ce
1588 reg = <0x0 0x
1589 clocks = <&rc
1590 st,bank-name
1591 ngpios = <16>
1592 gpio-ranges =
1593 };
1594
1595 gpiob: gpio@50003000
1596 gpio-controll
1597 #gpio-cells =
1598 interrupt-con
1599 #interrupt-ce
1600 reg = <0x1000
1601 clocks = <&rc
1602 st,bank-name
1603 ngpios = <16>
1604 gpio-ranges =
1605 };
1606
1607 gpioc: gpio@50004000
1608 gpio-controll
1609 #gpio-cells =
1610 interrupt-con
1611 #interrupt-ce
1612 reg = <0x2000
1613 clocks = <&rc
1614 st,bank-name
1615 ngpios = <16>
1616 gpio-ranges =
1617 };
1618
1619 gpiod: gpio@50005000
1620 gpio-controll
1621 #gpio-cells =
1622 interrupt-con
1623 #interrupt-ce
1624 reg = <0x3000
1625 clocks = <&rc
1626 st,bank-name
1627 ngpios = <16>
1628 gpio-ranges =
1629 };
1630
1631 gpioe: gpio@50006000
1632 gpio-controll
1633 #gpio-cells =
1634 interrupt-con
1635 #interrupt-ce
1636 reg = <0x4000
1637 clocks = <&rc
1638 st,bank-name
1639 ngpios = <16>
1640 gpio-ranges =
1641 };
1642
1643 gpiof: gpio@50007000
1644 gpio-controll
1645 #gpio-cells =
1646 interrupt-con
1647 #interrupt-ce
1648 reg = <0x5000
1649 clocks = <&rc
1650 st,bank-name
1651 ngpios = <16>
1652 gpio-ranges =
1653 };
1654
1655 gpiog: gpio@50008000
1656 gpio-controll
1657 #gpio-cells =
1658 interrupt-con
1659 #interrupt-ce
1660 reg = <0x6000
1661 clocks = <&rc
1662 st,bank-name
1663 ngpios = <16>
1664 gpio-ranges =
1665 };
1666
1667 gpioh: gpio@50009000
1668 gpio-controll
1669 #gpio-cells =
1670 interrupt-con
1671 #interrupt-ce
1672 reg = <0x7000
1673 clocks = <&rc
1674 st,bank-name
1675 ngpios = <15>
1676 gpio-ranges =
1677 };
1678
1679 gpioi: gpio@5000a000
1680 gpio-controll
1681 #gpio-cells =
1682 interrupt-con
1683 #interrupt-ce
1684 reg = <0x8000
1685 clocks = <&rc
1686 st,bank-name
1687 ngpios = <8>;
1688 gpio-ranges =
1689 };
1690 };
1691 };
1692 };
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