1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /* 2 /*
3 * Copyright (C) STMicroelectronics 2017 - All 3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */ 5 */
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h> 7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h> 8 #include <dt-bindings/reset/stm32mp1-resets.h>
9 9
10 / { 10 / {
11 #address-cells = <1>; 11 #address-cells = <1>;
12 #size-cells = <1>; 12 #size-cells = <1>;
13 13
14 cpus { 14 cpus {
15 #address-cells = <1>; 15 #address-cells = <1>;
16 #size-cells = <0>; 16 #size-cells = <0>;
17 17
18 cpu0: cpu@0 { 18 cpu0: cpu@0 {
19 compatible = "arm,cort 19 compatible = "arm,cortex-a7";
20 clock-frequency = <650 20 clock-frequency = <650000000>;
21 device_type = "cpu"; 21 device_type = "cpu";
22 reg = <0>; 22 reg = <0>;
23 }; 23 };
24 }; 24 };
25 25
26 arm-pmu { 26 arm-pmu {
27 compatible = "arm,cortex-a7-pm 27 compatible = "arm,cortex-a7-pmu";
28 interrupts = <GIC_SPI 200 IRQ_ 28 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
29 interrupt-affinity = <&cpu0>; 29 interrupt-affinity = <&cpu0>;
30 interrupt-parent = <&intc>; 30 interrupt-parent = <&intc>;
31 }; 31 };
32 32
33 psci { 33 psci {
34 compatible = "arm,psci-1.0"; 34 compatible = "arm,psci-1.0";
35 method = "smc"; 35 method = "smc";
36 }; 36 };
37 37
38 intc: interrupt-controller@a0021000 { 38 intc: interrupt-controller@a0021000 {
39 compatible = "arm,cortex-a7-gi 39 compatible = "arm,cortex-a7-gic";
40 #interrupt-cells = <3>; 40 #interrupt-cells = <3>;
41 interrupt-controller; 41 interrupt-controller;
42 reg = <0xa0021000 0x1000>, 42 reg = <0xa0021000 0x1000>,
43 <0xa0022000 0x2000>; 43 <0xa0022000 0x2000>;
44 }; 44 };
45 45
46 timer { 46 timer {
47 compatible = "arm,armv7-timer" 47 compatible = "arm,armv7-timer";
48 interrupts = <GIC_PPI 13 (GIC_ 48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
49 <GIC_PPI 14 (GIC_ 49 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 11 (GIC_ 50 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 10 (GIC_ 51 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
52 interrupt-parent = <&intc>; 52 interrupt-parent = <&intc>;
53 arm,no-tick-in-suspend; <<
54 }; 53 };
55 54
56 clocks { 55 clocks {
57 clk_hse: clk-hse { 56 clk_hse: clk-hse {
58 #clock-cells = <0>; 57 #clock-cells = <0>;
59 compatible = "fixed-cl 58 compatible = "fixed-clock";
60 clock-frequency = <240 59 clock-frequency = <24000000>;
61 }; 60 };
62 61
63 clk_hsi: clk-hsi { 62 clk_hsi: clk-hsi {
64 #clock-cells = <0>; 63 #clock-cells = <0>;
65 compatible = "fixed-cl 64 compatible = "fixed-clock";
66 clock-frequency = <640 65 clock-frequency = <64000000>;
67 }; 66 };
68 67
69 clk_lse: clk-lse { 68 clk_lse: clk-lse {
70 #clock-cells = <0>; 69 #clock-cells = <0>;
71 compatible = "fixed-cl 70 compatible = "fixed-clock";
72 clock-frequency = <327 71 clock-frequency = <32768>;
73 }; 72 };
74 73
75 clk_lsi: clk-lsi { 74 clk_lsi: clk-lsi {
76 #clock-cells = <0>; 75 #clock-cells = <0>;
77 compatible = "fixed-cl 76 compatible = "fixed-clock";
78 clock-frequency = <320 77 clock-frequency = <32000>;
79 }; 78 };
80 79
81 clk_csi: clk-csi { 80 clk_csi: clk-csi {
82 #clock-cells = <0>; 81 #clock-cells = <0>;
83 compatible = "fixed-cl 82 compatible = "fixed-clock";
84 clock-frequency = <400 83 clock-frequency = <4000000>;
85 }; 84 };
86 }; 85 };
87 86
88 thermal-zones { 87 thermal-zones {
89 cpu_thermal: cpu-thermal { 88 cpu_thermal: cpu-thermal {
90 polling-delay-passive 89 polling-delay-passive = <0>;
91 polling-delay = <0>; 90 polling-delay = <0>;
92 thermal-sensors = <&dt 91 thermal-sensors = <&dts>;
93 92
94 trips { 93 trips {
95 cpu_alert1: cp 94 cpu_alert1: cpu-alert1 {
96 temper 95 temperature = <85000>;
97 hyster 96 hysteresis = <0>;
98 type = 97 type = "passive";
99 }; 98 };
100 99
101 cpu-crit { 100 cpu-crit {
102 temper 101 temperature = <120000>;
103 hyster 102 hysteresis = <0>;
104 type = 103 type = "critical";
105 }; 104 };
106 }; 105 };
107 106
108 cooling-maps { 107 cooling-maps {
109 }; 108 };
110 }; 109 };
111 }; 110 };
112 111
113 booster: regulator-booster { 112 booster: regulator-booster {
114 compatible = "st,stm32mp1-boos 113 compatible = "st,stm32mp1-booster";
115 st,syscfg = <&syscfg>; 114 st,syscfg = <&syscfg>;
116 status = "disabled"; 115 status = "disabled";
117 }; 116 };
118 117
119 soc { 118 soc {
120 compatible = "simple-bus"; 119 compatible = "simple-bus";
121 #address-cells = <1>; 120 #address-cells = <1>;
122 #size-cells = <1>; 121 #size-cells = <1>;
123 interrupt-parent = <&intc>; 122 interrupt-parent = <&intc>;
124 ranges; 123 ranges;
125 124
>> 125 timers2: timer@40000000 {
>> 126 #address-cells = <1>;
>> 127 #size-cells = <0>;
>> 128 compatible = "st,stm32-timers";
>> 129 reg = <0x40000000 0x400>;
>> 130 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
>> 131 interrupt-names = "global";
>> 132 clocks = <&rcc TIM2_K>;
>> 133 clock-names = "int";
>> 134 dmas = <&dmamux1 18 0x400 0x1>,
>> 135 <&dmamux1 19 0x400 0x1>,
>> 136 <&dmamux1 20 0x400 0x1>,
>> 137 <&dmamux1 21 0x400 0x1>,
>> 138 <&dmamux1 22 0x400 0x1>;
>> 139 dma-names = "ch1", "ch2", "ch3", "ch4", "up";
>> 140 status = "disabled";
>> 141
>> 142 pwm {
>> 143 compatible = "st,stm32-pwm";
>> 144 #pwm-cells = <3>;
>> 145 status = "disabled";
>> 146 };
>> 147
>> 148 timer@1 {
>> 149 compatible = "st,stm32h7-timer-trigger";
>> 150 reg = <1>;
>> 151 status = "disabled";
>> 152 };
>> 153
>> 154 counter {
>> 155 compatible = "st,stm32-timer-counter";
>> 156 status = "disabled";
>> 157 };
>> 158 };
>> 159
>> 160 timers3: timer@40001000 {
>> 161 #address-cells = <1>;
>> 162 #size-cells = <0>;
>> 163 compatible = "st,stm32-timers";
>> 164 reg = <0x40001000 0x400>;
>> 165 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
>> 166 interrupt-names = "global";
>> 167 clocks = <&rcc TIM3_K>;
>> 168 clock-names = "int";
>> 169 dmas = <&dmamux1 23 0x400 0x1>,
>> 170 <&dmamux1 24 0x400 0x1>,
>> 171 <&dmamux1 25 0x400 0x1>,
>> 172 <&dmamux1 26 0x400 0x1>,
>> 173 <&dmamux1 27 0x400 0x1>,
>> 174 <&dmamux1 28 0x400 0x1>;
>> 175 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
>> 176 status = "disabled";
>> 177
>> 178 pwm {
>> 179 compatible = "st,stm32-pwm";
>> 180 #pwm-cells = <3>;
>> 181 status = "disabled";
>> 182 };
>> 183
>> 184 timer@2 {
>> 185 compatible = "st,stm32h7-timer-trigger";
>> 186 reg = <2>;
>> 187 status = "disabled";
>> 188 };
>> 189
>> 190 counter {
>> 191 compatible = "st,stm32-timer-counter";
>> 192 status = "disabled";
>> 193 };
>> 194 };
>> 195
>> 196 timers4: timer@40002000 {
>> 197 #address-cells = <1>;
>> 198 #size-cells = <0>;
>> 199 compatible = "st,stm32-timers";
>> 200 reg = <0x40002000 0x400>;
>> 201 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
>> 202 interrupt-names = "global";
>> 203 clocks = <&rcc TIM4_K>;
>> 204 clock-names = "int";
>> 205 dmas = <&dmamux1 29 0x400 0x1>,
>> 206 <&dmamux1 30 0x400 0x1>,
>> 207 <&dmamux1 31 0x400 0x1>,
>> 208 <&dmamux1 32 0x400 0x1>;
>> 209 dma-names = "ch1", "ch2", "ch3", "ch4";
>> 210 status = "disabled";
>> 211
>> 212 pwm {
>> 213 compatible = "st,stm32-pwm";
>> 214 #pwm-cells = <3>;
>> 215 status = "disabled";
>> 216 };
>> 217
>> 218 timer@3 {
>> 219 compatible = "st,stm32h7-timer-trigger";
>> 220 reg = <3>;
>> 221 status = "disabled";
>> 222 };
>> 223
>> 224 counter {
>> 225 compatible = "st,stm32-timer-counter";
>> 226 status = "disabled";
>> 227 };
>> 228 };
>> 229
>> 230 timers5: timer@40003000 {
>> 231 #address-cells = <1>;
>> 232 #size-cells = <0>;
>> 233 compatible = "st,stm32-timers";
>> 234 reg = <0x40003000 0x400>;
>> 235 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>> 236 interrupt-names = "global";
>> 237 clocks = <&rcc TIM5_K>;
>> 238 clock-names = "int";
>> 239 dmas = <&dmamux1 55 0x400 0x1>,
>> 240 <&dmamux1 56 0x400 0x1>,
>> 241 <&dmamux1 57 0x400 0x1>,
>> 242 <&dmamux1 58 0x400 0x1>,
>> 243 <&dmamux1 59 0x400 0x1>,
>> 244 <&dmamux1 60 0x400 0x1>;
>> 245 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
>> 246 status = "disabled";
>> 247
>> 248 pwm {
>> 249 compatible = "st,stm32-pwm";
>> 250 #pwm-cells = <3>;
>> 251 status = "disabled";
>> 252 };
>> 253
>> 254 timer@4 {
>> 255 compatible = "st,stm32h7-timer-trigger";
>> 256 reg = <4>;
>> 257 status = "disabled";
>> 258 };
>> 259
>> 260 counter {
>> 261 compatible = "st,stm32-timer-counter";
>> 262 status = "disabled";
>> 263 };
>> 264 };
>> 265
>> 266 timers6: timer@40004000 {
>> 267 #address-cells = <1>;
>> 268 #size-cells = <0>;
>> 269 compatible = "st,stm32-timers";
>> 270 reg = <0x40004000 0x400>;
>> 271 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
>> 272 interrupt-names = "global";
>> 273 clocks = <&rcc TIM6_K>;
>> 274 clock-names = "int";
>> 275 dmas = <&dmamux1 69 0x400 0x1>;
>> 276 dma-names = "up";
>> 277 status = "disabled";
>> 278
>> 279 timer@5 {
>> 280 compatible = "st,stm32h7-timer-trigger";
>> 281 reg = <5>;
>> 282 status = "disabled";
>> 283 };
>> 284 };
>> 285
>> 286 timers7: timer@40005000 {
>> 287 #address-cells = <1>;
>> 288 #size-cells = <0>;
>> 289 compatible = "st,stm32-timers";
>> 290 reg = <0x40005000 0x400>;
>> 291 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
>> 292 interrupt-names = "global";
>> 293 clocks = <&rcc TIM7_K>;
>> 294 clock-names = "int";
>> 295 dmas = <&dmamux1 70 0x400 0x1>;
>> 296 dma-names = "up";
>> 297 status = "disabled";
>> 298
>> 299 timer@6 {
>> 300 compatible = "st,stm32h7-timer-trigger";
>> 301 reg = <6>;
>> 302 status = "disabled";
>> 303 };
>> 304 };
>> 305
>> 306 timers12: timer@40006000 {
>> 307 #address-cells = <1>;
>> 308 #size-cells = <0>;
>> 309 compatible = "st,stm32-timers";
>> 310 reg = <0x40006000 0x400>;
>> 311 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
>> 312 interrupt-names = "global";
>> 313 clocks = <&rcc TIM12_K>;
>> 314 clock-names = "int";
>> 315 status = "disabled";
>> 316
>> 317 pwm {
>> 318 compatible = "st,stm32-pwm";
>> 319 #pwm-cells = <3>;
>> 320 status = "disabled";
>> 321 };
>> 322
>> 323 timer@11 {
>> 324 compatible = "st,stm32h7-timer-trigger";
>> 325 reg = <11>;
>> 326 status = "disabled";
>> 327 };
>> 328 };
>> 329
>> 330 timers13: timer@40007000 {
>> 331 #address-cells = <1>;
>> 332 #size-cells = <0>;
>> 333 compatible = "st,stm32-timers";
>> 334 reg = <0x40007000 0x400>;
>> 335 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
>> 336 interrupt-names = "global";
>> 337 clocks = <&rcc TIM13_K>;
>> 338 clock-names = "int";
>> 339 status = "disabled";
>> 340
>> 341 pwm {
>> 342 compatible = "st,stm32-pwm";
>> 343 #pwm-cells = <3>;
>> 344 status = "disabled";
>> 345 };
>> 346
>> 347 timer@12 {
>> 348 compatible = "st,stm32h7-timer-trigger";
>> 349 reg = <12>;
>> 350 status = "disabled";
>> 351 };
>> 352 };
>> 353
>> 354 timers14: timer@40008000 {
>> 355 #address-cells = <1>;
>> 356 #size-cells = <0>;
>> 357 compatible = "st,stm32-timers";
>> 358 reg = <0x40008000 0x400>;
>> 359 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
>> 360 interrupt-names = "global";
>> 361 clocks = <&rcc TIM14_K>;
>> 362 clock-names = "int";
>> 363 status = "disabled";
>> 364
>> 365 pwm {
>> 366 compatible = "st,stm32-pwm";
>> 367 #pwm-cells = <3>;
>> 368 status = "disabled";
>> 369 };
>> 370
>> 371 timer@13 {
>> 372 compatible = "st,stm32h7-timer-trigger";
>> 373 reg = <13>;
>> 374 status = "disabled";
>> 375 };
>> 376 };
>> 377
>> 378 lptimer1: timer@40009000 {
>> 379 #address-cells = <1>;
>> 380 #size-cells = <0>;
>> 381 compatible = "st,stm32-lptimer";
>> 382 reg = <0x40009000 0x400>;
>> 383 interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
>> 384 clocks = <&rcc LPTIM1_K>;
>> 385 clock-names = "mux";
>> 386 wakeup-source;
>> 387 status = "disabled";
>> 388
>> 389 pwm {
>> 390 compatible = "st,stm32-pwm-lp";
>> 391 #pwm-cells = <3>;
>> 392 status = "disabled";
>> 393 };
>> 394
>> 395 trigger@0 {
>> 396 compatible = "st,stm32-lptimer-trigger";
>> 397 reg = <0>;
>> 398 status = "disabled";
>> 399 };
>> 400
>> 401 counter {
>> 402 compatible = "st,stm32-lptimer-counter";
>> 403 status = "disabled";
>> 404 };
>> 405 };
>> 406
>> 407 spi2: spi@4000b000 {
>> 408 #address-cells = <1>;
>> 409 #size-cells = <0>;
>> 410 compatible = "st,stm32h7-spi";
>> 411 reg = <0x4000b000 0x400>;
>> 412 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
>> 413 clocks = <&rcc SPI2_K>;
>> 414 resets = <&rcc SPI2_R>;
>> 415 dmas = <&dmamux1 39 0x400 0x05>,
>> 416 <&dmamux1 40 0x400 0x05>;
>> 417 dma-names = "rx", "tx";
>> 418 status = "disabled";
>> 419 };
>> 420
>> 421 i2s2: audio-controller@4000b000 {
>> 422 compatible = "st,stm32h7-i2s";
>> 423 #sound-dai-cells = <0>;
>> 424 reg = <0x4000b000 0x400>;
>> 425 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
>> 426 dmas = <&dmamux1 39 0x400 0x01>,
>> 427 <&dmamux1 40 0x400 0x01>;
>> 428 dma-names = "rx", "tx";
>> 429 status = "disabled";
>> 430 };
>> 431
>> 432 spi3: spi@4000c000 {
>> 433 #address-cells = <1>;
>> 434 #size-cells = <0>;
>> 435 compatible = "st,stm32h7-spi";
>> 436 reg = <0x4000c000 0x400>;
>> 437 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
>> 438 clocks = <&rcc SPI3_K>;
>> 439 resets = <&rcc SPI3_R>;
>> 440 dmas = <&dmamux1 61 0x400 0x05>,
>> 441 <&dmamux1 62 0x400 0x05>;
>> 442 dma-names = "rx", "tx";
>> 443 status = "disabled";
>> 444 };
>> 445
>> 446 i2s3: audio-controller@4000c000 {
>> 447 compatible = "st,stm32h7-i2s";
>> 448 #sound-dai-cells = <0>;
>> 449 reg = <0x4000c000 0x400>;
>> 450 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
>> 451 dmas = <&dmamux1 61 0x400 0x01>,
>> 452 <&dmamux1 62 0x400 0x01>;
>> 453 dma-names = "rx", "tx";
>> 454 status = "disabled";
>> 455 };
>> 456
>> 457 spdifrx: audio-controller@4000d000 {
>> 458 compatible = "st,stm32h7-spdifrx";
>> 459 #sound-dai-cells = <0>;
>> 460 reg = <0x4000d000 0x400>;
>> 461 clocks = <&rcc SPDIF_K>;
>> 462 clock-names = "kclk";
>> 463 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
>> 464 dmas = <&dmamux1 93 0x400 0x01>,
>> 465 <&dmamux1 94 0x400 0x01>;
>> 466 dma-names = "rx", "rx-ctrl";
>> 467 status = "disabled";
>> 468 };
>> 469
>> 470 usart2: serial@4000e000 {
>> 471 compatible = "st,stm32h7-uart";
>> 472 reg = <0x4000e000 0x400>;
>> 473 interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
>> 474 clocks = <&rcc USART2_K>;
>> 475 wakeup-source;
>> 476 dmas = <&dmamux1 43 0x400 0x15>,
>> 477 <&dmamux1 44 0x400 0x11>;
>> 478 dma-names = "rx", "tx";
>> 479 status = "disabled";
>> 480 };
>> 481
>> 482 usart3: serial@4000f000 {
>> 483 compatible = "st,stm32h7-uart";
>> 484 reg = <0x4000f000 0x400>;
>> 485 interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
>> 486 clocks = <&rcc USART3_K>;
>> 487 wakeup-source;
>> 488 dmas = <&dmamux1 45 0x400 0x15>,
>> 489 <&dmamux1 46 0x400 0x11>;
>> 490 dma-names = "rx", "tx";
>> 491 status = "disabled";
>> 492 };
>> 493
>> 494 uart4: serial@40010000 {
>> 495 compatible = "st,stm32h7-uart";
>> 496 reg = <0x40010000 0x400>;
>> 497 interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
>> 498 clocks = <&rcc UART4_K>;
>> 499 wakeup-source;
>> 500 dmas = <&dmamux1 63 0x400 0x15>,
>> 501 <&dmamux1 64 0x400 0x11>;
>> 502 dma-names = "rx", "tx";
>> 503 status = "disabled";
>> 504 };
>> 505
>> 506 uart5: serial@40011000 {
>> 507 compatible = "st,stm32h7-uart";
>> 508 reg = <0x40011000 0x400>;
>> 509 interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
>> 510 clocks = <&rcc UART5_K>;
>> 511 wakeup-source;
>> 512 dmas = <&dmamux1 65 0x400 0x15>,
>> 513 <&dmamux1 66 0x400 0x11>;
>> 514 dma-names = "rx", "tx";
>> 515 status = "disabled";
>> 516 };
>> 517
>> 518 i2c1: i2c@40012000 {
>> 519 compatible = "st,stm32mp15-i2c";
>> 520 reg = <0x40012000 0x400>;
>> 521 interrupt-names = "event", "error";
>> 522 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
>> 523 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
>> 524 clocks = <&rcc I2C1_K>;
>> 525 resets = <&rcc I2C1_R>;
>> 526 #address-cells = <1>;
>> 527 #size-cells = <0>;
>> 528 st,syscfg-fmp = <&syscfg 0x4 0x1>;
>> 529 wakeup-source;
>> 530 i2c-analog-filter;
>> 531 status = "disabled";
>> 532 };
>> 533
>> 534 i2c2: i2c@40013000 {
>> 535 compatible = "st,stm32mp15-i2c";
>> 536 reg = <0x40013000 0x400>;
>> 537 interrupt-names = "event", "error";
>> 538 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
>> 539 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
>> 540 clocks = <&rcc I2C2_K>;
>> 541 resets = <&rcc I2C2_R>;
>> 542 #address-cells = <1>;
>> 543 #size-cells = <0>;
>> 544 st,syscfg-fmp = <&syscfg 0x4 0x2>;
>> 545 wakeup-source;
>> 546 i2c-analog-filter;
>> 547 status = "disabled";
>> 548 };
>> 549
>> 550 i2c3: i2c@40014000 {
>> 551 compatible = "st,stm32mp15-i2c";
>> 552 reg = <0x40014000 0x400>;
>> 553 interrupt-names = "event", "error";
>> 554 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
>> 555 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
>> 556 clocks = <&rcc I2C3_K>;
>> 557 resets = <&rcc I2C3_R>;
>> 558 #address-cells = <1>;
>> 559 #size-cells = <0>;
>> 560 st,syscfg-fmp = <&syscfg 0x4 0x4>;
>> 561 wakeup-source;
>> 562 i2c-analog-filter;
>> 563 status = "disabled";
>> 564 };
>> 565
>> 566 i2c5: i2c@40015000 {
>> 567 compatible = "st,stm32mp15-i2c";
>> 568 reg = <0x40015000 0x400>;
>> 569 interrupt-names = "event", "error";
>> 570 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
>> 571 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>> 572 clocks = <&rcc I2C5_K>;
>> 573 resets = <&rcc I2C5_R>;
>> 574 #address-cells = <1>;
>> 575 #size-cells = <0>;
>> 576 st,syscfg-fmp = <&syscfg 0x4 0x10>;
>> 577 wakeup-source;
>> 578 i2c-analog-filter;
>> 579 status = "disabled";
>> 580 };
>> 581
>> 582 cec: cec@40016000 {
>> 583 compatible = "st,stm32-cec";
>> 584 reg = <0x40016000 0x400>;
>> 585 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>> 586 clocks = <&rcc CEC_K>, <&rcc CEC>;
>> 587 clock-names = "cec", "hdmi-cec";
>> 588 status = "disabled";
>> 589 };
>> 590
>> 591 dac: dac@40017000 {
>> 592 compatible = "st,stm32h7-dac-core";
>> 593 reg = <0x40017000 0x400>;
>> 594 clocks = <&rcc DAC12>;
>> 595 clock-names = "pclk";
>> 596 #address-cells = <1>;
>> 597 #size-cells = <0>;
>> 598 status = "disabled";
>> 599
>> 600 dac1: dac@1 {
>> 601 compatible = "st,stm32-dac";
>> 602 #io-channel-cells = <1>;
>> 603 reg = <1>;
>> 604 status = "disabled";
>> 605 };
>> 606
>> 607 dac2: dac@2 {
>> 608 compatible = "st,stm32-dac";
>> 609 #io-channel-cells = <1>;
>> 610 reg = <2>;
>> 611 status = "disabled";
>> 612 };
>> 613 };
>> 614
>> 615 uart7: serial@40018000 {
>> 616 compatible = "st,stm32h7-uart";
>> 617 reg = <0x40018000 0x400>;
>> 618 interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
>> 619 clocks = <&rcc UART7_K>;
>> 620 wakeup-source;
>> 621 dmas = <&dmamux1 79 0x400 0x15>,
>> 622 <&dmamux1 80 0x400 0x11>;
>> 623 dma-names = "rx", "tx";
>> 624 status = "disabled";
>> 625 };
>> 626
>> 627 uart8: serial@40019000 {
>> 628 compatible = "st,stm32h7-uart";
>> 629 reg = <0x40019000 0x400>;
>> 630 interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
>> 631 clocks = <&rcc UART8_K>;
>> 632 wakeup-source;
>> 633 dmas = <&dmamux1 81 0x400 0x15>,
>> 634 <&dmamux1 82 0x400 0x11>;
>> 635 dma-names = "rx", "tx";
>> 636 status = "disabled";
>> 637 };
>> 638
>> 639 timers1: timer@44000000 {
>> 640 #address-cells = <1>;
>> 641 #size-cells = <0>;
>> 642 compatible = "st,stm32-timers";
>> 643 reg = <0x44000000 0x400>;
>> 644 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
>> 645 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
>> 646 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
>> 647 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
>> 648 interrupt-names = "brk", "up", "trg-com", "cc";
>> 649 clocks = <&rcc TIM1_K>;
>> 650 clock-names = "int";
>> 651 dmas = <&dmamux1 11 0x400 0x1>,
>> 652 <&dmamux1 12 0x400 0x1>,
>> 653 <&dmamux1 13 0x400 0x1>,
>> 654 <&dmamux1 14 0x400 0x1>,
>> 655 <&dmamux1 15 0x400 0x1>,
>> 656 <&dmamux1 16 0x400 0x1>,
>> 657 <&dmamux1 17 0x400 0x1>;
>> 658 dma-names = "ch1", "ch2", "ch3", "ch4",
>> 659 "up", "trig", "com";
>> 660 status = "disabled";
>> 661
>> 662 pwm {
>> 663 compatible = "st,stm32-pwm";
>> 664 #pwm-cells = <3>;
>> 665 status = "disabled";
>> 666 };
>> 667
>> 668 timer@0 {
>> 669 compatible = "st,stm32h7-timer-trigger";
>> 670 reg = <0>;
>> 671 status = "disabled";
>> 672 };
>> 673
>> 674 counter {
>> 675 compatible = "st,stm32-timer-counter";
>> 676 status = "disabled";
>> 677 };
>> 678 };
>> 679
>> 680 timers8: timer@44001000 {
>> 681 #address-cells = <1>;
>> 682 #size-cells = <0>;
>> 683 compatible = "st,stm32-timers";
>> 684 reg = <0x44001000 0x400>;
>> 685 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
>> 686 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
>> 687 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
>> 688 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
>> 689 interrupt-names = "brk", "up", "trg-com", "cc";
>> 690 clocks = <&rcc TIM8_K>;
>> 691 clock-names = "int";
>> 692 dmas = <&dmamux1 47 0x400 0x1>,
>> 693 <&dmamux1 48 0x400 0x1>,
>> 694 <&dmamux1 49 0x400 0x1>,
>> 695 <&dmamux1 50 0x400 0x1>,
>> 696 <&dmamux1 51 0x400 0x1>,
>> 697 <&dmamux1 52 0x400 0x1>,
>> 698 <&dmamux1 53 0x400 0x1>;
>> 699 dma-names = "ch1", "ch2", "ch3", "ch4",
>> 700 "up", "trig", "com";
>> 701 status = "disabled";
>> 702
>> 703 pwm {
>> 704 compatible = "st,stm32-pwm";
>> 705 #pwm-cells = <3>;
>> 706 status = "disabled";
>> 707 };
>> 708
>> 709 timer@7 {
>> 710 compatible = "st,stm32h7-timer-trigger";
>> 711 reg = <7>;
>> 712 status = "disabled";
>> 713 };
>> 714
>> 715 counter {
>> 716 compatible = "st,stm32-timer-counter";
>> 717 status = "disabled";
>> 718 };
>> 719 };
>> 720
>> 721 usart6: serial@44003000 {
>> 722 compatible = "st,stm32h7-uart";
>> 723 reg = <0x44003000 0x400>;
>> 724 interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
>> 725 clocks = <&rcc USART6_K>;
>> 726 wakeup-source;
>> 727 dmas = <&dmamux1 71 0x400 0x15>,
>> 728 <&dmamux1 72 0x400 0x11>;
>> 729 dma-names = "rx", "tx";
>> 730 status = "disabled";
>> 731 };
>> 732
>> 733 spi1: spi@44004000 {
>> 734 #address-cells = <1>;
>> 735 #size-cells = <0>;
>> 736 compatible = "st,stm32h7-spi";
>> 737 reg = <0x44004000 0x400>;
>> 738 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
>> 739 clocks = <&rcc SPI1_K>;
>> 740 resets = <&rcc SPI1_R>;
>> 741 dmas = <&dmamux1 37 0x400 0x05>,
>> 742 <&dmamux1 38 0x400 0x05>;
>> 743 dma-names = "rx", "tx";
>> 744 status = "disabled";
>> 745 };
>> 746
>> 747 i2s1: audio-controller@44004000 {
>> 748 compatible = "st,stm32h7-i2s";
>> 749 #sound-dai-cells = <0>;
>> 750 reg = <0x44004000 0x400>;
>> 751 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
>> 752 dmas = <&dmamux1 37 0x400 0x01>,
>> 753 <&dmamux1 38 0x400 0x01>;
>> 754 dma-names = "rx", "tx";
>> 755 status = "disabled";
>> 756 };
>> 757
>> 758 spi4: spi@44005000 {
>> 759 #address-cells = <1>;
>> 760 #size-cells = <0>;
>> 761 compatible = "st,stm32h7-spi";
>> 762 reg = <0x44005000 0x400>;
>> 763 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
>> 764 clocks = <&rcc SPI4_K>;
>> 765 resets = <&rcc SPI4_R>;
>> 766 dmas = <&dmamux1 83 0x400 0x05>,
>> 767 <&dmamux1 84 0x400 0x05>;
>> 768 dma-names = "rx", "tx";
>> 769 status = "disabled";
>> 770 };
>> 771
>> 772 timers15: timer@44006000 {
>> 773 #address-cells = <1>;
>> 774 #size-cells = <0>;
>> 775 compatible = "st,stm32-timers";
>> 776 reg = <0x44006000 0x400>;
>> 777 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
>> 778 interrupt-names = "global";
>> 779 clocks = <&rcc TIM15_K>;
>> 780 clock-names = "int";
>> 781 dmas = <&dmamux1 105 0x400 0x1>,
>> 782 <&dmamux1 106 0x400 0x1>,
>> 783 <&dmamux1 107 0x400 0x1>,
>> 784 <&dmamux1 108 0x400 0x1>;
>> 785 dma-names = "ch1", "up", "trig", "com";
>> 786 status = "disabled";
>> 787
>> 788 pwm {
>> 789 compatible = "st,stm32-pwm";
>> 790 #pwm-cells = <3>;
>> 791 status = "disabled";
>> 792 };
>> 793
>> 794 timer@14 {
>> 795 compatible = "st,stm32h7-timer-trigger";
>> 796 reg = <14>;
>> 797 status = "disabled";
>> 798 };
>> 799 };
>> 800
>> 801 timers16: timer@44007000 {
>> 802 #address-cells = <1>;
>> 803 #size-cells = <0>;
>> 804 compatible = "st,stm32-timers";
>> 805 reg = <0x44007000 0x400>;
>> 806 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
>> 807 interrupt-names = "global";
>> 808 clocks = <&rcc TIM16_K>;
>> 809 clock-names = "int";
>> 810 dmas = <&dmamux1 109 0x400 0x1>,
>> 811 <&dmamux1 110 0x400 0x1>;
>> 812 dma-names = "ch1", "up";
>> 813 status = "disabled";
>> 814
>> 815 pwm {
>> 816 compatible = "st,stm32-pwm";
>> 817 #pwm-cells = <3>;
>> 818 status = "disabled";
>> 819 };
>> 820 timer@15 {
>> 821 compatible = "st,stm32h7-timer-trigger";
>> 822 reg = <15>;
>> 823 status = "disabled";
>> 824 };
>> 825 };
>> 826
>> 827 timers17: timer@44008000 {
>> 828 #address-cells = <1>;
>> 829 #size-cells = <0>;
>> 830 compatible = "st,stm32-timers";
>> 831 reg = <0x44008000 0x400>;
>> 832 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
>> 833 interrupt-names = "global";
>> 834 clocks = <&rcc TIM17_K>;
>> 835 clock-names = "int";
>> 836 dmas = <&dmamux1 111 0x400 0x1>,
>> 837 <&dmamux1 112 0x400 0x1>;
>> 838 dma-names = "ch1", "up";
>> 839 status = "disabled";
>> 840
>> 841 pwm {
>> 842 compatible = "st,stm32-pwm";
>> 843 #pwm-cells = <3>;
>> 844 status = "disabled";
>> 845 };
>> 846
>> 847 timer@16 {
>> 848 compatible = "st,stm32h7-timer-trigger";
>> 849 reg = <16>;
>> 850 status = "disabled";
>> 851 };
>> 852 };
>> 853
>> 854 spi5: spi@44009000 {
>> 855 #address-cells = <1>;
>> 856 #size-cells = <0>;
>> 857 compatible = "st,stm32h7-spi";
>> 858 reg = <0x44009000 0x400>;
>> 859 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>> 860 clocks = <&rcc SPI5_K>;
>> 861 resets = <&rcc SPI5_R>;
>> 862 dmas = <&dmamux1 85 0x400 0x05>,
>> 863 <&dmamux1 86 0x400 0x05>;
>> 864 dma-names = "rx", "tx";
>> 865 status = "disabled";
>> 866 };
>> 867
>> 868 sai1: sai@4400a000 {
>> 869 compatible = "st,stm32h7-sai";
>> 870 #address-cells = <1>;
>> 871 #size-cells = <1>;
>> 872 ranges = <0 0x4400a000 0x400>;
>> 873 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
>> 874 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
>> 875 resets = <&rcc SAI1_R>;
>> 876 status = "disabled";
>> 877
>> 878 sai1a: audio-controller@4400a004 {
>> 879 #sound-dai-cells = <0>;
>> 880
>> 881 compatible = "st,stm32-sai-sub-a";
>> 882 reg = <0x4 0x20>;
>> 883 clocks = <&rcc SAI1_K>;
>> 884 clock-names = "sai_ck";
>> 885 dmas = <&dmamux1 87 0x400 0x01>;
>> 886 status = "disabled";
>> 887 };
>> 888
>> 889 sai1b: audio-controller@4400a024 {
>> 890 #sound-dai-cells = <0>;
>> 891 compatible = "st,stm32-sai-sub-b";
>> 892 reg = <0x24 0x20>;
>> 893 clocks = <&rcc SAI1_K>;
>> 894 clock-names = "sai_ck";
>> 895 dmas = <&dmamux1 88 0x400 0x01>;
>> 896 status = "disabled";
>> 897 };
>> 898 };
>> 899
>> 900 sai2: sai@4400b000 {
>> 901 compatible = "st,stm32h7-sai";
>> 902 #address-cells = <1>;
>> 903 #size-cells = <1>;
>> 904 ranges = <0 0x4400b000 0x400>;
>> 905 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
>> 906 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
>> 907 resets = <&rcc SAI2_R>;
>> 908 status = "disabled";
>> 909
>> 910 sai2a: audio-controller@4400b004 {
>> 911 #sound-dai-cells = <0>;
>> 912 compatible = "st,stm32-sai-sub-a";
>> 913 reg = <0x4 0x20>;
>> 914 clocks = <&rcc SAI2_K>;
>> 915 clock-names = "sai_ck";
>> 916 dmas = <&dmamux1 89 0x400 0x01>;
>> 917 status = "disabled";
>> 918 };
>> 919
>> 920 sai2b: audio-controller@4400b024 {
>> 921 #sound-dai-cells = <0>;
>> 922 compatible = "st,stm32-sai-sub-b";
>> 923 reg = <0x24 0x20>;
>> 924 clocks = <&rcc SAI2_K>;
>> 925 clock-names = "sai_ck";
>> 926 dmas = <&dmamux1 90 0x400 0x01>;
>> 927 status = "disabled";
>> 928 };
>> 929 };
>> 930
>> 931 sai3: sai@4400c000 {
>> 932 compatible = "st,stm32h7-sai";
>> 933 #address-cells = <1>;
>> 934 #size-cells = <1>;
>> 935 ranges = <0 0x4400c000 0x400>;
>> 936 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
>> 937 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
>> 938 resets = <&rcc SAI3_R>;
>> 939 status = "disabled";
>> 940
>> 941 sai3a: audio-controller@4400c004 {
>> 942 #sound-dai-cells = <0>;
>> 943 compatible = "st,stm32-sai-sub-a";
>> 944 reg = <0x04 0x20>;
>> 945 clocks = <&rcc SAI3_K>;
>> 946 clock-names = "sai_ck";
>> 947 dmas = <&dmamux1 113 0x400 0x01>;
>> 948 status = "disabled";
>> 949 };
>> 950
>> 951 sai3b: audio-controller@4400c024 {
>> 952 #sound-dai-cells = <0>;
>> 953 compatible = "st,stm32-sai-sub-b";
>> 954 reg = <0x24 0x20>;
>> 955 clocks = <&rcc SAI3_K>;
>> 956 clock-names = "sai_ck";
>> 957 dmas = <&dmamux1 114 0x400 0x01>;
>> 958 status = "disabled";
>> 959 };
>> 960 };
>> 961
>> 962 dfsdm: dfsdm@4400d000 {
>> 963 compatible = "st,stm32mp1-dfsdm";
>> 964 reg = <0x4400d000 0x800>;
>> 965 clocks = <&rcc DFSDM_K>;
>> 966 clock-names = "dfsdm";
>> 967 #address-cells = <1>;
>> 968 #size-cells = <0>;
>> 969 status = "disabled";
>> 970
>> 971 dfsdm0: filter@0 {
>> 972 compatible = "st,stm32-dfsdm-adc";
>> 973 #io-channel-cells = <1>;
>> 974 reg = <0>;
>> 975 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
>> 976 dmas = <&dmamux1 101 0x400 0x01>;
>> 977 dma-names = "rx";
>> 978 status = "disabled";
>> 979 };
>> 980
>> 981 dfsdm1: filter@1 {
>> 982 compatible = "st,stm32-dfsdm-adc";
>> 983 #io-channel-cells = <1>;
>> 984 reg = <1>;
>> 985 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
>> 986 dmas = <&dmamux1 102 0x400 0x01>;
>> 987 dma-names = "rx";
>> 988 status = "disabled";
>> 989 };
>> 990
>> 991 dfsdm2: filter@2 {
>> 992 compatible = "st,stm32-dfsdm-adc";
>> 993 #io-channel-cells = <1>;
>> 994 reg = <2>;
>> 995 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
>> 996 dmas = <&dmamux1 103 0x400 0x01>;
>> 997 dma-names = "rx";
>> 998 status = "disabled";
>> 999 };
>> 1000
>> 1001 dfsdm3: filter@3 {
>> 1002 compatible = "st,stm32-dfsdm-adc";
>> 1003 #io-channel-cells = <1>;
>> 1004 reg = <3>;
>> 1005 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
>> 1006 dmas = <&dmamux1 104 0x400 0x01>;
>> 1007 dma-names = "rx";
>> 1008 status = "disabled";
>> 1009 };
>> 1010
>> 1011 dfsdm4: filter@4 {
>> 1012 compatible = "st,stm32-dfsdm-adc";
>> 1013 #io-channel-cells = <1>;
>> 1014 reg = <4>;
>> 1015 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>> 1016 dmas = <&dmamux1 91 0x400 0x01>;
>> 1017 dma-names = "rx";
>> 1018 status = "disabled";
>> 1019 };
>> 1020
>> 1021 dfsdm5: filter@5 {
>> 1022 compatible = "st,stm32-dfsdm-adc";
>> 1023 #io-channel-cells = <1>;
>> 1024 reg = <5>;
>> 1025 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
>> 1026 dmas = <&dmamux1 92 0x400 0x01>;
>> 1027 dma-names = "rx";
>> 1028 status = "disabled";
>> 1029 };
>> 1030 };
>> 1031
>> 1032 dma1: dma-controller@48000000 {
>> 1033 compatible = "st,stm32-dma";
>> 1034 reg = <0x48000000 0x400>;
>> 1035 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
>> 1036 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
>> 1037 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
>> 1038 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
>> 1039 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
>> 1040 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
>> 1041 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
>> 1042 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
>> 1043 clocks = <&rcc DMA1>;
>> 1044 resets = <&rcc DMA1_R>;
>> 1045 #dma-cells = <4>;
>> 1046 st,mem2mem;
>> 1047 dma-requests = <8>;
>> 1048 };
>> 1049
>> 1050 dma2: dma-controller@48001000 {
>> 1051 compatible = "st,stm32-dma";
>> 1052 reg = <0x48001000 0x400>;
>> 1053 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
>> 1054 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
>> 1055 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
>> 1056 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
>> 1057 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
>> 1058 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
>> 1059 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
>> 1060 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
>> 1061 clocks = <&rcc DMA2>;
>> 1062 resets = <&rcc DMA2_R>;
>> 1063 #dma-cells = <4>;
>> 1064 st,mem2mem;
>> 1065 dma-requests = <8>;
>> 1066 };
>> 1067
>> 1068 dmamux1: dma-router@48002000 {
>> 1069 compatible = "st,stm32h7-dmamux";
>> 1070 reg = <0x48002000 0x40>;
>> 1071 #dma-cells = <3>;
>> 1072 dma-requests = <128>;
>> 1073 dma-masters = <&dma1 &dma2>;
>> 1074 dma-channels = <16>;
>> 1075 clocks = <&rcc DMAMUX>;
>> 1076 resets = <&rcc DMAMUX_R>;
>> 1077 };
>> 1078
>> 1079 adc: adc@48003000 {
>> 1080 compatible = "st,stm32mp1-adc-core";
>> 1081 reg = <0x48003000 0x400>;
>> 1082 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
>> 1083 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
>> 1084 clocks = <&rcc ADC12>, <&rcc ADC12_K>;
>> 1085 clock-names = "bus", "adc";
>> 1086 interrupt-controller;
>> 1087 st,syscfg = <&syscfg>;
>> 1088 #interrupt-cells = <1>;
>> 1089 #address-cells = <1>;
>> 1090 #size-cells = <0>;
>> 1091 status = "disabled";
>> 1092
>> 1093 adc1: adc@0 {
>> 1094 compatible = "st,stm32mp1-adc";
>> 1095 #io-channel-cells = <1>;
>> 1096 #address-cells = <1>;
>> 1097 #size-cells = <0>;
>> 1098 reg = <0x0>;
>> 1099 interrupt-parent = <&adc>;
>> 1100 interrupts = <0>;
>> 1101 dmas = <&dmamux1 9 0x400 0x01>;
>> 1102 dma-names = "rx";
>> 1103 status = "disabled";
>> 1104 };
>> 1105
>> 1106 adc2: adc@100 {
>> 1107 compatible = "st,stm32mp1-adc";
>> 1108 #io-channel-cells = <1>;
>> 1109 #address-cells = <1>;
>> 1110 #size-cells = <0>;
>> 1111 reg = <0x100>;
>> 1112 interrupt-parent = <&adc>;
>> 1113 interrupts = <1>;
>> 1114 dmas = <&dmamux1 10 0x400 0x01>;
>> 1115 dma-names = "rx";
>> 1116 nvmem-cells = <&vrefint>;
>> 1117 nvmem-cell-names = "vrefint";
>> 1118 status = "disabled";
>> 1119 channel@13 {
>> 1120 reg = <13>;
>> 1121 label = "vrefint";
>> 1122 };
>> 1123 channel@14 {
>> 1124 reg = <14>;
>> 1125 label = "vddcore";
>> 1126 };
>> 1127 };
>> 1128 };
>> 1129
>> 1130 sdmmc3: mmc@48004000 {
>> 1131 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>> 1132 arm,primecell-periphid = <0x00253180>;
>> 1133 reg = <0x48004000 0x400>;
>> 1134 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
>> 1135 clocks = <&rcc SDMMC3_K>;
>> 1136 clock-names = "apb_pclk";
>> 1137 resets = <&rcc SDMMC3_R>;
>> 1138 cap-sd-highspeed;
>> 1139 cap-mmc-highspeed;
>> 1140 max-frequency = <120000000>;
>> 1141 status = "disabled";
>> 1142 };
>> 1143
>> 1144 usbotg_hs: usb-otg@49000000 {
>> 1145 compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>> 1146 reg = <0x49000000 0x10000>;
>> 1147 clocks = <&rcc USBO_K>, <&usbphyc>;
>> 1148 clock-names = "otg", "utmi";
>> 1149 resets = <&rcc USBO_R>;
>> 1150 reset-names = "dwc2";
>> 1151 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
>> 1152 g-rx-fifo-size = <512>;
>> 1153 g-np-tx-fifo-size = <32>;
>> 1154 g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>> 1155 dr_mode = "otg";
>> 1156 otg-rev = <0x200>;
>> 1157 usb33d-supply = <&usb33>;
>> 1158 status = "disabled";
>> 1159 };
>> 1160
126 ipcc: mailbox@4c001000 { 1161 ipcc: mailbox@4c001000 {
127 compatible = "st,stm32 1162 compatible = "st,stm32mp1-ipcc";
128 #mbox-cells = <1>; 1163 #mbox-cells = <1>;
129 reg = <0x4c001000 0x40 1164 reg = <0x4c001000 0x400>;
130 st,proc-id = <0>; 1165 st,proc-id = <0>;
131 interrupts-extended = 1166 interrupts-extended =
132 <&exti 61 1>, 1167 <&exti 61 1>,
133 <&intc GIC_SPI 1168 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
134 interrupt-names = "rx" 1169 interrupt-names = "rx", "tx";
135 clocks = <&rcc IPCC>; 1170 clocks = <&rcc IPCC>;
136 wakeup-source; 1171 wakeup-source;
137 status = "disabled"; 1172 status = "disabled";
138 }; 1173 };
139 1174
>> 1175 dcmi: dcmi@4c006000 {
>> 1176 compatible = "st,stm32-dcmi";
>> 1177 reg = <0x4c006000 0x400>;
>> 1178 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
>> 1179 resets = <&rcc CAMITF_R>;
>> 1180 clocks = <&rcc DCMI>;
>> 1181 clock-names = "mclk";
>> 1182 dmas = <&dmamux1 75 0x400 0x01>;
>> 1183 dma-names = "tx";
>> 1184 status = "disabled";
>> 1185 };
>> 1186
140 rcc: rcc@50000000 { 1187 rcc: rcc@50000000 {
141 compatible = "st,stm32 1188 compatible = "st,stm32mp1-rcc", "syscon";
142 reg = <0x50000000 0x10 1189 reg = <0x50000000 0x1000>;
143 #clock-cells = <1>; 1190 #clock-cells = <1>;
144 #reset-cells = <1>; 1191 #reset-cells = <1>;
145 }; 1192 };
146 1193
147 pwr_regulators: pwr@50001000 { 1194 pwr_regulators: pwr@50001000 {
148 compatible = "st,stm32 1195 compatible = "st,stm32mp1,pwr-reg";
149 reg = <0x50001000 0x10 1196 reg = <0x50001000 0x10>;
150 1197
151 reg11: reg11 { 1198 reg11: reg11 {
152 regulator-name 1199 regulator-name = "reg11";
153 regulator-min- 1200 regulator-min-microvolt = <1100000>;
154 regulator-max- 1201 regulator-max-microvolt = <1100000>;
155 }; 1202 };
156 1203
157 reg18: reg18 { 1204 reg18: reg18 {
158 regulator-name 1205 regulator-name = "reg18";
159 regulator-min- 1206 regulator-min-microvolt = <1800000>;
160 regulator-max- 1207 regulator-max-microvolt = <1800000>;
161 }; 1208 };
162 1209
163 usb33: usb33 { 1210 usb33: usb33 {
164 regulator-name 1211 regulator-name = "usb33";
165 regulator-min- 1212 regulator-min-microvolt = <3300000>;
166 regulator-max- 1213 regulator-max-microvolt = <3300000>;
167 }; 1214 };
168 }; 1215 };
169 1216
170 pwr_mcu: pwr_mcu@50001014 { 1217 pwr_mcu: pwr_mcu@50001014 {
171 compatible = "st,stm32 1218 compatible = "st,stm32mp151-pwr-mcu", "syscon";
172 reg = <0x50001014 0x4> 1219 reg = <0x50001014 0x4>;
173 }; 1220 };
174 1221
175 exti: interrupt-controller@500 1222 exti: interrupt-controller@5000d000 {
176 compatible = "st,stm32 1223 compatible = "st,stm32mp1-exti", "syscon";
177 interrupt-controller; 1224 interrupt-controller;
178 #interrupt-cells = <2> 1225 #interrupt-cells = <2>;
179 reg = <0x5000d000 0x40 1226 reg = <0x5000d000 0x400>;
180 interrupts-extended = <<
181 <&intc GIC_SPI <<
182 <&intc GIC_SPI <<
183 <&intc GIC_SPI <<
184 <&intc GIC_SPI <<
185 <&intc GIC_SPI <<
186 <&intc GIC_SPI <<
187 <&intc GIC_SPI <<
188 <&intc GIC_SPI <<
189 <&intc GIC_SPI <<
190 <&intc GIC_SPI <<
191 <&intc GIC_SPI <<
192 <&intc GIC_SPI <<
193 <&intc GIC_SPI <<
194 <&intc GIC_SPI <<
195 <&intc GIC_SPI <<
196 <&intc GIC_SPI <<
197 <&intc GIC_SPI <<
198 <0>, <<
199 <0>, <<
200 <&intc GIC_SPI <<
201 <0>, <<
202 <&intc GIC_SPI <<
203 <&intc GIC_SPI <<
204 <&intc GIC_SPI <<
205 <&intc GIC_SPI <<
206 <&intc GIC_SPI <<
207 <&intc GIC_SPI <<
208 <&intc GIC_SPI <<
209 <&intc GIC_SPI <<
210 <&intc GIC_SPI <<
211 <&intc GIC_SPI <<
212 <&intc GIC_SPI <<
213 <&intc GIC_SPI <<
214 <&intc GIC_SPI <<
215 <0>, <<
216 <0>, <<
217 <0>, <<
218 <0>, <<
219 <0>, <<
220 <0>, <<
221 <0>, <<
222 <0>, <<
223 <0>, <<
224 <0>, <<
225 <0>, <<
226 <0>, <<
227 <&intc GIC_SPI <<
228 <&intc GIC_SPI <<
229 <&intc GIC_SPI <<
230 <0>, <<
231 <&intc GIC_SPI <<
232 <0>, <<
233 <&intc GIC_SPI <<
234 <&intc GIC_SPI <<
235 <&intc GIC_SPI <<
236 <0>, <<
237 <0>, <<
238 <0>, <<
239 <0>, <<
240 <0>, <<
241 <0>, <<
242 <&intc GIC_SPI <<
243 <0>, <<
244 <0>, <<
245 <0>, <<
246 <&intc GIC_SPI <<
247 <0>, <<
248 <0>, <<
249 <&intc GIC_SPI <<
250 <0>, <<
251 <&intc GIC_SPI <<
252 <0>, <<
253 <0>, <<
254 <&intc GIC_SPI <<
255 }; 1227 };
256 1228
257 syscfg: syscon@50020000 { 1229 syscfg: syscon@50020000 {
258 compatible = "st,stm32 1230 compatible = "st,stm32mp157-syscfg", "syscon";
259 reg = <0x50020000 0x40 1231 reg = <0x50020000 0x400>;
260 clocks = <&rcc SYSCFG> 1232 clocks = <&rcc SYSCFG>;
261 }; 1233 };
262 1234
>> 1235 lptimer2: timer@50021000 {
>> 1236 #address-cells = <1>;
>> 1237 #size-cells = <0>;
>> 1238 compatible = "st,stm32-lptimer";
>> 1239 reg = <0x50021000 0x400>;
>> 1240 interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
>> 1241 clocks = <&rcc LPTIM2_K>;
>> 1242 clock-names = "mux";
>> 1243 wakeup-source;
>> 1244 status = "disabled";
>> 1245
>> 1246 pwm {
>> 1247 compatible = "st,stm32-pwm-lp";
>> 1248 #pwm-cells = <3>;
>> 1249 status = "disabled";
>> 1250 };
>> 1251
>> 1252 trigger@1 {
>> 1253 compatible = "st,stm32-lptimer-trigger";
>> 1254 reg = <1>;
>> 1255 status = "disabled";
>> 1256 };
>> 1257
>> 1258 counter {
>> 1259 compatible = "st,stm32-lptimer-counter";
>> 1260 status = "disabled";
>> 1261 };
>> 1262 };
>> 1263
>> 1264 lptimer3: timer@50022000 {
>> 1265 #address-cells = <1>;
>> 1266 #size-cells = <0>;
>> 1267 compatible = "st,stm32-lptimer";
>> 1268 reg = <0x50022000 0x400>;
>> 1269 interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
>> 1270 clocks = <&rcc LPTIM3_K>;
>> 1271 clock-names = "mux";
>> 1272 wakeup-source;
>> 1273 status = "disabled";
>> 1274
>> 1275 pwm {
>> 1276 compatible = "st,stm32-pwm-lp";
>> 1277 #pwm-cells = <3>;
>> 1278 status = "disabled";
>> 1279 };
>> 1280
>> 1281 trigger@2 {
>> 1282 compatible = "st,stm32-lptimer-trigger";
>> 1283 reg = <2>;
>> 1284 status = "disabled";
>> 1285 };
>> 1286 };
>> 1287
>> 1288 lptimer4: timer@50023000 {
>> 1289 compatible = "st,stm32-lptimer";
>> 1290 reg = <0x50023000 0x400>;
>> 1291 interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
>> 1292 clocks = <&rcc LPTIM4_K>;
>> 1293 clock-names = "mux";
>> 1294 wakeup-source;
>> 1295 status = "disabled";
>> 1296
>> 1297 pwm {
>> 1298 compatible = "st,stm32-pwm-lp";
>> 1299 #pwm-cells = <3>;
>> 1300 status = "disabled";
>> 1301 };
>> 1302 };
>> 1303
>> 1304 lptimer5: timer@50024000 {
>> 1305 compatible = "st,stm32-lptimer";
>> 1306 reg = <0x50024000 0x400>;
>> 1307 interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
>> 1308 clocks = <&rcc LPTIM5_K>;
>> 1309 clock-names = "mux";
>> 1310 wakeup-source;
>> 1311 status = "disabled";
>> 1312
>> 1313 pwm {
>> 1314 compatible = "st,stm32-pwm-lp";
>> 1315 #pwm-cells = <3>;
>> 1316 status = "disabled";
>> 1317 };
>> 1318 };
>> 1319
>> 1320 vrefbuf: vrefbuf@50025000 {
>> 1321 compatible = "st,stm32-vrefbuf";
>> 1322 reg = <0x50025000 0x8>;
>> 1323 regulator-min-microvolt = <1500000>;
>> 1324 regulator-max-microvolt = <2500000>;
>> 1325 clocks = <&rcc VREF>;
>> 1326 status = "disabled";
>> 1327 };
>> 1328
>> 1329 sai4: sai@50027000 {
>> 1330 compatible = "st,stm32h7-sai";
>> 1331 #address-cells = <1>;
>> 1332 #size-cells = <1>;
>> 1333 ranges = <0 0x50027000 0x400>;
>> 1334 reg = <0x50027000 0x4>, <0x500273f0 0x10>;
>> 1335 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
>> 1336 resets = <&rcc SAI4_R>;
>> 1337 status = "disabled";
>> 1338
>> 1339 sai4a: audio-controller@50027004 {
>> 1340 #sound-dai-cells = <0>;
>> 1341 compatible = "st,stm32-sai-sub-a";
>> 1342 reg = <0x04 0x20>;
>> 1343 clocks = <&rcc SAI4_K>;
>> 1344 clock-names = "sai_ck";
>> 1345 dmas = <&dmamux1 99 0x400 0x01>;
>> 1346 status = "disabled";
>> 1347 };
>> 1348
>> 1349 sai4b: audio-controller@50027024 {
>> 1350 #sound-dai-cells = <0>;
>> 1351 compatible = "st,stm32-sai-sub-b";
>> 1352 reg = <0x24 0x20>;
>> 1353 clocks = <&rcc SAI4_K>;
>> 1354 clock-names = "sai_ck";
>> 1355 dmas = <&dmamux1 100 0x400 0x01>;
>> 1356 status = "disabled";
>> 1357 };
>> 1358 };
>> 1359
263 dts: thermal@50028000 { 1360 dts: thermal@50028000 {
264 compatible = "st,stm32 1361 compatible = "st,stm32-thermal";
265 reg = <0x50028000 0x10 1362 reg = <0x50028000 0x100>;
266 interrupts = <GIC_SPI 1363 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&rcc TMPSENS 1364 clocks = <&rcc TMPSENS>;
268 clock-names = "pclk"; 1365 clock-names = "pclk";
269 #thermal-sensor-cells 1366 #thermal-sensor-cells = <0>;
270 status = "disabled"; 1367 status = "disabled";
271 }; 1368 };
272 1369
>> 1370 hash1: hash@54002000 {
>> 1371 compatible = "st,stm32f756-hash";
>> 1372 reg = <0x54002000 0x400>;
>> 1373 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>> 1374 clocks = <&rcc HASH1>;
>> 1375 resets = <&rcc HASH1_R>;
>> 1376 dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>;
>> 1377 dma-names = "in";
>> 1378 dma-maxburst = <2>;
>> 1379 status = "disabled";
>> 1380 };
>> 1381
>> 1382 rng1: rng@54003000 {
>> 1383 compatible = "st,stm32-rng";
>> 1384 reg = <0x54003000 0x400>;
>> 1385 clocks = <&rcc RNG1_K>;
>> 1386 resets = <&rcc RNG1_R>;
>> 1387 status = "disabled";
>> 1388 };
>> 1389
273 mdma1: dma-controller@58000000 1390 mdma1: dma-controller@58000000 {
274 compatible = "st,stm32 1391 compatible = "st,stm32h7-mdma";
275 reg = <0x58000000 0x10 1392 reg = <0x58000000 0x1000>;
276 interrupts = <GIC_SPI 1393 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&rcc MDMA>; 1394 clocks = <&rcc MDMA>;
278 resets = <&rcc MDMA_R> 1395 resets = <&rcc MDMA_R>;
279 #dma-cells = <5>; 1396 #dma-cells = <5>;
280 dma-channels = <32>; 1397 dma-channels = <32>;
281 dma-requests = <48>; 1398 dma-requests = <48>;
282 }; 1399 };
283 1400
>> 1401 fmc: memory-controller@58002000 {
>> 1402 #address-cells = <2>;
>> 1403 #size-cells = <1>;
>> 1404 compatible = "st,stm32mp1-fmc2-ebi";
>> 1405 reg = <0x58002000 0x1000>;
>> 1406 clocks = <&rcc FMC_K>;
>> 1407 resets = <&rcc FMC_R>;
>> 1408 status = "disabled";
>> 1409
>> 1410 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
>> 1411 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
>> 1412 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
>> 1413 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
>> 1414 <4 0 0x80000000 0x10000000>; /* NAND */
>> 1415
>> 1416 nand-controller@4,0 {
>> 1417 #address-cells = <1>;
>> 1418 #size-cells = <0>;
>> 1419 compatible = "st,stm32mp1-fmc2-nfc";
>> 1420 reg = <4 0x00000000 0x1000>,
>> 1421 <4 0x08010000 0x1000>,
>> 1422 <4 0x08020000 0x1000>,
>> 1423 <4 0x01000000 0x1000>,
>> 1424 <4 0x09010000 0x1000>,
>> 1425 <4 0x09020000 0x1000>;
>> 1426 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
>> 1427 dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
>> 1428 <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
>> 1429 <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
>> 1430 dma-names = "tx", "rx", "ecc";
>> 1431 status = "disabled";
>> 1432 };
>> 1433 };
>> 1434
>> 1435 qspi: spi@58003000 {
>> 1436 compatible = "st,stm32f469-qspi";
>> 1437 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
>> 1438 reg-names = "qspi", "qspi_mm";
>> 1439 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
>> 1440 dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>,
>> 1441 <&mdma1 22 0x2 0x10100008 0x0 0x0>;
>> 1442 dma-names = "tx", "rx";
>> 1443 clocks = <&rcc QSPI_K>;
>> 1444 resets = <&rcc QSPI_R>;
>> 1445 #address-cells = <1>;
>> 1446 #size-cells = <0>;
>> 1447 status = "disabled";
>> 1448 };
>> 1449
284 sdmmc1: mmc@58005000 { 1450 sdmmc1: mmc@58005000 {
285 compatible = "st,stm32 1451 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
286 arm,primecell-periphid 1452 arm,primecell-periphid = <0x00253180>;
287 reg = <0x58005000 0x10 1453 reg = <0x58005000 0x1000>;
288 interrupts = <GIC_SPI 1454 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&rcc SDMMC1_ 1455 clocks = <&rcc SDMMC1_K>;
290 clock-names = "apb_pcl 1456 clock-names = "apb_pclk";
291 resets = <&rcc SDMMC1_ 1457 resets = <&rcc SDMMC1_R>;
292 cap-sd-highspeed; 1458 cap-sd-highspeed;
293 cap-mmc-highspeed; 1459 cap-mmc-highspeed;
294 max-frequency = <12000 1460 max-frequency = <120000000>;
295 status = "disabled"; 1461 status = "disabled";
296 }; 1462 };
297 1463
298 sdmmc2: mmc@58007000 { 1464 sdmmc2: mmc@58007000 {
299 compatible = "st,stm32 1465 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
300 arm,primecell-periphid 1466 arm,primecell-periphid = <0x00253180>;
301 reg = <0x58007000 0x10 1467 reg = <0x58007000 0x1000>;
302 interrupts = <GIC_SPI 1468 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
303 clocks = <&rcc SDMMC2_ 1469 clocks = <&rcc SDMMC2_K>;
304 clock-names = "apb_pcl 1470 clock-names = "apb_pclk";
305 resets = <&rcc SDMMC2_ 1471 resets = <&rcc SDMMC2_R>;
306 cap-sd-highspeed; 1472 cap-sd-highspeed;
307 cap-mmc-highspeed; 1473 cap-mmc-highspeed;
308 max-frequency = <12000 1474 max-frequency = <120000000>;
309 status = "disabled"; 1475 status = "disabled";
310 }; 1476 };
311 1477
312 crc1: crc@58009000 { 1478 crc1: crc@58009000 {
313 compatible = "st,stm32 1479 compatible = "st,stm32f7-crc";
314 reg = <0x58009000 0x40 1480 reg = <0x58009000 0x400>;
315 clocks = <&rcc CRC1>; 1481 clocks = <&rcc CRC1>;
316 status = "disabled"; 1482 status = "disabled";
317 }; 1483 };
318 1484
>> 1485 ethernet0: ethernet@5800a000 {
>> 1486 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
>> 1487 reg = <0x5800a000 0x2000>;
>> 1488 reg-names = "stmmaceth";
>> 1489 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
>> 1490 interrupt-names = "macirq";
>> 1491 clock-names = "stmmaceth",
>> 1492 "mac-clk-tx",
>> 1493 "mac-clk-rx",
>> 1494 "eth-ck",
>> 1495 "ptp_ref",
>> 1496 "ethstp";
>> 1497 clocks = <&rcc ETHMAC>,
>> 1498 <&rcc ETHTX>,
>> 1499 <&rcc ETHRX>,
>> 1500 <&rcc ETHCK_K>,
>> 1501 <&rcc ETHPTP_K>,
>> 1502 <&rcc ETHSTP>;
>> 1503 st,syscon = <&syscfg 0x4>;
>> 1504 snps,mixed-burst;
>> 1505 snps,pbl = <2>;
>> 1506 snps,en-tx-lpi-clockgating;
>> 1507 snps,axi-config = <&stmmac_axi_config_0>;
>> 1508 snps,tso;
>> 1509 status = "disabled";
>> 1510
>> 1511 stmmac_axi_config_0: stmmac-axi-config {
>> 1512 snps,wr_osr_lmt = <0x7>;
>> 1513 snps,rd_osr_lmt = <0x7>;
>> 1514 snps,blen = <0 0 0 0 16 8 4>;
>> 1515 };
>> 1516 };
>> 1517
319 usbh_ohci: usb@5800c000 { 1518 usbh_ohci: usb@5800c000 {
320 compatible = "generic- 1519 compatible = "generic-ohci";
321 reg = <0x5800c000 0x10 1520 reg = <0x5800c000 0x1000>;
322 clocks = <&usbphyc>, < 1521 clocks = <&usbphyc>, <&rcc USBH>;
323 resets = <&rcc USBH_R> 1522 resets = <&rcc USBH_R>;
324 interrupts = <GIC_SPI 1523 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
325 phys = <&usbphyc_port0 <<
326 phy-names = "usb"; <<
327 status = "disabled"; 1524 status = "disabled";
328 }; 1525 };
329 1526
330 usbh_ehci: usb@5800d000 { 1527 usbh_ehci: usb@5800d000 {
331 compatible = "generic- 1528 compatible = "generic-ehci";
332 reg = <0x5800d000 0x10 1529 reg = <0x5800d000 0x1000>;
333 clocks = <&usbphyc>, < 1530 clocks = <&usbphyc>, <&rcc USBH>;
334 resets = <&rcc USBH_R> 1531 resets = <&rcc USBH_R>;
335 interrupts = <GIC_SPI 1532 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
336 companion = <&usbh_ohc 1533 companion = <&usbh_ohci>;
337 phys = <&usbphyc_port0 <<
338 phy-names = "usb"; <<
339 status = "disabled"; 1534 status = "disabled";
340 }; 1535 };
341 1536
342 ltdc: display-controller@5a001 1537 ltdc: display-controller@5a001000 {
343 compatible = "st,stm32 1538 compatible = "st,stm32-ltdc";
344 reg = <0x5a001000 0x40 1539 reg = <0x5a001000 0x400>;
345 interrupts = <GIC_SPI 1540 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
346 <GIC_SPI 1541 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&rcc LTDC_PX 1542 clocks = <&rcc LTDC_PX>;
348 clock-names = "lcd"; 1543 clock-names = "lcd";
349 resets = <&rcc LTDC_R> 1544 resets = <&rcc LTDC_R>;
350 status = "disabled"; 1545 status = "disabled";
351 }; 1546 };
352 1547
353 iwdg2: watchdog@5a002000 { 1548 iwdg2: watchdog@5a002000 {
354 compatible = "st,stm32 1549 compatible = "st,stm32mp1-iwdg";
355 reg = <0x5a002000 0x40 1550 reg = <0x5a002000 0x400>;
356 clocks = <&rcc IWDG2>, 1551 clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
357 clock-names = "pclk", 1552 clock-names = "pclk", "lsi";
358 status = "disabled"; 1553 status = "disabled";
359 }; 1554 };
360 1555
361 usbphyc: usbphyc@5a006000 { 1556 usbphyc: usbphyc@5a006000 {
362 #address-cells = <1>; 1557 #address-cells = <1>;
363 #size-cells = <0>; 1558 #size-cells = <0>;
364 #clock-cells = <0>; 1559 #clock-cells = <0>;
365 compatible = "st,stm32 1560 compatible = "st,stm32mp1-usbphyc";
366 reg = <0x5a006000 0x10 1561 reg = <0x5a006000 0x1000>;
367 clocks = <&rcc USBPHY_ 1562 clocks = <&rcc USBPHY_K>;
368 resets = <&rcc USBPHY_ 1563 resets = <&rcc USBPHY_R>;
369 vdda1v1-supply = <® 1564 vdda1v1-supply = <®11>;
370 vdda1v8-supply = <® 1565 vdda1v8-supply = <®18>;
371 status = "disabled"; 1566 status = "disabled";
372 1567
373 usbphyc_port0: usb-phy 1568 usbphyc_port0: usb-phy@0 {
374 #phy-cells = < 1569 #phy-cells = <0>;
375 reg = <0>; 1570 reg = <0>;
376 }; 1571 };
377 1572
378 usbphyc_port1: usb-phy 1573 usbphyc_port1: usb-phy@1 {
379 #phy-cells = < 1574 #phy-cells = <1>;
380 reg = <1>; 1575 reg = <1>;
381 }; 1576 };
382 }; 1577 };
383 1578
>> 1579 usart1: serial@5c000000 {
>> 1580 compatible = "st,stm32h7-uart";
>> 1581 reg = <0x5c000000 0x400>;
>> 1582 interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
>> 1583 clocks = <&rcc USART1_K>;
>> 1584 wakeup-source;
>> 1585 status = "disabled";
>> 1586 };
>> 1587
>> 1588 spi6: spi@5c001000 {
>> 1589 #address-cells = <1>;
>> 1590 #size-cells = <0>;
>> 1591 compatible = "st,stm32h7-spi";
>> 1592 reg = <0x5c001000 0x400>;
>> 1593 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>> 1594 clocks = <&rcc SPI6_K>;
>> 1595 resets = <&rcc SPI6_R>;
>> 1596 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
>> 1597 <&mdma1 35 0x0 0x40002 0x0 0x0>;
>> 1598 dma-names = "rx", "tx";
>> 1599 status = "disabled";
>> 1600 };
>> 1601
>> 1602 i2c4: i2c@5c002000 {
>> 1603 compatible = "st,stm32mp15-i2c";
>> 1604 reg = <0x5c002000 0x400>;
>> 1605 interrupt-names = "event", "error";
>> 1606 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
>> 1607 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>> 1608 clocks = <&rcc I2C4_K>;
>> 1609 resets = <&rcc I2C4_R>;
>> 1610 #address-cells = <1>;
>> 1611 #size-cells = <0>;
>> 1612 st,syscfg-fmp = <&syscfg 0x4 0x8>;
>> 1613 wakeup-source;
>> 1614 i2c-analog-filter;
>> 1615 status = "disabled";
>> 1616 };
>> 1617
384 rtc: rtc@5c004000 { 1618 rtc: rtc@5c004000 {
385 compatible = "st,stm32 1619 compatible = "st,stm32mp1-rtc";
386 reg = <0x5c004000 0x40 1620 reg = <0x5c004000 0x400>;
387 clocks = <&rcc RTCAPB> 1621 clocks = <&rcc RTCAPB>, <&rcc RTC>;
388 clock-names = "pclk", 1622 clock-names = "pclk", "rtc_ck";
389 interrupts-extended = 1623 interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
390 status = "disabled"; 1624 status = "disabled";
391 }; 1625 };
392 1626
393 bsec: efuse@5c005000 { 1627 bsec: efuse@5c005000 {
394 compatible = "st,stm32 1628 compatible = "st,stm32mp15-bsec";
395 reg = <0x5c005000 0x40 1629 reg = <0x5c005000 0x400>;
396 #address-cells = <1>; 1630 #address-cells = <1>;
397 #size-cells = <1>; 1631 #size-cells = <1>;
398 part_number_otp: part- 1632 part_number_otp: part-number-otp@4 {
399 reg = <0x4 0x1 1633 reg = <0x4 0x1>;
400 }; 1634 };
401 vrefint: vrefin-cal@52 1635 vrefint: vrefin-cal@52 {
402 reg = <0x52 0x 1636 reg = <0x52 0x2>;
403 }; 1637 };
404 ts_cal1: calib@5c { 1638 ts_cal1: calib@5c {
405 reg = <0x5c 0x 1639 reg = <0x5c 0x2>;
406 }; 1640 };
407 ts_cal2: calib@5e { 1641 ts_cal2: calib@5e {
408 reg = <0x5e 0x 1642 reg = <0x5e 0x2>;
409 }; 1643 };
410 }; 1644 };
411 1645
412 etzpc: bus@5c007000 { !! 1646 i2c6: i2c@5c009000 {
413 compatible = "st,stm32 !! 1647 compatible = "st,stm32mp15-i2c";
414 reg = <0x5c007000 0x40 !! 1648 reg = <0x5c009000 0x400>;
>> 1649 interrupt-names = "event", "error";
>> 1650 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
>> 1651 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
>> 1652 clocks = <&rcc I2C6_K>;
>> 1653 resets = <&rcc I2C6_R>;
415 #address-cells = <1>; 1654 #address-cells = <1>;
416 #size-cells = <1>; !! 1655 #size-cells = <0>;
417 #access-controller-cel !! 1656 st,syscfg-fmp = <&syscfg 0x4 0x20>;
418 ranges; !! 1657 wakeup-source;
419 !! 1658 i2c-analog-filter;
420 timers2: timer@4000000 !! 1659 status = "disabled";
421 #address-cells <<
422 #size-cells = <<
423 compatible = " <<
424 reg = <0x40000 <<
425 interrupts = < <<
426 interrupt-name <<
427 clocks = <&rcc <<
428 clock-names = <<
429 dmas = <&dmamu <<
430 <&dmamu <<
431 <&dmamu <<
432 <&dmamu <<
433 <&dmamu <<
434 dma-names = "c <<
435 access-control <<
436 status = "disa <<
437 <<
438 pwm { <<
439 compat <<
440 #pwm-c <<
441 status <<
442 }; <<
443 <<
444 timer@1 { <<
445 compat <<
446 reg = <<
447 status <<
448 }; <<
449 <<
450 counter { <<
451 compat <<
452 status <<
453 }; <<
454 }; <<
455 <<
456 timers3: timer@4000100 <<
457 #address-cells <<
458 #size-cells = <<
459 compatible = " <<
460 reg = <0x40001 <<
461 interrupts = < <<
462 interrupt-name <<
463 clocks = <&rcc <<
464 clock-names = <<
465 dmas = <&dmamu <<
466 <&dmamu <<
467 <&dmamu <<
468 <&dmamu <<
469 <&dmamu <<
470 <&dmamu <<
471 dma-names = "c <<
472 access-control <<
473 status = "disa <<
474 <<
475 pwm { <<
476 compat <<
477 #pwm-c <<
478 status <<
479 }; <<
480 <<
481 timer@2 { <<
482 compat <<
483 reg = <<
484 status <<
485 }; <<
486 <<
487 counter { <<
488 compat <<
489 status <<
490 }; <<
491 }; <<
492 <<
493 timers4: timer@4000200 <<
494 #address-cells <<
495 #size-cells = <<
496 compatible = " <<
497 reg = <0x40002 <<
498 interrupts = < <<
499 interrupt-name <<
500 clocks = <&rcc <<
501 clock-names = <<
502 dmas = <&dmamu <<
503 <&dmamu <<
504 <&dmamu <<
505 <&dmamu <<
506 dma-names = "c <<
507 access-control <<
508 status = "disa <<
509 <<
510 pwm { <<
511 compat <<
512 #pwm-c <<
513 status <<
514 }; <<
515 <<
516 timer@3 { <<
517 compat <<
518 reg = <<
519 status <<
520 }; <<
521 <<
522 counter { <<
523 compat <<
524 status <<
525 }; <<
526 }; <<
527 <<
528 timers5: timer@4000300 <<
529 #address-cells <<
530 #size-cells = <<
531 compatible = " <<
532 reg = <0x40003 <<
533 interrupts = < <<
534 interrupt-name <<
535 clocks = <&rcc <<
536 clock-names = <<
537 dmas = <&dmamu <<
538 <&dmamu <<
539 <&dmamu <<
540 <&dmamu <<
541 <&dmamu <<
542 <&dmamu <<
543 dma-names = "c <<
544 access-control <<
545 status = "disa <<
546 <<
547 pwm { <<
548 compat <<
549 #pwm-c <<
550 status <<
551 }; <<
552 <<
553 timer@4 { <<
554 compat <<
555 reg = <<
556 status <<
557 }; <<
558 <<
559 counter { <<
560 compat <<
561 status <<
562 }; <<
563 }; <<
564 <<
565 timers6: timer@4000400 <<
566 #address-cells <<
567 #size-cells = <<
568 compatible = " <<
569 reg = <0x40004 <<
570 interrupts = < <<
571 interrupt-name <<
572 clocks = <&rcc <<
573 clock-names = <<
574 dmas = <&dmamu <<
575 dma-names = "u <<
576 access-control <<
577 status = "disa <<
578 <<
579 timer@5 { <<
580 compat <<
581 reg = <<
582 status <<
583 }; <<
584 }; <<
585 <<
586 timers7: timer@4000500 <<
587 #address-cells <<
588 #size-cells = <<
589 compatible = " <<
590 reg = <0x40005 <<
591 interrupts = < <<
592 interrupt-name <<
593 clocks = <&rcc <<
594 clock-names = <<
595 dmas = <&dmamu <<
596 dma-names = "u <<
597 access-control <<
598 status = "disa <<
599 <<
600 timer@6 { <<
601 compat <<
602 reg = <<
603 status <<
604 }; <<
605 }; <<
606 <<
607 timers12: timer@400060 <<
608 #address-cells <<
609 #size-cells = <<
610 compatible = " <<
611 reg = <0x40006 <<
612 interrupts = < <<
613 interrupt-name <<
614 clocks = <&rcc <<
615 clock-names = <<
616 access-control <<
617 status = "disa <<
618 <<
619 pwm { <<
620 compat <<
621 #pwm-c <<
622 status <<
623 }; <<
624 <<
625 timer@11 { <<
626 compat <<
627 reg = <<
628 status <<
629 }; <<
630 }; <<
631 <<
632 timers13: timer@400070 <<
633 #address-cells <<
634 #size-cells = <<
635 compatible = " <<
636 reg = <0x40007 <<
637 interrupts = < <<
638 interrupt-name <<
639 clocks = <&rcc <<
640 clock-names = <<
641 access-control <<
642 status = "disa <<
643 <<
644 pwm { <<
645 compat <<
646 #pwm-c <<
647 status <<
648 }; <<
649 <<
650 timer@12 { <<
651 compat <<
652 reg = <<
653 status <<
654 }; <<
655 }; <<
656 <<
657 timers14: timer@400080 <<
658 #address-cells <<
659 #size-cells = <<
660 compatible = " <<
661 reg = <0x40008 <<
662 interrupts = < <<
663 interrupt-name <<
664 clocks = <&rcc <<
665 clock-names = <<
666 access-control <<
667 status = "disa <<
668 <<
669 pwm { <<
670 compat <<
671 #pwm-c <<
672 status <<
673 }; <<
674 <<
675 timer@13 { <<
676 compat <<
677 reg = <<
678 status <<
679 }; <<
680 }; <<
681 <<
682 lptimer1: timer@400090 <<
683 #address-cells <<
684 #size-cells = <<
685 compatible = " <<
686 reg = <0x40009 <<
687 interrupts-ext <<
688 clocks = <&rcc <<
689 clock-names = <<
690 wakeup-source; <<
691 access-control <<
692 status = "disa <<
693 <<
694 pwm { <<
695 compat <<
696 #pwm-c <<
697 status <<
698 }; <<
699 <<
700 trigger@0 { <<
701 compat <<
702 reg = <<
703 status <<
704 }; <<
705 <<
706 counter { <<
707 compat <<
708 status <<
709 }; <<
710 }; <<
711 <<
712 i2s2: audio-controller <<
713 compatible = " <<
714 #sound-dai-cel <<
715 reg = <0x4000b <<
716 interrupts = < <<
717 dmas = <&dmamu <<
718 <&dmamu <<
719 dma-names = "r <<
720 access-control <<
721 status = "disa <<
722 }; <<
723 <<
724 spi2: spi@4000b000 { <<
725 #address-cells <<
726 #size-cells = <<
727 compatible = " <<
728 reg = <0x4000b <<
729 interrupts = < <<
730 clocks = <&rcc <<
731 resets = <&rcc <<
732 dmas = <&dmamu <<
733 <&dmamu <<
734 dma-names = "r <<
735 access-control <<
736 status = "disa <<
737 }; <<
738 <<
739 i2s3: audio-controller <<
740 compatible = " <<
741 #sound-dai-cel <<
742 reg = <0x4000c <<
743 interrupts = < <<
744 dmas = <&dmamu <<
745 <&dmamu <<
746 dma-names = "r <<
747 access-control <<
748 status = "disa <<
749 }; <<
750 <<
751 spi3: spi@4000c000 { <<
752 #address-cells <<
753 #size-cells = <<
754 compatible = " <<
755 reg = <0x4000c <<
756 interrupts = < <<
757 clocks = <&rcc <<
758 resets = <&rcc <<
759 dmas = <&dmamu <<
760 <&dmamu <<
761 dma-names = "r <<
762 access-control <<
763 status = "disa <<
764 }; <<
765 <<
766 spdifrx: audio-control <<
767 compatible = " <<
768 #sound-dai-cel <<
769 reg = <0x4000d <<
770 clocks = <&rcc <<
771 clock-names = <<
772 interrupts = < <<
773 dmas = <&dmamu <<
774 <&dmamu <<
775 dma-names = "r <<
776 access-control <<
777 status = "disa <<
778 }; <<
779 <<
780 usart2: serial@4000e00 <<
781 compatible = " <<
782 reg = <0x4000e <<
783 interrupts-ext <<
784 clocks = <&rcc <<
785 wakeup-source; <<
786 dmas = <&dmamu <<
787 <&dmamu <<
788 dma-names = "r <<
789 access-control <<
790 status = "disa <<
791 }; <<
792 <<
793 usart3: serial@4000f00 <<
794 compatible = " <<
795 reg = <0x4000f <<
796 interrupts-ext <<
797 clocks = <&rcc <<
798 wakeup-source; <<
799 dmas = <&dmamu <<
800 <&dmamu <<
801 dma-names = "r <<
802 access-control <<
803 status = "disa <<
804 }; <<
805 <<
806 uart4: serial@40010000 <<
807 compatible = " <<
808 reg = <0x40010 <<
809 interrupts-ext <<
810 clocks = <&rcc <<
811 wakeup-source; <<
812 dmas = <&dmamu <<
813 <&dmamu <<
814 dma-names = "r <<
815 access-control <<
816 status = "disa <<
817 }; <<
818 <<
819 uart5: serial@40011000 <<
820 compatible = " <<
821 reg = <0x40011 <<
822 interrupts-ext <<
823 clocks = <&rcc <<
824 wakeup-source; <<
825 dmas = <&dmamu <<
826 <&dmamu <<
827 dma-names = "r <<
828 access-control <<
829 status = "disa <<
830 }; <<
831 <<
832 i2c1: i2c@40012000 { <<
833 compatible = " <<
834 reg = <0x40012 <<
835 interrupt-name <<
836 interrupts = < <<
837 < <<
838 clocks = <&rcc <<
839 resets = <&rcc <<
840 #address-cells <<
841 #size-cells = <<
842 st,syscfg-fmp <<
843 wakeup-source; <<
844 i2c-analog-fil <<
845 access-control <<
846 status = "disa <<
847 }; <<
848 <<
849 i2c2: i2c@40013000 { <<
850 compatible = " <<
851 reg = <0x40013 <<
852 interrupt-name <<
853 interrupts = < <<
854 < <<
855 clocks = <&rcc <<
856 resets = <&rcc <<
857 #address-cells <<
858 #size-cells = <<
859 st,syscfg-fmp <<
860 wakeup-source; <<
861 i2c-analog-fil <<
862 access-control <<
863 status = "disa <<
864 }; <<
865 <<
866 i2c3: i2c@40014000 { <<
867 compatible = " <<
868 reg = <0x40014 <<
869 interrupt-name <<
870 interrupts = < <<
871 < <<
872 clocks = <&rcc <<
873 resets = <&rcc <<
874 #address-cells <<
875 #size-cells = <<
876 st,syscfg-fmp <<
877 wakeup-source; <<
878 i2c-analog-fil <<
879 access-control <<
880 status = "disa <<
881 }; <<
882 <<
883 i2c5: i2c@40015000 { <<
884 compatible = " <<
885 reg = <0x40015 <<
886 interrupt-name <<
887 interrupts = < <<
888 < <<
889 clocks = <&rcc <<
890 resets = <&rcc <<
891 #address-cells <<
892 #size-cells = <<
893 st,syscfg-fmp <<
894 wakeup-source; <<
895 i2c-analog-fil <<
896 access-control <<
897 status = "disa <<
898 }; <<
899 <<
900 cec: cec@40016000 { <<
901 compatible = " <<
902 reg = <0x40016 <<
903 interrupts = < <<
904 clocks = <&rcc <<
905 clock-names = <<
906 access-control <<
907 status = "disa <<
908 }; <<
909 <<
910 dac: dac@40017000 { <<
911 compatible = " <<
912 reg = <0x40017 <<
913 clocks = <&rcc <<
914 clock-names = <<
915 #address-cells <<
916 #size-cells = <<
917 access-control <<
918 status = "disa <<
919 <<
920 dac1: dac@1 { <<
921 compat <<
922 #io-ch <<
923 reg = <<
924 status <<
925 }; <<
926 <<
927 dac2: dac@2 { <<
928 compat <<
929 #io-ch <<
930 reg = <<
931 status <<
932 }; <<
933 }; <<
934 <<
935 uart7: serial@40018000 <<
936 compatible = " <<
937 reg = <0x40018 <<
938 interrupts-ext <<
939 clocks = <&rcc <<
940 wakeup-source; <<
941 dmas = <&dmamu <<
942 <&dmamu <<
943 dma-names = "r <<
944 access-control <<
945 status = "disa <<
946 }; <<
947 <<
948 uart8: serial@40019000 <<
949 compatible = " <<
950 reg = <0x40019 <<
951 interrupts-ext <<
952 clocks = <&rcc <<
953 wakeup-source; <<
954 dmas = <&dmamu <<
955 <&dmamu <<
956 dma-names = "r <<
957 access-control <<
958 status = "disa <<
959 }; <<
960 <<
961 timers1: timer@4400000 <<
962 #address-cells <<
963 #size-cells = <<
964 compatible = " <<
965 reg = <0x44000 <<
966 interrupts = < <<
967 < <<
968 < <<
969 < <<
970 interrupt-name <<
971 clocks = <&rcc <<
972 clock-names = <<
973 dmas = <&dmamu <<
974 <&dmamu <<
975 <&dmamu <<
976 <&dmamu <<
977 <&dmamu <<
978 <&dmamu <<
979 <&dmamu <<
980 dma-names = "c <<
981 "u <<
982 access-control <<
983 status = "disa <<
984 <<
985 pwm { <<
986 compat <<
987 #pwm-c <<
988 status <<
989 }; <<
990 <<
991 timer@0 { <<
992 compat <<
993 reg = <<
994 status <<
995 }; <<
996 <<
997 counter { <<
998 compat <<
999 status <<
1000 }; <<
1001 }; <<
1002 <<
1003 timers8: timer@440010 <<
1004 #address-cell <<
1005 #size-cells = <<
1006 compatible = <<
1007 reg = <0x4400 <<
1008 interrupts = <<
1009 <<
1010 <<
1011 <<
1012 interrupt-nam <<
1013 clocks = <&rc <<
1014 clock-names = <<
1015 dmas = <&dmam <<
1016 <&dmam <<
1017 <&dmam <<
1018 <&dmam <<
1019 <&dmam <<
1020 <&dmam <<
1021 <&dmam <<
1022 dma-names = " <<
1023 " <<
1024 access-contro <<
1025 status = "dis <<
1026 <<
1027 pwm { <<
1028 compa <<
1029 #pwm- <<
1030 statu <<
1031 }; <<
1032 <<
1033 timer@7 { <<
1034 compa <<
1035 reg = <<
1036 statu <<
1037 }; <<
1038 <<
1039 counter { <<
1040 compa <<
1041 statu <<
1042 }; <<
1043 }; <<
1044 <<
1045 usart6: serial@440030 <<
1046 compatible = <<
1047 reg = <0x4400 <<
1048 interrupts-ex <<
1049 clocks = <&rc <<
1050 wakeup-source <<
1051 dmas = <&dmam <<
1052 <&dmamux1 72 <<
1053 dma-names = " <<
1054 access-contro <<
1055 status = "dis <<
1056 }; <<
1057 <<
1058 i2s1: audio-controlle <<
1059 compatible = <<
1060 #sound-dai-ce <<
1061 reg = <0x4400 <<
1062 interrupts = <<
1063 dmas = <&dmam <<
1064 <&dmamux1 38 <<
1065 dma-names = " <<
1066 access-contro <<
1067 status = "dis <<
1068 }; <<
1069 <<
1070 spi1: spi@44004000 { <<
1071 #address-cell <<
1072 #size-cells = <<
1073 compatible = <<
1074 reg = <0x4400 <<
1075 interrupts = <<
1076 clocks = <&rc <<
1077 resets = <&rc <<
1078 dmas = <&dmam <<
1079 <&dmamux1 38 <<
1080 dma-names = " <<
1081 access-contro <<
1082 status = "dis <<
1083 }; <<
1084 <<
1085 spi4: spi@44005000 { <<
1086 #address-cell <<
1087 #size-cells = <<
1088 compatible = <<
1089 reg = <0x4400 <<
1090 interrupts = <<
1091 clocks = <&rc <<
1092 resets = <&rc <<
1093 dmas = <&dmam <<
1094 <&dmamux1 84 <<
1095 dma-names = " <<
1096 access-contro <<
1097 status = "dis <<
1098 }; <<
1099 <<
1100 timers15: timer@44006 <<
1101 #address-cell <<
1102 #size-cells = <<
1103 compatible = <<
1104 reg = <0x4400 <<
1105 interrupts = <<
1106 interrupt-nam <<
1107 clocks = <&rc <<
1108 clock-names = <<
1109 dmas = <&dmam <<
1110 <&dmam <<
1111 <&dmam <<
1112 <&dmam <<
1113 dma-names = " <<
1114 access-contro <<
1115 status = "dis <<
1116 <<
1117 pwm { <<
1118 compa <<
1119 #pwm- <<
1120 statu <<
1121 }; <<
1122 <<
1123 timer@14 { <<
1124 compa <<
1125 reg = <<
1126 statu <<
1127 }; <<
1128 }; <<
1129 <<
1130 timers16: timer@44007 <<
1131 #address-cell <<
1132 #size-cells = <<
1133 compatible = <<
1134 reg = <0x4400 <<
1135 interrupts = <<
1136 interrupt-nam <<
1137 clocks = <&rc <<
1138 clock-names = <<
1139 dmas = <&dmam <<
1140 <&dmamux1 110 <<
1141 dma-names = " <<
1142 access-contro <<
1143 status = "dis <<
1144 <<
1145 pwm { <<
1146 compa <<
1147 #pwm- <<
1148 statu <<
1149 }; <<
1150 timer@15 { <<
1151 compa <<
1152 reg = <<
1153 statu <<
1154 }; <<
1155 }; <<
1156 <<
1157 timers17: timer@44008 <<
1158 #address-cell <<
1159 #size-cells = <<
1160 compatible = <<
1161 reg = <0x4400 <<
1162 interrupts = <<
1163 interrupt-nam <<
1164 clocks = <&rc <<
1165 clock-names = <<
1166 dmas = <&dmam <<
1167 <&dmamux1 112 <<
1168 dma-names = " <<
1169 access-contro <<
1170 status = "dis <<
1171 <<
1172 pwm { <<
1173 compa <<
1174 #pwm- <<
1175 statu <<
1176 }; <<
1177 <<
1178 timer@16 { <<
1179 compa <<
1180 reg = <<
1181 statu <<
1182 }; <<
1183 }; <<
1184 <<
1185 spi5: spi@44009000 { <<
1186 #address-cell <<
1187 #size-cells = <<
1188 compatible = <<
1189 reg = <0x4400 <<
1190 interrupts = <<
1191 clocks = <&rc <<
1192 resets = <&rc <<
1193 dmas = <&dmam <<
1194 <&dmamux1 86 <<
1195 dma-names = " <<
1196 access-contro <<
1197 status = "dis <<
1198 }; <<
1199 <<
1200 sai1: sai@4400a000 { <<
1201 compatible = <<
1202 #address-cell <<
1203 #size-cells = <<
1204 ranges = <0 0 <<
1205 reg = <0x4400 <<
1206 interrupts = <<
1207 resets = <&rc <<
1208 access-contro <<
1209 status = "dis <<
1210 <<
1211 sai1a: audio- <<
1212 #soun <<
1213 <<
1214 compa <<
1215 reg = <<
1216 clock <<
1217 clock <<
1218 dmas <<
1219 statu <<
1220 }; <<
1221 <<
1222 sai1b: audio- <<
1223 #soun <<
1224 compa <<
1225 reg = <<
1226 clock <<
1227 clock <<
1228 dmas <<
1229 statu <<
1230 }; <<
1231 }; <<
1232 <<
1233 sai2: sai@4400b000 { <<
1234 compatible = <<
1235 #address-cell <<
1236 #size-cells = <<
1237 ranges = <0 0 <<
1238 reg = <0x4400 <<
1239 interrupts = <<
1240 resets = <&rc <<
1241 access-contro <<
1242 status = "dis <<
1243 <<
1244 sai2a: audio- <<
1245 #soun <<
1246 compa <<
1247 reg = <<
1248 clock <<
1249 clock <<
1250 dmas <<
1251 statu <<
1252 }; <<
1253 <<
1254 sai2b: audio- <<
1255 #soun <<
1256 compa <<
1257 reg = <<
1258 clock <<
1259 clock <<
1260 dmas <<
1261 statu <<
1262 }; <<
1263 }; <<
1264 <<
1265 sai3: sai@4400c000 { <<
1266 compatible = <<
1267 #address-cell <<
1268 #size-cells = <<
1269 ranges = <0 0 <<
1270 reg = <0x4400 <<
1271 interrupts = <<
1272 resets = <&rc <<
1273 access-contro <<
1274 status = "dis <<
1275 <<
1276 sai3a: audio- <<
1277 #soun <<
1278 compa <<
1279 reg = <<
1280 clock <<
1281 clock <<
1282 dmas <<
1283 statu <<
1284 }; <<
1285 <<
1286 sai3b: audio- <<
1287 #soun <<
1288 compa <<
1289 reg = <<
1290 clock <<
1291 clock <<
1292 dmas <<
1293 statu <<
1294 }; <<
1295 }; <<
1296 <<
1297 dfsdm: dfsdm@4400d000 <<
1298 compatible = <<
1299 reg = <0x4400 <<
1300 clocks = <&rc <<
1301 clock-names = <<
1302 #address-cell <<
1303 #size-cells = <<
1304 access-contro <<
1305 status = "dis <<
1306 <<
1307 dfsdm0: filte <<
1308 compa <<
1309 #io-c <<
1310 reg = <<
1311 inter <<
1312 dmas <<
1313 dma-n <<
1314 statu <<
1315 }; <<
1316 <<
1317 dfsdm1: filte <<
1318 compa <<
1319 #io-c <<
1320 reg = <<
1321 inter <<
1322 dmas <<
1323 dma-n <<
1324 statu <<
1325 }; <<
1326 <<
1327 dfsdm2: filte <<
1328 compa <<
1329 #io-c <<
1330 reg = <<
1331 inter <<
1332 dmas <<
1333 dma-n <<
1334 statu <<
1335 }; <<
1336 <<
1337 dfsdm3: filte <<
1338 compa <<
1339 #io-c <<
1340 reg = <<
1341 inter <<
1342 dmas <<
1343 dma-n <<
1344 statu <<
1345 }; <<
1346 <<
1347 dfsdm4: filte <<
1348 compa <<
1349 #io-c <<
1350 reg = <<
1351 inter <<
1352 dmas <<
1353 dma-n <<
1354 statu <<
1355 }; <<
1356 <<
1357 dfsdm5: filte <<
1358 compa <<
1359 #io-c <<
1360 reg = <<
1361 inter <<
1362 dmas <<
1363 dma-n <<
1364 statu <<
1365 }; <<
1366 }; <<
1367 <<
1368 dma1: dma-controller@ <<
1369 compatible = <<
1370 reg = <0x4800 <<
1371 interrupts = <<
1372 <<
1373 <<
1374 <<
1375 <<
1376 <<
1377 <<
1378 <<
1379 clocks = <&rc <<
1380 resets = <&rc <<
1381 #dma-cells = <<
1382 st,mem2mem; <<
1383 dma-requests <<
1384 access-contro <<
1385 }; <<
1386 <<
1387 dma2: dma-controller@ <<
1388 compatible = <<
1389 reg = <0x4800 <<
1390 interrupts = <<
1391 <<
1392 <<
1393 <<
1394 <<
1395 <<
1396 <<
1397 <<
1398 clocks = <&rc <<
1399 resets = <&rc <<
1400 #dma-cells = <<
1401 st,mem2mem; <<
1402 dma-requests <<
1403 access-contro <<
1404 }; <<
1405 <<
1406 dmamux1: dma-router@4 <<
1407 compatible = <<
1408 reg = <0x4800 <<
1409 #dma-cells = <<
1410 dma-requests <<
1411 dma-masters = <<
1412 dma-channels <<
1413 clocks = <&rc <<
1414 resets = <&rc <<
1415 access-contro <<
1416 }; <<
1417 <<
1418 adc: adc@48003000 { <<
1419 compatible = <<
1420 reg = <0x4800 <<
1421 interrupts = <<
1422 <<
1423 clocks = <&rc <<
1424 clock-names = <<
1425 interrupt-con <<
1426 st,syscfg = < <<
1427 #interrupt-ce <<
1428 #address-cell <<
1429 #size-cells = <<
1430 access-contro <<
1431 status = "dis <<
1432 <<
1433 adc1: adc@0 { <<
1434 compa <<
1435 #io-c <<
1436 #addr <<
1437 #size <<
1438 reg = <<
1439 inter <<
1440 inter <<
1441 dmas <<
1442 dma-n <<
1443 statu <<
1444 }; <<
1445 <<
1446 adc2: adc@100 <<
1447 compa <<
1448 #io-c <<
1449 #addr <<
1450 #size <<
1451 reg = <<
1452 inter <<
1453 inter <<
1454 dmas <<
1455 dma-n <<
1456 nvmem <<
1457 nvmem <<
1458 statu <<
1459 chann <<
1460 <<
1461 <<
1462 }; <<
1463 chann <<
1464 <<
1465 <<
1466 }; <<
1467 }; <<
1468 }; <<
1469 <<
1470 sdmmc3: mmc@48004000 <<
1471 compatible = <<
1472 arm,primecell <<
1473 reg = <0x4800 <<
1474 interrupts = <<
1475 clocks = <&rc <<
1476 clock-names = <<
1477 resets = <&rc <<
1478 cap-sd-highsp <<
1479 cap-mmc-highs <<
1480 max-frequency <<
1481 access-contro <<
1482 status = "dis <<
1483 }; <<
1484 <<
1485 usbotg_hs: usb-otg@49 <<
1486 compatible = <<
1487 reg = <0x4900 <<
1488 clocks = <&rc <<
1489 clock-names = <<
1490 resets = <&rc <<
1491 reset-names = <<
1492 interrupts = <<
1493 g-rx-fifo-siz <<
1494 g-np-tx-fifo- <<
1495 g-tx-fifo-siz <<
1496 dr_mode = "ot <<
1497 otg-rev = <0x <<
1498 usb33d-supply <<
1499 access-contro <<
1500 status = "dis <<
1501 }; <<
1502 <<
1503 dcmi: dcmi@4c006000 { <<
1504 compatible = <<
1505 reg = <0x4c00 <<
1506 interrupts = <<
1507 resets = <&rc <<
1508 clocks = <&rc <<
1509 clock-names = <<
1510 dmas = <&dmam <<
1511 dma-names = " <<
1512 access-contro <<
1513 status = "dis <<
1514 }; <<
1515 <<
1516 lptimer2: timer@50021 <<
1517 #address-cell <<
1518 #size-cells = <<
1519 compatible = <<
1520 reg = <0x5002 <<
1521 interrupts-ex <<
1522 clocks = <&rc <<
1523 clock-names = <<
1524 wakeup-source <<
1525 access-contro <<
1526 status = "dis <<
1527 <<
1528 pwm { <<
1529 compa <<
1530 #pwm- <<
1531 statu <<
1532 }; <<
1533 <<
1534 trigger@1 { <<
1535 compa <<
1536 reg = <<
1537 statu <<
1538 }; <<
1539 <<
1540 counter { <<
1541 compa <<
1542 statu <<
1543 }; <<
1544 }; <<
1545 <<
1546 lptimer3: timer@50022 <<
1547 #address-cell <<
1548 #size-cells = <<
1549 compatible = <<
1550 reg = <0x5002 <<
1551 interrupts-ex <<
1552 clocks = <&rc <<
1553 clock-names = <<
1554 wakeup-source <<
1555 access-contro <<
1556 status = "dis <<
1557 <<
1558 pwm { <<
1559 compa <<
1560 #pwm- <<
1561 statu <<
1562 }; <<
1563 <<
1564 trigger@2 { <<
1565 compa <<
1566 reg = <<
1567 statu <<
1568 }; <<
1569 }; <<
1570 <<
1571 lptimer4: timer@50023 <<
1572 compatible = <<
1573 reg = <0x5002 <<
1574 interrupts-ex <<
1575 clocks = <&rc <<
1576 clock-names = <<
1577 wakeup-source <<
1578 access-contro <<
1579 status = "dis <<
1580 <<
1581 pwm { <<
1582 compa <<
1583 #pwm- <<
1584 statu <<
1585 }; <<
1586 }; <<
1587 <<
1588 lptimer5: timer@50024 <<
1589 compatible = <<
1590 reg = <0x5002 <<
1591 interrupts-ex <<
1592 clocks = <&rc <<
1593 clock-names = <<
1594 wakeup-source <<
1595 access-contro <<
1596 status = "dis <<
1597 <<
1598 pwm { <<
1599 compa <<
1600 #pwm- <<
1601 statu <<
1602 }; <<
1603 }; <<
1604 <<
1605 vrefbuf: vrefbuf@5002 <<
1606 compatible = <<
1607 reg = <0x5002 <<
1608 regulator-min <<
1609 regulator-max <<
1610 clocks = <&rc <<
1611 access-contro <<
1612 status = "dis <<
1613 }; <<
1614 <<
1615 sai4: sai@50027000 { <<
1616 compatible = <<
1617 #address-cell <<
1618 #size-cells = <<
1619 ranges = <0 0 <<
1620 reg = <0x5002 <<
1621 interrupts = <<
1622 resets = <&rc <<
1623 access-contro <<
1624 status = "dis <<
1625 <<
1626 sai4a: audio- <<
1627 #soun <<
1628 compa <<
1629 reg = <<
1630 clock <<
1631 clock <<
1632 dmas <<
1633 statu <<
1634 }; <<
1635 <<
1636 sai4b: audio- <<
1637 #soun <<
1638 compa <<
1639 reg = <<
1640 clock <<
1641 clock <<
1642 dmas <<
1643 statu <<
1644 }; <<
1645 }; <<
1646 <<
1647 hash1: hash@54002000 <<
1648 compatible = <<
1649 reg = <0x5400 <<
1650 interrupts = <<
1651 clocks = <&rc <<
1652 resets = <&rc <<
1653 dmas = <&mdma <<
1654 dma-names = " <<
1655 dma-maxburst <<
1656 access-contro <<
1657 status = "dis <<
1658 }; <<
1659 <<
1660 rng1: rng@54003000 { <<
1661 compatible = <<
1662 reg = <0x5400 <<
1663 clocks = <&rc <<
1664 resets = <&rc <<
1665 access-contro <<
1666 status = "dis <<
1667 }; <<
1668 <<
1669 fmc: memory-controlle <<
1670 #address-cell <<
1671 #size-cells = <<
1672 compatible = <<
1673 reg = <0x5800 <<
1674 clocks = <&rc <<
1675 resets = <&rc <<
1676 access-contro <<
1677 status = "dis <<
1678 <<
1679 ranges = <0 0 <<
1680 <1 0 <<
1681 <2 0 <<
1682 <3 0 <<
1683 <4 0 <<
1684 <<
1685 nand-controll <<
1686 #addr <<
1687 #size <<
1688 compa <<
1689 reg = <<
1690 <<
1691 <<
1692 <<
1693 <<
1694 <<
1695 inter <<
1696 dmas <<
1697 <<
1698 <<
1699 dma-n <<
1700 statu <<
1701 }; <<
1702 }; <<
1703 <<
1704 qspi: spi@58003000 { <<
1705 compatible = <<
1706 reg = <0x5800 <<
1707 reg-names = " <<
1708 interrupts = <<
1709 dmas = <&mdma <<
1710 <&mdma <<
1711 dma-names = " <<
1712 clocks = <&rc <<
1713 resets = <&rc <<
1714 #address-cell <<
1715 #size-cells = <<
1716 access-contro <<
1717 status = "dis <<
1718 }; <<
1719 <<
1720 ethernet0: ethernet@5 <<
1721 compatible = <<
1722 reg = <0x5800 <<
1723 reg-names = " <<
1724 interrupts-ex <<
1725 interrupt-nam <<
1726 clock-names = <<
1727 <<
1728 <<
1729 <<
1730 <<
1731 <<
1732 clocks = <&rc <<
1733 <&rc <<
1734 <&rc <<
1735 <&rc <<
1736 <&rc <<
1737 <&rc <<
1738 st,syscon = < <<
1739 snps,mixed-bu <<
1740 snps,pbl = <2 <<
1741 snps,en-tx-lp <<
1742 snps,axi-conf <<
1743 snps,tso; <<
1744 access-contro <<
1745 status = "dis <<
1746 <<
1747 stmmac_axi_co <<
1748 snps, <<
1749 snps, <<
1750 snps, <<
1751 }; <<
1752 }; <<
1753 <<
1754 usart1: serial@5c0000 <<
1755 compatible = <<
1756 reg = <0x5c00 <<
1757 interrupts-ex <<
1758 clocks = <&rc <<
1759 wakeup-source <<
1760 access-contro <<
1761 status = "dis <<
1762 }; <<
1763 <<
1764 spi6: spi@5c001000 { <<
1765 #address-cell <<
1766 #size-cells = <<
1767 compatible = <<
1768 reg = <0x5c00 <<
1769 interrupts = <<
1770 clocks = <&rc <<
1771 resets = <&rc <<
1772 dmas = <&mdma <<
1773 <&mdma <<
1774 access-contro <<
1775 dma-names = " <<
1776 status = "dis <<
1777 }; <<
1778 <<
1779 i2c4: i2c@5c002000 { <<
1780 compatible = <<
1781 reg = <0x5c00 <<
1782 interrupt-nam <<
1783 interrupts = <<
1784 <<
1785 clocks = <&rc <<
1786 resets = <&rc <<
1787 #address-cell <<
1788 #size-cells = <<
1789 st,syscfg-fmp <<
1790 wakeup-source <<
1791 i2c-analog-fi <<
1792 access-contro <<
1793 status = "dis <<
1794 }; <<
1795 <<
1796 i2c6: i2c@5c009000 { <<
1797 compatible = <<
1798 reg = <0x5c00 <<
1799 interrupt-nam <<
1800 interrupts = <<
1801 <<
1802 clocks = <&rc <<
1803 resets = <&rc <<
1804 #address-cell <<
1805 #size-cells = <<
1806 st,syscfg-fmp <<
1807 wakeup-source <<
1808 i2c-analog-fi <<
1809 access-contro <<
1810 status = "dis <<
1811 }; <<
1812 }; 1660 };
1813 1661
1814 tamp: tamp@5c00a000 { 1662 tamp: tamp@5c00a000 {
1815 compatible = "st,stm3 1663 compatible = "st,stm32-tamp", "syscon", "simple-mfd";
1816 reg = <0x5c00a000 0x4 1664 reg = <0x5c00a000 0x400>;
1817 }; 1665 };
1818 1666
1819 /* 1667 /*
1820 * Break node order to solve 1668 * Break node order to solve dependency probe issue between
1821 * pinctrl and exti. 1669 * pinctrl and exti.
1822 */ 1670 */
1823 pinctrl: pinctrl@50002000 { 1671 pinctrl: pinctrl@50002000 {
1824 #address-cells = <1>; 1672 #address-cells = <1>;
1825 #size-cells = <1>; 1673 #size-cells = <1>;
1826 compatible = "st,stm3 1674 compatible = "st,stm32mp157-pinctrl";
1827 ranges = <0 0x5000200 1675 ranges = <0 0x50002000 0xa400>;
1828 interrupt-parent = <& 1676 interrupt-parent = <&exti>;
1829 st,syscfg = <&exti 0x 1677 st,syscfg = <&exti 0x60 0xff>;
1830 1678
1831 gpioa: gpio@50002000 1679 gpioa: gpio@50002000 {
1832 gpio-controll 1680 gpio-controller;
1833 #gpio-cells = 1681 #gpio-cells = <2>;
1834 interrupt-con 1682 interrupt-controller;
1835 #interrupt-ce 1683 #interrupt-cells = <2>;
1836 reg = <0x0 0x 1684 reg = <0x0 0x400>;
1837 clocks = <&rc 1685 clocks = <&rcc GPIOA>;
1838 st,bank-name 1686 st,bank-name = "GPIOA";
1839 status = "dis 1687 status = "disabled";
1840 }; 1688 };
1841 1689
1842 gpiob: gpio@50003000 1690 gpiob: gpio@50003000 {
1843 gpio-controll 1691 gpio-controller;
1844 #gpio-cells = 1692 #gpio-cells = <2>;
1845 interrupt-con 1693 interrupt-controller;
1846 #interrupt-ce 1694 #interrupt-cells = <2>;
1847 reg = <0x1000 1695 reg = <0x1000 0x400>;
1848 clocks = <&rc 1696 clocks = <&rcc GPIOB>;
1849 st,bank-name 1697 st,bank-name = "GPIOB";
1850 status = "dis 1698 status = "disabled";
1851 }; 1699 };
1852 1700
1853 gpioc: gpio@50004000 1701 gpioc: gpio@50004000 {
1854 gpio-controll 1702 gpio-controller;
1855 #gpio-cells = 1703 #gpio-cells = <2>;
1856 interrupt-con 1704 interrupt-controller;
1857 #interrupt-ce 1705 #interrupt-cells = <2>;
1858 reg = <0x2000 1706 reg = <0x2000 0x400>;
1859 clocks = <&rc 1707 clocks = <&rcc GPIOC>;
1860 st,bank-name 1708 st,bank-name = "GPIOC";
1861 status = "dis 1709 status = "disabled";
1862 }; 1710 };
1863 1711
1864 gpiod: gpio@50005000 1712 gpiod: gpio@50005000 {
1865 gpio-controll 1713 gpio-controller;
1866 #gpio-cells = 1714 #gpio-cells = <2>;
1867 interrupt-con 1715 interrupt-controller;
1868 #interrupt-ce 1716 #interrupt-cells = <2>;
1869 reg = <0x3000 1717 reg = <0x3000 0x400>;
1870 clocks = <&rc 1718 clocks = <&rcc GPIOD>;
1871 st,bank-name 1719 st,bank-name = "GPIOD";
1872 status = "dis 1720 status = "disabled";
1873 }; 1721 };
1874 1722
1875 gpioe: gpio@50006000 1723 gpioe: gpio@50006000 {
1876 gpio-controll 1724 gpio-controller;
1877 #gpio-cells = 1725 #gpio-cells = <2>;
1878 interrupt-con 1726 interrupt-controller;
1879 #interrupt-ce 1727 #interrupt-cells = <2>;
1880 reg = <0x4000 1728 reg = <0x4000 0x400>;
1881 clocks = <&rc 1729 clocks = <&rcc GPIOE>;
1882 st,bank-name 1730 st,bank-name = "GPIOE";
1883 status = "dis 1731 status = "disabled";
1884 }; 1732 };
1885 1733
1886 gpiof: gpio@50007000 1734 gpiof: gpio@50007000 {
1887 gpio-controll 1735 gpio-controller;
1888 #gpio-cells = 1736 #gpio-cells = <2>;
1889 interrupt-con 1737 interrupt-controller;
1890 #interrupt-ce 1738 #interrupt-cells = <2>;
1891 reg = <0x5000 1739 reg = <0x5000 0x400>;
1892 clocks = <&rc 1740 clocks = <&rcc GPIOF>;
1893 st,bank-name 1741 st,bank-name = "GPIOF";
1894 status = "dis 1742 status = "disabled";
1895 }; 1743 };
1896 1744
1897 gpiog: gpio@50008000 1745 gpiog: gpio@50008000 {
1898 gpio-controll 1746 gpio-controller;
1899 #gpio-cells = 1747 #gpio-cells = <2>;
1900 interrupt-con 1748 interrupt-controller;
1901 #interrupt-ce 1749 #interrupt-cells = <2>;
1902 reg = <0x6000 1750 reg = <0x6000 0x400>;
1903 clocks = <&rc 1751 clocks = <&rcc GPIOG>;
1904 st,bank-name 1752 st,bank-name = "GPIOG";
1905 status = "dis 1753 status = "disabled";
1906 }; 1754 };
1907 1755
1908 gpioh: gpio@50009000 1756 gpioh: gpio@50009000 {
1909 gpio-controll 1757 gpio-controller;
1910 #gpio-cells = 1758 #gpio-cells = <2>;
1911 interrupt-con 1759 interrupt-controller;
1912 #interrupt-ce 1760 #interrupt-cells = <2>;
1913 reg = <0x7000 1761 reg = <0x7000 0x400>;
1914 clocks = <&rc 1762 clocks = <&rcc GPIOH>;
1915 st,bank-name 1763 st,bank-name = "GPIOH";
1916 status = "dis 1764 status = "disabled";
1917 }; 1765 };
1918 1766
1919 gpioi: gpio@5000a000 1767 gpioi: gpio@5000a000 {
1920 gpio-controll 1768 gpio-controller;
1921 #gpio-cells = 1769 #gpio-cells = <2>;
1922 interrupt-con 1770 interrupt-controller;
1923 #interrupt-ce 1771 #interrupt-cells = <2>;
1924 reg = <0x8000 1772 reg = <0x8000 0x400>;
1925 clocks = <&rc 1773 clocks = <&rcc GPIOI>;
1926 st,bank-name 1774 st,bank-name = "GPIOI";
1927 status = "dis 1775 status = "disabled";
1928 }; 1776 };
1929 1777
1930 gpioj: gpio@5000b000 1778 gpioj: gpio@5000b000 {
1931 gpio-controll 1779 gpio-controller;
1932 #gpio-cells = 1780 #gpio-cells = <2>;
1933 interrupt-con 1781 interrupt-controller;
1934 #interrupt-ce 1782 #interrupt-cells = <2>;
1935 reg = <0x9000 1783 reg = <0x9000 0x400>;
1936 clocks = <&rc 1784 clocks = <&rcc GPIOJ>;
1937 st,bank-name 1785 st,bank-name = "GPIOJ";
1938 status = "dis 1786 status = "disabled";
1939 }; 1787 };
1940 1788
1941 gpiok: gpio@5000c000 1789 gpiok: gpio@5000c000 {
1942 gpio-controll 1790 gpio-controller;
1943 #gpio-cells = 1791 #gpio-cells = <2>;
1944 interrupt-con 1792 interrupt-controller;
1945 #interrupt-ce 1793 #interrupt-cells = <2>;
1946 reg = <0xa000 1794 reg = <0xa000 0x400>;
1947 clocks = <&rc 1795 clocks = <&rcc GPIOK>;
1948 st,bank-name 1796 st,bank-name = "GPIOK";
1949 status = "dis 1797 status = "disabled";
1950 }; 1798 };
1951 }; 1799 };
1952 1800
1953 pinctrl_z: pinctrl@54004000 { 1801 pinctrl_z: pinctrl@54004000 {
1954 #address-cells = <1>; 1802 #address-cells = <1>;
1955 #size-cells = <1>; 1803 #size-cells = <1>;
1956 compatible = "st,stm3 1804 compatible = "st,stm32mp157-z-pinctrl";
1957 ranges = <0 0x5400400 1805 ranges = <0 0x54004000 0x400>;
1958 interrupt-parent = <& 1806 interrupt-parent = <&exti>;
1959 st,syscfg = <&exti 0x 1807 st,syscfg = <&exti 0x60 0xff>;
1960 1808
1961 gpioz: gpio@54004000 1809 gpioz: gpio@54004000 {
1962 gpio-controll 1810 gpio-controller;
1963 #gpio-cells = 1811 #gpio-cells = <2>;
1964 interrupt-con 1812 interrupt-controller;
1965 #interrupt-ce 1813 #interrupt-cells = <2>;
1966 reg = <0 0x40 1814 reg = <0 0x400>;
1967 clocks = <&rc 1815 clocks = <&rcc GPIOZ>;
1968 st,bank-name 1816 st,bank-name = "GPIOZ";
1969 st,bank-iopor 1817 st,bank-ioport = <11>;
1970 status = "dis 1818 status = "disabled";
1971 }; 1819 };
1972 }; 1820 };
1973 }; 1821 };
1974 1822
1975 mlahb: ahb { 1823 mlahb: ahb {
1976 compatible = "st,mlahb", "sim 1824 compatible = "st,mlahb", "simple-bus";
1977 #address-cells = <1>; 1825 #address-cells = <1>;
1978 #size-cells = <1>; 1826 #size-cells = <1>;
1979 ranges; 1827 ranges;
1980 dma-ranges = <0x00000000 0x38 1828 dma-ranges = <0x00000000 0x38000000 0x10000>,
1981 <0x10000000 0x10 1829 <0x10000000 0x10000000 0x60000>,
1982 <0x30000000 0x30 1830 <0x30000000 0x30000000 0x60000>;
1983 1831
1984 m4_rproc: m4@10000000 { 1832 m4_rproc: m4@10000000 {
1985 compatible = "st,stm3 1833 compatible = "st,stm32mp1-m4";
1986 reg = <0x10000000 0x4 1834 reg = <0x10000000 0x40000>,
1987 <0x30000000 0x4 1835 <0x30000000 0x40000>,
1988 <0x38000000 0x1 1836 <0x38000000 0x10000>;
1989 resets = <&rcc MCU_R> 1837 resets = <&rcc MCU_R>;
1990 reset-names = "mcu_rs 1838 reset-names = "mcu_rst";
1991 st,syscfg-holdboot = 1839 st,syscfg-holdboot = <&rcc 0x10C 0x1>;
1992 st,syscfg-pdds = <&pw 1840 st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
1993 st,syscfg-rsc-tbl = < 1841 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
1994 st,syscfg-m4-state = 1842 st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;
1995 status = "disabled"; 1843 status = "disabled";
1996 }; 1844 };
1997 }; 1845 };
1998 }; 1846 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.