1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /* 2 /*
3 * Copyright (C) STMicroelectronics 2017 - All 3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */ 5 */
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h> 7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h> 8 #include <dt-bindings/reset/stm32mp1-resets.h>
9 9
10 / { 10 / {
11 #address-cells = <1>; 11 #address-cells = <1>;
12 #size-cells = <1>; 12 #size-cells = <1>;
13 13
14 cpus { 14 cpus {
15 #address-cells = <1>; 15 #address-cells = <1>;
16 #size-cells = <0>; 16 #size-cells = <0>;
17 17
18 cpu0: cpu@0 { 18 cpu0: cpu@0 {
19 compatible = "arm,cort 19 compatible = "arm,cortex-a7";
20 clock-frequency = <650 20 clock-frequency = <650000000>;
21 device_type = "cpu"; 21 device_type = "cpu";
22 reg = <0>; 22 reg = <0>;
23 }; 23 };
24 }; 24 };
25 25
26 arm-pmu { 26 arm-pmu {
27 compatible = "arm,cortex-a7-pm 27 compatible = "arm,cortex-a7-pmu";
28 interrupts = <GIC_SPI 200 IRQ_ 28 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
29 interrupt-affinity = <&cpu0>; 29 interrupt-affinity = <&cpu0>;
30 interrupt-parent = <&intc>; 30 interrupt-parent = <&intc>;
31 }; 31 };
32 32
33 psci { 33 psci {
34 compatible = "arm,psci-1.0"; 34 compatible = "arm,psci-1.0";
35 method = "smc"; 35 method = "smc";
36 }; 36 };
37 37
38 intc: interrupt-controller@a0021000 { 38 intc: interrupt-controller@a0021000 {
39 compatible = "arm,cortex-a7-gi 39 compatible = "arm,cortex-a7-gic";
40 #interrupt-cells = <3>; 40 #interrupt-cells = <3>;
41 interrupt-controller; 41 interrupt-controller;
42 reg = <0xa0021000 0x1000>, 42 reg = <0xa0021000 0x1000>,
43 <0xa0022000 0x2000>; 43 <0xa0022000 0x2000>;
44 }; 44 };
45 45
46 timer { 46 timer {
47 compatible = "arm,armv7-timer" 47 compatible = "arm,armv7-timer";
48 interrupts = <GIC_PPI 13 (GIC_ 48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
49 <GIC_PPI 14 (GIC_ 49 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 11 (GIC_ 50 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 10 (GIC_ 51 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
52 interrupt-parent = <&intc>; 52 interrupt-parent = <&intc>;
53 arm,no-tick-in-suspend; 53 arm,no-tick-in-suspend;
54 }; 54 };
55 55
56 clocks { 56 clocks {
57 clk_hse: clk-hse { 57 clk_hse: clk-hse {
58 #clock-cells = <0>; 58 #clock-cells = <0>;
59 compatible = "fixed-cl 59 compatible = "fixed-clock";
60 clock-frequency = <240 60 clock-frequency = <24000000>;
61 }; 61 };
62 62
63 clk_hsi: clk-hsi { 63 clk_hsi: clk-hsi {
64 #clock-cells = <0>; 64 #clock-cells = <0>;
65 compatible = "fixed-cl 65 compatible = "fixed-clock";
66 clock-frequency = <640 66 clock-frequency = <64000000>;
67 }; 67 };
68 68
69 clk_lse: clk-lse { 69 clk_lse: clk-lse {
70 #clock-cells = <0>; 70 #clock-cells = <0>;
71 compatible = "fixed-cl 71 compatible = "fixed-clock";
72 clock-frequency = <327 72 clock-frequency = <32768>;
73 }; 73 };
74 74
75 clk_lsi: clk-lsi { 75 clk_lsi: clk-lsi {
76 #clock-cells = <0>; 76 #clock-cells = <0>;
77 compatible = "fixed-cl 77 compatible = "fixed-clock";
78 clock-frequency = <320 78 clock-frequency = <32000>;
79 }; 79 };
80 80
81 clk_csi: clk-csi { 81 clk_csi: clk-csi {
82 #clock-cells = <0>; 82 #clock-cells = <0>;
83 compatible = "fixed-cl 83 compatible = "fixed-clock";
84 clock-frequency = <400 84 clock-frequency = <4000000>;
85 }; 85 };
86 }; 86 };
87 87
88 thermal-zones { 88 thermal-zones {
89 cpu_thermal: cpu-thermal { 89 cpu_thermal: cpu-thermal {
90 polling-delay-passive 90 polling-delay-passive = <0>;
91 polling-delay = <0>; 91 polling-delay = <0>;
92 thermal-sensors = <&dt 92 thermal-sensors = <&dts>;
93 93
94 trips { 94 trips {
95 cpu_alert1: cp 95 cpu_alert1: cpu-alert1 {
96 temper 96 temperature = <85000>;
97 hyster 97 hysteresis = <0>;
98 type = 98 type = "passive";
99 }; 99 };
100 100
101 cpu-crit { 101 cpu-crit {
102 temper 102 temperature = <120000>;
103 hyster 103 hysteresis = <0>;
104 type = 104 type = "critical";
105 }; 105 };
106 }; 106 };
107 107
108 cooling-maps { 108 cooling-maps {
109 }; 109 };
110 }; 110 };
111 }; 111 };
112 112
113 booster: regulator-booster { 113 booster: regulator-booster {
114 compatible = "st,stm32mp1-boos 114 compatible = "st,stm32mp1-booster";
115 st,syscfg = <&syscfg>; 115 st,syscfg = <&syscfg>;
116 status = "disabled"; 116 status = "disabled";
117 }; 117 };
118 118
119 soc { 119 soc {
120 compatible = "simple-bus"; 120 compatible = "simple-bus";
121 #address-cells = <1>; 121 #address-cells = <1>;
122 #size-cells = <1>; 122 #size-cells = <1>;
123 interrupt-parent = <&intc>; 123 interrupt-parent = <&intc>;
124 ranges; 124 ranges;
125 125
126 ipcc: mailbox@4c001000 { !! 126 timers2: timer@40000000 {
127 compatible = "st,stm32 !! 127 #address-cells = <1>;
128 #mbox-cells = <1>; !! 128 #size-cells = <0>;
129 reg = <0x4c001000 0x40 !! 129 compatible = "st,stm32-timers";
130 st,proc-id = <0>; !! 130 reg = <0x40000000 0x400>;
131 interrupts-extended = !! 131 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
132 <&exti 61 1>, !! 132 interrupt-names = "global";
133 <&intc GIC_SPI !! 133 clocks = <&rcc TIM2_K>;
134 interrupt-names = "rx" !! 134 clock-names = "int";
135 clocks = <&rcc IPCC>; !! 135 dmas = <&dmamux1 18 0x400 0x1>,
136 wakeup-source; !! 136 <&dmamux1 19 0x400 0x1>,
>> 137 <&dmamux1 20 0x400 0x1>,
>> 138 <&dmamux1 21 0x400 0x1>,
>> 139 <&dmamux1 22 0x400 0x1>;
>> 140 dma-names = "ch1", "ch2", "ch3", "ch4", "up";
137 status = "disabled"; 141 status = "disabled";
>> 142
>> 143 pwm {
>> 144 compatible = "st,stm32-pwm";
>> 145 #pwm-cells = <3>;
>> 146 status = "disabled";
>> 147 };
>> 148
>> 149 timer@1 {
>> 150 compatible = "st,stm32h7-timer-trigger";
>> 151 reg = <1>;
>> 152 status = "disabled";
>> 153 };
>> 154
>> 155 counter {
>> 156 compatible = "st,stm32-timer-counter";
>> 157 status = "disabled";
>> 158 };
138 }; 159 };
139 160
140 rcc: rcc@50000000 { !! 161 timers3: timer@40001000 {
141 compatible = "st,stm32 !! 162 #address-cells = <1>;
142 reg = <0x50000000 0x10 !! 163 #size-cells = <0>;
143 #clock-cells = <1>; !! 164 compatible = "st,stm32-timers";
144 #reset-cells = <1>; !! 165 reg = <0x40001000 0x400>;
>> 166 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
>> 167 interrupt-names = "global";
>> 168 clocks = <&rcc TIM3_K>;
>> 169 clock-names = "int";
>> 170 dmas = <&dmamux1 23 0x400 0x1>,
>> 171 <&dmamux1 24 0x400 0x1>,
>> 172 <&dmamux1 25 0x400 0x1>,
>> 173 <&dmamux1 26 0x400 0x1>,
>> 174 <&dmamux1 27 0x400 0x1>,
>> 175 <&dmamux1 28 0x400 0x1>;
>> 176 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
>> 177 status = "disabled";
>> 178
>> 179 pwm {
>> 180 compatible = "st,stm32-pwm";
>> 181 #pwm-cells = <3>;
>> 182 status = "disabled";
>> 183 };
>> 184
>> 185 timer@2 {
>> 186 compatible = "st,stm32h7-timer-trigger";
>> 187 reg = <2>;
>> 188 status = "disabled";
>> 189 };
>> 190
>> 191 counter {
>> 192 compatible = "st,stm32-timer-counter";
>> 193 status = "disabled";
>> 194 };
145 }; 195 };
146 196
147 pwr_regulators: pwr@50001000 { !! 197 timers4: timer@40002000 {
148 compatible = "st,stm32 !! 198 #address-cells = <1>;
149 reg = <0x50001000 0x10 !! 199 #size-cells = <0>;
>> 200 compatible = "st,stm32-timers";
>> 201 reg = <0x40002000 0x400>;
>> 202 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
>> 203 interrupt-names = "global";
>> 204 clocks = <&rcc TIM4_K>;
>> 205 clock-names = "int";
>> 206 dmas = <&dmamux1 29 0x400 0x1>,
>> 207 <&dmamux1 30 0x400 0x1>,
>> 208 <&dmamux1 31 0x400 0x1>,
>> 209 <&dmamux1 32 0x400 0x1>;
>> 210 dma-names = "ch1", "ch2", "ch3", "ch4";
>> 211 status = "disabled";
150 212
151 reg11: reg11 { !! 213 pwm {
152 regulator-name !! 214 compatible = "st,stm32-pwm";
153 regulator-min- !! 215 #pwm-cells = <3>;
154 regulator-max- !! 216 status = "disabled";
155 }; 217 };
156 218
157 reg18: reg18 { !! 219 timer@3 {
158 regulator-name !! 220 compatible = "st,stm32h7-timer-trigger";
159 regulator-min- !! 221 reg = <3>;
160 regulator-max- !! 222 status = "disabled";
161 }; 223 };
162 224
163 usb33: usb33 { !! 225 counter {
164 regulator-name !! 226 compatible = "st,stm32-timer-counter";
165 regulator-min- !! 227 status = "disabled";
166 regulator-max- <<
167 }; 228 };
168 }; 229 };
169 230
170 pwr_mcu: pwr_mcu@50001014 { !! 231 timers5: timer@40003000 {
171 compatible = "st,stm32 !! 232 #address-cells = <1>;
172 reg = <0x50001014 0x4> !! 233 #size-cells = <0>;
>> 234 compatible = "st,stm32-timers";
>> 235 reg = <0x40003000 0x400>;
>> 236 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>> 237 interrupt-names = "global";
>> 238 clocks = <&rcc TIM5_K>;
>> 239 clock-names = "int";
>> 240 dmas = <&dmamux1 55 0x400 0x1>,
>> 241 <&dmamux1 56 0x400 0x1>,
>> 242 <&dmamux1 57 0x400 0x1>,
>> 243 <&dmamux1 58 0x400 0x1>,
>> 244 <&dmamux1 59 0x400 0x1>,
>> 245 <&dmamux1 60 0x400 0x1>;
>> 246 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
>> 247 status = "disabled";
>> 248
>> 249 pwm {
>> 250 compatible = "st,stm32-pwm";
>> 251 #pwm-cells = <3>;
>> 252 status = "disabled";
>> 253 };
>> 254
>> 255 timer@4 {
>> 256 compatible = "st,stm32h7-timer-trigger";
>> 257 reg = <4>;
>> 258 status = "disabled";
>> 259 };
>> 260
>> 261 counter {
>> 262 compatible = "st,stm32-timer-counter";
>> 263 status = "disabled";
>> 264 };
173 }; 265 };
174 266
175 exti: interrupt-controller@500 !! 267 timers6: timer@40004000 {
176 compatible = "st,stm32 !! 268 #address-cells = <1>;
177 interrupt-controller; !! 269 #size-cells = <0>;
178 #interrupt-cells = <2> !! 270 compatible = "st,stm32-timers";
179 reg = <0x5000d000 0x40 !! 271 reg = <0x40004000 0x400>;
180 interrupts-extended = !! 272 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
181 <&intc GIC_SPI !! 273 interrupt-names = "global";
182 <&intc GIC_SPI !! 274 clocks = <&rcc TIM6_K>;
183 <&intc GIC_SPI !! 275 clock-names = "int";
184 <&intc GIC_SPI !! 276 dmas = <&dmamux1 69 0x400 0x1>;
185 <&intc GIC_SPI !! 277 dma-names = "up";
186 <&intc GIC_SPI !! 278 status = "disabled";
187 <&intc GIC_SPI !! 279
188 <&intc GIC_SPI !! 280 timer@5 {
189 <&intc GIC_SPI !! 281 compatible = "st,stm32h7-timer-trigger";
190 <&intc GIC_SPI !! 282 reg = <5>;
191 <&intc GIC_SPI !! 283 status = "disabled";
192 <&intc GIC_SPI !! 284 };
193 <&intc GIC_SPI <<
194 <&intc GIC_SPI <<
195 <&intc GIC_SPI <<
196 <&intc GIC_SPI <<
197 <&intc GIC_SPI <<
198 <0>, <<
199 <0>, <<
200 <&intc GIC_SPI <<
201 <0>, <<
202 <&intc GIC_SPI <<
203 <&intc GIC_SPI <<
204 <&intc GIC_SPI <<
205 <&intc GIC_SPI <<
206 <&intc GIC_SPI <<
207 <&intc GIC_SPI <<
208 <&intc GIC_SPI <<
209 <&intc GIC_SPI <<
210 <&intc GIC_SPI <<
211 <&intc GIC_SPI <<
212 <&intc GIC_SPI <<
213 <&intc GIC_SPI <<
214 <&intc GIC_SPI <<
215 <0>, <<
216 <0>, <<
217 <0>, <<
218 <0>, <<
219 <0>, <<
220 <0>, <<
221 <0>, <<
222 <0>, <<
223 <0>, <<
224 <0>, <<
225 <0>, <<
226 <0>, <<
227 <&intc GIC_SPI <<
228 <&intc GIC_SPI <<
229 <&intc GIC_SPI <<
230 <0>, <<
231 <&intc GIC_SPI <<
232 <0>, <<
233 <&intc GIC_SPI <<
234 <&intc GIC_SPI <<
235 <&intc GIC_SPI <<
236 <0>, <<
237 <0>, <<
238 <0>, <<
239 <0>, <<
240 <0>, <<
241 <0>, <<
242 <&intc GIC_SPI <<
243 <0>, <<
244 <0>, <<
245 <0>, <<
246 <&intc GIC_SPI <<
247 <0>, <<
248 <0>, <<
249 <&intc GIC_SPI <<
250 <0>, <<
251 <&intc GIC_SPI <<
252 <0>, <<
253 <0>, <<
254 <&intc GIC_SPI <<
255 }; 285 };
256 286
257 syscfg: syscon@50020000 { !! 287 timers7: timer@40005000 {
258 compatible = "st,stm32 !! 288 #address-cells = <1>;
259 reg = <0x50020000 0x40 !! 289 #size-cells = <0>;
260 clocks = <&rcc SYSCFG> !! 290 compatible = "st,stm32-timers";
>> 291 reg = <0x40005000 0x400>;
>> 292 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
>> 293 interrupt-names = "global";
>> 294 clocks = <&rcc TIM7_K>;
>> 295 clock-names = "int";
>> 296 dmas = <&dmamux1 70 0x400 0x1>;
>> 297 dma-names = "up";
>> 298 status = "disabled";
>> 299
>> 300 timer@6 {
>> 301 compatible = "st,stm32h7-timer-trigger";
>> 302 reg = <6>;
>> 303 status = "disabled";
>> 304 };
261 }; 305 };
262 306
263 dts: thermal@50028000 { !! 307 timers12: timer@40006000 {
264 compatible = "st,stm32 !! 308 #address-cells = <1>;
265 reg = <0x50028000 0x10 !! 309 #size-cells = <0>;
266 interrupts = <GIC_SPI !! 310 compatible = "st,stm32-timers";
267 clocks = <&rcc TMPSENS !! 311 reg = <0x40006000 0x400>;
268 clock-names = "pclk"; !! 312 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
269 #thermal-sensor-cells !! 313 interrupt-names = "global";
>> 314 clocks = <&rcc TIM12_K>;
>> 315 clock-names = "int";
270 status = "disabled"; 316 status = "disabled";
>> 317
>> 318 pwm {
>> 319 compatible = "st,stm32-pwm";
>> 320 #pwm-cells = <3>;
>> 321 status = "disabled";
>> 322 };
>> 323
>> 324 timer@11 {
>> 325 compatible = "st,stm32h7-timer-trigger";
>> 326 reg = <11>;
>> 327 status = "disabled";
>> 328 };
271 }; 329 };
272 330
273 mdma1: dma-controller@58000000 !! 331 timers13: timer@40007000 {
274 compatible = "st,stm32 !! 332 #address-cells = <1>;
275 reg = <0x58000000 0x10 !! 333 #size-cells = <0>;
276 interrupts = <GIC_SPI !! 334 compatible = "st,stm32-timers";
277 clocks = <&rcc MDMA>; !! 335 reg = <0x40007000 0x400>;
278 resets = <&rcc MDMA_R> !! 336 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
279 #dma-cells = <5>; !! 337 interrupt-names = "global";
280 dma-channels = <32>; !! 338 clocks = <&rcc TIM13_K>;
281 dma-requests = <48>; !! 339 clock-names = "int";
>> 340 status = "disabled";
>> 341
>> 342 pwm {
>> 343 compatible = "st,stm32-pwm";
>> 344 #pwm-cells = <3>;
>> 345 status = "disabled";
>> 346 };
>> 347
>> 348 timer@12 {
>> 349 compatible = "st,stm32h7-timer-trigger";
>> 350 reg = <12>;
>> 351 status = "disabled";
>> 352 };
282 }; 353 };
283 354
284 sdmmc1: mmc@58005000 { !! 355 timers14: timer@40008000 {
285 compatible = "st,stm32 !! 356 #address-cells = <1>;
286 arm,primecell-periphid !! 357 #size-cells = <0>;
287 reg = <0x58005000 0x10 !! 358 compatible = "st,stm32-timers";
288 interrupts = <GIC_SPI !! 359 reg = <0x40008000 0x400>;
289 clocks = <&rcc SDMMC1_ !! 360 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
290 clock-names = "apb_pcl !! 361 interrupt-names = "global";
291 resets = <&rcc SDMMC1_ !! 362 clocks = <&rcc TIM14_K>;
292 cap-sd-highspeed; !! 363 clock-names = "int";
293 cap-mmc-highspeed; <<
294 max-frequency = <12000 <<
295 status = "disabled"; 364 status = "disabled";
>> 365
>> 366 pwm {
>> 367 compatible = "st,stm32-pwm";
>> 368 #pwm-cells = <3>;
>> 369 status = "disabled";
>> 370 };
>> 371
>> 372 timer@13 {
>> 373 compatible = "st,stm32h7-timer-trigger";
>> 374 reg = <13>;
>> 375 status = "disabled";
>> 376 };
296 }; 377 };
297 378
298 sdmmc2: mmc@58007000 { !! 379 lptimer1: timer@40009000 {
299 compatible = "st,stm32 !! 380 #address-cells = <1>;
300 arm,primecell-periphid !! 381 #size-cells = <0>;
301 reg = <0x58007000 0x10 !! 382 compatible = "st,stm32-lptimer";
302 interrupts = <GIC_SPI !! 383 reg = <0x40009000 0x400>;
303 clocks = <&rcc SDMMC2_ !! 384 interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
304 clock-names = "apb_pcl !! 385 clocks = <&rcc LPTIM1_K>;
305 resets = <&rcc SDMMC2_ !! 386 clock-names = "mux";
306 cap-sd-highspeed; !! 387 wakeup-source;
307 cap-mmc-highspeed; <<
308 max-frequency = <12000 <<
309 status = "disabled"; 388 status = "disabled";
>> 389
>> 390 pwm {
>> 391 compatible = "st,stm32-pwm-lp";
>> 392 #pwm-cells = <3>;
>> 393 status = "disabled";
>> 394 };
>> 395
>> 396 trigger@0 {
>> 397 compatible = "st,stm32-lptimer-trigger";
>> 398 reg = <0>;
>> 399 status = "disabled";
>> 400 };
>> 401
>> 402 counter {
>> 403 compatible = "st,stm32-lptimer-counter";
>> 404 status = "disabled";
>> 405 };
310 }; 406 };
311 407
312 crc1: crc@58009000 { !! 408 spi2: spi@4000b000 {
313 compatible = "st,stm32 !! 409 #address-cells = <1>;
314 reg = <0x58009000 0x40 !! 410 #size-cells = <0>;
315 clocks = <&rcc CRC1>; !! 411 compatible = "st,stm32h7-spi";
>> 412 reg = <0x4000b000 0x400>;
>> 413 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
>> 414 clocks = <&rcc SPI2_K>;
>> 415 resets = <&rcc SPI2_R>;
>> 416 dmas = <&dmamux1 39 0x400 0x05>,
>> 417 <&dmamux1 40 0x400 0x05>;
>> 418 dma-names = "rx", "tx";
316 status = "disabled"; 419 status = "disabled";
317 }; 420 };
318 421
319 usbh_ohci: usb@5800c000 { !! 422 i2s2: audio-controller@4000b000 {
320 compatible = "generic- !! 423 compatible = "st,stm32h7-i2s";
321 reg = <0x5800c000 0x10 !! 424 #sound-dai-cells = <0>;
322 clocks = <&usbphyc>, < !! 425 reg = <0x4000b000 0x400>;
323 resets = <&rcc USBH_R> !! 426 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
324 interrupts = <GIC_SPI !! 427 dmas = <&dmamux1 39 0x400 0x01>,
325 phys = <&usbphyc_port0 !! 428 <&dmamux1 40 0x400 0x01>;
326 phy-names = "usb"; !! 429 dma-names = "rx", "tx";
327 status = "disabled"; 430 status = "disabled";
328 }; 431 };
329 432
330 usbh_ehci: usb@5800d000 { !! 433 spi3: spi@4000c000 {
331 compatible = "generic- !! 434 #address-cells = <1>;
332 reg = <0x5800d000 0x10 !! 435 #size-cells = <0>;
333 clocks = <&usbphyc>, < !! 436 compatible = "st,stm32h7-spi";
334 resets = <&rcc USBH_R> !! 437 reg = <0x4000c000 0x400>;
335 interrupts = <GIC_SPI !! 438 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
336 companion = <&usbh_ohc !! 439 clocks = <&rcc SPI3_K>;
337 phys = <&usbphyc_port0 !! 440 resets = <&rcc SPI3_R>;
338 phy-names = "usb"; !! 441 dmas = <&dmamux1 61 0x400 0x05>,
>> 442 <&dmamux1 62 0x400 0x05>;
>> 443 dma-names = "rx", "tx";
339 status = "disabled"; 444 status = "disabled";
340 }; 445 };
341 446
342 ltdc: display-controller@5a001 !! 447 i2s3: audio-controller@4000c000 {
343 compatible = "st,stm32 !! 448 compatible = "st,stm32h7-i2s";
344 reg = <0x5a001000 0x40 !! 449 #sound-dai-cells = <0>;
345 interrupts = <GIC_SPI !! 450 reg = <0x4000c000 0x400>;
346 <GIC_SPI !! 451 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&rcc LTDC_PX !! 452 dmas = <&dmamux1 61 0x400 0x01>,
348 clock-names = "lcd"; !! 453 <&dmamux1 62 0x400 0x01>;
349 resets = <&rcc LTDC_R> !! 454 dma-names = "rx", "tx";
350 status = "disabled"; 455 status = "disabled";
351 }; 456 };
352 457
353 iwdg2: watchdog@5a002000 { !! 458 spdifrx: audio-controller@4000d000 {
354 compatible = "st,stm32 !! 459 compatible = "st,stm32h7-spdifrx";
355 reg = <0x5a002000 0x40 !! 460 #sound-dai-cells = <0>;
356 clocks = <&rcc IWDG2>, !! 461 reg = <0x4000d000 0x400>;
357 clock-names = "pclk", !! 462 clocks = <&rcc SPDIF_K>;
>> 463 clock-names = "kclk";
>> 464 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
>> 465 dmas = <&dmamux1 93 0x400 0x01>,
>> 466 <&dmamux1 94 0x400 0x01>;
>> 467 dma-names = "rx", "rx-ctrl";
358 status = "disabled"; 468 status = "disabled";
359 }; 469 };
360 470
361 usbphyc: usbphyc@5a006000 { !! 471 usart2: serial@4000e000 {
362 #address-cells = <1>; !! 472 compatible = "st,stm32h7-uart";
363 #size-cells = <0>; !! 473 reg = <0x4000e000 0x400>;
364 #clock-cells = <0>; !! 474 interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
365 compatible = "st,stm32 !! 475 clocks = <&rcc USART2_K>;
366 reg = <0x5a006000 0x10 !! 476 wakeup-source;
367 clocks = <&rcc USBPHY_ !! 477 dmas = <&dmamux1 43 0x400 0x15>,
368 resets = <&rcc USBPHY_ !! 478 <&dmamux1 44 0x400 0x11>;
369 vdda1v1-supply = <® !! 479 dma-names = "rx", "tx";
370 vdda1v8-supply = <® <<
371 status = "disabled"; 480 status = "disabled";
>> 481 };
372 482
373 usbphyc_port0: usb-phy !! 483 usart3: serial@4000f000 {
374 #phy-cells = < !! 484 compatible = "st,stm32h7-uart";
375 reg = <0>; !! 485 reg = <0x4000f000 0x400>;
376 }; !! 486 interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
>> 487 clocks = <&rcc USART3_K>;
>> 488 wakeup-source;
>> 489 dmas = <&dmamux1 45 0x400 0x15>,
>> 490 <&dmamux1 46 0x400 0x11>;
>> 491 dma-names = "rx", "tx";
>> 492 status = "disabled";
>> 493 };
377 494
378 usbphyc_port1: usb-phy !! 495 uart4: serial@40010000 {
379 #phy-cells = < !! 496 compatible = "st,stm32h7-uart";
380 reg = <1>; !! 497 reg = <0x40010000 0x400>;
381 }; !! 498 interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
>> 499 clocks = <&rcc UART4_K>;
>> 500 wakeup-source;
>> 501 dmas = <&dmamux1 63 0x400 0x15>,
>> 502 <&dmamux1 64 0x400 0x11>;
>> 503 dma-names = "rx", "tx";
>> 504 status = "disabled";
382 }; 505 };
383 506
384 rtc: rtc@5c004000 { !! 507 uart5: serial@40011000 {
385 compatible = "st,stm32 !! 508 compatible = "st,stm32h7-uart";
386 reg = <0x5c004000 0x40 !! 509 reg = <0x40011000 0x400>;
387 clocks = <&rcc RTCAPB> !! 510 interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
388 clock-names = "pclk", !! 511 clocks = <&rcc UART5_K>;
389 interrupts-extended = !! 512 wakeup-source;
>> 513 dmas = <&dmamux1 65 0x400 0x15>,
>> 514 <&dmamux1 66 0x400 0x11>;
>> 515 dma-names = "rx", "tx";
390 status = "disabled"; 516 status = "disabled";
391 }; 517 };
392 518
393 bsec: efuse@5c005000 { !! 519 i2c1: i2c@40012000 {
394 compatible = "st,stm32 !! 520 compatible = "st,stm32mp15-i2c";
395 reg = <0x5c005000 0x40 !! 521 reg = <0x40012000 0x400>;
>> 522 interrupt-names = "event", "error";
>> 523 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
>> 524 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
>> 525 clocks = <&rcc I2C1_K>;
>> 526 resets = <&rcc I2C1_R>;
396 #address-cells = <1>; 527 #address-cells = <1>;
397 #size-cells = <1>; !! 528 #size-cells = <0>;
398 part_number_otp: part- !! 529 st,syscfg-fmp = <&syscfg 0x4 0x1>;
399 reg = <0x4 0x1 !! 530 wakeup-source;
400 }; !! 531 i2c-analog-filter;
401 vrefint: vrefin-cal@52 !! 532 status = "disabled";
402 reg = <0x52 0x <<
403 }; <<
404 ts_cal1: calib@5c { <<
405 reg = <0x5c 0x <<
406 }; <<
407 ts_cal2: calib@5e { <<
408 reg = <0x5e 0x <<
409 }; <<
410 }; 533 };
411 534
412 etzpc: bus@5c007000 { !! 535 i2c2: i2c@40013000 {
413 compatible = "st,stm32 !! 536 compatible = "st,stm32mp15-i2c";
414 reg = <0x5c007000 0x40 !! 537 reg = <0x40013000 0x400>;
>> 538 interrupt-names = "event", "error";
>> 539 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
>> 540 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
>> 541 clocks = <&rcc I2C2_K>;
>> 542 resets = <&rcc I2C2_R>;
415 #address-cells = <1>; 543 #address-cells = <1>;
416 #size-cells = <1>; !! 544 #size-cells = <0>;
417 #access-controller-cel !! 545 st,syscfg-fmp = <&syscfg 0x4 0x2>;
418 ranges; !! 546 wakeup-source;
419 !! 547 i2c-analog-filter;
420 timers2: timer@4000000 !! 548 status = "disabled";
421 #address-cells !! 549 };
422 #size-cells = <<
423 compatible = " <<
424 reg = <0x40000 <<
425 interrupts = < <<
426 interrupt-name <<
427 clocks = <&rcc <<
428 clock-names = <<
429 dmas = <&dmamu <<
430 <&dmamu <<
431 <&dmamu <<
432 <&dmamu <<
433 <&dmamu <<
434 dma-names = "c <<
435 access-control <<
436 status = "disa <<
437 <<
438 pwm { <<
439 compat <<
440 #pwm-c <<
441 status <<
442 }; <<
443 550
444 timer@1 { !! 551 i2c3: i2c@40014000 {
445 compat !! 552 compatible = "st,stm32mp15-i2c";
446 reg = !! 553 reg = <0x40014000 0x400>;
447 status !! 554 interrupt-names = "event", "error";
448 }; !! 555 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
>> 556 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
>> 557 clocks = <&rcc I2C3_K>;
>> 558 resets = <&rcc I2C3_R>;
>> 559 #address-cells = <1>;
>> 560 #size-cells = <0>;
>> 561 st,syscfg-fmp = <&syscfg 0x4 0x4>;
>> 562 wakeup-source;
>> 563 i2c-analog-filter;
>> 564 status = "disabled";
>> 565 };
449 566
450 counter { !! 567 i2c5: i2c@40015000 {
451 compat !! 568 compatible = "st,stm32mp15-i2c";
452 status !! 569 reg = <0x40015000 0x400>;
453 }; !! 570 interrupt-names = "event", "error";
454 }; !! 571 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
>> 572 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>> 573 clocks = <&rcc I2C5_K>;
>> 574 resets = <&rcc I2C5_R>;
>> 575 #address-cells = <1>;
>> 576 #size-cells = <0>;
>> 577 st,syscfg-fmp = <&syscfg 0x4 0x10>;
>> 578 wakeup-source;
>> 579 i2c-analog-filter;
>> 580 status = "disabled";
>> 581 };
455 582
456 timers3: timer@4000100 !! 583 cec: cec@40016000 {
457 #address-cells !! 584 compatible = "st,stm32-cec";
458 #size-cells = !! 585 reg = <0x40016000 0x400>;
459 compatible = " !! 586 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
460 reg = <0x40001 !! 587 clocks = <&rcc CEC_K>, <&rcc CEC>;
461 interrupts = < !! 588 clock-names = "cec", "hdmi-cec";
462 interrupt-name !! 589 status = "disabled";
463 clocks = <&rcc !! 590 };
464 clock-names = <<
465 dmas = <&dmamu <<
466 <&dmamu <<
467 <&dmamu <<
468 <&dmamu <<
469 <&dmamu <<
470 <&dmamu <<
471 dma-names = "c <<
472 access-control <<
473 status = "disa <<
474 <<
475 pwm { <<
476 compat <<
477 #pwm-c <<
478 status <<
479 }; <<
480 591
481 timer@2 { !! 592 dac: dac@40017000 {
482 compat !! 593 compatible = "st,stm32h7-dac-core";
483 reg = !! 594 reg = <0x40017000 0x400>;
484 status !! 595 clocks = <&rcc DAC12>;
485 }; !! 596 clock-names = "pclk";
>> 597 #address-cells = <1>;
>> 598 #size-cells = <0>;
>> 599 status = "disabled";
486 600
487 counter { !! 601 dac1: dac@1 {
488 compat !! 602 compatible = "st,stm32-dac";
489 status !! 603 #io-channel-cells = <1>;
490 }; !! 604 reg = <1>;
>> 605 status = "disabled";
491 }; 606 };
492 607
493 timers4: timer@4000200 !! 608 dac2: dac@2 {
494 #address-cells !! 609 compatible = "st,stm32-dac";
495 #size-cells = !! 610 #io-channel-cells = <1>;
496 compatible = " !! 611 reg = <2>;
497 reg = <0x40002 !! 612 status = "disabled";
498 interrupts = < <<
499 interrupt-name <<
500 clocks = <&rcc <<
501 clock-names = <<
502 dmas = <&dmamu <<
503 <&dmamu <<
504 <&dmamu <<
505 <&dmamu <<
506 dma-names = "c <<
507 access-control <<
508 status = "disa <<
509 <<
510 pwm { <<
511 compat <<
512 #pwm-c <<
513 status <<
514 }; <<
515 <<
516 timer@3 { <<
517 compat <<
518 reg = <<
519 status <<
520 }; <<
521 <<
522 counter { <<
523 compat <<
524 status <<
525 }; <<
526 }; 613 };
>> 614 };
527 615
528 timers5: timer@4000300 !! 616 uart7: serial@40018000 {
529 #address-cells !! 617 compatible = "st,stm32h7-uart";
530 #size-cells = !! 618 reg = <0x40018000 0x400>;
531 compatible = " !! 619 interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
532 reg = <0x40003 !! 620 clocks = <&rcc UART7_K>;
533 interrupts = < !! 621 wakeup-source;
534 interrupt-name !! 622 dmas = <&dmamux1 79 0x400 0x15>,
535 clocks = <&rcc !! 623 <&dmamux1 80 0x400 0x11>;
536 clock-names = !! 624 dma-names = "rx", "tx";
537 dmas = <&dmamu !! 625 status = "disabled";
538 <&dmamu !! 626 };
539 <&dmamu <<
540 <&dmamu <<
541 <&dmamu <<
542 <&dmamu <<
543 dma-names = "c <<
544 access-control <<
545 status = "disa <<
546 <<
547 pwm { <<
548 compat <<
549 #pwm-c <<
550 status <<
551 }; <<
552 627
553 timer@4 { !! 628 uart8: serial@40019000 {
554 compat !! 629 compatible = "st,stm32h7-uart";
555 reg = !! 630 reg = <0x40019000 0x400>;
556 status !! 631 interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
557 }; !! 632 clocks = <&rcc UART8_K>;
>> 633 wakeup-source;
>> 634 dmas = <&dmamux1 81 0x400 0x15>,
>> 635 <&dmamux1 82 0x400 0x11>;
>> 636 dma-names = "rx", "tx";
>> 637 status = "disabled";
>> 638 };
558 639
559 counter { !! 640 timers1: timer@44000000 {
560 compat !! 641 #address-cells = <1>;
561 status !! 642 #size-cells = <0>;
562 }; !! 643 compatible = "st,stm32-timers";
563 }; !! 644 reg = <0x44000000 0x400>;
>> 645 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
>> 646 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
>> 647 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
>> 648 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
>> 649 interrupt-names = "brk", "up", "trg-com", "cc";
>> 650 clocks = <&rcc TIM1_K>;
>> 651 clock-names = "int";
>> 652 dmas = <&dmamux1 11 0x400 0x1>,
>> 653 <&dmamux1 12 0x400 0x1>,
>> 654 <&dmamux1 13 0x400 0x1>,
>> 655 <&dmamux1 14 0x400 0x1>,
>> 656 <&dmamux1 15 0x400 0x1>,
>> 657 <&dmamux1 16 0x400 0x1>,
>> 658 <&dmamux1 17 0x400 0x1>;
>> 659 dma-names = "ch1", "ch2", "ch3", "ch4",
>> 660 "up", "trig", "com";
>> 661 status = "disabled";
564 662
565 timers6: timer@4000400 !! 663 pwm {
566 #address-cells !! 664 compatible = "st,stm32-pwm";
567 #size-cells = !! 665 #pwm-cells = <3>;
568 compatible = " <<
569 reg = <0x40004 <<
570 interrupts = < <<
571 interrupt-name <<
572 clocks = <&rcc <<
573 clock-names = <<
574 dmas = <&dmamu <<
575 dma-names = "u <<
576 access-control <<
577 status = "disa 666 status = "disabled";
578 <<
579 timer@5 { <<
580 compat <<
581 reg = <<
582 status <<
583 }; <<
584 }; 667 };
585 668
586 timers7: timer@4000500 !! 669 timer@0 {
587 #address-cells !! 670 compatible = "st,stm32h7-timer-trigger";
588 #size-cells = !! 671 reg = <0>;
589 compatible = " <<
590 reg = <0x40005 <<
591 interrupts = < <<
592 interrupt-name <<
593 clocks = <&rcc <<
594 clock-names = <<
595 dmas = <&dmamu <<
596 dma-names = "u <<
597 access-control <<
598 status = "disa 672 status = "disabled";
599 <<
600 timer@6 { <<
601 compat <<
602 reg = <<
603 status <<
604 }; <<
605 }; 673 };
606 674
607 timers12: timer@400060 !! 675 counter {
608 #address-cells !! 676 compatible = "st,stm32-timer-counter";
609 #size-cells = <<
610 compatible = " <<
611 reg = <0x40006 <<
612 interrupts = < <<
613 interrupt-name <<
614 clocks = <&rcc <<
615 clock-names = <<
616 access-control <<
617 status = "disa 677 status = "disabled";
>> 678 };
>> 679 };
618 680
619 pwm { !! 681 timers8: timer@44001000 {
620 compat !! 682 #address-cells = <1>;
621 #pwm-c !! 683 #size-cells = <0>;
622 status !! 684 compatible = "st,stm32-timers";
623 }; !! 685 reg = <0x44001000 0x400>;
>> 686 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
>> 687 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
>> 688 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
>> 689 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
>> 690 interrupt-names = "brk", "up", "trg-com", "cc";
>> 691 clocks = <&rcc TIM8_K>;
>> 692 clock-names = "int";
>> 693 dmas = <&dmamux1 47 0x400 0x1>,
>> 694 <&dmamux1 48 0x400 0x1>,
>> 695 <&dmamux1 49 0x400 0x1>,
>> 696 <&dmamux1 50 0x400 0x1>,
>> 697 <&dmamux1 51 0x400 0x1>,
>> 698 <&dmamux1 52 0x400 0x1>,
>> 699 <&dmamux1 53 0x400 0x1>;
>> 700 dma-names = "ch1", "ch2", "ch3", "ch4",
>> 701 "up", "trig", "com";
>> 702 status = "disabled";
624 703
625 timer@11 { !! 704 pwm {
626 compat !! 705 compatible = "st,stm32-pwm";
627 reg = !! 706 #pwm-cells = <3>;
628 status !! 707 status = "disabled";
629 }; <<
630 }; 708 };
631 709
632 timers13: timer@400070 !! 710 timer@7 {
633 #address-cells !! 711 compatible = "st,stm32h7-timer-trigger";
634 #size-cells = !! 712 reg = <7>;
635 compatible = " <<
636 reg = <0x40007 <<
637 interrupts = < <<
638 interrupt-name <<
639 clocks = <&rcc <<
640 clock-names = <<
641 access-control <<
642 status = "disa 713 status = "disabled";
643 <<
644 pwm { <<
645 compat <<
646 #pwm-c <<
647 status <<
648 }; <<
649 <<
650 timer@12 { <<
651 compat <<
652 reg = <<
653 status <<
654 }; <<
655 }; 714 };
656 715
657 timers14: timer@400080 !! 716 counter {
658 #address-cells !! 717 compatible = "st,stm32-timer-counter";
659 #size-cells = <<
660 compatible = " <<
661 reg = <0x40008 <<
662 interrupts = < <<
663 interrupt-name <<
664 clocks = <&rcc <<
665 clock-names = <<
666 access-control <<
667 status = "disa 718 status = "disabled";
668 <<
669 pwm { <<
670 compat <<
671 #pwm-c <<
672 status <<
673 }; <<
674 <<
675 timer@13 { <<
676 compat <<
677 reg = <<
678 status <<
679 }; <<
680 }; 719 };
>> 720 };
681 721
682 lptimer1: timer@400090 !! 722 usart6: serial@44003000 {
683 #address-cells !! 723 compatible = "st,stm32h7-uart";
684 #size-cells = !! 724 reg = <0x44003000 0x400>;
685 compatible = " !! 725 interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
686 reg = <0x40009 !! 726 clocks = <&rcc USART6_K>;
687 interrupts-ext !! 727 wakeup-source;
688 clocks = <&rcc !! 728 dmas = <&dmamux1 71 0x400 0x15>,
689 clock-names = !! 729 <&dmamux1 72 0x400 0x11>;
690 wakeup-source; !! 730 dma-names = "rx", "tx";
691 access-control !! 731 status = "disabled";
692 status = "disa !! 732 };
693 733
694 pwm { !! 734 spi1: spi@44004000 {
695 compat !! 735 #address-cells = <1>;
696 #pwm-c !! 736 #size-cells = <0>;
697 status !! 737 compatible = "st,stm32h7-spi";
698 }; !! 738 reg = <0x44004000 0x400>;
>> 739 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
>> 740 clocks = <&rcc SPI1_K>;
>> 741 resets = <&rcc SPI1_R>;
>> 742 dmas = <&dmamux1 37 0x400 0x05>,
>> 743 <&dmamux1 38 0x400 0x05>;
>> 744 dma-names = "rx", "tx";
>> 745 status = "disabled";
>> 746 };
699 747
700 trigger@0 { !! 748 i2s1: audio-controller@44004000 {
701 compat !! 749 compatible = "st,stm32h7-i2s";
702 reg = !! 750 #sound-dai-cells = <0>;
703 status !! 751 reg = <0x44004000 0x400>;
704 }; !! 752 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
>> 753 dmas = <&dmamux1 37 0x400 0x01>,
>> 754 <&dmamux1 38 0x400 0x01>;
>> 755 dma-names = "rx", "tx";
>> 756 status = "disabled";
>> 757 };
705 758
706 counter { !! 759 spi4: spi@44005000 {
707 compat !! 760 #address-cells = <1>;
708 status !! 761 #size-cells = <0>;
709 }; !! 762 compatible = "st,stm32h7-spi";
710 }; !! 763 reg = <0x44005000 0x400>;
>> 764 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
>> 765 clocks = <&rcc SPI4_K>;
>> 766 resets = <&rcc SPI4_R>;
>> 767 dmas = <&dmamux1 83 0x400 0x05>,
>> 768 <&dmamux1 84 0x400 0x05>;
>> 769 dma-names = "rx", "tx";
>> 770 status = "disabled";
>> 771 };
711 772
712 i2s2: audio-controller !! 773 timers15: timer@44006000 {
713 compatible = " !! 774 #address-cells = <1>;
714 #sound-dai-cel !! 775 #size-cells = <0>;
715 reg = <0x4000b !! 776 compatible = "st,stm32-timers";
716 interrupts = < !! 777 reg = <0x44006000 0x400>;
717 dmas = <&dmamu !! 778 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
718 <&dmamu !! 779 interrupt-names = "global";
719 dma-names = "r !! 780 clocks = <&rcc TIM15_K>;
720 access-control !! 781 clock-names = "int";
>> 782 dmas = <&dmamux1 105 0x400 0x1>,
>> 783 <&dmamux1 106 0x400 0x1>,
>> 784 <&dmamux1 107 0x400 0x1>,
>> 785 <&dmamux1 108 0x400 0x1>;
>> 786 dma-names = "ch1", "up", "trig", "com";
>> 787 status = "disabled";
>> 788
>> 789 pwm {
>> 790 compatible = "st,stm32-pwm";
>> 791 #pwm-cells = <3>;
721 status = "disa 792 status = "disabled";
722 }; 793 };
723 794
724 spi2: spi@4000b000 { !! 795 timer@14 {
725 #address-cells !! 796 compatible = "st,stm32h7-timer-trigger";
726 #size-cells = !! 797 reg = <14>;
727 compatible = " <<
728 reg = <0x4000b <<
729 interrupts = < <<
730 clocks = <&rcc <<
731 resets = <&rcc <<
732 dmas = <&dmamu <<
733 <&dmamu <<
734 dma-names = "r <<
735 access-control <<
736 status = "disa 798 status = "disabled";
737 }; 799 };
>> 800 };
738 801
739 i2s3: audio-controller !! 802 timers16: timer@44007000 {
740 compatible = " !! 803 #address-cells = <1>;
741 #sound-dai-cel !! 804 #size-cells = <0>;
742 reg = <0x4000c !! 805 compatible = "st,stm32-timers";
743 interrupts = < !! 806 reg = <0x44007000 0x400>;
744 dmas = <&dmamu !! 807 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
745 <&dmamu !! 808 interrupt-names = "global";
746 dma-names = "r !! 809 clocks = <&rcc TIM16_K>;
747 access-control !! 810 clock-names = "int";
>> 811 dmas = <&dmamux1 109 0x400 0x1>,
>> 812 <&dmamux1 110 0x400 0x1>;
>> 813 dma-names = "ch1", "up";
>> 814 status = "disabled";
>> 815
>> 816 pwm {
>> 817 compatible = "st,stm32-pwm";
>> 818 #pwm-cells = <3>;
748 status = "disa 819 status = "disabled";
749 }; 820 };
750 !! 821 timer@15 {
751 spi3: spi@4000c000 { !! 822 compatible = "st,stm32h7-timer-trigger";
752 #address-cells !! 823 reg = <15>;
753 #size-cells = <<
754 compatible = " <<
755 reg = <0x4000c <<
756 interrupts = < <<
757 clocks = <&rcc <<
758 resets = <&rcc <<
759 dmas = <&dmamu <<
760 <&dmamu <<
761 dma-names = "r <<
762 access-control <<
763 status = "disa 824 status = "disabled";
764 }; 825 };
>> 826 };
765 827
766 spdifrx: audio-control !! 828 timers17: timer@44008000 {
767 compatible = " !! 829 #address-cells = <1>;
768 #sound-dai-cel !! 830 #size-cells = <0>;
769 reg = <0x4000d !! 831 compatible = "st,stm32-timers";
770 clocks = <&rcc !! 832 reg = <0x44008000 0x400>;
771 clock-names = !! 833 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
772 interrupts = < !! 834 interrupt-names = "global";
773 dmas = <&dmamu !! 835 clocks = <&rcc TIM17_K>;
774 <&dmamu !! 836 clock-names = "int";
775 dma-names = "r !! 837 dmas = <&dmamux1 111 0x400 0x1>,
776 access-control !! 838 <&dmamux1 112 0x400 0x1>;
777 status = "disa !! 839 dma-names = "ch1", "up";
778 }; !! 840 status = "disabled";
779 !! 841
780 usart2: serial@4000e00 !! 842 pwm {
781 compatible = " !! 843 compatible = "st,stm32-pwm";
782 reg = <0x4000e !! 844 #pwm-cells = <3>;
783 interrupts-ext <<
784 clocks = <&rcc <<
785 wakeup-source; <<
786 dmas = <&dmamu <<
787 <&dmamu <<
788 dma-names = "r <<
789 access-control <<
790 status = "disa <<
791 }; <<
792 <<
793 usart3: serial@4000f00 <<
794 compatible = " <<
795 reg = <0x4000f <<
796 interrupts-ext <<
797 clocks = <&rcc <<
798 wakeup-source; <<
799 dmas = <&dmamu <<
800 <&dmamu <<
801 dma-names = "r <<
802 access-control <<
803 status = "disa <<
804 }; <<
805 <<
806 uart4: serial@40010000 <<
807 compatible = " <<
808 reg = <0x40010 <<
809 interrupts-ext <<
810 clocks = <&rcc <<
811 wakeup-source; <<
812 dmas = <&dmamu <<
813 <&dmamu <<
814 dma-names = "r <<
815 access-control <<
816 status = "disa <<
817 }; <<
818 <<
819 uart5: serial@40011000 <<
820 compatible = " <<
821 reg = <0x40011 <<
822 interrupts-ext <<
823 clocks = <&rcc <<
824 wakeup-source; <<
825 dmas = <&dmamu <<
826 <&dmamu <<
827 dma-names = "r <<
828 access-control <<
829 status = "disa <<
830 }; <<
831 <<
832 i2c1: i2c@40012000 { <<
833 compatible = " <<
834 reg = <0x40012 <<
835 interrupt-name <<
836 interrupts = < <<
837 < <<
838 clocks = <&rcc <<
839 resets = <&rcc <<
840 #address-cells <<
841 #size-cells = <<
842 st,syscfg-fmp <<
843 wakeup-source; <<
844 i2c-analog-fil <<
845 access-control <<
846 status = "disa 845 status = "disabled";
847 }; 846 };
848 847
849 i2c2: i2c@40013000 { !! 848 timer@16 {
850 compatible = " !! 849 compatible = "st,stm32h7-timer-trigger";
851 reg = <0x40013 !! 850 reg = <16>;
852 interrupt-name <<
853 interrupts = < <<
854 < <<
855 clocks = <&rcc <<
856 resets = <&rcc <<
857 #address-cells <<
858 #size-cells = <<
859 st,syscfg-fmp <<
860 wakeup-source; <<
861 i2c-analog-fil <<
862 access-control <<
863 status = "disa 851 status = "disabled";
864 }; 852 };
>> 853 };
865 854
866 i2c3: i2c@40014000 { !! 855 spi5: spi@44009000 {
867 compatible = " !! 856 #address-cells = <1>;
868 reg = <0x40014 !! 857 #size-cells = <0>;
869 interrupt-name !! 858 compatible = "st,stm32h7-spi";
870 interrupts = < !! 859 reg = <0x44009000 0x400>;
871 < !! 860 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
872 clocks = <&rcc !! 861 clocks = <&rcc SPI5_K>;
873 resets = <&rcc !! 862 resets = <&rcc SPI5_R>;
874 #address-cells !! 863 dmas = <&dmamux1 85 0x400 0x05>,
875 #size-cells = !! 864 <&dmamux1 86 0x400 0x05>;
876 st,syscfg-fmp !! 865 dma-names = "rx", "tx";
877 wakeup-source; !! 866 status = "disabled";
878 i2c-analog-fil !! 867 };
879 access-control !! 868
>> 869 sai1: sai@4400a000 {
>> 870 compatible = "st,stm32h7-sai";
>> 871 #address-cells = <1>;
>> 872 #size-cells = <1>;
>> 873 ranges = <0 0x4400a000 0x400>;
>> 874 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
>> 875 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
>> 876 resets = <&rcc SAI1_R>;
>> 877 status = "disabled";
>> 878
>> 879 sai1a: audio-controller@4400a004 {
>> 880 #sound-dai-cells = <0>;
>> 881
>> 882 compatible = "st,stm32-sai-sub-a";
>> 883 reg = <0x4 0x20>;
>> 884 clocks = <&rcc SAI1_K>;
>> 885 clock-names = "sai_ck";
>> 886 dmas = <&dmamux1 87 0x400 0x01>;
880 status = "disa 887 status = "disabled";
881 }; 888 };
882 889
883 i2c5: i2c@40015000 { !! 890 sai1b: audio-controller@4400a024 {
884 compatible = " !! 891 #sound-dai-cells = <0>;
885 reg = <0x40015 !! 892 compatible = "st,stm32-sai-sub-b";
886 interrupt-name !! 893 reg = <0x24 0x20>;
887 interrupts = < !! 894 clocks = <&rcc SAI1_K>;
888 < !! 895 clock-names = "sai_ck";
889 clocks = <&rcc !! 896 dmas = <&dmamux1 88 0x400 0x01>;
890 resets = <&rcc <<
891 #address-cells <<
892 #size-cells = <<
893 st,syscfg-fmp <<
894 wakeup-source; <<
895 i2c-analog-fil <<
896 access-control <<
897 status = "disa 897 status = "disabled";
898 }; 898 };
>> 899 };
899 900
900 cec: cec@40016000 { !! 901 sai2: sai@4400b000 {
901 compatible = " !! 902 compatible = "st,stm32h7-sai";
902 reg = <0x40016 !! 903 #address-cells = <1>;
903 interrupts = < !! 904 #size-cells = <1>;
904 clocks = <&rcc !! 905 ranges = <0 0x4400b000 0x400>;
905 clock-names = !! 906 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
906 access-control !! 907 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
>> 908 resets = <&rcc SAI2_R>;
>> 909 status = "disabled";
>> 910
>> 911 sai2a: audio-controller@4400b004 {
>> 912 #sound-dai-cells = <0>;
>> 913 compatible = "st,stm32-sai-sub-a";
>> 914 reg = <0x4 0x20>;
>> 915 clocks = <&rcc SAI2_K>;
>> 916 clock-names = "sai_ck";
>> 917 dmas = <&dmamux1 89 0x400 0x01>;
907 status = "disa 918 status = "disabled";
908 }; 919 };
909 920
910 dac: dac@40017000 { !! 921 sai2b: audio-controller@4400b024 {
911 compatible = " !! 922 #sound-dai-cells = <0>;
912 reg = <0x40017 !! 923 compatible = "st,stm32-sai-sub-b";
913 clocks = <&rcc !! 924 reg = <0x24 0x20>;
914 clock-names = !! 925 clocks = <&rcc SAI2_K>;
915 #address-cells !! 926 clock-names = "sai_ck";
916 #size-cells = !! 927 dmas = <&dmamux1 90 0x400 0x01>;
917 access-control <<
918 status = "disa 928 status = "disabled";
919 <<
920 dac1: dac@1 { <<
921 compat <<
922 #io-ch <<
923 reg = <<
924 status <<
925 }; <<
926 <<
927 dac2: dac@2 { <<
928 compat <<
929 #io-ch <<
930 reg = <<
931 status <<
932 }; <<
933 }; 929 };
>> 930 };
934 931
935 uart7: serial@40018000 !! 932 sai3: sai@4400c000 {
936 compatible = " !! 933 compatible = "st,stm32h7-sai";
937 reg = <0x40018 !! 934 #address-cells = <1>;
938 interrupts-ext !! 935 #size-cells = <1>;
939 clocks = <&rcc !! 936 ranges = <0 0x4400c000 0x400>;
940 wakeup-source; !! 937 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
941 dmas = <&dmamu !! 938 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
942 <&dmamu !! 939 resets = <&rcc SAI3_R>;
943 dma-names = "r !! 940 status = "disabled";
944 access-control !! 941
>> 942 sai3a: audio-controller@4400c004 {
>> 943 #sound-dai-cells = <0>;
>> 944 compatible = "st,stm32-sai-sub-a";
>> 945 reg = <0x04 0x20>;
>> 946 clocks = <&rcc SAI3_K>;
>> 947 clock-names = "sai_ck";
>> 948 dmas = <&dmamux1 113 0x400 0x01>;
945 status = "disa 949 status = "disabled";
946 }; 950 };
947 951
948 uart8: serial@40019000 !! 952 sai3b: audio-controller@4400c024 {
949 compatible = " !! 953 #sound-dai-cells = <0>;
950 reg = <0x40019 !! 954 compatible = "st,stm32-sai-sub-b";
951 interrupts-ext !! 955 reg = <0x24 0x20>;
952 clocks = <&rcc !! 956 clocks = <&rcc SAI3_K>;
953 wakeup-source; !! 957 clock-names = "sai_ck";
954 dmas = <&dmamu !! 958 dmas = <&dmamux1 114 0x400 0x01>;
955 <&dmamu <<
956 dma-names = "r <<
957 access-control <<
958 status = "disa 959 status = "disabled";
959 }; 960 };
>> 961 };
960 962
961 timers1: timer@4400000 !! 963 dfsdm: dfsdm@4400d000 {
962 #address-cells !! 964 compatible = "st,stm32mp1-dfsdm";
963 #size-cells = !! 965 reg = <0x4400d000 0x800>;
964 compatible = " !! 966 clocks = <&rcc DFSDM_K>;
965 reg = <0x44000 !! 967 clock-names = "dfsdm";
966 interrupts = < !! 968 #address-cells = <1>;
967 < !! 969 #size-cells = <0>;
968 < !! 970 status = "disabled";
969 < <<
970 interrupt-name <<
971 clocks = <&rcc <<
972 clock-names = <<
973 dmas = <&dmamu <<
974 <&dmamu <<
975 <&dmamu <<
976 <&dmamu <<
977 <&dmamu <<
978 <&dmamu <<
979 <&dmamu <<
980 dma-names = "c <<
981 "u <<
982 access-control <<
983 status = "disa <<
984 <<
985 pwm { <<
986 compat <<
987 #pwm-c <<
988 status <<
989 }; <<
990 <<
991 timer@0 { <<
992 compat <<
993 reg = <<
994 status <<
995 }; <<
996 971
997 counter { !! 972 dfsdm0: filter@0 {
998 compat !! 973 compatible = "st,stm32-dfsdm-adc";
999 status !! 974 #io-channel-cells = <1>;
1000 }; !! 975 reg = <0>;
>> 976 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
>> 977 dmas = <&dmamux1 101 0x400 0x01>;
>> 978 dma-names = "rx";
>> 979 status = "disabled";
1001 }; 980 };
1002 981
1003 timers8: timer@440010 !! 982 dfsdm1: filter@1 {
1004 #address-cell !! 983 compatible = "st,stm32-dfsdm-adc";
1005 #size-cells = !! 984 #io-channel-cells = <1>;
1006 compatible = !! 985 reg = <1>;
1007 reg = <0x4400 !! 986 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1008 interrupts = !! 987 dmas = <&dmamux1 102 0x400 0x01>;
1009 !! 988 dma-names = "rx";
1010 !! 989 status = "disabled";
1011 <<
1012 interrupt-nam <<
1013 clocks = <&rc <<
1014 clock-names = <<
1015 dmas = <&dmam <<
1016 <&dmam <<
1017 <&dmam <<
1018 <&dmam <<
1019 <&dmam <<
1020 <&dmam <<
1021 <&dmam <<
1022 dma-names = " <<
1023 " <<
1024 access-contro <<
1025 status = "dis <<
1026 <<
1027 pwm { <<
1028 compa <<
1029 #pwm- <<
1030 statu <<
1031 }; <<
1032 <<
1033 timer@7 { <<
1034 compa <<
1035 reg = <<
1036 statu <<
1037 }; <<
1038 <<
1039 counter { <<
1040 compa <<
1041 statu <<
1042 }; <<
1043 }; 990 };
1044 991
1045 usart6: serial@440030 !! 992 dfsdm2: filter@2 {
1046 compatible = !! 993 compatible = "st,stm32-dfsdm-adc";
1047 reg = <0x4400 !! 994 #io-channel-cells = <1>;
1048 interrupts-ex !! 995 reg = <2>;
1049 clocks = <&rc !! 996 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1050 wakeup-source !! 997 dmas = <&dmamux1 103 0x400 0x01>;
1051 dmas = <&dmam !! 998 dma-names = "rx";
1052 <&dmamux1 72 <<
1053 dma-names = " <<
1054 access-contro <<
1055 status = "dis 999 status = "disabled";
1056 }; 1000 };
1057 1001
1058 i2s1: audio-controlle !! 1002 dfsdm3: filter@3 {
1059 compatible = !! 1003 compatible = "st,stm32-dfsdm-adc";
1060 #sound-dai-ce !! 1004 #io-channel-cells = <1>;
1061 reg = <0x4400 !! 1005 reg = <3>;
1062 interrupts = !! 1006 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1063 dmas = <&dmam !! 1007 dmas = <&dmamux1 104 0x400 0x01>;
1064 <&dmamux1 38 !! 1008 dma-names = "rx";
1065 dma-names = " <<
1066 access-contro <<
1067 status = "dis 1009 status = "disabled";
1068 }; 1010 };
1069 1011
1070 spi1: spi@44004000 { !! 1012 dfsdm4: filter@4 {
1071 #address-cell !! 1013 compatible = "st,stm32-dfsdm-adc";
1072 #size-cells = !! 1014 #io-channel-cells = <1>;
1073 compatible = !! 1015 reg = <4>;
1074 reg = <0x4400 !! 1016 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
1075 interrupts = !! 1017 dmas = <&dmamux1 91 0x400 0x01>;
1076 clocks = <&rc !! 1018 dma-names = "rx";
1077 resets = <&rc <<
1078 dmas = <&dmam <<
1079 <&dmamux1 38 <<
1080 dma-names = " <<
1081 access-contro <<
1082 status = "dis 1019 status = "disabled";
1083 }; 1020 };
1084 1021
1085 spi4: spi@44005000 { !! 1022 dfsdm5: filter@5 {
1086 #address-cell !! 1023 compatible = "st,stm32-dfsdm-adc";
1087 #size-cells = !! 1024 #io-channel-cells = <1>;
1088 compatible = !! 1025 reg = <5>;
1089 reg = <0x4400 !! 1026 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
1090 interrupts = !! 1027 dmas = <&dmamux1 92 0x400 0x01>;
1091 clocks = <&rc !! 1028 dma-names = "rx";
1092 resets = <&rc <<
1093 dmas = <&dmam <<
1094 <&dmamux1 84 <<
1095 dma-names = " <<
1096 access-contro <<
1097 status = "dis 1029 status = "disabled";
1098 }; 1030 };
>> 1031 };
1099 1032
1100 timers15: timer@44006 !! 1033 dma1: dma-controller@48000000 {
1101 #address-cell !! 1034 compatible = "st,stm32-dma";
1102 #size-cells = !! 1035 reg = <0x48000000 0x400>;
1103 compatible = !! 1036 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
1104 reg = <0x4400 !! 1037 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1105 interrupts = !! 1038 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
1106 interrupt-nam !! 1039 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
1107 clocks = <&rc !! 1040 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
1108 clock-names = !! 1041 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
1109 dmas = <&dmam !! 1042 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
1110 <&dmam !! 1043 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1111 <&dmam !! 1044 clocks = <&rcc DMA1>;
1112 <&dmam !! 1045 resets = <&rcc DMA1_R>;
1113 dma-names = " !! 1046 #dma-cells = <4>;
1114 access-contro !! 1047 st,mem2mem;
1115 status = "dis !! 1048 dma-requests = <8>;
1116 !! 1049 };
1117 pwm { <<
1118 compa <<
1119 #pwm- <<
1120 statu <<
1121 }; <<
1122 1050
1123 timer@14 { !! 1051 dma2: dma-controller@48001000 {
1124 compa !! 1052 compatible = "st,stm32-dma";
1125 reg = !! 1053 reg = <0x48001000 0x400>;
1126 statu !! 1054 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1127 }; !! 1055 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1128 }; !! 1056 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
>> 1057 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
>> 1058 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
>> 1059 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
>> 1060 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
>> 1061 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
>> 1062 clocks = <&rcc DMA2>;
>> 1063 resets = <&rcc DMA2_R>;
>> 1064 #dma-cells = <4>;
>> 1065 st,mem2mem;
>> 1066 dma-requests = <8>;
>> 1067 };
>> 1068
>> 1069 dmamux1: dma-router@48002000 {
>> 1070 compatible = "st,stm32h7-dmamux";
>> 1071 reg = <0x48002000 0x40>;
>> 1072 #dma-cells = <3>;
>> 1073 dma-requests = <128>;
>> 1074 dma-masters = <&dma1 &dma2>;
>> 1075 dma-channels = <16>;
>> 1076 clocks = <&rcc DMAMUX>;
>> 1077 resets = <&rcc DMAMUX_R>;
>> 1078 };
>> 1079
>> 1080 adc: adc@48003000 {
>> 1081 compatible = "st,stm32mp1-adc-core";
>> 1082 reg = <0x48003000 0x400>;
>> 1083 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
>> 1084 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
>> 1085 clocks = <&rcc ADC12>, <&rcc ADC12_K>;
>> 1086 clock-names = "bus", "adc";
>> 1087 interrupt-controller;
>> 1088 st,syscfg = <&syscfg>;
>> 1089 #interrupt-cells = <1>;
>> 1090 #address-cells = <1>;
>> 1091 #size-cells = <0>;
>> 1092 status = "disabled";
1129 1093
1130 timers16: timer@44007 !! 1094 adc1: adc@0 {
>> 1095 compatible = "st,stm32mp1-adc";
>> 1096 #io-channel-cells = <1>;
1131 #address-cell 1097 #address-cells = <1>;
1132 #size-cells = 1098 #size-cells = <0>;
1133 compatible = !! 1099 reg = <0x0>;
1134 reg = <0x4400 !! 1100 interrupt-parent = <&adc>;
1135 interrupts = !! 1101 interrupts = <0>;
1136 interrupt-nam !! 1102 dmas = <&dmamux1 9 0x400 0x01>;
1137 clocks = <&rc !! 1103 dma-names = "rx";
1138 clock-names = !! 1104 status = "disabled";
1139 dmas = <&dmam <<
1140 <&dmamux1 110 <<
1141 dma-names = " <<
1142 access-contro <<
1143 status = "dis <<
1144 <<
1145 pwm { <<
1146 compa <<
1147 #pwm- <<
1148 statu <<
1149 }; <<
1150 timer@15 { <<
1151 compa <<
1152 reg = <<
1153 statu <<
1154 }; <<
1155 }; 1105 };
1156 1106
1157 timers17: timer@44008 !! 1107 adc2: adc@100 {
>> 1108 compatible = "st,stm32mp1-adc";
>> 1109 #io-channel-cells = <1>;
1158 #address-cell 1110 #address-cells = <1>;
1159 #size-cells = 1111 #size-cells = <0>;
1160 compatible = !! 1112 reg = <0x100>;
1161 reg = <0x4400 !! 1113 interrupt-parent = <&adc>;
1162 interrupts = !! 1114 interrupts = <1>;
1163 interrupt-nam !! 1115 dmas = <&dmamux1 10 0x400 0x01>;
1164 clocks = <&rc !! 1116 dma-names = "rx";
1165 clock-names = !! 1117 nvmem-cells = <&vrefint>;
1166 dmas = <&dmam !! 1118 nvmem-cell-names = "vrefint";
1167 <&dmamux1 112 !! 1119 status = "disabled";
1168 dma-names = " !! 1120 channel@13 {
1169 access-contro !! 1121 reg = <13>;
1170 status = "dis !! 1122 label = "vrefint";
1171 <<
1172 pwm { <<
1173 compa <<
1174 #pwm- <<
1175 statu <<
1176 }; 1123 };
1177 !! 1124 channel@14 {
1178 timer@16 { !! 1125 reg = <14>;
1179 compa !! 1126 label = "vddcore";
1180 reg = <<
1181 statu <<
1182 }; 1127 };
1183 }; 1128 };
>> 1129 };
1184 1130
1185 spi5: spi@44009000 { !! 1131 sdmmc3: mmc@48004000 {
1186 #address-cell !! 1132 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1187 #size-cells = !! 1133 arm,primecell-periphid = <0x00253180>;
1188 compatible = !! 1134 reg = <0x48004000 0x400>;
1189 reg = <0x4400 !! 1135 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1190 interrupts = !! 1136 clocks = <&rcc SDMMC3_K>;
1191 clocks = <&rc !! 1137 clock-names = "apb_pclk";
1192 resets = <&rc !! 1138 resets = <&rcc SDMMC3_R>;
1193 dmas = <&dmam !! 1139 cap-sd-highspeed;
1194 <&dmamux1 86 !! 1140 cap-mmc-highspeed;
1195 dma-names = " !! 1141 max-frequency = <120000000>;
1196 access-contro !! 1142 status = "disabled";
1197 status = "dis !! 1143 };
1198 }; <<
1199 1144
1200 sai1: sai@4400a000 { !! 1145 usbotg_hs: usb-otg@49000000 {
1201 compatible = !! 1146 compatible = "st,stm32mp15-hsotg", "snps,dwc2";
1202 #address-cell !! 1147 reg = <0x49000000 0x10000>;
1203 #size-cells = !! 1148 clocks = <&rcc USBO_K>, <&usbphyc>;
1204 ranges = <0 0 !! 1149 clock-names = "otg", "utmi";
1205 reg = <0x4400 !! 1150 resets = <&rcc USBO_R>;
1206 interrupts = !! 1151 reset-names = "dwc2";
1207 resets = <&rc !! 1152 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1208 access-contro !! 1153 g-rx-fifo-size = <512>;
1209 status = "dis !! 1154 g-np-tx-fifo-size = <32>;
1210 !! 1155 g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
1211 sai1a: audio- !! 1156 dr_mode = "otg";
1212 #soun !! 1157 otg-rev = <0x200>;
1213 !! 1158 usb33d-supply = <&usb33>;
1214 compa !! 1159 status = "disabled";
1215 reg = !! 1160 };
1216 clock <<
1217 clock <<
1218 dmas <<
1219 statu <<
1220 }; <<
1221 1161
1222 sai1b: audio- !! 1162 ipcc: mailbox@4c001000 {
1223 #soun !! 1163 compatible = "st,stm32mp1-ipcc";
1224 compa !! 1164 #mbox-cells = <1>;
1225 reg = !! 1165 reg = <0x4c001000 0x400>;
1226 clock !! 1166 st,proc-id = <0>;
1227 clock !! 1167 interrupts-extended =
1228 dmas !! 1168 <&exti 61 1>,
1229 statu !! 1169 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1230 }; !! 1170 interrupt-names = "rx", "tx";
1231 }; !! 1171 clocks = <&rcc IPCC>;
>> 1172 wakeup-source;
>> 1173 status = "disabled";
>> 1174 };
1232 1175
1233 sai2: sai@4400b000 { !! 1176 dcmi: dcmi@4c006000 {
1234 compatible = !! 1177 compatible = "st,stm32-dcmi";
1235 #address-cell !! 1178 reg = <0x4c006000 0x400>;
1236 #size-cells = !! 1179 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1237 ranges = <0 0 !! 1180 resets = <&rcc CAMITF_R>;
1238 reg = <0x4400 !! 1181 clocks = <&rcc DCMI>;
1239 interrupts = !! 1182 clock-names = "mclk";
1240 resets = <&rc !! 1183 dmas = <&dmamux1 75 0x400 0x01>;
1241 access-contro !! 1184 dma-names = "tx";
1242 status = "dis !! 1185 status = "disabled";
1243 !! 1186 };
1244 sai2a: audio- <<
1245 #soun <<
1246 compa <<
1247 reg = <<
1248 clock <<
1249 clock <<
1250 dmas <<
1251 statu <<
1252 }; <<
1253 1187
1254 sai2b: audio- !! 1188 rcc: rcc@50000000 {
1255 #soun !! 1189 compatible = "st,stm32mp1-rcc", "syscon";
1256 compa !! 1190 reg = <0x50000000 0x1000>;
1257 reg = !! 1191 #clock-cells = <1>;
1258 clock !! 1192 #reset-cells = <1>;
1259 clock !! 1193 };
1260 dmas <<
1261 statu <<
1262 }; <<
1263 }; <<
1264 1194
1265 sai3: sai@4400c000 { !! 1195 pwr_regulators: pwr@50001000 {
1266 compatible = !! 1196 compatible = "st,stm32mp1,pwr-reg";
1267 #address-cell !! 1197 reg = <0x50001000 0x10>;
1268 #size-cells = <<
1269 ranges = <0 0 <<
1270 reg = <0x4400 <<
1271 interrupts = <<
1272 resets = <&rc <<
1273 access-contro <<
1274 status = "dis <<
1275 <<
1276 sai3a: audio- <<
1277 #soun <<
1278 compa <<
1279 reg = <<
1280 clock <<
1281 clock <<
1282 dmas <<
1283 statu <<
1284 }; <<
1285 1198
1286 sai3b: audio- !! 1199 reg11: reg11 {
1287 #soun !! 1200 regulator-name = "reg11";
1288 compa !! 1201 regulator-min-microvolt = <1100000>;
1289 reg = !! 1202 regulator-max-microvolt = <1100000>;
1290 clock <<
1291 clock <<
1292 dmas <<
1293 statu <<
1294 }; <<
1295 }; 1203 };
1296 1204
1297 dfsdm: dfsdm@4400d000 !! 1205 reg18: reg18 {
1298 compatible = !! 1206 regulator-name = "reg18";
1299 reg = <0x4400 !! 1207 regulator-min-microvolt = <1800000>;
1300 clocks = <&rc !! 1208 regulator-max-microvolt = <1800000>;
1301 clock-names = !! 1209 };
1302 #address-cell <<
1303 #size-cells = <<
1304 access-contro <<
1305 status = "dis <<
1306 1210
1307 dfsdm0: filte !! 1211 usb33: usb33 {
1308 compa !! 1212 regulator-name = "usb33";
1309 #io-c !! 1213 regulator-min-microvolt = <3300000>;
1310 reg = !! 1214 regulator-max-microvolt = <3300000>;
1311 inter !! 1215 };
1312 dmas !! 1216 };
1313 dma-n <<
1314 statu <<
1315 }; <<
1316 1217
1317 dfsdm1: filte !! 1218 pwr_mcu: pwr_mcu@50001014 {
1318 compa !! 1219 compatible = "st,stm32mp151-pwr-mcu", "syscon";
1319 #io-c !! 1220 reg = <0x50001014 0x4>;
1320 reg = !! 1221 };
1321 inter <<
1322 dmas <<
1323 dma-n <<
1324 statu <<
1325 }; <<
1326 1222
1327 dfsdm2: filte !! 1223 exti: interrupt-controller@5000d000 {
1328 compa !! 1224 compatible = "st,stm32mp1-exti", "syscon";
1329 #io-c !! 1225 interrupt-controller;
1330 reg = !! 1226 #interrupt-cells = <2>;
1331 inter !! 1227 reg = <0x5000d000 0x400>;
1332 dmas !! 1228 };
1333 dma-n <<
1334 statu <<
1335 }; <<
1336 1229
1337 dfsdm3: filte !! 1230 syscfg: syscon@50020000 {
1338 compa !! 1231 compatible = "st,stm32mp157-syscfg", "syscon";
1339 #io-c !! 1232 reg = <0x50020000 0x400>;
1340 reg = !! 1233 clocks = <&rcc SYSCFG>;
1341 inter !! 1234 };
1342 dmas <<
1343 dma-n <<
1344 statu <<
1345 }; <<
1346 1235
1347 dfsdm4: filte !! 1236 lptimer2: timer@50021000 {
1348 compa !! 1237 #address-cells = <1>;
1349 #io-c !! 1238 #size-cells = <0>;
1350 reg = !! 1239 compatible = "st,stm32-lptimer";
1351 inter !! 1240 reg = <0x50021000 0x400>;
1352 dmas !! 1241 interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
1353 dma-n !! 1242 clocks = <&rcc LPTIM2_K>;
1354 statu !! 1243 clock-names = "mux";
1355 }; !! 1244 wakeup-source;
>> 1245 status = "disabled";
1356 1246
1357 dfsdm5: filte !! 1247 pwm {
1358 compa !! 1248 compatible = "st,stm32-pwm-lp";
1359 #io-c !! 1249 #pwm-cells = <3>;
1360 reg = !! 1250 status = "disabled";
1361 inter <<
1362 dmas <<
1363 dma-n <<
1364 statu <<
1365 }; <<
1366 }; 1251 };
1367 1252
1368 dma1: dma-controller@ !! 1253 trigger@1 {
1369 compatible = !! 1254 compatible = "st,stm32-lptimer-trigger";
1370 reg = <0x4800 !! 1255 reg = <1>;
1371 interrupts = <<
1372 <<
1373 <<
1374 <<
1375 <<
1376 <<
1377 <<
1378 <<
1379 clocks = <&rc <<
1380 resets = <&rc <<
1381 #dma-cells = <<
1382 st,mem2mem; <<
1383 dma-requests <<
1384 access-contro <<
1385 }; <<
1386 <<
1387 dma2: dma-controller@ <<
1388 compatible = <<
1389 reg = <0x4800 <<
1390 interrupts = <<
1391 <<
1392 <<
1393 <<
1394 <<
1395 <<
1396 <<
1397 <<
1398 clocks = <&rc <<
1399 resets = <&rc <<
1400 #dma-cells = <<
1401 st,mem2mem; <<
1402 dma-requests <<
1403 access-contro <<
1404 }; <<
1405 <<
1406 dmamux1: dma-router@4 <<
1407 compatible = <<
1408 reg = <0x4800 <<
1409 #dma-cells = <<
1410 dma-requests <<
1411 dma-masters = <<
1412 dma-channels <<
1413 clocks = <&rc <<
1414 resets = <&rc <<
1415 access-contro <<
1416 }; <<
1417 <<
1418 adc: adc@48003000 { <<
1419 compatible = <<
1420 reg = <0x4800 <<
1421 interrupts = <<
1422 <<
1423 clocks = <&rc <<
1424 clock-names = <<
1425 interrupt-con <<
1426 st,syscfg = < <<
1427 #interrupt-ce <<
1428 #address-cell <<
1429 #size-cells = <<
1430 access-contro <<
1431 status = "dis 1256 status = "disabled";
1432 <<
1433 adc1: adc@0 { <<
1434 compa <<
1435 #io-c <<
1436 #addr <<
1437 #size <<
1438 reg = <<
1439 inter <<
1440 inter <<
1441 dmas <<
1442 dma-n <<
1443 statu <<
1444 }; <<
1445 <<
1446 adc2: adc@100 <<
1447 compa <<
1448 #io-c <<
1449 #addr <<
1450 #size <<
1451 reg = <<
1452 inter <<
1453 inter <<
1454 dmas <<
1455 dma-n <<
1456 nvmem <<
1457 nvmem <<
1458 statu <<
1459 chann <<
1460 <<
1461 <<
1462 }; <<
1463 chann <<
1464 <<
1465 <<
1466 }; <<
1467 }; <<
1468 }; 1257 };
1469 1258
1470 sdmmc3: mmc@48004000 !! 1259 counter {
1471 compatible = !! 1260 compatible = "st,stm32-lptimer-counter";
1472 arm,primecell <<
1473 reg = <0x4800 <<
1474 interrupts = <<
1475 clocks = <&rc <<
1476 clock-names = <<
1477 resets = <&rc <<
1478 cap-sd-highsp <<
1479 cap-mmc-highs <<
1480 max-frequency <<
1481 access-contro <<
1482 status = "dis 1261 status = "disabled";
1483 }; 1262 };
>> 1263 };
>> 1264
>> 1265 lptimer3: timer@50022000 {
>> 1266 #address-cells = <1>;
>> 1267 #size-cells = <0>;
>> 1268 compatible = "st,stm32-lptimer";
>> 1269 reg = <0x50022000 0x400>;
>> 1270 interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
>> 1271 clocks = <&rcc LPTIM3_K>;
>> 1272 clock-names = "mux";
>> 1273 wakeup-source;
>> 1274 status = "disabled";
1484 1275
1485 usbotg_hs: usb-otg@49 !! 1276 pwm {
1486 compatible = !! 1277 compatible = "st,stm32-pwm-lp";
1487 reg = <0x4900 !! 1278 #pwm-cells = <3>;
1488 clocks = <&rc <<
1489 clock-names = <<
1490 resets = <&rc <<
1491 reset-names = <<
1492 interrupts = <<
1493 g-rx-fifo-siz <<
1494 g-np-tx-fifo- <<
1495 g-tx-fifo-siz <<
1496 dr_mode = "ot <<
1497 otg-rev = <0x <<
1498 usb33d-supply <<
1499 access-contro <<
1500 status = "dis 1279 status = "disabled";
1501 }; 1280 };
1502 1281
1503 dcmi: dcmi@4c006000 { !! 1282 trigger@2 {
1504 compatible = !! 1283 compatible = "st,stm32-lptimer-trigger";
1505 reg = <0x4c00 !! 1284 reg = <2>;
1506 interrupts = <<
1507 resets = <&rc <<
1508 clocks = <&rc <<
1509 clock-names = <<
1510 dmas = <&dmam <<
1511 dma-names = " <<
1512 access-contro <<
1513 status = "dis 1285 status = "disabled";
1514 }; 1286 };
>> 1287 };
1515 1288
1516 lptimer2: timer@50021 !! 1289 lptimer4: timer@50023000 {
1517 #address-cell !! 1290 compatible = "st,stm32-lptimer";
1518 #size-cells = !! 1291 reg = <0x50023000 0x400>;
1519 compatible = !! 1292 interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
1520 reg = <0x5002 !! 1293 clocks = <&rcc LPTIM4_K>;
1521 interrupts-ex !! 1294 clock-names = "mux";
1522 clocks = <&rc !! 1295 wakeup-source;
1523 clock-names = !! 1296 status = "disabled";
1524 wakeup-source <<
1525 access-contro <<
1526 status = "dis <<
1527 1297
1528 pwm { !! 1298 pwm {
1529 compa !! 1299 compatible = "st,stm32-pwm-lp";
1530 #pwm- !! 1300 #pwm-cells = <3>;
1531 statu !! 1301 status = "disabled";
1532 }; !! 1302 };
>> 1303 };
1533 1304
1534 trigger@1 { !! 1305 lptimer5: timer@50024000 {
1535 compa !! 1306 compatible = "st,stm32-lptimer";
1536 reg = !! 1307 reg = <0x50024000 0x400>;
1537 statu !! 1308 interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
1538 }; !! 1309 clocks = <&rcc LPTIM5_K>;
>> 1310 clock-names = "mux";
>> 1311 wakeup-source;
>> 1312 status = "disabled";
1539 1313
1540 counter { !! 1314 pwm {
1541 compa !! 1315 compatible = "st,stm32-pwm-lp";
1542 statu !! 1316 #pwm-cells = <3>;
1543 }; !! 1317 status = "disabled";
1544 }; 1318 };
>> 1319 };
1545 1320
1546 lptimer3: timer@50022 !! 1321 vrefbuf: vrefbuf@50025000 {
1547 #address-cell !! 1322 compatible = "st,stm32-vrefbuf";
1548 #size-cells = !! 1323 reg = <0x50025000 0x8>;
1549 compatible = !! 1324 regulator-min-microvolt = <1500000>;
1550 reg = <0x5002 !! 1325 regulator-max-microvolt = <2500000>;
1551 interrupts-ex !! 1326 clocks = <&rcc VREF>;
1552 clocks = <&rc !! 1327 status = "disabled";
1553 clock-names = !! 1328 };
1554 wakeup-source <<
1555 access-contro <<
1556 status = "dis <<
1557 1329
1558 pwm { !! 1330 sai4: sai@50027000 {
1559 compa !! 1331 compatible = "st,stm32h7-sai";
1560 #pwm- !! 1332 #address-cells = <1>;
1561 statu !! 1333 #size-cells = <1>;
1562 }; !! 1334 ranges = <0 0x50027000 0x400>;
>> 1335 reg = <0x50027000 0x4>, <0x500273f0 0x10>;
>> 1336 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
>> 1337 resets = <&rcc SAI4_R>;
>> 1338 status = "disabled";
1563 1339
1564 trigger@2 { !! 1340 sai4a: audio-controller@50027004 {
1565 compa !! 1341 #sound-dai-cells = <0>;
1566 reg = !! 1342 compatible = "st,stm32-sai-sub-a";
1567 statu !! 1343 reg = <0x04 0x20>;
1568 }; !! 1344 clocks = <&rcc SAI4_K>;
>> 1345 clock-names = "sai_ck";
>> 1346 dmas = <&dmamux1 99 0x400 0x01>;
>> 1347 status = "disabled";
1569 }; 1348 };
1570 1349
1571 lptimer4: timer@50023 !! 1350 sai4b: audio-controller@50027024 {
1572 compatible = !! 1351 #sound-dai-cells = <0>;
1573 reg = <0x5002 !! 1352 compatible = "st,stm32-sai-sub-b";
1574 interrupts-ex !! 1353 reg = <0x24 0x20>;
1575 clocks = <&rc !! 1354 clocks = <&rcc SAI4_K>;
1576 clock-names = !! 1355 clock-names = "sai_ck";
1577 wakeup-source !! 1356 dmas = <&dmamux1 100 0x400 0x01>;
1578 access-contro <<
1579 status = "dis 1357 status = "disabled";
1580 <<
1581 pwm { <<
1582 compa <<
1583 #pwm- <<
1584 statu <<
1585 }; <<
1586 }; 1358 };
>> 1359 };
1587 1360
1588 lptimer5: timer@50024 !! 1361 dts: thermal@50028000 {
1589 compatible = !! 1362 compatible = "st,stm32-thermal";
1590 reg = <0x5002 !! 1363 reg = <0x50028000 0x100>;
1591 interrupts-ex !! 1364 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1592 clocks = <&rc !! 1365 clocks = <&rcc TMPSENS>;
1593 clock-names = !! 1366 clock-names = "pclk";
1594 wakeup-source !! 1367 #thermal-sensor-cells = <0>;
1595 access-contro !! 1368 status = "disabled";
1596 status = "dis !! 1369 };
1597 1370
1598 pwm { !! 1371 hash1: hash@54002000 {
1599 compa !! 1372 compatible = "st,stm32f756-hash";
1600 #pwm- !! 1373 reg = <0x54002000 0x400>;
1601 statu !! 1374 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1602 }; !! 1375 clocks = <&rcc HASH1>;
1603 }; !! 1376 resets = <&rcc HASH1_R>;
>> 1377 dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>;
>> 1378 dma-names = "in";
>> 1379 dma-maxburst = <2>;
>> 1380 status = "disabled";
>> 1381 };
1604 1382
1605 vrefbuf: vrefbuf@5002 !! 1383 rng1: rng@54003000 {
1606 compatible = !! 1384 compatible = "st,stm32-rng";
1607 reg = <0x5002 !! 1385 reg = <0x54003000 0x400>;
1608 regulator-min !! 1386 clocks = <&rcc RNG1_K>;
1609 regulator-max !! 1387 resets = <&rcc RNG1_R>;
1610 clocks = <&rc !! 1388 status = "disabled";
1611 access-contro !! 1389 };
1612 status = "dis <<
1613 }; <<
1614 1390
1615 sai4: sai@50027000 { !! 1391 mdma1: dma-controller@58000000 {
1616 compatible = !! 1392 compatible = "st,stm32h7-mdma";
1617 #address-cell !! 1393 reg = <0x58000000 0x1000>;
1618 #size-cells = !! 1394 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1619 ranges = <0 0 !! 1395 clocks = <&rcc MDMA>;
1620 reg = <0x5002 !! 1396 resets = <&rcc MDMA_R>;
1621 interrupts = !! 1397 #dma-cells = <5>;
1622 resets = <&rc !! 1398 dma-channels = <32>;
1623 access-contro !! 1399 dma-requests = <48>;
1624 status = "dis !! 1400 };
1625 <<
1626 sai4a: audio- <<
1627 #soun <<
1628 compa <<
1629 reg = <<
1630 clock <<
1631 clock <<
1632 dmas <<
1633 statu <<
1634 }; <<
1635 1401
1636 sai4b: audio- !! 1402 fmc: memory-controller@58002000 {
1637 #soun !! 1403 #address-cells = <2>;
1638 compa !! 1404 #size-cells = <1>;
1639 reg = !! 1405 compatible = "st,stm32mp1-fmc2-ebi";
1640 clock !! 1406 reg = <0x58002000 0x1000>;
1641 clock !! 1407 clocks = <&rcc FMC_K>;
1642 dmas !! 1408 resets = <&rcc FMC_R>;
1643 statu !! 1409 status = "disabled";
1644 }; <<
1645 }; <<
1646 1410
1647 hash1: hash@54002000 !! 1411 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
1648 compatible = !! 1412 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
1649 reg = <0x5400 !! 1413 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
1650 interrupts = !! 1414 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
1651 clocks = <&rc !! 1415 <4 0 0x80000000 0x10000000>; /* NAND */
1652 resets = <&rc !! 1416
1653 dmas = <&mdma !! 1417 nand-controller@4,0 {
1654 dma-names = " !! 1418 #address-cells = <1>;
1655 dma-maxburst !! 1419 #size-cells = <0>;
1656 access-contro !! 1420 compatible = "st,stm32mp1-fmc2-nfc";
>> 1421 reg = <4 0x00000000 0x1000>,
>> 1422 <4 0x08010000 0x1000>,
>> 1423 <4 0x08020000 0x1000>,
>> 1424 <4 0x01000000 0x1000>,
>> 1425 <4 0x09010000 0x1000>,
>> 1426 <4 0x09020000 0x1000>;
>> 1427 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
>> 1428 dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
>> 1429 <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
>> 1430 <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
>> 1431 dma-names = "tx", "rx", "ecc";
1657 status = "dis 1432 status = "disabled";
1658 }; 1433 };
>> 1434 };
1659 1435
1660 rng1: rng@54003000 { !! 1436 qspi: spi@58003000 {
1661 compatible = !! 1437 compatible = "st,stm32f469-qspi";
1662 reg = <0x5400 !! 1438 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1663 clocks = <&rc !! 1439 reg-names = "qspi", "qspi_mm";
1664 resets = <&rc !! 1440 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1665 access-contro !! 1441 dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>,
1666 status = "dis !! 1442 <&mdma1 22 0x2 0x10100008 0x0 0x0>;
1667 }; !! 1443 dma-names = "tx", "rx";
>> 1444 clocks = <&rcc QSPI_K>;
>> 1445 resets = <&rcc QSPI_R>;
>> 1446 #address-cells = <1>;
>> 1447 #size-cells = <0>;
>> 1448 status = "disabled";
>> 1449 };
1668 1450
1669 fmc: memory-controlle !! 1451 sdmmc1: mmc@58005000 {
1670 #address-cell !! 1452 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1671 #size-cells = !! 1453 arm,primecell-periphid = <0x00253180>;
1672 compatible = !! 1454 reg = <0x58005000 0x1000>;
1673 reg = <0x5800 !! 1455 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1674 clocks = <&rc !! 1456 clocks = <&rcc SDMMC1_K>;
1675 resets = <&rc !! 1457 clock-names = "apb_pclk";
1676 access-contro !! 1458 resets = <&rcc SDMMC1_R>;
1677 status = "dis !! 1459 cap-sd-highspeed;
1678 !! 1460 cap-mmc-highspeed;
1679 ranges = <0 0 !! 1461 max-frequency = <120000000>;
1680 <1 0 !! 1462 status = "disabled";
1681 <2 0 !! 1463 };
1682 <3 0 <<
1683 <4 0 <<
1684 <<
1685 nand-controll <<
1686 #addr <<
1687 #size <<
1688 compa <<
1689 reg = <<
1690 <<
1691 <<
1692 <<
1693 <<
1694 <<
1695 inter <<
1696 dmas <<
1697 <<
1698 <<
1699 dma-n <<
1700 statu <<
1701 }; <<
1702 }; <<
1703 1464
1704 qspi: spi@58003000 { !! 1465 sdmmc2: mmc@58007000 {
1705 compatible = !! 1466 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1706 reg = <0x5800 !! 1467 arm,primecell-periphid = <0x00253180>;
1707 reg-names = " !! 1468 reg = <0x58007000 0x1000>;
1708 interrupts = !! 1469 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1709 dmas = <&mdma !! 1470 clocks = <&rcc SDMMC2_K>;
1710 <&mdma !! 1471 clock-names = "apb_pclk";
1711 dma-names = " !! 1472 resets = <&rcc SDMMC2_R>;
1712 clocks = <&rc !! 1473 cap-sd-highspeed;
1713 resets = <&rc !! 1474 cap-mmc-highspeed;
1714 #address-cell !! 1475 max-frequency = <120000000>;
1715 #size-cells = !! 1476 status = "disabled";
1716 access-contro !! 1477 };
1717 status = "dis <<
1718 }; <<
1719 1478
1720 ethernet0: ethernet@5 !! 1479 crc1: crc@58009000 {
1721 compatible = !! 1480 compatible = "st,stm32f7-crc";
1722 reg = <0x5800 !! 1481 reg = <0x58009000 0x400>;
1723 reg-names = " !! 1482 clocks = <&rcc CRC1>;
1724 interrupts-ex !! 1483 status = "disabled";
1725 interrupt-nam !! 1484 };
1726 clock-names = <<
1727 <<
1728 <<
1729 <<
1730 <<
1731 <<
1732 clocks = <&rc <<
1733 <&rc <<
1734 <&rc <<
1735 <&rc <<
1736 <&rc <<
1737 <&rc <<
1738 st,syscon = < <<
1739 snps,mixed-bu <<
1740 snps,pbl = <2 <<
1741 snps,en-tx-lp <<
1742 snps,axi-conf <<
1743 snps,tso; <<
1744 access-contro <<
1745 status = "dis <<
1746 <<
1747 stmmac_axi_co <<
1748 snps, <<
1749 snps, <<
1750 snps, <<
1751 }; <<
1752 }; <<
1753 1485
1754 usart1: serial@5c0000 !! 1486 ethernet0: ethernet@5800a000 {
1755 compatible = !! 1487 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
1756 reg = <0x5c00 !! 1488 reg = <0x5800a000 0x2000>;
1757 interrupts-ex !! 1489 reg-names = "stmmaceth";
1758 clocks = <&rc !! 1490 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1759 wakeup-source !! 1491 interrupt-names = "macirq";
1760 access-contro !! 1492 clock-names = "stmmaceth",
1761 status = "dis !! 1493 "mac-clk-tx",
>> 1494 "mac-clk-rx",
>> 1495 "eth-ck",
>> 1496 "ptp_ref",
>> 1497 "ethstp";
>> 1498 clocks = <&rcc ETHMAC>,
>> 1499 <&rcc ETHTX>,
>> 1500 <&rcc ETHRX>,
>> 1501 <&rcc ETHCK_K>,
>> 1502 <&rcc ETHPTP_K>,
>> 1503 <&rcc ETHSTP>;
>> 1504 st,syscon = <&syscfg 0x4>;
>> 1505 snps,mixed-burst;
>> 1506 snps,pbl = <2>;
>> 1507 snps,en-tx-lpi-clockgating;
>> 1508 snps,axi-config = <&stmmac_axi_config_0>;
>> 1509 snps,tso;
>> 1510 status = "disabled";
>> 1511
>> 1512 stmmac_axi_config_0: stmmac-axi-config {
>> 1513 snps,wr_osr_lmt = <0x7>;
>> 1514 snps,rd_osr_lmt = <0x7>;
>> 1515 snps,blen = <0 0 0 0 16 8 4>;
1762 }; 1516 };
>> 1517 };
1763 1518
1764 spi6: spi@5c001000 { !! 1519 usbh_ohci: usb@5800c000 {
1765 #address-cell !! 1520 compatible = "generic-ohci";
1766 #size-cells = !! 1521 reg = <0x5800c000 0x1000>;
1767 compatible = !! 1522 clocks = <&usbphyc>, <&rcc USBH>;
1768 reg = <0x5c00 !! 1523 resets = <&rcc USBH_R>;
1769 interrupts = !! 1524 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1770 clocks = <&rc !! 1525 status = "disabled";
1771 resets = <&rc !! 1526 };
1772 dmas = <&mdma !! 1527
1773 <&mdma !! 1528 usbh_ehci: usb@5800d000 {
1774 access-contro !! 1529 compatible = "generic-ehci";
1775 dma-names = " !! 1530 reg = <0x5800d000 0x1000>;
1776 status = "dis !! 1531 clocks = <&usbphyc>, <&rcc USBH>;
>> 1532 resets = <&rcc USBH_R>;
>> 1533 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
>> 1534 companion = <&usbh_ohci>;
>> 1535 status = "disabled";
>> 1536 };
>> 1537
>> 1538 ltdc: display-controller@5a001000 {
>> 1539 compatible = "st,stm32-ltdc";
>> 1540 reg = <0x5a001000 0x400>;
>> 1541 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
>> 1542 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
>> 1543 clocks = <&rcc LTDC_PX>;
>> 1544 clock-names = "lcd";
>> 1545 resets = <&rcc LTDC_R>;
>> 1546 status = "disabled";
>> 1547 };
>> 1548
>> 1549 iwdg2: watchdog@5a002000 {
>> 1550 compatible = "st,stm32mp1-iwdg";
>> 1551 reg = <0x5a002000 0x400>;
>> 1552 clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
>> 1553 clock-names = "pclk", "lsi";
>> 1554 status = "disabled";
>> 1555 };
>> 1556
>> 1557 usbphyc: usbphyc@5a006000 {
>> 1558 #address-cells = <1>;
>> 1559 #size-cells = <0>;
>> 1560 #clock-cells = <0>;
>> 1561 compatible = "st,stm32mp1-usbphyc";
>> 1562 reg = <0x5a006000 0x1000>;
>> 1563 clocks = <&rcc USBPHY_K>;
>> 1564 resets = <&rcc USBPHY_R>;
>> 1565 vdda1v1-supply = <®11>;
>> 1566 vdda1v8-supply = <®18>;
>> 1567 status = "disabled";
>> 1568
>> 1569 usbphyc_port0: usb-phy@0 {
>> 1570 #phy-cells = <0>;
>> 1571 reg = <0>;
1777 }; 1572 };
1778 1573
1779 i2c4: i2c@5c002000 { !! 1574 usbphyc_port1: usb-phy@1 {
1780 compatible = !! 1575 #phy-cells = <1>;
1781 reg = <0x5c00 !! 1576 reg = <1>;
1782 interrupt-nam <<
1783 interrupts = <<
1784 <<
1785 clocks = <&rc <<
1786 resets = <&rc <<
1787 #address-cell <<
1788 #size-cells = <<
1789 st,syscfg-fmp <<
1790 wakeup-source <<
1791 i2c-analog-fi <<
1792 access-contro <<
1793 status = "dis <<
1794 }; 1577 };
>> 1578 };
1795 1579
1796 i2c6: i2c@5c009000 { !! 1580 usart1: serial@5c000000 {
1797 compatible = !! 1581 compatible = "st,stm32h7-uart";
1798 reg = <0x5c00 !! 1582 reg = <0x5c000000 0x400>;
1799 interrupt-nam !! 1583 interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
1800 interrupts = !! 1584 clocks = <&rcc USART1_K>;
1801 !! 1585 wakeup-source;
1802 clocks = <&rc !! 1586 status = "disabled";
1803 resets = <&rc !! 1587 };
1804 #address-cell !! 1588
1805 #size-cells = !! 1589 spi6: spi@5c001000 {
1806 st,syscfg-fmp !! 1590 #address-cells = <1>;
1807 wakeup-source !! 1591 #size-cells = <0>;
1808 i2c-analog-fi !! 1592 compatible = "st,stm32h7-spi";
1809 access-contro !! 1593 reg = <0x5c001000 0x400>;
1810 status = "dis !! 1594 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>> 1595 clocks = <&rcc SPI6_K>;
>> 1596 resets = <&rcc SPI6_R>;
>> 1597 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
>> 1598 <&mdma1 35 0x0 0x40002 0x0 0x0>;
>> 1599 dma-names = "rx", "tx";
>> 1600 status = "disabled";
>> 1601 };
>> 1602
>> 1603 i2c4: i2c@5c002000 {
>> 1604 compatible = "st,stm32mp15-i2c";
>> 1605 reg = <0x5c002000 0x400>;
>> 1606 interrupt-names = "event", "error";
>> 1607 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
>> 1608 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>> 1609 clocks = <&rcc I2C4_K>;
>> 1610 resets = <&rcc I2C4_R>;
>> 1611 #address-cells = <1>;
>> 1612 #size-cells = <0>;
>> 1613 st,syscfg-fmp = <&syscfg 0x4 0x8>;
>> 1614 wakeup-source;
>> 1615 i2c-analog-filter;
>> 1616 status = "disabled";
>> 1617 };
>> 1618
>> 1619 rtc: rtc@5c004000 {
>> 1620 compatible = "st,stm32mp1-rtc";
>> 1621 reg = <0x5c004000 0x400>;
>> 1622 clocks = <&rcc RTCAPB>, <&rcc RTC>;
>> 1623 clock-names = "pclk", "rtc_ck";
>> 1624 interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
>> 1625 status = "disabled";
>> 1626 };
>> 1627
>> 1628 bsec: efuse@5c005000 {
>> 1629 compatible = "st,stm32mp15-bsec";
>> 1630 reg = <0x5c005000 0x400>;
>> 1631 #address-cells = <1>;
>> 1632 #size-cells = <1>;
>> 1633 part_number_otp: part-number-otp@4 {
>> 1634 reg = <0x4 0x1>;
>> 1635 };
>> 1636 vrefint: vrefin-cal@52 {
>> 1637 reg = <0x52 0x2>;
1811 }; 1638 };
>> 1639 ts_cal1: calib@5c {
>> 1640 reg = <0x5c 0x2>;
>> 1641 };
>> 1642 ts_cal2: calib@5e {
>> 1643 reg = <0x5e 0x2>;
>> 1644 };
>> 1645 };
>> 1646
>> 1647 i2c6: i2c@5c009000 {
>> 1648 compatible = "st,stm32mp15-i2c";
>> 1649 reg = <0x5c009000 0x400>;
>> 1650 interrupt-names = "event", "error";
>> 1651 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
>> 1652 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
>> 1653 clocks = <&rcc I2C6_K>;
>> 1654 resets = <&rcc I2C6_R>;
>> 1655 #address-cells = <1>;
>> 1656 #size-cells = <0>;
>> 1657 st,syscfg-fmp = <&syscfg 0x4 0x20>;
>> 1658 wakeup-source;
>> 1659 i2c-analog-filter;
>> 1660 status = "disabled";
1812 }; 1661 };
1813 1662
1814 tamp: tamp@5c00a000 { 1663 tamp: tamp@5c00a000 {
1815 compatible = "st,stm3 1664 compatible = "st,stm32-tamp", "syscon", "simple-mfd";
1816 reg = <0x5c00a000 0x4 1665 reg = <0x5c00a000 0x400>;
1817 }; 1666 };
1818 1667
1819 /* 1668 /*
1820 * Break node order to solve 1669 * Break node order to solve dependency probe issue between
1821 * pinctrl and exti. 1670 * pinctrl and exti.
1822 */ 1671 */
1823 pinctrl: pinctrl@50002000 { 1672 pinctrl: pinctrl@50002000 {
1824 #address-cells = <1>; 1673 #address-cells = <1>;
1825 #size-cells = <1>; 1674 #size-cells = <1>;
1826 compatible = "st,stm3 1675 compatible = "st,stm32mp157-pinctrl";
1827 ranges = <0 0x5000200 1676 ranges = <0 0x50002000 0xa400>;
1828 interrupt-parent = <& 1677 interrupt-parent = <&exti>;
1829 st,syscfg = <&exti 0x 1678 st,syscfg = <&exti 0x60 0xff>;
1830 1679
1831 gpioa: gpio@50002000 1680 gpioa: gpio@50002000 {
1832 gpio-controll 1681 gpio-controller;
1833 #gpio-cells = 1682 #gpio-cells = <2>;
1834 interrupt-con 1683 interrupt-controller;
1835 #interrupt-ce 1684 #interrupt-cells = <2>;
1836 reg = <0x0 0x 1685 reg = <0x0 0x400>;
1837 clocks = <&rc 1686 clocks = <&rcc GPIOA>;
1838 st,bank-name 1687 st,bank-name = "GPIOA";
1839 status = "dis 1688 status = "disabled";
1840 }; 1689 };
1841 1690
1842 gpiob: gpio@50003000 1691 gpiob: gpio@50003000 {
1843 gpio-controll 1692 gpio-controller;
1844 #gpio-cells = 1693 #gpio-cells = <2>;
1845 interrupt-con 1694 interrupt-controller;
1846 #interrupt-ce 1695 #interrupt-cells = <2>;
1847 reg = <0x1000 1696 reg = <0x1000 0x400>;
1848 clocks = <&rc 1697 clocks = <&rcc GPIOB>;
1849 st,bank-name 1698 st,bank-name = "GPIOB";
1850 status = "dis 1699 status = "disabled";
1851 }; 1700 };
1852 1701
1853 gpioc: gpio@50004000 1702 gpioc: gpio@50004000 {
1854 gpio-controll 1703 gpio-controller;
1855 #gpio-cells = 1704 #gpio-cells = <2>;
1856 interrupt-con 1705 interrupt-controller;
1857 #interrupt-ce 1706 #interrupt-cells = <2>;
1858 reg = <0x2000 1707 reg = <0x2000 0x400>;
1859 clocks = <&rc 1708 clocks = <&rcc GPIOC>;
1860 st,bank-name 1709 st,bank-name = "GPIOC";
1861 status = "dis 1710 status = "disabled";
1862 }; 1711 };
1863 1712
1864 gpiod: gpio@50005000 1713 gpiod: gpio@50005000 {
1865 gpio-controll 1714 gpio-controller;
1866 #gpio-cells = 1715 #gpio-cells = <2>;
1867 interrupt-con 1716 interrupt-controller;
1868 #interrupt-ce 1717 #interrupt-cells = <2>;
1869 reg = <0x3000 1718 reg = <0x3000 0x400>;
1870 clocks = <&rc 1719 clocks = <&rcc GPIOD>;
1871 st,bank-name 1720 st,bank-name = "GPIOD";
1872 status = "dis 1721 status = "disabled";
1873 }; 1722 };
1874 1723
1875 gpioe: gpio@50006000 1724 gpioe: gpio@50006000 {
1876 gpio-controll 1725 gpio-controller;
1877 #gpio-cells = 1726 #gpio-cells = <2>;
1878 interrupt-con 1727 interrupt-controller;
1879 #interrupt-ce 1728 #interrupt-cells = <2>;
1880 reg = <0x4000 1729 reg = <0x4000 0x400>;
1881 clocks = <&rc 1730 clocks = <&rcc GPIOE>;
1882 st,bank-name 1731 st,bank-name = "GPIOE";
1883 status = "dis 1732 status = "disabled";
1884 }; 1733 };
1885 1734
1886 gpiof: gpio@50007000 1735 gpiof: gpio@50007000 {
1887 gpio-controll 1736 gpio-controller;
1888 #gpio-cells = 1737 #gpio-cells = <2>;
1889 interrupt-con 1738 interrupt-controller;
1890 #interrupt-ce 1739 #interrupt-cells = <2>;
1891 reg = <0x5000 1740 reg = <0x5000 0x400>;
1892 clocks = <&rc 1741 clocks = <&rcc GPIOF>;
1893 st,bank-name 1742 st,bank-name = "GPIOF";
1894 status = "dis 1743 status = "disabled";
1895 }; 1744 };
1896 1745
1897 gpiog: gpio@50008000 1746 gpiog: gpio@50008000 {
1898 gpio-controll 1747 gpio-controller;
1899 #gpio-cells = 1748 #gpio-cells = <2>;
1900 interrupt-con 1749 interrupt-controller;
1901 #interrupt-ce 1750 #interrupt-cells = <2>;
1902 reg = <0x6000 1751 reg = <0x6000 0x400>;
1903 clocks = <&rc 1752 clocks = <&rcc GPIOG>;
1904 st,bank-name 1753 st,bank-name = "GPIOG";
1905 status = "dis 1754 status = "disabled";
1906 }; 1755 };
1907 1756
1908 gpioh: gpio@50009000 1757 gpioh: gpio@50009000 {
1909 gpio-controll 1758 gpio-controller;
1910 #gpio-cells = 1759 #gpio-cells = <2>;
1911 interrupt-con 1760 interrupt-controller;
1912 #interrupt-ce 1761 #interrupt-cells = <2>;
1913 reg = <0x7000 1762 reg = <0x7000 0x400>;
1914 clocks = <&rc 1763 clocks = <&rcc GPIOH>;
1915 st,bank-name 1764 st,bank-name = "GPIOH";
1916 status = "dis 1765 status = "disabled";
1917 }; 1766 };
1918 1767
1919 gpioi: gpio@5000a000 1768 gpioi: gpio@5000a000 {
1920 gpio-controll 1769 gpio-controller;
1921 #gpio-cells = 1770 #gpio-cells = <2>;
1922 interrupt-con 1771 interrupt-controller;
1923 #interrupt-ce 1772 #interrupt-cells = <2>;
1924 reg = <0x8000 1773 reg = <0x8000 0x400>;
1925 clocks = <&rc 1774 clocks = <&rcc GPIOI>;
1926 st,bank-name 1775 st,bank-name = "GPIOI";
1927 status = "dis 1776 status = "disabled";
1928 }; 1777 };
1929 1778
1930 gpioj: gpio@5000b000 1779 gpioj: gpio@5000b000 {
1931 gpio-controll 1780 gpio-controller;
1932 #gpio-cells = 1781 #gpio-cells = <2>;
1933 interrupt-con 1782 interrupt-controller;
1934 #interrupt-ce 1783 #interrupt-cells = <2>;
1935 reg = <0x9000 1784 reg = <0x9000 0x400>;
1936 clocks = <&rc 1785 clocks = <&rcc GPIOJ>;
1937 st,bank-name 1786 st,bank-name = "GPIOJ";
1938 status = "dis 1787 status = "disabled";
1939 }; 1788 };
1940 1789
1941 gpiok: gpio@5000c000 1790 gpiok: gpio@5000c000 {
1942 gpio-controll 1791 gpio-controller;
1943 #gpio-cells = 1792 #gpio-cells = <2>;
1944 interrupt-con 1793 interrupt-controller;
1945 #interrupt-ce 1794 #interrupt-cells = <2>;
1946 reg = <0xa000 1795 reg = <0xa000 0x400>;
1947 clocks = <&rc 1796 clocks = <&rcc GPIOK>;
1948 st,bank-name 1797 st,bank-name = "GPIOK";
1949 status = "dis 1798 status = "disabled";
1950 }; 1799 };
1951 }; 1800 };
1952 1801
1953 pinctrl_z: pinctrl@54004000 { 1802 pinctrl_z: pinctrl@54004000 {
1954 #address-cells = <1>; 1803 #address-cells = <1>;
1955 #size-cells = <1>; 1804 #size-cells = <1>;
1956 compatible = "st,stm3 1805 compatible = "st,stm32mp157-z-pinctrl";
1957 ranges = <0 0x5400400 1806 ranges = <0 0x54004000 0x400>;
1958 interrupt-parent = <& 1807 interrupt-parent = <&exti>;
1959 st,syscfg = <&exti 0x 1808 st,syscfg = <&exti 0x60 0xff>;
1960 1809
1961 gpioz: gpio@54004000 1810 gpioz: gpio@54004000 {
1962 gpio-controll 1811 gpio-controller;
1963 #gpio-cells = 1812 #gpio-cells = <2>;
1964 interrupt-con 1813 interrupt-controller;
1965 #interrupt-ce 1814 #interrupt-cells = <2>;
1966 reg = <0 0x40 1815 reg = <0 0x400>;
1967 clocks = <&rc 1816 clocks = <&rcc GPIOZ>;
1968 st,bank-name 1817 st,bank-name = "GPIOZ";
1969 st,bank-iopor 1818 st,bank-ioport = <11>;
1970 status = "dis 1819 status = "disabled";
1971 }; 1820 };
1972 }; 1821 };
1973 }; 1822 };
1974 1823
1975 mlahb: ahb { 1824 mlahb: ahb {
1976 compatible = "st,mlahb", "sim 1825 compatible = "st,mlahb", "simple-bus";
1977 #address-cells = <1>; 1826 #address-cells = <1>;
1978 #size-cells = <1>; 1827 #size-cells = <1>;
1979 ranges; 1828 ranges;
1980 dma-ranges = <0x00000000 0x38 1829 dma-ranges = <0x00000000 0x38000000 0x10000>,
1981 <0x10000000 0x10 1830 <0x10000000 0x10000000 0x60000>,
1982 <0x30000000 0x30 1831 <0x30000000 0x30000000 0x60000>;
1983 1832
1984 m4_rproc: m4@10000000 { 1833 m4_rproc: m4@10000000 {
1985 compatible = "st,stm3 1834 compatible = "st,stm32mp1-m4";
1986 reg = <0x10000000 0x4 1835 reg = <0x10000000 0x40000>,
1987 <0x30000000 0x4 1836 <0x30000000 0x40000>,
1988 <0x38000000 0x1 1837 <0x38000000 0x10000>;
1989 resets = <&rcc MCU_R> 1838 resets = <&rcc MCU_R>;
1990 reset-names = "mcu_rs 1839 reset-names = "mcu_rst";
1991 st,syscfg-holdboot = 1840 st,syscfg-holdboot = <&rcc 0x10C 0x1>;
1992 st,syscfg-pdds = <&pw 1841 st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
1993 st,syscfg-rsc-tbl = < 1842 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
1994 st,syscfg-m4-state = 1843 st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;
1995 status = "disabled"; 1844 status = "disabled";
1996 }; 1845 };
1997 }; 1846 };
1998 }; 1847 };
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