1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /* 2 /*
3 * Copyright (C) STMicroelectronics 2017 - All 3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */ 5 */
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h> 7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h> 8 #include <dt-bindings/reset/stm32mp1-resets.h>
9 9
10 / { 10 / {
11 #address-cells = <1>; 11 #address-cells = <1>;
12 #size-cells = <1>; 12 #size-cells = <1>;
13 13
14 cpus { 14 cpus {
15 #address-cells = <1>; 15 #address-cells = <1>;
16 #size-cells = <0>; 16 #size-cells = <0>;
17 17
18 cpu0: cpu@0 { 18 cpu0: cpu@0 {
19 compatible = "arm,cort 19 compatible = "arm,cortex-a7";
20 clock-frequency = <650 20 clock-frequency = <650000000>;
21 device_type = "cpu"; 21 device_type = "cpu";
22 reg = <0>; 22 reg = <0>;
23 }; 23 };
24 }; 24 };
25 25
26 arm-pmu { 26 arm-pmu {
27 compatible = "arm,cortex-a7-pm 27 compatible = "arm,cortex-a7-pmu";
28 interrupts = <GIC_SPI 200 IRQ_ 28 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
29 interrupt-affinity = <&cpu0>; 29 interrupt-affinity = <&cpu0>;
30 interrupt-parent = <&intc>; 30 interrupt-parent = <&intc>;
31 }; 31 };
32 32
33 psci { 33 psci {
34 compatible = "arm,psci-1.0"; 34 compatible = "arm,psci-1.0";
35 method = "smc"; 35 method = "smc";
36 }; 36 };
37 37
38 intc: interrupt-controller@a0021000 { 38 intc: interrupt-controller@a0021000 {
39 compatible = "arm,cortex-a7-gi 39 compatible = "arm,cortex-a7-gic";
40 #interrupt-cells = <3>; 40 #interrupt-cells = <3>;
41 interrupt-controller; 41 interrupt-controller;
42 reg = <0xa0021000 0x1000>, 42 reg = <0xa0021000 0x1000>,
43 <0xa0022000 0x2000>; 43 <0xa0022000 0x2000>;
44 }; 44 };
45 45
46 timer { 46 timer {
47 compatible = "arm,armv7-timer" 47 compatible = "arm,armv7-timer";
48 interrupts = <GIC_PPI 13 (GIC_ 48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
49 <GIC_PPI 14 (GIC_ 49 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 11 (GIC_ 50 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 10 (GIC_ 51 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
52 interrupt-parent = <&intc>; 52 interrupt-parent = <&intc>;
53 arm,no-tick-in-suspend; 53 arm,no-tick-in-suspend;
54 }; 54 };
55 55
56 clocks { 56 clocks {
57 clk_hse: clk-hse { 57 clk_hse: clk-hse {
58 #clock-cells = <0>; 58 #clock-cells = <0>;
59 compatible = "fixed-cl 59 compatible = "fixed-clock";
60 clock-frequency = <240 60 clock-frequency = <24000000>;
61 }; 61 };
62 62
63 clk_hsi: clk-hsi { 63 clk_hsi: clk-hsi {
64 #clock-cells = <0>; 64 #clock-cells = <0>;
65 compatible = "fixed-cl 65 compatible = "fixed-clock";
66 clock-frequency = <640 66 clock-frequency = <64000000>;
67 }; 67 };
68 68
69 clk_lse: clk-lse { 69 clk_lse: clk-lse {
70 #clock-cells = <0>; 70 #clock-cells = <0>;
71 compatible = "fixed-cl 71 compatible = "fixed-clock";
72 clock-frequency = <327 72 clock-frequency = <32768>;
73 }; 73 };
74 74
75 clk_lsi: clk-lsi { 75 clk_lsi: clk-lsi {
76 #clock-cells = <0>; 76 #clock-cells = <0>;
77 compatible = "fixed-cl 77 compatible = "fixed-clock";
78 clock-frequency = <320 78 clock-frequency = <32000>;
79 }; 79 };
80 80
81 clk_csi: clk-csi { 81 clk_csi: clk-csi {
82 #clock-cells = <0>; 82 #clock-cells = <0>;
83 compatible = "fixed-cl 83 compatible = "fixed-clock";
84 clock-frequency = <400 84 clock-frequency = <4000000>;
85 }; 85 };
86 }; 86 };
87 87
88 thermal-zones { 88 thermal-zones {
89 cpu_thermal: cpu-thermal { 89 cpu_thermal: cpu-thermal {
90 polling-delay-passive 90 polling-delay-passive = <0>;
91 polling-delay = <0>; 91 polling-delay = <0>;
92 thermal-sensors = <&dt 92 thermal-sensors = <&dts>;
93 93
94 trips { 94 trips {
95 cpu_alert1: cp 95 cpu_alert1: cpu-alert1 {
96 temper 96 temperature = <85000>;
97 hyster 97 hysteresis = <0>;
98 type = 98 type = "passive";
99 }; 99 };
100 100
101 cpu-crit { 101 cpu-crit {
102 temper 102 temperature = <120000>;
103 hyster 103 hysteresis = <0>;
104 type = 104 type = "critical";
105 }; 105 };
106 }; 106 };
107 107
108 cooling-maps { 108 cooling-maps {
109 }; 109 };
110 }; 110 };
111 }; 111 };
112 112
113 booster: regulator-booster { 113 booster: regulator-booster {
114 compatible = "st,stm32mp1-boos 114 compatible = "st,stm32mp1-booster";
115 st,syscfg = <&syscfg>; 115 st,syscfg = <&syscfg>;
116 status = "disabled"; 116 status = "disabled";
117 }; 117 };
118 118
119 soc { 119 soc {
120 compatible = "simple-bus"; 120 compatible = "simple-bus";
121 #address-cells = <1>; 121 #address-cells = <1>;
122 #size-cells = <1>; 122 #size-cells = <1>;
123 interrupt-parent = <&intc>; 123 interrupt-parent = <&intc>;
124 ranges; 124 ranges;
125 125
126 ipcc: mailbox@4c001000 { 126 ipcc: mailbox@4c001000 {
127 compatible = "st,stm32 127 compatible = "st,stm32mp1-ipcc";
128 #mbox-cells = <1>; 128 #mbox-cells = <1>;
129 reg = <0x4c001000 0x40 129 reg = <0x4c001000 0x400>;
130 st,proc-id = <0>; 130 st,proc-id = <0>;
131 interrupts-extended = 131 interrupts-extended =
132 <&exti 61 1>, 132 <&exti 61 1>,
133 <&intc GIC_SPI 133 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
134 interrupt-names = "rx" 134 interrupt-names = "rx", "tx";
135 clocks = <&rcc IPCC>; 135 clocks = <&rcc IPCC>;
136 wakeup-source; 136 wakeup-source;
137 status = "disabled"; 137 status = "disabled";
138 }; 138 };
139 139
140 rcc: rcc@50000000 { 140 rcc: rcc@50000000 {
141 compatible = "st,stm32 141 compatible = "st,stm32mp1-rcc", "syscon";
142 reg = <0x50000000 0x10 142 reg = <0x50000000 0x1000>;
143 #clock-cells = <1>; 143 #clock-cells = <1>;
144 #reset-cells = <1>; 144 #reset-cells = <1>;
145 }; 145 };
146 146
147 pwr_regulators: pwr@50001000 { 147 pwr_regulators: pwr@50001000 {
148 compatible = "st,stm32 148 compatible = "st,stm32mp1,pwr-reg";
149 reg = <0x50001000 0x10 149 reg = <0x50001000 0x10>;
150 150
151 reg11: reg11 { 151 reg11: reg11 {
152 regulator-name 152 regulator-name = "reg11";
153 regulator-min- 153 regulator-min-microvolt = <1100000>;
154 regulator-max- 154 regulator-max-microvolt = <1100000>;
155 }; 155 };
156 156
157 reg18: reg18 { 157 reg18: reg18 {
158 regulator-name 158 regulator-name = "reg18";
159 regulator-min- 159 regulator-min-microvolt = <1800000>;
160 regulator-max- 160 regulator-max-microvolt = <1800000>;
161 }; 161 };
162 162
163 usb33: usb33 { 163 usb33: usb33 {
164 regulator-name 164 regulator-name = "usb33";
165 regulator-min- 165 regulator-min-microvolt = <3300000>;
166 regulator-max- 166 regulator-max-microvolt = <3300000>;
167 }; 167 };
168 }; 168 };
169 169
170 pwr_mcu: pwr_mcu@50001014 { 170 pwr_mcu: pwr_mcu@50001014 {
171 compatible = "st,stm32 171 compatible = "st,stm32mp151-pwr-mcu", "syscon";
172 reg = <0x50001014 0x4> 172 reg = <0x50001014 0x4>;
173 }; 173 };
174 174
175 exti: interrupt-controller@500 175 exti: interrupt-controller@5000d000 {
176 compatible = "st,stm32 176 compatible = "st,stm32mp1-exti", "syscon";
177 interrupt-controller; 177 interrupt-controller;
178 #interrupt-cells = <2> 178 #interrupt-cells = <2>;
179 reg = <0x5000d000 0x40 179 reg = <0x5000d000 0x400>;
180 interrupts-extended = 180 interrupts-extended =
181 <&intc GIC_SPI 181 <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */
182 <&intc GIC_SPI 182 <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
183 <&intc GIC_SPI 183 <&intc GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
184 <&intc GIC_SPI 184 <&intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
185 <&intc GIC_SPI 185 <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
186 <&intc GIC_SPI 186 <&intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
187 <&intc GIC_SPI 187 <&intc GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
188 <&intc GIC_SPI 188 <&intc GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
189 <&intc GIC_SPI 189 <&intc GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
190 <&intc GIC_SPI 190 <&intc GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
191 <&intc GIC_SPI 191 <&intc GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */
192 <&intc GIC_SPI 192 <&intc GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
193 <&intc GIC_SPI 193 <&intc GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
194 <&intc GIC_SPI 194 <&intc GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
195 <&intc GIC_SPI 195 <&intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
196 <&intc GIC_SPI 196 <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
197 <&intc GIC_SPI 197 <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
198 <0>, 198 <0>,
199 <0>, 199 <0>,
200 <&intc GIC_SPI 200 <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
201 <0>, 201 <0>, /* EXTI_20 */
202 <&intc GIC_SPI 202 <&intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
203 <&intc GIC_SPI 203 <&intc GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
204 <&intc GIC_SPI 204 <&intc GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
205 <&intc GIC_SPI 205 <&intc GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
206 <&intc GIC_SPI 206 <&intc GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
207 <&intc GIC_SPI 207 <&intc GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
208 <&intc GIC_SPI 208 <&intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
209 <&intc GIC_SPI 209 <&intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
210 <&intc GIC_SPI 210 <&intc GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
211 <&intc GIC_SPI 211 <&intc GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */
212 <&intc GIC_SPI 212 <&intc GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
213 <&intc GIC_SPI 213 <&intc GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
214 <&intc GIC_SPI 214 <&intc GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
215 <0>, 215 <0>,
216 <0>, 216 <0>,
217 <0>, 217 <0>,
218 <0>, 218 <0>,
219 <0>, 219 <0>,
220 <0>, 220 <0>,
221 <0>, 221 <0>, /* EXTI_40 */
222 <0>, 222 <0>,
223 <0>, 223 <0>,
224 <0>, 224 <0>,
225 <0>, 225 <0>,
226 <0>, 226 <0>,
227 <&intc GIC_SPI 227 <&intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
228 <&intc GIC_SPI 228 <&intc GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
229 <&intc GIC_SPI 229 <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
230 <0>, 230 <0>,
231 <&intc GIC_SPI 231 <&intc GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */
232 <0>, 232 <0>,
233 <&intc GIC_SPI 233 <&intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
234 <&intc GIC_SPI 234 <&intc GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
235 <&intc GIC_SPI 235 <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
236 <0>, 236 <0>,
237 <0>, 237 <0>,
238 <0>, 238 <0>,
239 <0>, 239 <0>,
240 <0>, 240 <0>,
241 <0>, 241 <0>, /* EXTI_60 */
242 <&intc GIC_SPI 242 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
243 <0>, 243 <0>,
244 <0>, 244 <0>,
245 <0>, 245 <0>,
246 <&intc GIC_SPI 246 <&intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
247 <0>, 247 <0>,
248 <0>, 248 <0>,
249 <&intc GIC_SPI 249 <&intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
250 <0>, 250 <0>,
251 <&intc GIC_SPI 251 <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */
252 <0>, 252 <0>,
253 <0>, 253 <0>,
254 <&intc GIC_SPI 254 <&intc GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
255 }; 255 };
256 256
257 syscfg: syscon@50020000 { 257 syscfg: syscon@50020000 {
258 compatible = "st,stm32 258 compatible = "st,stm32mp157-syscfg", "syscon";
259 reg = <0x50020000 0x40 259 reg = <0x50020000 0x400>;
260 clocks = <&rcc SYSCFG> 260 clocks = <&rcc SYSCFG>;
261 }; 261 };
262 262
263 dts: thermal@50028000 { 263 dts: thermal@50028000 {
264 compatible = "st,stm32 264 compatible = "st,stm32-thermal";
265 reg = <0x50028000 0x10 265 reg = <0x50028000 0x100>;
266 interrupts = <GIC_SPI 266 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&rcc TMPSENS 267 clocks = <&rcc TMPSENS>;
268 clock-names = "pclk"; 268 clock-names = "pclk";
269 #thermal-sensor-cells 269 #thermal-sensor-cells = <0>;
270 status = "disabled"; 270 status = "disabled";
271 }; 271 };
272 272
273 mdma1: dma-controller@58000000 273 mdma1: dma-controller@58000000 {
274 compatible = "st,stm32 274 compatible = "st,stm32h7-mdma";
275 reg = <0x58000000 0x10 275 reg = <0x58000000 0x1000>;
276 interrupts = <GIC_SPI 276 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&rcc MDMA>; 277 clocks = <&rcc MDMA>;
278 resets = <&rcc MDMA_R> 278 resets = <&rcc MDMA_R>;
279 #dma-cells = <5>; 279 #dma-cells = <5>;
280 dma-channels = <32>; 280 dma-channels = <32>;
281 dma-requests = <48>; 281 dma-requests = <48>;
282 }; 282 };
283 283
284 sdmmc1: mmc@58005000 { 284 sdmmc1: mmc@58005000 {
285 compatible = "st,stm32 285 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
286 arm,primecell-periphid 286 arm,primecell-periphid = <0x00253180>;
287 reg = <0x58005000 0x10 287 reg = <0x58005000 0x1000>;
288 interrupts = <GIC_SPI 288 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&rcc SDMMC1_ 289 clocks = <&rcc SDMMC1_K>;
290 clock-names = "apb_pcl 290 clock-names = "apb_pclk";
291 resets = <&rcc SDMMC1_ 291 resets = <&rcc SDMMC1_R>;
292 cap-sd-highspeed; 292 cap-sd-highspeed;
293 cap-mmc-highspeed; 293 cap-mmc-highspeed;
294 max-frequency = <12000 294 max-frequency = <120000000>;
295 status = "disabled"; 295 status = "disabled";
296 }; 296 };
297 297
298 sdmmc2: mmc@58007000 { 298 sdmmc2: mmc@58007000 {
299 compatible = "st,stm32 299 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
300 arm,primecell-periphid 300 arm,primecell-periphid = <0x00253180>;
301 reg = <0x58007000 0x10 301 reg = <0x58007000 0x1000>;
302 interrupts = <GIC_SPI 302 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
303 clocks = <&rcc SDMMC2_ 303 clocks = <&rcc SDMMC2_K>;
304 clock-names = "apb_pcl 304 clock-names = "apb_pclk";
305 resets = <&rcc SDMMC2_ 305 resets = <&rcc SDMMC2_R>;
306 cap-sd-highspeed; 306 cap-sd-highspeed;
307 cap-mmc-highspeed; 307 cap-mmc-highspeed;
308 max-frequency = <12000 308 max-frequency = <120000000>;
309 status = "disabled"; 309 status = "disabled";
310 }; 310 };
311 311
312 crc1: crc@58009000 { 312 crc1: crc@58009000 {
313 compatible = "st,stm32 313 compatible = "st,stm32f7-crc";
314 reg = <0x58009000 0x40 314 reg = <0x58009000 0x400>;
315 clocks = <&rcc CRC1>; 315 clocks = <&rcc CRC1>;
316 status = "disabled"; 316 status = "disabled";
317 }; 317 };
318 318
319 usbh_ohci: usb@5800c000 { 319 usbh_ohci: usb@5800c000 {
320 compatible = "generic- 320 compatible = "generic-ohci";
321 reg = <0x5800c000 0x10 321 reg = <0x5800c000 0x1000>;
322 clocks = <&usbphyc>, < 322 clocks = <&usbphyc>, <&rcc USBH>;
323 resets = <&rcc USBH_R> 323 resets = <&rcc USBH_R>;
324 interrupts = <GIC_SPI 324 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
325 phys = <&usbphyc_port0 325 phys = <&usbphyc_port0>;
326 phy-names = "usb"; 326 phy-names = "usb";
327 status = "disabled"; 327 status = "disabled";
328 }; 328 };
329 329
330 usbh_ehci: usb@5800d000 { 330 usbh_ehci: usb@5800d000 {
331 compatible = "generic- 331 compatible = "generic-ehci";
332 reg = <0x5800d000 0x10 332 reg = <0x5800d000 0x1000>;
333 clocks = <&usbphyc>, < 333 clocks = <&usbphyc>, <&rcc USBH>;
334 resets = <&rcc USBH_R> 334 resets = <&rcc USBH_R>;
335 interrupts = <GIC_SPI 335 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
336 companion = <&usbh_ohc 336 companion = <&usbh_ohci>;
337 phys = <&usbphyc_port0 337 phys = <&usbphyc_port0>;
338 phy-names = "usb"; 338 phy-names = "usb";
339 status = "disabled"; 339 status = "disabled";
340 }; 340 };
341 341
342 ltdc: display-controller@5a001 342 ltdc: display-controller@5a001000 {
343 compatible = "st,stm32 343 compatible = "st,stm32-ltdc";
344 reg = <0x5a001000 0x40 344 reg = <0x5a001000 0x400>;
345 interrupts = <GIC_SPI 345 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
346 <GIC_SPI 346 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&rcc LTDC_PX 347 clocks = <&rcc LTDC_PX>;
348 clock-names = "lcd"; 348 clock-names = "lcd";
349 resets = <&rcc LTDC_R> 349 resets = <&rcc LTDC_R>;
350 status = "disabled"; 350 status = "disabled";
351 }; 351 };
352 352
353 iwdg2: watchdog@5a002000 { 353 iwdg2: watchdog@5a002000 {
354 compatible = "st,stm32 354 compatible = "st,stm32mp1-iwdg";
355 reg = <0x5a002000 0x40 355 reg = <0x5a002000 0x400>;
356 clocks = <&rcc IWDG2>, 356 clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
357 clock-names = "pclk", 357 clock-names = "pclk", "lsi";
358 status = "disabled"; 358 status = "disabled";
359 }; 359 };
360 360
361 usbphyc: usbphyc@5a006000 { 361 usbphyc: usbphyc@5a006000 {
362 #address-cells = <1>; 362 #address-cells = <1>;
363 #size-cells = <0>; 363 #size-cells = <0>;
364 #clock-cells = <0>; 364 #clock-cells = <0>;
365 compatible = "st,stm32 365 compatible = "st,stm32mp1-usbphyc";
366 reg = <0x5a006000 0x10 366 reg = <0x5a006000 0x1000>;
367 clocks = <&rcc USBPHY_ 367 clocks = <&rcc USBPHY_K>;
368 resets = <&rcc USBPHY_ 368 resets = <&rcc USBPHY_R>;
369 vdda1v1-supply = <® 369 vdda1v1-supply = <®11>;
370 vdda1v8-supply = <® 370 vdda1v8-supply = <®18>;
371 status = "disabled"; 371 status = "disabled";
372 372
373 usbphyc_port0: usb-phy 373 usbphyc_port0: usb-phy@0 {
374 #phy-cells = < 374 #phy-cells = <0>;
375 reg = <0>; 375 reg = <0>;
376 }; 376 };
377 377
378 usbphyc_port1: usb-phy 378 usbphyc_port1: usb-phy@1 {
379 #phy-cells = < 379 #phy-cells = <1>;
380 reg = <1>; 380 reg = <1>;
381 }; 381 };
382 }; 382 };
383 383
384 rtc: rtc@5c004000 { 384 rtc: rtc@5c004000 {
385 compatible = "st,stm32 385 compatible = "st,stm32mp1-rtc";
386 reg = <0x5c004000 0x40 386 reg = <0x5c004000 0x400>;
387 clocks = <&rcc RTCAPB> 387 clocks = <&rcc RTCAPB>, <&rcc RTC>;
388 clock-names = "pclk", 388 clock-names = "pclk", "rtc_ck";
389 interrupts-extended = 389 interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
390 status = "disabled"; 390 status = "disabled";
391 }; 391 };
392 392
393 bsec: efuse@5c005000 { 393 bsec: efuse@5c005000 {
394 compatible = "st,stm32 394 compatible = "st,stm32mp15-bsec";
395 reg = <0x5c005000 0x40 395 reg = <0x5c005000 0x400>;
396 #address-cells = <1>; 396 #address-cells = <1>;
397 #size-cells = <1>; 397 #size-cells = <1>;
398 part_number_otp: part- 398 part_number_otp: part-number-otp@4 {
399 reg = <0x4 0x1 399 reg = <0x4 0x1>;
400 }; 400 };
401 vrefint: vrefin-cal@52 401 vrefint: vrefin-cal@52 {
402 reg = <0x52 0x 402 reg = <0x52 0x2>;
403 }; 403 };
404 ts_cal1: calib@5c { 404 ts_cal1: calib@5c {
405 reg = <0x5c 0x 405 reg = <0x5c 0x2>;
406 }; 406 };
407 ts_cal2: calib@5e { 407 ts_cal2: calib@5e {
408 reg = <0x5e 0x 408 reg = <0x5e 0x2>;
409 }; 409 };
410 }; 410 };
411 411
412 etzpc: bus@5c007000 { 412 etzpc: bus@5c007000 {
413 compatible = "st,stm32 413 compatible = "st,stm32-etzpc", "simple-bus";
414 reg = <0x5c007000 0x40 414 reg = <0x5c007000 0x400>;
415 #address-cells = <1>; 415 #address-cells = <1>;
416 #size-cells = <1>; 416 #size-cells = <1>;
417 #access-controller-cel 417 #access-controller-cells = <1>;
418 ranges; 418 ranges;
419 419
420 timers2: timer@4000000 420 timers2: timer@40000000 {
421 #address-cells 421 #address-cells = <1>;
422 #size-cells = 422 #size-cells = <0>;
423 compatible = " 423 compatible = "st,stm32-timers";
424 reg = <0x40000 424 reg = <0x40000000 0x400>;
425 interrupts = < 425 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
426 interrupt-name 426 interrupt-names = "global";
427 clocks = <&rcc 427 clocks = <&rcc TIM2_K>;
428 clock-names = 428 clock-names = "int";
429 dmas = <&dmamu 429 dmas = <&dmamux1 18 0x400 0x1>,
430 <&dmamu 430 <&dmamux1 19 0x400 0x1>,
431 <&dmamu 431 <&dmamux1 20 0x400 0x1>,
432 <&dmamu 432 <&dmamux1 21 0x400 0x1>,
433 <&dmamu 433 <&dmamux1 22 0x400 0x1>;
434 dma-names = "c 434 dma-names = "ch1", "ch2", "ch3", "ch4", "up";
435 access-control 435 access-controllers = <&etzpc 16>;
436 status = "disa 436 status = "disabled";
437 437
438 pwm { 438 pwm {
439 compat 439 compatible = "st,stm32-pwm";
440 #pwm-c 440 #pwm-cells = <3>;
441 status 441 status = "disabled";
442 }; 442 };
443 443
444 timer@1 { 444 timer@1 {
445 compat 445 compatible = "st,stm32h7-timer-trigger";
446 reg = 446 reg = <1>;
447 status 447 status = "disabled";
448 }; 448 };
449 449
450 counter { 450 counter {
451 compat 451 compatible = "st,stm32-timer-counter";
452 status 452 status = "disabled";
453 }; 453 };
454 }; 454 };
455 455
456 timers3: timer@4000100 456 timers3: timer@40001000 {
457 #address-cells 457 #address-cells = <1>;
458 #size-cells = 458 #size-cells = <0>;
459 compatible = " 459 compatible = "st,stm32-timers";
460 reg = <0x40001 460 reg = <0x40001000 0x400>;
461 interrupts = < 461 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
462 interrupt-name 462 interrupt-names = "global";
463 clocks = <&rcc 463 clocks = <&rcc TIM3_K>;
464 clock-names = 464 clock-names = "int";
465 dmas = <&dmamu 465 dmas = <&dmamux1 23 0x400 0x1>,
466 <&dmamu 466 <&dmamux1 24 0x400 0x1>,
467 <&dmamu 467 <&dmamux1 25 0x400 0x1>,
468 <&dmamu 468 <&dmamux1 26 0x400 0x1>,
469 <&dmamu 469 <&dmamux1 27 0x400 0x1>,
470 <&dmamu 470 <&dmamux1 28 0x400 0x1>;
471 dma-names = "c 471 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
472 access-control 472 access-controllers = <&etzpc 17>;
473 status = "disa 473 status = "disabled";
474 474
475 pwm { 475 pwm {
476 compat 476 compatible = "st,stm32-pwm";
477 #pwm-c 477 #pwm-cells = <3>;
478 status 478 status = "disabled";
479 }; 479 };
480 480
481 timer@2 { 481 timer@2 {
482 compat 482 compatible = "st,stm32h7-timer-trigger";
483 reg = 483 reg = <2>;
484 status 484 status = "disabled";
485 }; 485 };
486 486
487 counter { 487 counter {
488 compat 488 compatible = "st,stm32-timer-counter";
489 status 489 status = "disabled";
490 }; 490 };
491 }; 491 };
492 492
493 timers4: timer@4000200 493 timers4: timer@40002000 {
494 #address-cells 494 #address-cells = <1>;
495 #size-cells = 495 #size-cells = <0>;
496 compatible = " 496 compatible = "st,stm32-timers";
497 reg = <0x40002 497 reg = <0x40002000 0x400>;
498 interrupts = < 498 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
499 interrupt-name 499 interrupt-names = "global";
500 clocks = <&rcc 500 clocks = <&rcc TIM4_K>;
501 clock-names = 501 clock-names = "int";
502 dmas = <&dmamu 502 dmas = <&dmamux1 29 0x400 0x1>,
503 <&dmamu 503 <&dmamux1 30 0x400 0x1>,
504 <&dmamu 504 <&dmamux1 31 0x400 0x1>,
505 <&dmamu 505 <&dmamux1 32 0x400 0x1>;
506 dma-names = "c 506 dma-names = "ch1", "ch2", "ch3", "ch4";
507 access-control 507 access-controllers = <&etzpc 18>;
508 status = "disa 508 status = "disabled";
509 509
510 pwm { 510 pwm {
511 compat 511 compatible = "st,stm32-pwm";
512 #pwm-c 512 #pwm-cells = <3>;
513 status 513 status = "disabled";
514 }; 514 };
515 515
516 timer@3 { 516 timer@3 {
517 compat 517 compatible = "st,stm32h7-timer-trigger";
518 reg = 518 reg = <3>;
519 status 519 status = "disabled";
520 }; 520 };
521 521
522 counter { 522 counter {
523 compat 523 compatible = "st,stm32-timer-counter";
524 status 524 status = "disabled";
525 }; 525 };
526 }; 526 };
527 527
528 timers5: timer@4000300 528 timers5: timer@40003000 {
529 #address-cells 529 #address-cells = <1>;
530 #size-cells = 530 #size-cells = <0>;
531 compatible = " 531 compatible = "st,stm32-timers";
532 reg = <0x40003 532 reg = <0x40003000 0x400>;
533 interrupts = < 533 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
534 interrupt-name 534 interrupt-names = "global";
535 clocks = <&rcc 535 clocks = <&rcc TIM5_K>;
536 clock-names = 536 clock-names = "int";
537 dmas = <&dmamu 537 dmas = <&dmamux1 55 0x400 0x1>,
538 <&dmamu 538 <&dmamux1 56 0x400 0x1>,
539 <&dmamu 539 <&dmamux1 57 0x400 0x1>,
540 <&dmamu 540 <&dmamux1 58 0x400 0x1>,
541 <&dmamu 541 <&dmamux1 59 0x400 0x1>,
542 <&dmamu 542 <&dmamux1 60 0x400 0x1>;
543 dma-names = "c 543 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
544 access-control 544 access-controllers = <&etzpc 19>;
545 status = "disa 545 status = "disabled";
546 546
547 pwm { 547 pwm {
548 compat 548 compatible = "st,stm32-pwm";
549 #pwm-c 549 #pwm-cells = <3>;
550 status 550 status = "disabled";
551 }; 551 };
552 552
553 timer@4 { 553 timer@4 {
554 compat 554 compatible = "st,stm32h7-timer-trigger";
555 reg = 555 reg = <4>;
556 status 556 status = "disabled";
557 }; 557 };
558 558
559 counter { 559 counter {
560 compat 560 compatible = "st,stm32-timer-counter";
561 status 561 status = "disabled";
562 }; 562 };
563 }; 563 };
564 564
565 timers6: timer@4000400 565 timers6: timer@40004000 {
566 #address-cells 566 #address-cells = <1>;
567 #size-cells = 567 #size-cells = <0>;
568 compatible = " 568 compatible = "st,stm32-timers";
569 reg = <0x40004 569 reg = <0x40004000 0x400>;
570 interrupts = < 570 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
571 interrupt-name 571 interrupt-names = "global";
572 clocks = <&rcc 572 clocks = <&rcc TIM6_K>;
573 clock-names = 573 clock-names = "int";
574 dmas = <&dmamu 574 dmas = <&dmamux1 69 0x400 0x1>;
575 dma-names = "u 575 dma-names = "up";
576 access-control 576 access-controllers = <&etzpc 20>;
577 status = "disa 577 status = "disabled";
578 578
579 timer@5 { 579 timer@5 {
580 compat 580 compatible = "st,stm32h7-timer-trigger";
581 reg = 581 reg = <5>;
582 status 582 status = "disabled";
583 }; 583 };
584 }; 584 };
585 585
586 timers7: timer@4000500 586 timers7: timer@40005000 {
587 #address-cells 587 #address-cells = <1>;
588 #size-cells = 588 #size-cells = <0>;
589 compatible = " 589 compatible = "st,stm32-timers";
590 reg = <0x40005 590 reg = <0x40005000 0x400>;
591 interrupts = < 591 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
592 interrupt-name 592 interrupt-names = "global";
593 clocks = <&rcc 593 clocks = <&rcc TIM7_K>;
594 clock-names = 594 clock-names = "int";
595 dmas = <&dmamu 595 dmas = <&dmamux1 70 0x400 0x1>;
596 dma-names = "u 596 dma-names = "up";
597 access-control 597 access-controllers = <&etzpc 21>;
598 status = "disa 598 status = "disabled";
599 599
600 timer@6 { 600 timer@6 {
601 compat 601 compatible = "st,stm32h7-timer-trigger";
602 reg = 602 reg = <6>;
603 status 603 status = "disabled";
604 }; 604 };
605 }; 605 };
606 606
607 timers12: timer@400060 607 timers12: timer@40006000 {
608 #address-cells 608 #address-cells = <1>;
609 #size-cells = 609 #size-cells = <0>;
610 compatible = " 610 compatible = "st,stm32-timers";
611 reg = <0x40006 611 reg = <0x40006000 0x400>;
612 interrupts = < 612 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
613 interrupt-name 613 interrupt-names = "global";
614 clocks = <&rcc 614 clocks = <&rcc TIM12_K>;
615 clock-names = 615 clock-names = "int";
616 access-control 616 access-controllers = <&etzpc 22>;
617 status = "disa 617 status = "disabled";
618 618
619 pwm { 619 pwm {
620 compat 620 compatible = "st,stm32-pwm";
621 #pwm-c 621 #pwm-cells = <3>;
622 status 622 status = "disabled";
623 }; 623 };
624 624
625 timer@11 { 625 timer@11 {
626 compat 626 compatible = "st,stm32h7-timer-trigger";
627 reg = 627 reg = <11>;
628 status 628 status = "disabled";
629 }; 629 };
630 }; 630 };
631 631
632 timers13: timer@400070 632 timers13: timer@40007000 {
633 #address-cells 633 #address-cells = <1>;
634 #size-cells = 634 #size-cells = <0>;
635 compatible = " 635 compatible = "st,stm32-timers";
636 reg = <0x40007 636 reg = <0x40007000 0x400>;
637 interrupts = < 637 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
638 interrupt-name 638 interrupt-names = "global";
639 clocks = <&rcc 639 clocks = <&rcc TIM13_K>;
640 clock-names = 640 clock-names = "int";
641 access-control 641 access-controllers = <&etzpc 23>;
642 status = "disa 642 status = "disabled";
643 643
644 pwm { 644 pwm {
645 compat 645 compatible = "st,stm32-pwm";
646 #pwm-c 646 #pwm-cells = <3>;
647 status 647 status = "disabled";
648 }; 648 };
649 649
650 timer@12 { 650 timer@12 {
651 compat 651 compatible = "st,stm32h7-timer-trigger";
652 reg = 652 reg = <12>;
653 status 653 status = "disabled";
654 }; 654 };
655 }; 655 };
656 656
657 timers14: timer@400080 657 timers14: timer@40008000 {
658 #address-cells 658 #address-cells = <1>;
659 #size-cells = 659 #size-cells = <0>;
660 compatible = " 660 compatible = "st,stm32-timers";
661 reg = <0x40008 661 reg = <0x40008000 0x400>;
662 interrupts = < 662 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
663 interrupt-name 663 interrupt-names = "global";
664 clocks = <&rcc 664 clocks = <&rcc TIM14_K>;
665 clock-names = 665 clock-names = "int";
666 access-control 666 access-controllers = <&etzpc 24>;
667 status = "disa 667 status = "disabled";
668 668
669 pwm { 669 pwm {
670 compat 670 compatible = "st,stm32-pwm";
671 #pwm-c 671 #pwm-cells = <3>;
672 status 672 status = "disabled";
673 }; 673 };
674 674
675 timer@13 { 675 timer@13 {
676 compat 676 compatible = "st,stm32h7-timer-trigger";
677 reg = 677 reg = <13>;
678 status 678 status = "disabled";
679 }; 679 };
680 }; 680 };
681 681
682 lptimer1: timer@400090 682 lptimer1: timer@40009000 {
683 #address-cells 683 #address-cells = <1>;
684 #size-cells = 684 #size-cells = <0>;
685 compatible = " 685 compatible = "st,stm32-lptimer";
686 reg = <0x40009 686 reg = <0x40009000 0x400>;
687 interrupts-ext 687 interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
688 clocks = <&rcc 688 clocks = <&rcc LPTIM1_K>;
689 clock-names = 689 clock-names = "mux";
690 wakeup-source; 690 wakeup-source;
691 access-control 691 access-controllers = <&etzpc 25>;
692 status = "disa 692 status = "disabled";
693 693
694 pwm { 694 pwm {
695 compat 695 compatible = "st,stm32-pwm-lp";
696 #pwm-c 696 #pwm-cells = <3>;
697 status 697 status = "disabled";
698 }; 698 };
699 699
700 trigger@0 { 700 trigger@0 {
701 compat 701 compatible = "st,stm32-lptimer-trigger";
702 reg = 702 reg = <0>;
703 status 703 status = "disabled";
704 }; 704 };
705 705
706 counter { 706 counter {
707 compat 707 compatible = "st,stm32-lptimer-counter";
708 status 708 status = "disabled";
709 }; 709 };
710 }; 710 };
711 711
712 i2s2: audio-controller 712 i2s2: audio-controller@4000b000 {
713 compatible = " 713 compatible = "st,stm32h7-i2s";
714 #sound-dai-cel 714 #sound-dai-cells = <0>;
715 reg = <0x4000b 715 reg = <0x4000b000 0x400>;
716 interrupts = < 716 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
717 dmas = <&dmamu 717 dmas = <&dmamux1 39 0x400 0x01>,
718 <&dmamu 718 <&dmamux1 40 0x400 0x01>;
719 dma-names = "r 719 dma-names = "rx", "tx";
720 access-control 720 access-controllers = <&etzpc 27>;
721 status = "disa 721 status = "disabled";
722 }; 722 };
723 723
724 spi2: spi@4000b000 { 724 spi2: spi@4000b000 {
725 #address-cells 725 #address-cells = <1>;
726 #size-cells = 726 #size-cells = <0>;
727 compatible = " 727 compatible = "st,stm32h7-spi";
728 reg = <0x4000b 728 reg = <0x4000b000 0x400>;
729 interrupts = < 729 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
730 clocks = <&rcc 730 clocks = <&rcc SPI2_K>;
731 resets = <&rcc 731 resets = <&rcc SPI2_R>;
732 dmas = <&dmamu 732 dmas = <&dmamux1 39 0x400 0x05>,
733 <&dmamu 733 <&dmamux1 40 0x400 0x05>;
734 dma-names = "r 734 dma-names = "rx", "tx";
735 access-control 735 access-controllers = <&etzpc 27>;
736 status = "disa 736 status = "disabled";
737 }; 737 };
738 738
739 i2s3: audio-controller 739 i2s3: audio-controller@4000c000 {
740 compatible = " 740 compatible = "st,stm32h7-i2s";
741 #sound-dai-cel 741 #sound-dai-cells = <0>;
742 reg = <0x4000c 742 reg = <0x4000c000 0x400>;
743 interrupts = < 743 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
744 dmas = <&dmamu 744 dmas = <&dmamux1 61 0x400 0x01>,
745 <&dmamu 745 <&dmamux1 62 0x400 0x01>;
746 dma-names = "r 746 dma-names = "rx", "tx";
747 access-control 747 access-controllers = <&etzpc 28>;
748 status = "disa 748 status = "disabled";
749 }; 749 };
750 750
751 spi3: spi@4000c000 { 751 spi3: spi@4000c000 {
752 #address-cells 752 #address-cells = <1>;
753 #size-cells = 753 #size-cells = <0>;
754 compatible = " 754 compatible = "st,stm32h7-spi";
755 reg = <0x4000c 755 reg = <0x4000c000 0x400>;
756 interrupts = < 756 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
757 clocks = <&rcc 757 clocks = <&rcc SPI3_K>;
758 resets = <&rcc 758 resets = <&rcc SPI3_R>;
759 dmas = <&dmamu 759 dmas = <&dmamux1 61 0x400 0x05>,
760 <&dmamu 760 <&dmamux1 62 0x400 0x05>;
761 dma-names = "r 761 dma-names = "rx", "tx";
762 access-control 762 access-controllers = <&etzpc 28>;
763 status = "disa 763 status = "disabled";
764 }; 764 };
765 765
766 spdifrx: audio-control 766 spdifrx: audio-controller@4000d000 {
767 compatible = " 767 compatible = "st,stm32h7-spdifrx";
768 #sound-dai-cel 768 #sound-dai-cells = <0>;
769 reg = <0x4000d 769 reg = <0x4000d000 0x400>;
770 clocks = <&rcc 770 clocks = <&rcc SPDIF_K>;
771 clock-names = 771 clock-names = "kclk";
772 interrupts = < 772 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
773 dmas = <&dmamu 773 dmas = <&dmamux1 93 0x400 0x01>,
774 <&dmamu 774 <&dmamux1 94 0x400 0x01>;
775 dma-names = "r 775 dma-names = "rx", "rx-ctrl";
776 access-control 776 access-controllers = <&etzpc 29>;
777 status = "disa 777 status = "disabled";
778 }; 778 };
779 779
780 usart2: serial@4000e00 780 usart2: serial@4000e000 {
781 compatible = " 781 compatible = "st,stm32h7-uart";
782 reg = <0x4000e 782 reg = <0x4000e000 0x400>;
783 interrupts-ext 783 interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
784 clocks = <&rcc 784 clocks = <&rcc USART2_K>;
785 wakeup-source; 785 wakeup-source;
786 dmas = <&dmamu 786 dmas = <&dmamux1 43 0x400 0x15>,
787 <&dmamu 787 <&dmamux1 44 0x400 0x11>;
788 dma-names = "r 788 dma-names = "rx", "tx";
789 access-control 789 access-controllers = <&etzpc 30>;
790 status = "disa 790 status = "disabled";
791 }; 791 };
792 792
793 usart3: serial@4000f00 793 usart3: serial@4000f000 {
794 compatible = " 794 compatible = "st,stm32h7-uart";
795 reg = <0x4000f 795 reg = <0x4000f000 0x400>;
796 interrupts-ext 796 interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
797 clocks = <&rcc 797 clocks = <&rcc USART3_K>;
798 wakeup-source; 798 wakeup-source;
799 dmas = <&dmamu 799 dmas = <&dmamux1 45 0x400 0x15>,
800 <&dmamu 800 <&dmamux1 46 0x400 0x11>;
801 dma-names = "r 801 dma-names = "rx", "tx";
802 access-control 802 access-controllers = <&etzpc 31>;
803 status = "disa 803 status = "disabled";
804 }; 804 };
805 805
806 uart4: serial@40010000 806 uart4: serial@40010000 {
807 compatible = " 807 compatible = "st,stm32h7-uart";
808 reg = <0x40010 808 reg = <0x40010000 0x400>;
809 interrupts-ext 809 interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
810 clocks = <&rcc 810 clocks = <&rcc UART4_K>;
811 wakeup-source; 811 wakeup-source;
812 dmas = <&dmamu 812 dmas = <&dmamux1 63 0x400 0x15>,
813 <&dmamu 813 <&dmamux1 64 0x400 0x11>;
814 dma-names = "r 814 dma-names = "rx", "tx";
815 access-control 815 access-controllers = <&etzpc 32>;
816 status = "disa 816 status = "disabled";
817 }; 817 };
818 818
819 uart5: serial@40011000 819 uart5: serial@40011000 {
820 compatible = " 820 compatible = "st,stm32h7-uart";
821 reg = <0x40011 821 reg = <0x40011000 0x400>;
822 interrupts-ext 822 interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
823 clocks = <&rcc 823 clocks = <&rcc UART5_K>;
824 wakeup-source; 824 wakeup-source;
825 dmas = <&dmamu 825 dmas = <&dmamux1 65 0x400 0x15>,
826 <&dmamu 826 <&dmamux1 66 0x400 0x11>;
827 dma-names = "r 827 dma-names = "rx", "tx";
828 access-control 828 access-controllers = <&etzpc 33>;
829 status = "disa 829 status = "disabled";
830 }; 830 };
831 831
832 i2c1: i2c@40012000 { 832 i2c1: i2c@40012000 {
833 compatible = " 833 compatible = "st,stm32mp15-i2c";
834 reg = <0x40012 834 reg = <0x40012000 0x400>;
835 interrupt-name 835 interrupt-names = "event", "error";
836 interrupts = < 836 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
837 < 837 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
838 clocks = <&rcc 838 clocks = <&rcc I2C1_K>;
839 resets = <&rcc 839 resets = <&rcc I2C1_R>;
840 #address-cells 840 #address-cells = <1>;
841 #size-cells = 841 #size-cells = <0>;
842 st,syscfg-fmp 842 st,syscfg-fmp = <&syscfg 0x4 0x1>;
843 wakeup-source; 843 wakeup-source;
844 i2c-analog-fil 844 i2c-analog-filter;
845 access-control 845 access-controllers = <&etzpc 34>;
846 status = "disa 846 status = "disabled";
847 }; 847 };
848 848
849 i2c2: i2c@40013000 { 849 i2c2: i2c@40013000 {
850 compatible = " 850 compatible = "st,stm32mp15-i2c";
851 reg = <0x40013 851 reg = <0x40013000 0x400>;
852 interrupt-name 852 interrupt-names = "event", "error";
853 interrupts = < 853 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
854 < 854 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
855 clocks = <&rcc 855 clocks = <&rcc I2C2_K>;
856 resets = <&rcc 856 resets = <&rcc I2C2_R>;
857 #address-cells 857 #address-cells = <1>;
858 #size-cells = 858 #size-cells = <0>;
859 st,syscfg-fmp 859 st,syscfg-fmp = <&syscfg 0x4 0x2>;
860 wakeup-source; 860 wakeup-source;
861 i2c-analog-fil 861 i2c-analog-filter;
862 access-control 862 access-controllers = <&etzpc 35>;
863 status = "disa 863 status = "disabled";
864 }; 864 };
865 865
866 i2c3: i2c@40014000 { 866 i2c3: i2c@40014000 {
867 compatible = " 867 compatible = "st,stm32mp15-i2c";
868 reg = <0x40014 868 reg = <0x40014000 0x400>;
869 interrupt-name 869 interrupt-names = "event", "error";
870 interrupts = < 870 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
871 < 871 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
872 clocks = <&rcc 872 clocks = <&rcc I2C3_K>;
873 resets = <&rcc 873 resets = <&rcc I2C3_R>;
874 #address-cells 874 #address-cells = <1>;
875 #size-cells = 875 #size-cells = <0>;
876 st,syscfg-fmp 876 st,syscfg-fmp = <&syscfg 0x4 0x4>;
877 wakeup-source; 877 wakeup-source;
878 i2c-analog-fil 878 i2c-analog-filter;
879 access-control 879 access-controllers = <&etzpc 36>;
880 status = "disa 880 status = "disabled";
881 }; 881 };
882 882
883 i2c5: i2c@40015000 { 883 i2c5: i2c@40015000 {
884 compatible = " 884 compatible = "st,stm32mp15-i2c";
885 reg = <0x40015 885 reg = <0x40015000 0x400>;
886 interrupt-name 886 interrupt-names = "event", "error";
887 interrupts = < 887 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
888 < 888 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
889 clocks = <&rcc 889 clocks = <&rcc I2C5_K>;
890 resets = <&rcc 890 resets = <&rcc I2C5_R>;
891 #address-cells 891 #address-cells = <1>;
892 #size-cells = 892 #size-cells = <0>;
893 st,syscfg-fmp 893 st,syscfg-fmp = <&syscfg 0x4 0x10>;
894 wakeup-source; 894 wakeup-source;
895 i2c-analog-fil 895 i2c-analog-filter;
896 access-control 896 access-controllers = <&etzpc 37>;
897 status = "disa 897 status = "disabled";
898 }; 898 };
899 899
900 cec: cec@40016000 { 900 cec: cec@40016000 {
901 compatible = " 901 compatible = "st,stm32-cec";
902 reg = <0x40016 902 reg = <0x40016000 0x400>;
903 interrupts = < 903 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
904 clocks = <&rcc 904 clocks = <&rcc CEC_K>, <&rcc CEC>;
905 clock-names = 905 clock-names = "cec", "hdmi-cec";
906 access-control 906 access-controllers = <&etzpc 38>;
907 status = "disa 907 status = "disabled";
908 }; 908 };
909 909
910 dac: dac@40017000 { 910 dac: dac@40017000 {
911 compatible = " 911 compatible = "st,stm32h7-dac-core";
912 reg = <0x40017 912 reg = <0x40017000 0x400>;
913 clocks = <&rcc 913 clocks = <&rcc DAC12>;
914 clock-names = 914 clock-names = "pclk";
915 #address-cells 915 #address-cells = <1>;
916 #size-cells = 916 #size-cells = <0>;
917 access-control 917 access-controllers = <&etzpc 39>;
918 status = "disa 918 status = "disabled";
919 919
920 dac1: dac@1 { 920 dac1: dac@1 {
921 compat 921 compatible = "st,stm32-dac";
922 #io-ch 922 #io-channel-cells = <1>;
923 reg = 923 reg = <1>;
924 status 924 status = "disabled";
925 }; 925 };
926 926
927 dac2: dac@2 { 927 dac2: dac@2 {
928 compat 928 compatible = "st,stm32-dac";
929 #io-ch 929 #io-channel-cells = <1>;
930 reg = 930 reg = <2>;
931 status 931 status = "disabled";
932 }; 932 };
933 }; 933 };
934 934
935 uart7: serial@40018000 935 uart7: serial@40018000 {
936 compatible = " 936 compatible = "st,stm32h7-uart";
937 reg = <0x40018 937 reg = <0x40018000 0x400>;
938 interrupts-ext 938 interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
939 clocks = <&rcc 939 clocks = <&rcc UART7_K>;
940 wakeup-source; 940 wakeup-source;
941 dmas = <&dmamu 941 dmas = <&dmamux1 79 0x400 0x15>,
942 <&dmamu 942 <&dmamux1 80 0x400 0x11>;
943 dma-names = "r 943 dma-names = "rx", "tx";
944 access-control 944 access-controllers = <&etzpc 40>;
945 status = "disa 945 status = "disabled";
946 }; 946 };
947 947
948 uart8: serial@40019000 948 uart8: serial@40019000 {
949 compatible = " 949 compatible = "st,stm32h7-uart";
950 reg = <0x40019 950 reg = <0x40019000 0x400>;
951 interrupts-ext 951 interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
952 clocks = <&rcc 952 clocks = <&rcc UART8_K>;
953 wakeup-source; 953 wakeup-source;
954 dmas = <&dmamu 954 dmas = <&dmamux1 81 0x400 0x15>,
955 <&dmamu 955 <&dmamux1 82 0x400 0x11>;
956 dma-names = "r 956 dma-names = "rx", "tx";
957 access-control 957 access-controllers = <&etzpc 41>;
958 status = "disa 958 status = "disabled";
959 }; 959 };
960 960
961 timers1: timer@4400000 961 timers1: timer@44000000 {
962 #address-cells 962 #address-cells = <1>;
963 #size-cells = 963 #size-cells = <0>;
964 compatible = " 964 compatible = "st,stm32-timers";
965 reg = <0x44000 965 reg = <0x44000000 0x400>;
966 interrupts = < 966 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
967 < 967 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
968 < 968 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
969 < 969 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
970 interrupt-name 970 interrupt-names = "brk", "up", "trg-com", "cc";
971 clocks = <&rcc 971 clocks = <&rcc TIM1_K>;
972 clock-names = 972 clock-names = "int";
973 dmas = <&dmamu 973 dmas = <&dmamux1 11 0x400 0x1>,
974 <&dmamu 974 <&dmamux1 12 0x400 0x1>,
975 <&dmamu 975 <&dmamux1 13 0x400 0x1>,
976 <&dmamu 976 <&dmamux1 14 0x400 0x1>,
977 <&dmamu 977 <&dmamux1 15 0x400 0x1>,
978 <&dmamu 978 <&dmamux1 16 0x400 0x1>,
979 <&dmamu 979 <&dmamux1 17 0x400 0x1>;
980 dma-names = "c 980 dma-names = "ch1", "ch2", "ch3", "ch4",
981 "u 981 "up", "trig", "com";
982 access-control 982 access-controllers = <&etzpc 48>;
983 status = "disa 983 status = "disabled";
984 984
985 pwm { 985 pwm {
986 compat 986 compatible = "st,stm32-pwm";
987 #pwm-c 987 #pwm-cells = <3>;
988 status 988 status = "disabled";
989 }; 989 };
990 990
991 timer@0 { 991 timer@0 {
992 compat 992 compatible = "st,stm32h7-timer-trigger";
993 reg = 993 reg = <0>;
994 status 994 status = "disabled";
995 }; 995 };
996 996
997 counter { 997 counter {
998 compat 998 compatible = "st,stm32-timer-counter";
999 status 999 status = "disabled";
1000 }; 1000 };
1001 }; 1001 };
1002 1002
1003 timers8: timer@440010 1003 timers8: timer@44001000 {
1004 #address-cell 1004 #address-cells = <1>;
1005 #size-cells = 1005 #size-cells = <0>;
1006 compatible = 1006 compatible = "st,stm32-timers";
1007 reg = <0x4400 1007 reg = <0x44001000 0x400>;
1008 interrupts = 1008 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1009 1009 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1010 1010 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1011 1011 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1012 interrupt-nam 1012 interrupt-names = "brk", "up", "trg-com", "cc";
1013 clocks = <&rc 1013 clocks = <&rcc TIM8_K>;
1014 clock-names = 1014 clock-names = "int";
1015 dmas = <&dmam 1015 dmas = <&dmamux1 47 0x400 0x1>,
1016 <&dmam 1016 <&dmamux1 48 0x400 0x1>,
1017 <&dmam 1017 <&dmamux1 49 0x400 0x1>,
1018 <&dmam 1018 <&dmamux1 50 0x400 0x1>,
1019 <&dmam 1019 <&dmamux1 51 0x400 0x1>,
1020 <&dmam 1020 <&dmamux1 52 0x400 0x1>,
1021 <&dmam 1021 <&dmamux1 53 0x400 0x1>;
1022 dma-names = " 1022 dma-names = "ch1", "ch2", "ch3", "ch4",
1023 " 1023 "up", "trig", "com";
1024 access-contro 1024 access-controllers = <&etzpc 49>;
1025 status = "dis 1025 status = "disabled";
1026 1026
1027 pwm { 1027 pwm {
1028 compa 1028 compatible = "st,stm32-pwm";
1029 #pwm- 1029 #pwm-cells = <3>;
1030 statu 1030 status = "disabled";
1031 }; 1031 };
1032 1032
1033 timer@7 { 1033 timer@7 {
1034 compa 1034 compatible = "st,stm32h7-timer-trigger";
1035 reg = 1035 reg = <7>;
1036 statu 1036 status = "disabled";
1037 }; 1037 };
1038 1038
1039 counter { 1039 counter {
1040 compa 1040 compatible = "st,stm32-timer-counter";
1041 statu 1041 status = "disabled";
1042 }; 1042 };
1043 }; 1043 };
1044 1044
1045 usart6: serial@440030 1045 usart6: serial@44003000 {
1046 compatible = 1046 compatible = "st,stm32h7-uart";
1047 reg = <0x4400 1047 reg = <0x44003000 0x400>;
1048 interrupts-ex 1048 interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
1049 clocks = <&rc 1049 clocks = <&rcc USART6_K>;
1050 wakeup-source 1050 wakeup-source;
1051 dmas = <&dmam 1051 dmas = <&dmamux1 71 0x400 0x15>,
1052 <&dmamux1 72 1052 <&dmamux1 72 0x400 0x11>;
1053 dma-names = " 1053 dma-names = "rx", "tx";
1054 access-contro 1054 access-controllers = <&etzpc 51>;
1055 status = "dis 1055 status = "disabled";
1056 }; 1056 };
1057 1057
1058 i2s1: audio-controlle 1058 i2s1: audio-controller@44004000 {
1059 compatible = 1059 compatible = "st,stm32h7-i2s";
1060 #sound-dai-ce 1060 #sound-dai-cells = <0>;
1061 reg = <0x4400 1061 reg = <0x44004000 0x400>;
1062 interrupts = 1062 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1063 dmas = <&dmam 1063 dmas = <&dmamux1 37 0x400 0x01>,
1064 <&dmamux1 38 1064 <&dmamux1 38 0x400 0x01>;
1065 dma-names = " 1065 dma-names = "rx", "tx";
1066 access-contro 1066 access-controllers = <&etzpc 52>;
1067 status = "dis 1067 status = "disabled";
1068 }; 1068 };
1069 1069
1070 spi1: spi@44004000 { 1070 spi1: spi@44004000 {
1071 #address-cell 1071 #address-cells = <1>;
1072 #size-cells = 1072 #size-cells = <0>;
1073 compatible = 1073 compatible = "st,stm32h7-spi";
1074 reg = <0x4400 1074 reg = <0x44004000 0x400>;
1075 interrupts = 1075 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1076 clocks = <&rc 1076 clocks = <&rcc SPI1_K>;
1077 resets = <&rc 1077 resets = <&rcc SPI1_R>;
1078 dmas = <&dmam 1078 dmas = <&dmamux1 37 0x400 0x05>,
1079 <&dmamux1 38 1079 <&dmamux1 38 0x400 0x05>;
1080 dma-names = " 1080 dma-names = "rx", "tx";
1081 access-contro 1081 access-controllers = <&etzpc 52>;
1082 status = "dis 1082 status = "disabled";
1083 }; 1083 };
1084 1084
1085 spi4: spi@44005000 { 1085 spi4: spi@44005000 {
1086 #address-cell 1086 #address-cells = <1>;
1087 #size-cells = 1087 #size-cells = <0>;
1088 compatible = 1088 compatible = "st,stm32h7-spi";
1089 reg = <0x4400 1089 reg = <0x44005000 0x400>;
1090 interrupts = 1090 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1091 clocks = <&rc 1091 clocks = <&rcc SPI4_K>;
1092 resets = <&rc 1092 resets = <&rcc SPI4_R>;
1093 dmas = <&dmam 1093 dmas = <&dmamux1 83 0x400 0x05>,
1094 <&dmamux1 84 1094 <&dmamux1 84 0x400 0x05>;
1095 dma-names = " 1095 dma-names = "rx", "tx";
1096 access-contro 1096 access-controllers = <&etzpc 53>;
1097 status = "dis 1097 status = "disabled";
1098 }; 1098 };
1099 1099
1100 timers15: timer@44006 1100 timers15: timer@44006000 {
1101 #address-cell 1101 #address-cells = <1>;
1102 #size-cells = 1102 #size-cells = <0>;
1103 compatible = 1103 compatible = "st,stm32-timers";
1104 reg = <0x4400 1104 reg = <0x44006000 0x400>;
1105 interrupts = 1105 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1106 interrupt-nam 1106 interrupt-names = "global";
1107 clocks = <&rc 1107 clocks = <&rcc TIM15_K>;
1108 clock-names = 1108 clock-names = "int";
1109 dmas = <&dmam 1109 dmas = <&dmamux1 105 0x400 0x1>,
1110 <&dmam 1110 <&dmamux1 106 0x400 0x1>,
1111 <&dmam 1111 <&dmamux1 107 0x400 0x1>,
1112 <&dmam 1112 <&dmamux1 108 0x400 0x1>;
1113 dma-names = " 1113 dma-names = "ch1", "up", "trig", "com";
1114 access-contro 1114 access-controllers = <&etzpc 54>;
1115 status = "dis 1115 status = "disabled";
1116 1116
1117 pwm { 1117 pwm {
1118 compa 1118 compatible = "st,stm32-pwm";
1119 #pwm- 1119 #pwm-cells = <3>;
1120 statu 1120 status = "disabled";
1121 }; 1121 };
1122 1122
1123 timer@14 { 1123 timer@14 {
1124 compa 1124 compatible = "st,stm32h7-timer-trigger";
1125 reg = 1125 reg = <14>;
1126 statu 1126 status = "disabled";
1127 }; 1127 };
1128 }; 1128 };
1129 1129
1130 timers16: timer@44007 1130 timers16: timer@44007000 {
1131 #address-cell 1131 #address-cells = <1>;
1132 #size-cells = 1132 #size-cells = <0>;
1133 compatible = 1133 compatible = "st,stm32-timers";
1134 reg = <0x4400 1134 reg = <0x44007000 0x400>;
1135 interrupts = 1135 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1136 interrupt-nam 1136 interrupt-names = "global";
1137 clocks = <&rc 1137 clocks = <&rcc TIM16_K>;
1138 clock-names = 1138 clock-names = "int";
1139 dmas = <&dmam 1139 dmas = <&dmamux1 109 0x400 0x1>,
1140 <&dmamux1 110 1140 <&dmamux1 110 0x400 0x1>;
1141 dma-names = " 1141 dma-names = "ch1", "up";
1142 access-contro 1142 access-controllers = <&etzpc 55>;
1143 status = "dis 1143 status = "disabled";
1144 1144
1145 pwm { 1145 pwm {
1146 compa 1146 compatible = "st,stm32-pwm";
1147 #pwm- 1147 #pwm-cells = <3>;
1148 statu 1148 status = "disabled";
1149 }; 1149 };
1150 timer@15 { 1150 timer@15 {
1151 compa 1151 compatible = "st,stm32h7-timer-trigger";
1152 reg = 1152 reg = <15>;
1153 statu 1153 status = "disabled";
1154 }; 1154 };
1155 }; 1155 };
1156 1156
1157 timers17: timer@44008 1157 timers17: timer@44008000 {
1158 #address-cell 1158 #address-cells = <1>;
1159 #size-cells = 1159 #size-cells = <0>;
1160 compatible = 1160 compatible = "st,stm32-timers";
1161 reg = <0x4400 1161 reg = <0x44008000 0x400>;
1162 interrupts = 1162 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1163 interrupt-nam 1163 interrupt-names = "global";
1164 clocks = <&rc 1164 clocks = <&rcc TIM17_K>;
1165 clock-names = 1165 clock-names = "int";
1166 dmas = <&dmam 1166 dmas = <&dmamux1 111 0x400 0x1>,
1167 <&dmamux1 112 1167 <&dmamux1 112 0x400 0x1>;
1168 dma-names = " 1168 dma-names = "ch1", "up";
1169 access-contro 1169 access-controllers = <&etzpc 56>;
1170 status = "dis 1170 status = "disabled";
1171 1171
1172 pwm { 1172 pwm {
1173 compa 1173 compatible = "st,stm32-pwm";
1174 #pwm- 1174 #pwm-cells = <3>;
1175 statu 1175 status = "disabled";
1176 }; 1176 };
1177 1177
1178 timer@16 { 1178 timer@16 {
1179 compa 1179 compatible = "st,stm32h7-timer-trigger";
1180 reg = 1180 reg = <16>;
1181 statu 1181 status = "disabled";
1182 }; 1182 };
1183 }; 1183 };
1184 1184
1185 spi5: spi@44009000 { 1185 spi5: spi@44009000 {
1186 #address-cell 1186 #address-cells = <1>;
1187 #size-cells = 1187 #size-cells = <0>;
1188 compatible = 1188 compatible = "st,stm32h7-spi";
1189 reg = <0x4400 1189 reg = <0x44009000 0x400>;
1190 interrupts = 1190 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1191 clocks = <&rc 1191 clocks = <&rcc SPI5_K>;
1192 resets = <&rc 1192 resets = <&rcc SPI5_R>;
1193 dmas = <&dmam 1193 dmas = <&dmamux1 85 0x400 0x05>,
1194 <&dmamux1 86 1194 <&dmamux1 86 0x400 0x05>;
1195 dma-names = " 1195 dma-names = "rx", "tx";
1196 access-contro 1196 access-controllers = <&etzpc 57>;
1197 status = "dis 1197 status = "disabled";
1198 }; 1198 };
1199 1199
1200 sai1: sai@4400a000 { 1200 sai1: sai@4400a000 {
1201 compatible = 1201 compatible = "st,stm32h7-sai";
1202 #address-cell 1202 #address-cells = <1>;
1203 #size-cells = 1203 #size-cells = <1>;
1204 ranges = <0 0 1204 ranges = <0 0x4400a000 0x400>;
1205 reg = <0x4400 1205 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
1206 interrupts = 1206 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1207 resets = <&rc 1207 resets = <&rcc SAI1_R>;
1208 access-contro 1208 access-controllers = <&etzpc 58>;
1209 status = "dis 1209 status = "disabled";
1210 1210
1211 sai1a: audio- 1211 sai1a: audio-controller@4400a004 {
1212 #soun 1212 #sound-dai-cells = <0>;
1213 1213
1214 compa 1214 compatible = "st,stm32-sai-sub-a";
1215 reg = 1215 reg = <0x4 0x20>;
1216 clock 1216 clocks = <&rcc SAI1_K>;
1217 clock 1217 clock-names = "sai_ck";
1218 dmas 1218 dmas = <&dmamux1 87 0x400 0x01>;
1219 statu 1219 status = "disabled";
1220 }; 1220 };
1221 1221
1222 sai1b: audio- 1222 sai1b: audio-controller@4400a024 {
1223 #soun 1223 #sound-dai-cells = <0>;
1224 compa 1224 compatible = "st,stm32-sai-sub-b";
1225 reg = 1225 reg = <0x24 0x20>;
1226 clock 1226 clocks = <&rcc SAI1_K>;
1227 clock 1227 clock-names = "sai_ck";
1228 dmas 1228 dmas = <&dmamux1 88 0x400 0x01>;
1229 statu 1229 status = "disabled";
1230 }; 1230 };
1231 }; 1231 };
1232 1232
1233 sai2: sai@4400b000 { 1233 sai2: sai@4400b000 {
1234 compatible = 1234 compatible = "st,stm32h7-sai";
1235 #address-cell 1235 #address-cells = <1>;
1236 #size-cells = 1236 #size-cells = <1>;
1237 ranges = <0 0 1237 ranges = <0 0x4400b000 0x400>;
1238 reg = <0x4400 1238 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
1239 interrupts = 1239 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1240 resets = <&rc 1240 resets = <&rcc SAI2_R>;
1241 access-contro 1241 access-controllers = <&etzpc 59>;
1242 status = "dis 1242 status = "disabled";
1243 1243
1244 sai2a: audio- 1244 sai2a: audio-controller@4400b004 {
1245 #soun 1245 #sound-dai-cells = <0>;
1246 compa 1246 compatible = "st,stm32-sai-sub-a";
1247 reg = 1247 reg = <0x4 0x20>;
1248 clock 1248 clocks = <&rcc SAI2_K>;
1249 clock 1249 clock-names = "sai_ck";
1250 dmas 1250 dmas = <&dmamux1 89 0x400 0x01>;
1251 statu 1251 status = "disabled";
1252 }; 1252 };
1253 1253
1254 sai2b: audio- 1254 sai2b: audio-controller@4400b024 {
1255 #soun 1255 #sound-dai-cells = <0>;
1256 compa 1256 compatible = "st,stm32-sai-sub-b";
1257 reg = 1257 reg = <0x24 0x20>;
1258 clock 1258 clocks = <&rcc SAI2_K>;
1259 clock 1259 clock-names = "sai_ck";
1260 dmas 1260 dmas = <&dmamux1 90 0x400 0x01>;
1261 statu 1261 status = "disabled";
1262 }; 1262 };
1263 }; 1263 };
1264 1264
1265 sai3: sai@4400c000 { 1265 sai3: sai@4400c000 {
1266 compatible = 1266 compatible = "st,stm32h7-sai";
1267 #address-cell 1267 #address-cells = <1>;
1268 #size-cells = 1268 #size-cells = <1>;
1269 ranges = <0 0 1269 ranges = <0 0x4400c000 0x400>;
1270 reg = <0x4400 1270 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
1271 interrupts = 1271 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1272 resets = <&rc 1272 resets = <&rcc SAI3_R>;
1273 access-contro 1273 access-controllers = <&etzpc 60>;
1274 status = "dis 1274 status = "disabled";
1275 1275
1276 sai3a: audio- 1276 sai3a: audio-controller@4400c004 {
1277 #soun 1277 #sound-dai-cells = <0>;
1278 compa 1278 compatible = "st,stm32-sai-sub-a";
1279 reg = 1279 reg = <0x04 0x20>;
1280 clock 1280 clocks = <&rcc SAI3_K>;
1281 clock 1281 clock-names = "sai_ck";
1282 dmas 1282 dmas = <&dmamux1 113 0x400 0x01>;
1283 statu 1283 status = "disabled";
1284 }; 1284 };
1285 1285
1286 sai3b: audio- 1286 sai3b: audio-controller@4400c024 {
1287 #soun 1287 #sound-dai-cells = <0>;
1288 compa 1288 compatible = "st,stm32-sai-sub-b";
1289 reg = 1289 reg = <0x24 0x20>;
1290 clock 1290 clocks = <&rcc SAI3_K>;
1291 clock 1291 clock-names = "sai_ck";
1292 dmas 1292 dmas = <&dmamux1 114 0x400 0x01>;
1293 statu 1293 status = "disabled";
1294 }; 1294 };
1295 }; 1295 };
1296 1296
1297 dfsdm: dfsdm@4400d000 1297 dfsdm: dfsdm@4400d000 {
1298 compatible = 1298 compatible = "st,stm32mp1-dfsdm";
1299 reg = <0x4400 1299 reg = <0x4400d000 0x800>;
1300 clocks = <&rc 1300 clocks = <&rcc DFSDM_K>;
1301 clock-names = 1301 clock-names = "dfsdm";
1302 #address-cell 1302 #address-cells = <1>;
1303 #size-cells = 1303 #size-cells = <0>;
1304 access-contro 1304 access-controllers = <&etzpc 61>;
1305 status = "dis 1305 status = "disabled";
1306 1306
1307 dfsdm0: filte 1307 dfsdm0: filter@0 {
1308 compa 1308 compatible = "st,stm32-dfsdm-adc";
1309 #io-c 1309 #io-channel-cells = <1>;
1310 reg = 1310 reg = <0>;
1311 inter 1311 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
1312 dmas 1312 dmas = <&dmamux1 101 0x400 0x01>;
1313 dma-n 1313 dma-names = "rx";
1314 statu 1314 status = "disabled";
1315 }; 1315 };
1316 1316
1317 dfsdm1: filte 1317 dfsdm1: filter@1 {
1318 compa 1318 compatible = "st,stm32-dfsdm-adc";
1319 #io-c 1319 #io-channel-cells = <1>;
1320 reg = 1320 reg = <1>;
1321 inter 1321 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1322 dmas 1322 dmas = <&dmamux1 102 0x400 0x01>;
1323 dma-n 1323 dma-names = "rx";
1324 statu 1324 status = "disabled";
1325 }; 1325 };
1326 1326
1327 dfsdm2: filte 1327 dfsdm2: filter@2 {
1328 compa 1328 compatible = "st,stm32-dfsdm-adc";
1329 #io-c 1329 #io-channel-cells = <1>;
1330 reg = 1330 reg = <2>;
1331 inter 1331 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1332 dmas 1332 dmas = <&dmamux1 103 0x400 0x01>;
1333 dma-n 1333 dma-names = "rx";
1334 statu 1334 status = "disabled";
1335 }; 1335 };
1336 1336
1337 dfsdm3: filte 1337 dfsdm3: filter@3 {
1338 compa 1338 compatible = "st,stm32-dfsdm-adc";
1339 #io-c 1339 #io-channel-cells = <1>;
1340 reg = 1340 reg = <3>;
1341 inter 1341 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1342 dmas 1342 dmas = <&dmamux1 104 0x400 0x01>;
1343 dma-n 1343 dma-names = "rx";
1344 statu 1344 status = "disabled";
1345 }; 1345 };
1346 1346
1347 dfsdm4: filte 1347 dfsdm4: filter@4 {
1348 compa 1348 compatible = "st,stm32-dfsdm-adc";
1349 #io-c 1349 #io-channel-cells = <1>;
1350 reg = 1350 reg = <4>;
1351 inter 1351 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
1352 dmas 1352 dmas = <&dmamux1 91 0x400 0x01>;
1353 dma-n 1353 dma-names = "rx";
1354 statu 1354 status = "disabled";
1355 }; 1355 };
1356 1356
1357 dfsdm5: filte 1357 dfsdm5: filter@5 {
1358 compa 1358 compatible = "st,stm32-dfsdm-adc";
1359 #io-c 1359 #io-channel-cells = <1>;
1360 reg = 1360 reg = <5>;
1361 inter 1361 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
1362 dmas 1362 dmas = <&dmamux1 92 0x400 0x01>;
1363 dma-n 1363 dma-names = "rx";
1364 statu 1364 status = "disabled";
1365 }; 1365 };
1366 }; 1366 };
1367 1367
1368 dma1: dma-controller@ 1368 dma1: dma-controller@48000000 {
1369 compatible = 1369 compatible = "st,stm32-dma";
1370 reg = <0x4800 1370 reg = <0x48000000 0x400>;
1371 interrupts = 1371 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
1372 1372 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1373 1373 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
1374 1374 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
1375 1375 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
1376 1376 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
1377 1377 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
1378 1378 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1379 clocks = <&rc 1379 clocks = <&rcc DMA1>;
1380 resets = <&rc 1380 resets = <&rcc DMA1_R>;
1381 #dma-cells = 1381 #dma-cells = <4>;
1382 st,mem2mem; 1382 st,mem2mem;
1383 dma-requests 1383 dma-requests = <8>;
1384 access-contro 1384 access-controllers = <&etzpc 88>;
1385 }; 1385 };
1386 1386
1387 dma2: dma-controller@ 1387 dma2: dma-controller@48001000 {
1388 compatible = 1388 compatible = "st,stm32-dma";
1389 reg = <0x4800 1389 reg = <0x48001000 0x400>;
1390 interrupts = 1390 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1391 1391 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1392 1392 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1393 1393 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1394 1394 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
1395 1395 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
1396 1396 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1397 1397 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1398 clocks = <&rc 1398 clocks = <&rcc DMA2>;
1399 resets = <&rc 1399 resets = <&rcc DMA2_R>;
1400 #dma-cells = 1400 #dma-cells = <4>;
1401 st,mem2mem; 1401 st,mem2mem;
1402 dma-requests 1402 dma-requests = <8>;
1403 access-contro 1403 access-controllers = <&etzpc 89>;
1404 }; 1404 };
1405 1405
1406 dmamux1: dma-router@4 1406 dmamux1: dma-router@48002000 {
1407 compatible = 1407 compatible = "st,stm32h7-dmamux";
1408 reg = <0x4800 1408 reg = <0x48002000 0x40>;
1409 #dma-cells = 1409 #dma-cells = <3>;
1410 dma-requests 1410 dma-requests = <128>;
1411 dma-masters = 1411 dma-masters = <&dma1 &dma2>;
1412 dma-channels 1412 dma-channels = <16>;
1413 clocks = <&rc 1413 clocks = <&rcc DMAMUX>;
1414 resets = <&rc 1414 resets = <&rcc DMAMUX_R>;
1415 access-contro 1415 access-controllers = <&etzpc 90>;
1416 }; 1416 };
1417 1417
1418 adc: adc@48003000 { 1418 adc: adc@48003000 {
1419 compatible = 1419 compatible = "st,stm32mp1-adc-core";
1420 reg = <0x4800 1420 reg = <0x48003000 0x400>;
1421 interrupts = 1421 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
1422 1422 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1423 clocks = <&rc 1423 clocks = <&rcc ADC12>, <&rcc ADC12_K>;
1424 clock-names = 1424 clock-names = "bus", "adc";
1425 interrupt-con 1425 interrupt-controller;
1426 st,syscfg = < 1426 st,syscfg = <&syscfg>;
1427 #interrupt-ce 1427 #interrupt-cells = <1>;
1428 #address-cell 1428 #address-cells = <1>;
1429 #size-cells = 1429 #size-cells = <0>;
1430 access-contro 1430 access-controllers = <&etzpc 72>;
1431 status = "dis 1431 status = "disabled";
1432 1432
1433 adc1: adc@0 { 1433 adc1: adc@0 {
1434 compa 1434 compatible = "st,stm32mp1-adc";
1435 #io-c 1435 #io-channel-cells = <1>;
1436 #addr 1436 #address-cells = <1>;
1437 #size 1437 #size-cells = <0>;
1438 reg = 1438 reg = <0x0>;
1439 inter 1439 interrupt-parent = <&adc>;
1440 inter 1440 interrupts = <0>;
1441 dmas 1441 dmas = <&dmamux1 9 0x400 0x01>;
1442 dma-n 1442 dma-names = "rx";
1443 statu 1443 status = "disabled";
1444 }; 1444 };
1445 1445
1446 adc2: adc@100 1446 adc2: adc@100 {
1447 compa 1447 compatible = "st,stm32mp1-adc";
1448 #io-c 1448 #io-channel-cells = <1>;
1449 #addr 1449 #address-cells = <1>;
1450 #size 1450 #size-cells = <0>;
1451 reg = 1451 reg = <0x100>;
1452 inter 1452 interrupt-parent = <&adc>;
1453 inter 1453 interrupts = <1>;
1454 dmas 1454 dmas = <&dmamux1 10 0x400 0x01>;
1455 dma-n 1455 dma-names = "rx";
1456 nvmem 1456 nvmem-cells = <&vrefint>;
1457 nvmem 1457 nvmem-cell-names = "vrefint";
1458 statu 1458 status = "disabled";
1459 chann 1459 channel@13 {
1460 1460 reg = <13>;
1461 1461 label = "vrefint";
1462 }; 1462 };
1463 chann 1463 channel@14 {
1464 1464 reg = <14>;
1465 1465 label = "vddcore";
1466 }; 1466 };
1467 }; 1467 };
1468 }; 1468 };
1469 1469
1470 sdmmc3: mmc@48004000 1470 sdmmc3: mmc@48004000 {
1471 compatible = 1471 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1472 arm,primecell 1472 arm,primecell-periphid = <0x00253180>;
1473 reg = <0x4800 1473 reg = <0x48004000 0x400>;
1474 interrupts = 1474 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1475 clocks = <&rc 1475 clocks = <&rcc SDMMC3_K>;
1476 clock-names = 1476 clock-names = "apb_pclk";
1477 resets = <&rc 1477 resets = <&rcc SDMMC3_R>;
1478 cap-sd-highsp 1478 cap-sd-highspeed;
1479 cap-mmc-highs 1479 cap-mmc-highspeed;
1480 max-frequency 1480 max-frequency = <120000000>;
1481 access-contro 1481 access-controllers = <&etzpc 86>;
1482 status = "dis 1482 status = "disabled";
1483 }; 1483 };
1484 1484
1485 usbotg_hs: usb-otg@49 1485 usbotg_hs: usb-otg@49000000 {
1486 compatible = 1486 compatible = "st,stm32mp15-hsotg", "snps,dwc2";
1487 reg = <0x4900 1487 reg = <0x49000000 0x10000>;
1488 clocks = <&rc 1488 clocks = <&rcc USBO_K>, <&usbphyc>;
1489 clock-names = 1489 clock-names = "otg", "utmi";
1490 resets = <&rc 1490 resets = <&rcc USBO_R>;
1491 reset-names = 1491 reset-names = "dwc2";
1492 interrupts = 1492 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1493 g-rx-fifo-siz 1493 g-rx-fifo-size = <512>;
1494 g-np-tx-fifo- 1494 g-np-tx-fifo-size = <32>;
1495 g-tx-fifo-siz 1495 g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
1496 dr_mode = "ot 1496 dr_mode = "otg";
1497 otg-rev = <0x 1497 otg-rev = <0x200>;
1498 usb33d-supply 1498 usb33d-supply = <&usb33>;
1499 access-contro 1499 access-controllers = <&etzpc 85>;
1500 status = "dis 1500 status = "disabled";
1501 }; 1501 };
1502 1502
1503 dcmi: dcmi@4c006000 { 1503 dcmi: dcmi@4c006000 {
1504 compatible = 1504 compatible = "st,stm32-dcmi";
1505 reg = <0x4c00 1505 reg = <0x4c006000 0x400>;
1506 interrupts = 1506 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1507 resets = <&rc 1507 resets = <&rcc CAMITF_R>;
1508 clocks = <&rc 1508 clocks = <&rcc DCMI>;
1509 clock-names = 1509 clock-names = "mclk";
1510 dmas = <&dmam 1510 dmas = <&dmamux1 75 0x400 0x01>;
1511 dma-names = " 1511 dma-names = "tx";
1512 access-contro 1512 access-controllers = <&etzpc 70>;
1513 status = "dis 1513 status = "disabled";
1514 }; 1514 };
1515 1515
1516 lptimer2: timer@50021 1516 lptimer2: timer@50021000 {
1517 #address-cell 1517 #address-cells = <1>;
1518 #size-cells = 1518 #size-cells = <0>;
1519 compatible = 1519 compatible = "st,stm32-lptimer";
1520 reg = <0x5002 1520 reg = <0x50021000 0x400>;
1521 interrupts-ex 1521 interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
1522 clocks = <&rc 1522 clocks = <&rcc LPTIM2_K>;
1523 clock-names = 1523 clock-names = "mux";
1524 wakeup-source 1524 wakeup-source;
1525 access-contro 1525 access-controllers = <&etzpc 64>;
1526 status = "dis 1526 status = "disabled";
1527 1527
1528 pwm { 1528 pwm {
1529 compa 1529 compatible = "st,stm32-pwm-lp";
1530 #pwm- 1530 #pwm-cells = <3>;
1531 statu 1531 status = "disabled";
1532 }; 1532 };
1533 1533
1534 trigger@1 { 1534 trigger@1 {
1535 compa 1535 compatible = "st,stm32-lptimer-trigger";
1536 reg = 1536 reg = <1>;
1537 statu 1537 status = "disabled";
1538 }; 1538 };
1539 1539
1540 counter { 1540 counter {
1541 compa 1541 compatible = "st,stm32-lptimer-counter";
1542 statu 1542 status = "disabled";
1543 }; 1543 };
1544 }; 1544 };
1545 1545
1546 lptimer3: timer@50022 1546 lptimer3: timer@50022000 {
1547 #address-cell 1547 #address-cells = <1>;
1548 #size-cells = 1548 #size-cells = <0>;
1549 compatible = 1549 compatible = "st,stm32-lptimer";
1550 reg = <0x5002 1550 reg = <0x50022000 0x400>;
1551 interrupts-ex 1551 interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
1552 clocks = <&rc 1552 clocks = <&rcc LPTIM3_K>;
1553 clock-names = 1553 clock-names = "mux";
1554 wakeup-source 1554 wakeup-source;
1555 access-contro 1555 access-controllers = <&etzpc 65>;
1556 status = "dis 1556 status = "disabled";
1557 1557
1558 pwm { 1558 pwm {
1559 compa 1559 compatible = "st,stm32-pwm-lp";
1560 #pwm- 1560 #pwm-cells = <3>;
1561 statu 1561 status = "disabled";
1562 }; 1562 };
1563 1563
1564 trigger@2 { 1564 trigger@2 {
1565 compa 1565 compatible = "st,stm32-lptimer-trigger";
1566 reg = 1566 reg = <2>;
1567 statu 1567 status = "disabled";
1568 }; 1568 };
1569 }; 1569 };
1570 1570
1571 lptimer4: timer@50023 1571 lptimer4: timer@50023000 {
1572 compatible = 1572 compatible = "st,stm32-lptimer";
1573 reg = <0x5002 1573 reg = <0x50023000 0x400>;
1574 interrupts-ex 1574 interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
1575 clocks = <&rc 1575 clocks = <&rcc LPTIM4_K>;
1576 clock-names = 1576 clock-names = "mux";
1577 wakeup-source 1577 wakeup-source;
1578 access-contro 1578 access-controllers = <&etzpc 66>;
1579 status = "dis 1579 status = "disabled";
1580 1580
1581 pwm { 1581 pwm {
1582 compa 1582 compatible = "st,stm32-pwm-lp";
1583 #pwm- 1583 #pwm-cells = <3>;
1584 statu 1584 status = "disabled";
1585 }; 1585 };
1586 }; 1586 };
1587 1587
1588 lptimer5: timer@50024 1588 lptimer5: timer@50024000 {
1589 compatible = 1589 compatible = "st,stm32-lptimer";
1590 reg = <0x5002 1590 reg = <0x50024000 0x400>;
1591 interrupts-ex 1591 interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
1592 clocks = <&rc 1592 clocks = <&rcc LPTIM5_K>;
1593 clock-names = 1593 clock-names = "mux";
1594 wakeup-source 1594 wakeup-source;
1595 access-contro 1595 access-controllers = <&etzpc 67>;
1596 status = "dis 1596 status = "disabled";
1597 1597
1598 pwm { 1598 pwm {
1599 compa 1599 compatible = "st,stm32-pwm-lp";
1600 #pwm- 1600 #pwm-cells = <3>;
1601 statu 1601 status = "disabled";
1602 }; 1602 };
1603 }; 1603 };
1604 1604
1605 vrefbuf: vrefbuf@5002 1605 vrefbuf: vrefbuf@50025000 {
1606 compatible = 1606 compatible = "st,stm32-vrefbuf";
1607 reg = <0x5002 1607 reg = <0x50025000 0x8>;
1608 regulator-min 1608 regulator-min-microvolt = <1500000>;
1609 regulator-max 1609 regulator-max-microvolt = <2500000>;
1610 clocks = <&rc 1610 clocks = <&rcc VREF>;
1611 access-contro 1611 access-controllers = <&etzpc 69>;
1612 status = "dis 1612 status = "disabled";
1613 }; 1613 };
1614 1614
1615 sai4: sai@50027000 { 1615 sai4: sai@50027000 {
1616 compatible = 1616 compatible = "st,stm32h7-sai";
1617 #address-cell 1617 #address-cells = <1>;
1618 #size-cells = 1618 #size-cells = <1>;
1619 ranges = <0 0 1619 ranges = <0 0x50027000 0x400>;
1620 reg = <0x5002 1620 reg = <0x50027000 0x4>, <0x500273f0 0x10>;
1621 interrupts = 1621 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1622 resets = <&rc 1622 resets = <&rcc SAI4_R>;
1623 access-contro 1623 access-controllers = <&etzpc 68>;
1624 status = "dis 1624 status = "disabled";
1625 1625
1626 sai4a: audio- 1626 sai4a: audio-controller@50027004 {
1627 #soun 1627 #sound-dai-cells = <0>;
1628 compa 1628 compatible = "st,stm32-sai-sub-a";
1629 reg = 1629 reg = <0x04 0x20>;
1630 clock 1630 clocks = <&rcc SAI4_K>;
1631 clock 1631 clock-names = "sai_ck";
1632 dmas 1632 dmas = <&dmamux1 99 0x400 0x01>;
1633 statu 1633 status = "disabled";
1634 }; 1634 };
1635 1635
1636 sai4b: audio- 1636 sai4b: audio-controller@50027024 {
1637 #soun 1637 #sound-dai-cells = <0>;
1638 compa 1638 compatible = "st,stm32-sai-sub-b";
1639 reg = 1639 reg = <0x24 0x20>;
1640 clock 1640 clocks = <&rcc SAI4_K>;
1641 clock 1641 clock-names = "sai_ck";
1642 dmas 1642 dmas = <&dmamux1 100 0x400 0x01>;
1643 statu 1643 status = "disabled";
1644 }; 1644 };
1645 }; 1645 };
1646 1646
1647 hash1: hash@54002000 1647 hash1: hash@54002000 {
1648 compatible = 1648 compatible = "st,stm32f756-hash";
1649 reg = <0x5400 1649 reg = <0x54002000 0x400>;
1650 interrupts = 1650 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1651 clocks = <&rc 1651 clocks = <&rcc HASH1>;
1652 resets = <&rc 1652 resets = <&rcc HASH1_R>;
1653 dmas = <&mdma 1653 dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>;
1654 dma-names = " 1654 dma-names = "in";
1655 dma-maxburst 1655 dma-maxburst = <2>;
1656 access-contro 1656 access-controllers = <&etzpc 8>;
1657 status = "dis 1657 status = "disabled";
1658 }; 1658 };
1659 1659
1660 rng1: rng@54003000 { 1660 rng1: rng@54003000 {
1661 compatible = 1661 compatible = "st,stm32-rng";
1662 reg = <0x5400 1662 reg = <0x54003000 0x400>;
1663 clocks = <&rc 1663 clocks = <&rcc RNG1_K>;
1664 resets = <&rc 1664 resets = <&rcc RNG1_R>;
1665 access-contro 1665 access-controllers = <&etzpc 7>;
1666 status = "dis 1666 status = "disabled";
1667 }; 1667 };
1668 1668
1669 fmc: memory-controlle 1669 fmc: memory-controller@58002000 {
1670 #address-cell 1670 #address-cells = <2>;
1671 #size-cells = 1671 #size-cells = <1>;
1672 compatible = 1672 compatible = "st,stm32mp1-fmc2-ebi";
1673 reg = <0x5800 1673 reg = <0x58002000 0x1000>;
1674 clocks = <&rc 1674 clocks = <&rcc FMC_K>;
1675 resets = <&rc 1675 resets = <&rcc FMC_R>;
1676 access-contro 1676 access-controllers = <&etzpc 91>;
1677 status = "dis 1677 status = "disabled";
1678 1678
1679 ranges = <0 0 1679 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
1680 <1 0 1680 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
1681 <2 0 1681 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
1682 <3 0 1682 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
1683 <4 0 1683 <4 0 0x80000000 0x10000000>; /* NAND */
1684 1684
1685 nand-controll 1685 nand-controller@4,0 {
1686 #addr 1686 #address-cells = <1>;
1687 #size 1687 #size-cells = <0>;
1688 compa 1688 compatible = "st,stm32mp1-fmc2-nfc";
1689 reg = 1689 reg = <4 0x00000000 0x1000>,
1690 1690 <4 0x08010000 0x1000>,
1691 1691 <4 0x08020000 0x1000>,
1692 1692 <4 0x01000000 0x1000>,
1693 1693 <4 0x09010000 0x1000>,
1694 1694 <4 0x09020000 0x1000>;
1695 inter 1695 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1696 dmas 1696 dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
1697 1697 <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
1698 1698 <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
1699 dma-n 1699 dma-names = "tx", "rx", "ecc";
1700 statu 1700 status = "disabled";
1701 }; 1701 };
1702 }; 1702 };
1703 1703
1704 qspi: spi@58003000 { 1704 qspi: spi@58003000 {
1705 compatible = 1705 compatible = "st,stm32f469-qspi";
1706 reg = <0x5800 1706 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1707 reg-names = " 1707 reg-names = "qspi", "qspi_mm";
1708 interrupts = 1708 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1709 dmas = <&mdma 1709 dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>,
1710 <&mdma 1710 <&mdma1 22 0x2 0x10100008 0x0 0x0>;
1711 dma-names = " 1711 dma-names = "tx", "rx";
1712 clocks = <&rc 1712 clocks = <&rcc QSPI_K>;
1713 resets = <&rc 1713 resets = <&rcc QSPI_R>;
1714 #address-cell 1714 #address-cells = <1>;
1715 #size-cells = 1715 #size-cells = <0>;
1716 access-contro 1716 access-controllers = <&etzpc 92>;
1717 status = "dis 1717 status = "disabled";
1718 }; 1718 };
1719 1719
1720 ethernet0: ethernet@5 1720 ethernet0: ethernet@5800a000 {
1721 compatible = 1721 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
1722 reg = <0x5800 1722 reg = <0x5800a000 0x2000>;
1723 reg-names = " 1723 reg-names = "stmmaceth";
1724 interrupts-ex 1724 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1725 interrupt-nam 1725 interrupt-names = "macirq";
1726 clock-names = 1726 clock-names = "stmmaceth",
1727 1727 "mac-clk-tx",
1728 1728 "mac-clk-rx",
1729 1729 "eth-ck",
1730 1730 "ptp_ref",
1731 1731 "ethstp";
1732 clocks = <&rc 1732 clocks = <&rcc ETHMAC>,
1733 <&rc 1733 <&rcc ETHTX>,
1734 <&rc 1734 <&rcc ETHRX>,
1735 <&rc 1735 <&rcc ETHCK_K>,
1736 <&rc 1736 <&rcc ETHPTP_K>,
1737 <&rc 1737 <&rcc ETHSTP>;
1738 st,syscon = < 1738 st,syscon = <&syscfg 0x4>;
1739 snps,mixed-bu 1739 snps,mixed-burst;
1740 snps,pbl = <2 1740 snps,pbl = <2>;
1741 snps,en-tx-lp 1741 snps,en-tx-lpi-clockgating;
1742 snps,axi-conf 1742 snps,axi-config = <&stmmac_axi_config_0>;
1743 snps,tso; 1743 snps,tso;
1744 access-contro 1744 access-controllers = <&etzpc 94>;
1745 status = "dis 1745 status = "disabled";
1746 1746
1747 stmmac_axi_co 1747 stmmac_axi_config_0: stmmac-axi-config {
1748 snps, 1748 snps,wr_osr_lmt = <0x7>;
1749 snps, 1749 snps,rd_osr_lmt = <0x7>;
1750 snps, 1750 snps,blen = <0 0 0 0 16 8 4>;
1751 }; 1751 };
1752 }; 1752 };
1753 1753
1754 usart1: serial@5c0000 1754 usart1: serial@5c000000 {
1755 compatible = 1755 compatible = "st,stm32h7-uart";
1756 reg = <0x5c00 1756 reg = <0x5c000000 0x400>;
1757 interrupts-ex 1757 interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
1758 clocks = <&rc 1758 clocks = <&rcc USART1_K>;
1759 wakeup-source 1759 wakeup-source;
1760 access-contro 1760 access-controllers = <&etzpc 3>;
1761 status = "dis 1761 status = "disabled";
1762 }; 1762 };
1763 1763
1764 spi6: spi@5c001000 { 1764 spi6: spi@5c001000 {
1765 #address-cell 1765 #address-cells = <1>;
1766 #size-cells = 1766 #size-cells = <0>;
1767 compatible = 1767 compatible = "st,stm32h7-spi";
1768 reg = <0x5c00 1768 reg = <0x5c001000 0x400>;
1769 interrupts = 1769 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1770 clocks = <&rc 1770 clocks = <&rcc SPI6_K>;
1771 resets = <&rc 1771 resets = <&rcc SPI6_R>;
1772 dmas = <&mdma 1772 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1773 <&mdma 1773 <&mdma1 35 0x0 0x40002 0x0 0x0>;
1774 access-contro 1774 access-controllers = <&etzpc 4>;
1775 dma-names = " 1775 dma-names = "rx", "tx";
1776 status = "dis 1776 status = "disabled";
1777 }; 1777 };
1778 1778
1779 i2c4: i2c@5c002000 { 1779 i2c4: i2c@5c002000 {
1780 compatible = 1780 compatible = "st,stm32mp15-i2c";
1781 reg = <0x5c00 1781 reg = <0x5c002000 0x400>;
1782 interrupt-nam 1782 interrupt-names = "event", "error";
1783 interrupts = 1783 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1784 1784 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1785 clocks = <&rc 1785 clocks = <&rcc I2C4_K>;
1786 resets = <&rc 1786 resets = <&rcc I2C4_R>;
1787 #address-cell 1787 #address-cells = <1>;
1788 #size-cells = 1788 #size-cells = <0>;
1789 st,syscfg-fmp 1789 st,syscfg-fmp = <&syscfg 0x4 0x8>;
1790 wakeup-source 1790 wakeup-source;
1791 i2c-analog-fi 1791 i2c-analog-filter;
1792 access-contro 1792 access-controllers = <&etzpc 5>;
1793 status = "dis 1793 status = "disabled";
1794 }; 1794 };
1795 1795
1796 i2c6: i2c@5c009000 { 1796 i2c6: i2c@5c009000 {
1797 compatible = 1797 compatible = "st,stm32mp15-i2c";
1798 reg = <0x5c00 1798 reg = <0x5c009000 0x400>;
1799 interrupt-nam 1799 interrupt-names = "event", "error";
1800 interrupts = 1800 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1801 1801 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1802 clocks = <&rc 1802 clocks = <&rcc I2C6_K>;
1803 resets = <&rc 1803 resets = <&rcc I2C6_R>;
1804 #address-cell 1804 #address-cells = <1>;
1805 #size-cells = 1805 #size-cells = <0>;
1806 st,syscfg-fmp 1806 st,syscfg-fmp = <&syscfg 0x4 0x20>;
1807 wakeup-source 1807 wakeup-source;
1808 i2c-analog-fi 1808 i2c-analog-filter;
1809 access-contro 1809 access-controllers = <&etzpc 12>;
1810 status = "dis 1810 status = "disabled";
1811 }; 1811 };
1812 }; 1812 };
1813 1813
1814 tamp: tamp@5c00a000 { 1814 tamp: tamp@5c00a000 {
1815 compatible = "st,stm3 1815 compatible = "st,stm32-tamp", "syscon", "simple-mfd";
1816 reg = <0x5c00a000 0x4 1816 reg = <0x5c00a000 0x400>;
1817 }; 1817 };
1818 1818
1819 /* 1819 /*
1820 * Break node order to solve 1820 * Break node order to solve dependency probe issue between
1821 * pinctrl and exti. 1821 * pinctrl and exti.
1822 */ 1822 */
1823 pinctrl: pinctrl@50002000 { 1823 pinctrl: pinctrl@50002000 {
1824 #address-cells = <1>; 1824 #address-cells = <1>;
1825 #size-cells = <1>; 1825 #size-cells = <1>;
1826 compatible = "st,stm3 1826 compatible = "st,stm32mp157-pinctrl";
1827 ranges = <0 0x5000200 1827 ranges = <0 0x50002000 0xa400>;
1828 interrupt-parent = <& 1828 interrupt-parent = <&exti>;
1829 st,syscfg = <&exti 0x 1829 st,syscfg = <&exti 0x60 0xff>;
1830 1830
1831 gpioa: gpio@50002000 1831 gpioa: gpio@50002000 {
1832 gpio-controll 1832 gpio-controller;
1833 #gpio-cells = 1833 #gpio-cells = <2>;
1834 interrupt-con 1834 interrupt-controller;
1835 #interrupt-ce 1835 #interrupt-cells = <2>;
1836 reg = <0x0 0x 1836 reg = <0x0 0x400>;
1837 clocks = <&rc 1837 clocks = <&rcc GPIOA>;
1838 st,bank-name 1838 st,bank-name = "GPIOA";
1839 status = "dis 1839 status = "disabled";
1840 }; 1840 };
1841 1841
1842 gpiob: gpio@50003000 1842 gpiob: gpio@50003000 {
1843 gpio-controll 1843 gpio-controller;
1844 #gpio-cells = 1844 #gpio-cells = <2>;
1845 interrupt-con 1845 interrupt-controller;
1846 #interrupt-ce 1846 #interrupt-cells = <2>;
1847 reg = <0x1000 1847 reg = <0x1000 0x400>;
1848 clocks = <&rc 1848 clocks = <&rcc GPIOB>;
1849 st,bank-name 1849 st,bank-name = "GPIOB";
1850 status = "dis 1850 status = "disabled";
1851 }; 1851 };
1852 1852
1853 gpioc: gpio@50004000 1853 gpioc: gpio@50004000 {
1854 gpio-controll 1854 gpio-controller;
1855 #gpio-cells = 1855 #gpio-cells = <2>;
1856 interrupt-con 1856 interrupt-controller;
1857 #interrupt-ce 1857 #interrupt-cells = <2>;
1858 reg = <0x2000 1858 reg = <0x2000 0x400>;
1859 clocks = <&rc 1859 clocks = <&rcc GPIOC>;
1860 st,bank-name 1860 st,bank-name = "GPIOC";
1861 status = "dis 1861 status = "disabled";
1862 }; 1862 };
1863 1863
1864 gpiod: gpio@50005000 1864 gpiod: gpio@50005000 {
1865 gpio-controll 1865 gpio-controller;
1866 #gpio-cells = 1866 #gpio-cells = <2>;
1867 interrupt-con 1867 interrupt-controller;
1868 #interrupt-ce 1868 #interrupt-cells = <2>;
1869 reg = <0x3000 1869 reg = <0x3000 0x400>;
1870 clocks = <&rc 1870 clocks = <&rcc GPIOD>;
1871 st,bank-name 1871 st,bank-name = "GPIOD";
1872 status = "dis 1872 status = "disabled";
1873 }; 1873 };
1874 1874
1875 gpioe: gpio@50006000 1875 gpioe: gpio@50006000 {
1876 gpio-controll 1876 gpio-controller;
1877 #gpio-cells = 1877 #gpio-cells = <2>;
1878 interrupt-con 1878 interrupt-controller;
1879 #interrupt-ce 1879 #interrupt-cells = <2>;
1880 reg = <0x4000 1880 reg = <0x4000 0x400>;
1881 clocks = <&rc 1881 clocks = <&rcc GPIOE>;
1882 st,bank-name 1882 st,bank-name = "GPIOE";
1883 status = "dis 1883 status = "disabled";
1884 }; 1884 };
1885 1885
1886 gpiof: gpio@50007000 1886 gpiof: gpio@50007000 {
1887 gpio-controll 1887 gpio-controller;
1888 #gpio-cells = 1888 #gpio-cells = <2>;
1889 interrupt-con 1889 interrupt-controller;
1890 #interrupt-ce 1890 #interrupt-cells = <2>;
1891 reg = <0x5000 1891 reg = <0x5000 0x400>;
1892 clocks = <&rc 1892 clocks = <&rcc GPIOF>;
1893 st,bank-name 1893 st,bank-name = "GPIOF";
1894 status = "dis 1894 status = "disabled";
1895 }; 1895 };
1896 1896
1897 gpiog: gpio@50008000 1897 gpiog: gpio@50008000 {
1898 gpio-controll 1898 gpio-controller;
1899 #gpio-cells = 1899 #gpio-cells = <2>;
1900 interrupt-con 1900 interrupt-controller;
1901 #interrupt-ce 1901 #interrupt-cells = <2>;
1902 reg = <0x6000 1902 reg = <0x6000 0x400>;
1903 clocks = <&rc 1903 clocks = <&rcc GPIOG>;
1904 st,bank-name 1904 st,bank-name = "GPIOG";
1905 status = "dis 1905 status = "disabled";
1906 }; 1906 };
1907 1907
1908 gpioh: gpio@50009000 1908 gpioh: gpio@50009000 {
1909 gpio-controll 1909 gpio-controller;
1910 #gpio-cells = 1910 #gpio-cells = <2>;
1911 interrupt-con 1911 interrupt-controller;
1912 #interrupt-ce 1912 #interrupt-cells = <2>;
1913 reg = <0x7000 1913 reg = <0x7000 0x400>;
1914 clocks = <&rc 1914 clocks = <&rcc GPIOH>;
1915 st,bank-name 1915 st,bank-name = "GPIOH";
1916 status = "dis 1916 status = "disabled";
1917 }; 1917 };
1918 1918
1919 gpioi: gpio@5000a000 1919 gpioi: gpio@5000a000 {
1920 gpio-controll 1920 gpio-controller;
1921 #gpio-cells = 1921 #gpio-cells = <2>;
1922 interrupt-con 1922 interrupt-controller;
1923 #interrupt-ce 1923 #interrupt-cells = <2>;
1924 reg = <0x8000 1924 reg = <0x8000 0x400>;
1925 clocks = <&rc 1925 clocks = <&rcc GPIOI>;
1926 st,bank-name 1926 st,bank-name = "GPIOI";
1927 status = "dis 1927 status = "disabled";
1928 }; 1928 };
1929 1929
1930 gpioj: gpio@5000b000 1930 gpioj: gpio@5000b000 {
1931 gpio-controll 1931 gpio-controller;
1932 #gpio-cells = 1932 #gpio-cells = <2>;
1933 interrupt-con 1933 interrupt-controller;
1934 #interrupt-ce 1934 #interrupt-cells = <2>;
1935 reg = <0x9000 1935 reg = <0x9000 0x400>;
1936 clocks = <&rc 1936 clocks = <&rcc GPIOJ>;
1937 st,bank-name 1937 st,bank-name = "GPIOJ";
1938 status = "dis 1938 status = "disabled";
1939 }; 1939 };
1940 1940
1941 gpiok: gpio@5000c000 1941 gpiok: gpio@5000c000 {
1942 gpio-controll 1942 gpio-controller;
1943 #gpio-cells = 1943 #gpio-cells = <2>;
1944 interrupt-con 1944 interrupt-controller;
1945 #interrupt-ce 1945 #interrupt-cells = <2>;
1946 reg = <0xa000 1946 reg = <0xa000 0x400>;
1947 clocks = <&rc 1947 clocks = <&rcc GPIOK>;
1948 st,bank-name 1948 st,bank-name = "GPIOK";
1949 status = "dis 1949 status = "disabled";
1950 }; 1950 };
1951 }; 1951 };
1952 1952
1953 pinctrl_z: pinctrl@54004000 { 1953 pinctrl_z: pinctrl@54004000 {
1954 #address-cells = <1>; 1954 #address-cells = <1>;
1955 #size-cells = <1>; 1955 #size-cells = <1>;
1956 compatible = "st,stm3 1956 compatible = "st,stm32mp157-z-pinctrl";
1957 ranges = <0 0x5400400 1957 ranges = <0 0x54004000 0x400>;
1958 interrupt-parent = <& 1958 interrupt-parent = <&exti>;
1959 st,syscfg = <&exti 0x 1959 st,syscfg = <&exti 0x60 0xff>;
1960 1960
1961 gpioz: gpio@54004000 1961 gpioz: gpio@54004000 {
1962 gpio-controll 1962 gpio-controller;
1963 #gpio-cells = 1963 #gpio-cells = <2>;
1964 interrupt-con 1964 interrupt-controller;
1965 #interrupt-ce 1965 #interrupt-cells = <2>;
1966 reg = <0 0x40 1966 reg = <0 0x400>;
1967 clocks = <&rc 1967 clocks = <&rcc GPIOZ>;
1968 st,bank-name 1968 st,bank-name = "GPIOZ";
1969 st,bank-iopor 1969 st,bank-ioport = <11>;
1970 status = "dis 1970 status = "disabled";
1971 }; 1971 };
1972 }; 1972 };
1973 }; 1973 };
1974 1974
1975 mlahb: ahb { 1975 mlahb: ahb {
1976 compatible = "st,mlahb", "sim 1976 compatible = "st,mlahb", "simple-bus";
1977 #address-cells = <1>; 1977 #address-cells = <1>;
1978 #size-cells = <1>; 1978 #size-cells = <1>;
1979 ranges; 1979 ranges;
1980 dma-ranges = <0x00000000 0x38 1980 dma-ranges = <0x00000000 0x38000000 0x10000>,
1981 <0x10000000 0x10 1981 <0x10000000 0x10000000 0x60000>,
1982 <0x30000000 0x30 1982 <0x30000000 0x30000000 0x60000>;
1983 1983
1984 m4_rproc: m4@10000000 { 1984 m4_rproc: m4@10000000 {
1985 compatible = "st,stm3 1985 compatible = "st,stm32mp1-m4";
1986 reg = <0x10000000 0x4 1986 reg = <0x10000000 0x40000>,
1987 <0x30000000 0x4 1987 <0x30000000 0x40000>,
1988 <0x38000000 0x1 1988 <0x38000000 0x10000>;
1989 resets = <&rcc MCU_R> 1989 resets = <&rcc MCU_R>;
1990 reset-names = "mcu_rs 1990 reset-names = "mcu_rst";
1991 st,syscfg-holdboot = 1991 st,syscfg-holdboot = <&rcc 0x10C 0x1>;
1992 st,syscfg-pdds = <&pw 1992 st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
1993 st,syscfg-rsc-tbl = < 1993 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
1994 st,syscfg-m4-state = 1994 st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;
1995 status = "disabled"; 1995 status = "disabled";
1996 }; 1996 };
1997 }; 1997 };
1998 }; 1998 };
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