1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Device Tree Include file for Marvell Armada
4 *
5 * Sebastian Hesselbarth <sebastian.hesselbarth
6 *
7 * based on GPL'ed 2.6 kernel sources
8 * (c) Marvell International Ltd.
9 */
10
11 #include <dt-bindings/clock/berlin2.h>
12 #include <dt-bindings/interrupt-controller/arm
13
14 / {
15 model = "Marvell Armada 1500 (BG2) SoC
16 compatible = "marvell,berlin2", "marve
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 serial0 = &uart0;
22 serial1 = &uart1;
23 serial2 = &uart2;
24 };
25
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,berli
30
31 cpu@0 {
32 compatible = "marvell,
33 device_type = "cpu";
34 next-level-cache = <&l
35 reg = <0>;
36
37 clocks = <&chip_clk CL
38 clock-latency = <10000
39 operating-points = <
40 /* kHz uV *
41 1200000 120000
42 1000000 120000
43 800000 120000
44 600000 120000
45 >;
46 };
47
48 cpu@1 {
49 compatible = "marvell,
50 device_type = "cpu";
51 next-level-cache = <&l
52 reg = <1>;
53
54 clocks = <&chip_clk CL
55 clock-latency = <10000
56 operating-points = <
57 /* kHz uV *
58 1200000 120000
59 1000000 120000
60 800000 120000
61 600000 120000
62 >;
63 };
64 };
65
66 refclk: oscillator {
67 compatible = "fixed-clock";
68 #clock-cells = <0>;
69 clock-frequency = <25000000>;
70 };
71
72 soc@f7000000 {
73 compatible = "simple-bus";
74 #address-cells = <1>;
75 #size-cells = <1>;
76 interrupt-parent = <&gic>;
77
78 ranges = <0 0xf7000000 0x10000
79
80 sdhci0: mmc@ab0000 {
81 compatible = "mrvl,pxa
82 reg = <0xab0000 0x200>
83 clocks = <&chip_clk CL
84 clock-names = "io", "c
85 interrupts = <GIC_SPI
86 status = "disabled";
87 };
88
89 sdhci1: mmc@ab0800 {
90 compatible = "mrvl,pxa
91 reg = <0xab0800 0x200>
92 clocks = <&chip_clk CL
93 clock-names = "io", "c
94 interrupts = <GIC_SPI
95 status = "disabled";
96 };
97
98 sdhci2: mmc@ab1000 {
99 compatible = "mrvl,pxa
100 reg = <0xab1000 0x200>
101 interrupts = <GIC_SPI
102 clocks = <&chip_clk CL
103 clock-names = "io", "c
104 pinctrl-0 = <&emmc_pmu
105 pinctrl-names = "defau
106 status = "disabled";
107 };
108
109 l2: cache-controller@ac0000 {
110 compatible = "marvell,
111 reg = <0xac0000 0x1000
112 cache-unified;
113 cache-level = <2>;
114 };
115
116 scu: snoop-control-unit@ad0000
117 compatible = "arm,cort
118 reg = <0xad0000 0x58>;
119 };
120
121 gic: interrupt-controller@ad10
122 compatible = "arm,cort
123 reg = <0xad1000 0x1000
124 interrupt-controller;
125 #interrupt-cells = <3>
126 };
127
128 local-timer@ad0600 {
129 compatible = "arm,cort
130 reg = <0xad0600 0x20>;
131 interrupts = <GIC_PPI
132 clocks = <&chip_clk CL
133 };
134
135 eth1: ethernet@b90000 {
136 compatible = "marvell,
137 reg = <0xb90000 0x1000
138 clocks = <&chip_clk CL
139 interrupts = <GIC_SPI
140 /* set by bootloader *
141 local-mac-address = [0
142 #address-cells = <1>;
143 #size-cells = <0>;
144 phy-connection-type =
145 phy-handle = <ðphy1
146 status = "disabled";
147
148 ethphy1: ethernet-phy@
149 reg = <0>;
150 };
151 };
152
153 cpu-ctrl@dd0000 {
154 compatible = "marvell,
155 reg = <0xdd0000 0x1000
156 };
157
158 eth0: ethernet@e50000 {
159 compatible = "marvell,
160 reg = <0xe50000 0x1000
161 clocks = <&chip_clk CL
162 interrupts = <GIC_SPI
163 /* set by bootloader *
164 local-mac-address = [0
165 #address-cells = <1>;
166 #size-cells = <0>;
167 phy-connection-type =
168 phy-handle = <ðphy0
169 status = "disabled";
170
171 ethphy0: ethernet-phy@
172 reg = <0>;
173 };
174 };
175
176 apb@e80000 {
177 compatible = "simple-b
178 #address-cells = <1>;
179 #size-cells = <1>;
180
181 ranges = <0 0xe80000 0
182 interrupt-parent = <&a
183
184 gpio0: gpio@400 {
185 compatible = "
186 reg = <0x0400
187 #address-cells
188 #size-cells =
189
190 porta: gpio-po
191 compat
192 gpio-c
193 #gpio-
194 ngpios
195 reg =
196 interr
197 #inter
198 interr
199 };
200 };
201
202 gpio1: gpio@800 {
203 compatible = "
204 reg = <0x0800
205 #address-cells
206 #size-cells =
207
208 portb: gpio-po
209 compat
210 gpio-c
211 #gpio-
212 ngpios
213 reg =
214 interr
215 #inter
216 interr
217 };
218 };
219
220 gpio2: gpio@c00 {
221 compatible = "
222 reg = <0x0c00
223 #address-cells
224 #size-cells =
225
226 portc: gpio-po
227 compat
228 gpio-c
229 #gpio-
230 ngpios
231 reg =
232 interr
233 #inter
234 interr
235 };
236 };
237
238 gpio3: gpio@1000 {
239 compatible = "
240 reg = <0x1000
241 #address-cells
242 #size-cells =
243
244 portd: gpio-po
245 compat
246 gpio-c
247 #gpio-
248 ngpios
249 reg =
250 interr
251 #inter
252 interr
253 };
254 };
255
256 timer0: timer@2c00 {
257 compatible = "
258 reg = <0x2c00
259 interrupts = <
260 clocks = <&chi
261 clock-names =
262 status = "okay
263 };
264
265 timer1: timer@2c14 {
266 compatible = "
267 reg = <0x2c14
268 interrupts = <
269 clocks = <&chi
270 clock-names =
271 status = "okay
272 };
273
274 timer2: timer@2c28 {
275 compatible = "
276 reg = <0x2c28
277 interrupts = <
278 clocks = <&chi
279 clock-names =
280 status = "disa
281 };
282
283 timer3: timer@2c3c {
284 compatible = "
285 reg = <0x2c3c
286 interrupts = <
287 clocks = <&chi
288 clock-names =
289 status = "disa
290 };
291
292 timer4: timer@2c50 {
293 compatible = "
294 reg = <0x2c50
295 interrupts = <
296 clocks = <&chi
297 clock-names =
298 status = "disa
299 };
300
301 timer5: timer@2c64 {
302 compatible = "
303 reg = <0x2c64
304 interrupts = <
305 clocks = <&chi
306 clock-names =
307 status = "disa
308 };
309
310 timer6: timer@2c78 {
311 compatible = "
312 reg = <0x2c78
313 interrupts = <
314 clocks = <&chi
315 clock-names =
316 status = "disa
317 };
318
319 timer7: timer@2c8c {
320 compatible = "
321 reg = <0x2c8c
322 interrupts = <
323 clocks = <&chi
324 clock-names =
325 status = "disa
326 };
327
328 aic: interrupt-control
329 compatible = "
330 reg = <0x3000
331 interrupt-cont
332 #interrupt-cel
333 interrupt-pare
334 interrupts = <
335 };
336 };
337
338 ahci: sata@e90000 {
339 compatible = "marvell,
340 reg = <0xe90000 0x1000
341 interrupts = <GIC_SPI
342 clocks = <&chip_clk CL
343 #address-cells = <1>;
344 #size-cells = <0>;
345
346 sata0: sata-port@0 {
347 reg = <0>;
348 phys = <&sata_
349 status = "disa
350 };
351
352 sata1: sata-port@1 {
353 reg = <1>;
354 phys = <&sata_
355 status = "disa
356 };
357 };
358
359 sata_phy: phy@e900a0 {
360 compatible = "marvell,
361 reg = <0xe900a0 0x200>
362 clocks = <&chip_clk CL
363 #address-cells = <1>;
364 #size-cells = <0>;
365 #phy-cells = <1>;
366 status = "disabled";
367
368 sata-phy@0 {
369 reg = <0>;
370 };
371
372 sata-phy@1 {
373 reg = <1>;
374 };
375 };
376
377 chip: chip-control@ea0000 {
378 compatible = "simple-m
379 reg = <0xea0000 0x400>
380
381 chip_clk: clock {
382 compatible = "
383 #clock-cells =
384 clocks = <&ref
385 clock-names =
386 };
387
388 soc_pinctrl: pin-contr
389 compatible = "
390
391 emmc_pmux: emm
392 groups
393 functi
394 };
395 };
396
397 chip_rst: reset {
398 compatible = "
399 #reset-cells =
400 };
401 };
402
403 pwm: pwm@f20000 {
404 compatible = "marvell,
405 reg = <0xf20000 0x40>;
406 clocks = <&chip_clk CL
407 #pwm-cells = <3>;
408 };
409
410 apb@fc0000 {
411 compatible = "simple-b
412 #address-cells = <1>;
413 #size-cells = <1>;
414
415 ranges = <0 0xfc0000 0
416 interrupt-parent = <&s
417
418 wdt0: watchdog@1000 {
419 compatible = "
420 reg = <0x1000
421 clocks = <&ref
422 interrupts = <
423 };
424
425 wdt1: watchdog@2000 {
426 compatible = "
427 reg = <0x2000
428 clocks = <&ref
429 interrupts = <
430 };
431
432 wdt2: watchdog@3000 {
433 compatible = "
434 reg = <0x3000
435 clocks = <&ref
436 interrupts = <
437 };
438
439 sm_gpio1: gpio@5000 {
440 compatible = "
441 reg = <0x5000
442 #address-cells
443 #size-cells =
444
445 portf: gpio-po
446 compat
447 gpio-c
448 #gpio-
449 ngpios
450 reg =
451 };
452 };
453
454 sm_gpio0: gpio@c000 {
455 compatible = "
456 reg = <0xc000
457 #address-cells
458 #size-cells =
459
460 porte: gpio-po
461 compat
462 gpio-c
463 #gpio-
464 ngpios
465 reg =
466 interr
467 #inter
468 interr
469 };
470 };
471
472 uart0: serial@9000 {
473 compatible = "
474 reg = <0x9000
475 reg-shift = <2
476 reg-io-width =
477 interrupts = <
478 clocks = <&ref
479 pinctrl-0 = <&
480 pinctrl-names
481 status = "disa
482 };
483
484 uart1: serial@a000 {
485 compatible = "
486 reg = <0xa000
487 reg-shift = <2
488 reg-io-width =
489 interrupts = <
490 clocks = <&ref
491 pinctrl-0 = <&
492 pinctrl-names
493 status = "disa
494 };
495
496 uart2: serial@b000 {
497 compatible = "
498 reg = <0xb000
499 reg-shift = <2
500 reg-io-width =
501 interrupts = <
502 clocks = <&ref
503 pinctrl-0 = <&
504 pinctrl-names
505 status = "disa
506 };
507
508 sysctrl: system-contro
509 compatible = "
510 reg = <0xd000
511
512 sys_pinctrl: p
513 compat
514 uart0_
515
516
517 };
518
519 uart1_
520
521
522 };
523 uart2_
524
525
526 };
527 };
528 };
529
530 sic: interrupt-control
531 compatible = "
532 reg = <0xe000
533 interrupt-cont
534 #interrupt-cel
535 interrupt-pare
536 interrupts = <
537 };
538 };
539 };
540 };
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