1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* 2 /*
3 * Device Tree Include file for Marvell Armada 3 * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
4 * 4 *
5 * Sebastian Hesselbarth <sebastian.hesselbarth 5 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
6 * 6 *
7 * based on GPL'ed 2.6 kernel sources 7 * based on GPL'ed 2.6 kernel sources
8 * (c) Marvell International Ltd. 8 * (c) Marvell International Ltd.
9 */ 9 */
10 10
11 #include <dt-bindings/clock/berlin2.h> 11 #include <dt-bindings/clock/berlin2.h>
12 #include <dt-bindings/interrupt-controller/arm 12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 13
14 / { 14 / {
15 model = "Marvell Armada 1500-mini (BG2 15 model = "Marvell Armada 1500-mini (BG2CD) SoC";
16 compatible = "marvell,berlin2cd", "mar 16 compatible = "marvell,berlin2cd", "marvell,berlin";
17 #address-cells = <1>; 17 #address-cells = <1>;
18 #size-cells = <1>; 18 #size-cells = <1>;
19 19
20 aliases { 20 aliases {
21 serial0 = &uart0; 21 serial0 = &uart0;
22 serial1 = &uart1; 22 serial1 = &uart1;
23 }; 23 };
24 24
25 cpus { 25 cpus {
26 #address-cells = <1>; 26 #address-cells = <1>;
27 #size-cells = <0>; 27 #size-cells = <0>;
28 28
29 cpu: cpu@0 { 29 cpu: cpu@0 {
30 compatible = "arm,cort 30 compatible = "arm,cortex-a9";
31 device_type = "cpu"; 31 device_type = "cpu";
32 next-level-cache = <&l 32 next-level-cache = <&l2>;
33 reg = <0>; 33 reg = <0>;
34 34
35 clocks = <&chip_clk CL 35 clocks = <&chip_clk CLKID_CPU>;
36 clock-latency = <10000 36 clock-latency = <100000>;
37 operating-points = < 37 operating-points = <
38 /* kHz uV * 38 /* kHz uV */
39 800000 120000 39 800000 1200000
40 600000 120000 40 600000 1200000
41 >; 41 >;
42 }; 42 };
43 }; 43 };
44 44
45 pmu { 45 pmu {
46 compatible = "arm,cortex-a9-pm 46 compatible = "arm,cortex-a9-pmu";
47 interrupt-parent = <&gic>; 47 interrupt-parent = <&gic>;
48 interrupts = <GIC_SPI 30 IRQ_T 48 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
49 }; 49 };
50 50
51 refclk: oscillator { 51 refclk: oscillator {
52 compatible = "fixed-clock"; 52 compatible = "fixed-clock";
53 #clock-cells = <0>; 53 #clock-cells = <0>;
54 clock-frequency = <25000000>; 54 clock-frequency = <25000000>;
55 }; 55 };
56 56
57 soc@f7000000 { 57 soc@f7000000 {
58 compatible = "simple-bus"; 58 compatible = "simple-bus";
59 #address-cells = <1>; 59 #address-cells = <1>;
60 #size-cells = <1>; 60 #size-cells = <1>;
61 interrupt-parent = <&gic>; 61 interrupt-parent = <&gic>;
62 62
63 ranges = <0 0xf7000000 0x10000 63 ranges = <0 0xf7000000 0x1000000>;
64 64
65 sdhci0: mmc@ab0000 { 65 sdhci0: mmc@ab0000 {
66 compatible = "mrvl,pxa 66 compatible = "mrvl,pxav3-mmc";
67 reg = <0xab0000 0x200> 67 reg = <0xab0000 0x200>;
68 clocks = <&chip_clk CL 68 clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>;
69 clock-names = "io", "c 69 clock-names = "io", "core";
70 interrupts = <GIC_SPI 70 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
71 status = "disabled"; 71 status = "disabled";
72 }; 72 };
73 73
74 l2: cache-controller@ac0000 { 74 l2: cache-controller@ac0000 {
75 compatible = "arm,pl31 75 compatible = "arm,pl310-cache";
76 reg = <0xac0000 0x1000 76 reg = <0xac0000 0x1000>;
77 cache-unified; 77 cache-unified;
78 cache-level = <2>; 78 cache-level = <2>;
79 }; 79 };
80 80
81 snoop-control-unit@ad0000 { 81 snoop-control-unit@ad0000 {
82 compatible = "arm,cort 82 compatible = "arm,cortex-a9-scu";
83 reg = <0xad0000 0x100> 83 reg = <0xad0000 0x100>;
84 }; 84 };
85 85
86 gic: interrupt-controller@ad10 86 gic: interrupt-controller@ad1000 {
87 compatible = "arm,cort 87 compatible = "arm,cortex-a9-gic";
88 reg = <0xad1000 0x1000 88 reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
89 interrupt-controller; 89 interrupt-controller;
90 #interrupt-cells = <3> 90 #interrupt-cells = <3>;
91 }; 91 };
92 92
93 global-timer@ad0200 { 93 global-timer@ad0200 {
94 compatible = "arm,cort 94 compatible = "arm,cortex-a9-global-timer";
95 reg = <0xad0200 0x20>; 95 reg = <0xad0200 0x20>;
96 interrupts = <GIC_PPI 96 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>;
97 clocks = <&chip_clk CL 97 clocks = <&chip_clk CLKID_TWD>;
98 }; 98 };
99 99
100 local-timer@ad0600 { 100 local-timer@ad0600 {
101 compatible = "arm,cort 101 compatible = "arm,cortex-a9-twd-timer";
102 reg = <0xad0600 0x20>; 102 reg = <0xad0600 0x20>;
103 interrupts = <GIC_PPI 103 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>;
104 clocks = <&chip_clk CL 104 clocks = <&chip_clk CLKID_TWD>;
105 }; 105 };
106 106
107 local-wdt@ad0620 { 107 local-wdt@ad0620 {
108 compatible = "arm,cort 108 compatible = "arm,cortex-a9-twd-wdt";
109 reg = <0xad0620 0x20>; 109 reg = <0xad0620 0x20>;
110 interrupts = <GIC_PPI 110 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>;
111 clocks = <&chip_clk CL 111 clocks = <&chip_clk CLKID_TWD>;
112 }; 112 };
113 113
114 usb_phy0: usb-phy@b74000 { 114 usb_phy0: usb-phy@b74000 {
115 compatible = "marvell, 115 compatible = "marvell,berlin2cd-usb-phy";
116 reg = <0xb74000 0x128> 116 reg = <0xb74000 0x128>;
117 #phy-cells = <0>; 117 #phy-cells = <0>;
118 resets = <&chip_rst 0x 118 resets = <&chip_rst 0x178 23>;
119 status = "disabled"; 119 status = "disabled";
120 }; 120 };
121 121
122 usb_phy1: usb-phy@b78000 { 122 usb_phy1: usb-phy@b78000 {
123 compatible = "marvell, 123 compatible = "marvell,berlin2cd-usb-phy";
124 reg = <0xb78000 0x128> 124 reg = <0xb78000 0x128>;
125 #phy-cells = <0>; 125 #phy-cells = <0>;
126 resets = <&chip_rst 0x 126 resets = <&chip_rst 0x178 24>;
127 status = "disabled"; 127 status = "disabled";
128 }; 128 };
129 129
130 eth1: ethernet@b90000 { 130 eth1: ethernet@b90000 {
131 compatible = "marvell, 131 compatible = "marvell,pxa168-eth";
132 reg = <0xb90000 0x1000 132 reg = <0xb90000 0x10000>;
133 clocks = <&chip_clk CL 133 clocks = <&chip_clk CLKID_GETH1>;
134 interrupts = <GIC_SPI 134 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
135 /* set by bootloader * 135 /* set by bootloader */
136 local-mac-address = [0 136 local-mac-address = [00 00 00 00 00 00];
137 #address-cells = <1>; 137 #address-cells = <1>;
138 #size-cells = <0>; 138 #size-cells = <0>;
139 phy-connection-type = 139 phy-connection-type = "mii";
140 phy-handle = <ðphy1 140 phy-handle = <ðphy1>;
141 status = "disabled"; 141 status = "disabled";
142 142
143 ethphy1: ethernet-phy@ 143 ethphy1: ethernet-phy@0 {
144 reg = <0>; 144 reg = <0>;
145 }; 145 };
146 }; 146 };
147 147
148 eth0: ethernet@e50000 { 148 eth0: ethernet@e50000 {
149 compatible = "marvell, 149 compatible = "marvell,pxa168-eth";
150 reg = <0xe50000 0x1000 150 reg = <0xe50000 0x10000>;
151 clocks = <&chip_clk CL 151 clocks = <&chip_clk CLKID_GETH0>;
152 interrupts = <GIC_SPI 152 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
153 /* set by bootloader * 153 /* set by bootloader */
154 local-mac-address = [0 154 local-mac-address = [00 00 00 00 00 00];
155 #address-cells = <1>; 155 #address-cells = <1>;
156 #size-cells = <0>; 156 #size-cells = <0>;
157 phy-connection-type = 157 phy-connection-type = "mii";
158 phy-handle = <ðphy0 158 phy-handle = <ðphy0>;
159 status = "disabled"; 159 status = "disabled";
160 160
161 ethphy0: ethernet-phy@ 161 ethphy0: ethernet-phy@0 {
162 reg = <0>; 162 reg = <0>;
163 }; 163 };
164 }; 164 };
165 165
166 apb@e80000 { 166 apb@e80000 {
167 compatible = "simple-b 167 compatible = "simple-bus";
168 #address-cells = <1>; 168 #address-cells = <1>;
169 #size-cells = <1>; 169 #size-cells = <1>;
170 170
171 ranges = <0 0xe80000 0 171 ranges = <0 0xe80000 0x10000>;
172 interrupt-parent = <&a 172 interrupt-parent = <&aic>;
173 173
174 gpio0: gpio@400 { 174 gpio0: gpio@400 {
175 compatible = " 175 compatible = "snps,dw-apb-gpio";
176 reg = <0x0400 176 reg = <0x0400 0x400>;
177 #address-cells 177 #address-cells = <1>;
178 #size-cells = 178 #size-cells = <0>;
179 179
180 porta: gpio-po 180 porta: gpio-port@0 {
181 compat 181 compatible = "snps,dw-apb-gpio-port";
182 gpio-c 182 gpio-controller;
183 #gpio- 183 #gpio-cells = <2>;
184 ngpios 184 ngpios = <8>;
185 reg = 185 reg = <0>;
186 interr 186 interrupt-controller;
187 #inter 187 #interrupt-cells = <2>;
188 interr 188 interrupts = <0>;
189 }; 189 };
190 }; 190 };
191 191
192 gpio1: gpio@800 { 192 gpio1: gpio@800 {
193 compatible = " 193 compatible = "snps,dw-apb-gpio";
194 reg = <0x0800 194 reg = <0x0800 0x400>;
195 #address-cells 195 #address-cells = <1>;
196 #size-cells = 196 #size-cells = <0>;
197 197
198 portb: gpio-po 198 portb: gpio-port@1 {
199 compat 199 compatible = "snps,dw-apb-gpio-port";
200 gpio-c 200 gpio-controller;
201 #gpio- 201 #gpio-cells = <2>;
202 ngpios 202 ngpios = <8>;
203 reg = 203 reg = <0>;
204 interr 204 interrupt-controller;
205 #inter 205 #interrupt-cells = <2>;
206 interr 206 interrupts = <1>;
207 }; 207 };
208 }; 208 };
209 209
210 gpio2: gpio@c00 { 210 gpio2: gpio@c00 {
211 compatible = " 211 compatible = "snps,dw-apb-gpio";
212 reg = <0x0c00 212 reg = <0x0c00 0x400>;
213 #address-cells 213 #address-cells = <1>;
214 #size-cells = 214 #size-cells = <0>;
215 215
216 portc: gpio-po 216 portc: gpio-port@2 {
217 compat 217 compatible = "snps,dw-apb-gpio-port";
218 gpio-c 218 gpio-controller;
219 #gpio- 219 #gpio-cells = <2>;
220 ngpios 220 ngpios = <8>;
221 reg = 221 reg = <0>;
222 interr 222 interrupt-controller;
223 #inter 223 #interrupt-cells = <2>;
224 interr 224 interrupts = <2>;
225 }; 225 };
226 }; 226 };
227 227
228 gpio3: gpio@1000 { 228 gpio3: gpio@1000 {
229 compatible = " 229 compatible = "snps,dw-apb-gpio";
230 reg = <0x1000 230 reg = <0x1000 0x400>;
231 #address-cells 231 #address-cells = <1>;
232 #size-cells = 232 #size-cells = <0>;
233 233
234 portd: gpio-po 234 portd: gpio-port@3 {
235 compat 235 compatible = "snps,dw-apb-gpio-port";
236 gpio-c 236 gpio-controller;
237 #gpio- 237 #gpio-cells = <2>;
238 ngpios 238 ngpios = <8>;
239 reg = 239 reg = <0>;
240 interr 240 interrupt-controller;
241 #inter 241 #interrupt-cells = <2>;
242 interr 242 interrupts = <3>;
243 }; 243 };
244 }; 244 };
245 245
246 i2c0: i2c@1400 { 246 i2c0: i2c@1400 {
247 compatible = " 247 compatible = "snps,designware-i2c";
248 #address-cells 248 #address-cells = <1>;
249 #size-cells = 249 #size-cells = <0>;
250 reg = <0x1400 250 reg = <0x1400 0x100>;
251 interrupts = < 251 interrupts = <16>;
252 clocks = <&chi 252 clocks = <&chip_clk CLKID_CFG>;
253 status = "disa 253 status = "disabled";
254 }; 254 };
255 255
256 i2c1: i2c@1800 { 256 i2c1: i2c@1800 {
257 compatible = " 257 compatible = "snps,designware-i2c";
258 #address-cells 258 #address-cells = <1>;
259 #size-cells = 259 #size-cells = <0>;
260 reg = <0x1800 260 reg = <0x1800 0x100>;
261 interrupts = < 261 interrupts = <17>;
262 clocks = <&chi 262 clocks = <&chip_clk CLKID_CFG>;
263 status = "disa 263 status = "disabled";
264 }; 264 };
265 265
266 spi0: spi@1c00 { 266 spi0: spi@1c00 {
267 compatible = " 267 compatible = "snps,dw-apb-ssi";
268 #address-cells 268 #address-cells = <1>;
269 #size-cells = 269 #size-cells = <0>;
270 reg = <0x1c00 270 reg = <0x1c00 0x100>;
271 interrupts = < 271 interrupts = <4>;
272 clocks = <&chi 272 clocks = <&chip_clk CLKID_CFG>;
273 status = "disa 273 status = "disabled";
274 }; 274 };
275 275
276 wdt4: watchdog@2000 { 276 wdt4: watchdog@2000 {
277 compatible = " 277 compatible = "snps,dw-wdt";
278 reg = <0x2000 278 reg = <0x2000 0x100>;
279 clocks = <&chi 279 clocks = <&chip_clk CLKID_CFG>;
280 interrupts = < 280 interrupts = <5>;
281 status = "disa 281 status = "disabled";
282 }; 282 };
283 283
284 wdt5: watchdog@2400 { 284 wdt5: watchdog@2400 {
285 compatible = " 285 compatible = "snps,dw-wdt";
286 reg = <0x2400 286 reg = <0x2400 0x100>;
287 clocks = <&chi 287 clocks = <&chip_clk CLKID_CFG>;
288 interrupts = < 288 interrupts = <6>;
289 status = "disa 289 status = "disabled";
290 }; 290 };
291 291
292 wdt6: watchdog@2800 { 292 wdt6: watchdog@2800 {
293 compatible = " 293 compatible = "snps,dw-wdt";
294 reg = <0x2800 294 reg = <0x2800 0x100>;
295 clocks = <&chi 295 clocks = <&chip_clk CLKID_CFG>;
296 interrupts = < 296 interrupts = <7>;
297 status = "disa 297 status = "disabled";
298 }; 298 };
299 299
300 timer0: timer@2c00 { 300 timer0: timer@2c00 {
301 compatible = " 301 compatible = "snps,dw-apb-timer";
302 reg = <0x2c00 302 reg = <0x2c00 0x14>;
303 interrupts = < 303 interrupts = <8>;
304 clocks = <&chi 304 clocks = <&chip_clk CLKID_CFG>;
305 clock-names = 305 clock-names = "timer";
306 status = "okay 306 status = "okay";
307 }; 307 };
308 308
309 timer1: timer@2c14 { 309 timer1: timer@2c14 {
310 compatible = " 310 compatible = "snps,dw-apb-timer";
311 reg = <0x2c14 311 reg = <0x2c14 0x14>;
312 interrupts = < 312 interrupts = <9>;
313 clocks = <&chi 313 clocks = <&chip_clk CLKID_CFG>;
314 clock-names = 314 clock-names = "timer";
315 status = "okay 315 status = "okay";
316 }; 316 };
317 317
318 timer2: timer@2c28 { 318 timer2: timer@2c28 {
319 compatible = " 319 compatible = "snps,dw-apb-timer";
320 reg = <0x2c28 320 reg = <0x2c28 0x14>;
321 interrupts = < 321 interrupts = <10>;
322 clocks = <&chi 322 clocks = <&chip_clk CLKID_CFG>;
323 clock-names = 323 clock-names = "timer";
324 status = "disa 324 status = "disabled";
325 }; 325 };
326 326
327 timer3: timer@2c3c { 327 timer3: timer@2c3c {
328 compatible = " 328 compatible = "snps,dw-apb-timer";
329 reg = <0x2c3c 329 reg = <0x2c3c 0x14>;
330 interrupts = < 330 interrupts = <11>;
331 clocks = <&chi 331 clocks = <&chip_clk CLKID_CFG>;
332 clock-names = 332 clock-names = "timer";
333 status = "disa 333 status = "disabled";
334 }; 334 };
335 335
336 timer4: timer@2c50 { 336 timer4: timer@2c50 {
337 compatible = " 337 compatible = "snps,dw-apb-timer";
338 reg = <0x2c50 338 reg = <0x2c50 0x14>;
339 interrupts = < 339 interrupts = <12>;
340 clocks = <&chi 340 clocks = <&chip_clk CLKID_CFG>;
341 clock-names = 341 clock-names = "timer";
342 status = "disa 342 status = "disabled";
343 }; 343 };
344 344
345 timer5: timer@2c64 { 345 timer5: timer@2c64 {
346 compatible = " 346 compatible = "snps,dw-apb-timer";
347 reg = <0x2c64 347 reg = <0x2c64 0x14>;
348 interrupts = < 348 interrupts = <13>;
349 clocks = <&chi 349 clocks = <&chip_clk CLKID_CFG>;
350 clock-names = 350 clock-names = "timer";
351 status = "disa 351 status = "disabled";
352 }; 352 };
353 353
354 timer6: timer@2c78 { 354 timer6: timer@2c78 {
355 compatible = " 355 compatible = "snps,dw-apb-timer";
356 reg = <0x2c78 356 reg = <0x2c78 0x14>;
357 interrupts = < 357 interrupts = <14>;
358 clocks = <&chi 358 clocks = <&chip_clk CLKID_CFG>;
359 clock-names = 359 clock-names = "timer";
360 status = "disa 360 status = "disabled";
361 }; 361 };
362 362
363 timer7: timer@2c8c { 363 timer7: timer@2c8c {
364 compatible = " 364 compatible = "snps,dw-apb-timer";
365 reg = <0x2c8c 365 reg = <0x2c8c 0x14>;
366 interrupts = < 366 interrupts = <15>;
367 clocks = <&chi 367 clocks = <&chip_clk CLKID_CFG>;
368 clock-names = 368 clock-names = "timer";
369 status = "disa 369 status = "disabled";
370 }; 370 };
371 371
372 aic: interrupt-control 372 aic: interrupt-controller@3000 {
373 compatible = " 373 compatible = "snps,dw-apb-ictl";
374 reg = <0x3000 374 reg = <0x3000 0xc00>;
375 interrupt-cont 375 interrupt-controller;
376 #interrupt-cel 376 #interrupt-cells = <1>;
377 interrupt-pare 377 interrupt-parent = <&gic>;
378 interrupts = < 378 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
379 }; 379 };
380 }; 380 };
381 381
382 chip: chip-control@ea0000 { 382 chip: chip-control@ea0000 {
383 compatible = "simple-m 383 compatible = "simple-mfd", "syscon";
384 reg = <0xea0000 0x400> 384 reg = <0xea0000 0x400>;
385 385
386 chip_clk: clock { 386 chip_clk: clock {
387 compatible = " 387 compatible = "marvell,berlin2-clk";
388 #clock-cells = 388 #clock-cells = <1>;
389 clocks = <&ref 389 clocks = <&refclk>;
390 clock-names = 390 clock-names = "refclk";
391 }; 391 };
392 392
393 soc_pinctrl: pin-contr 393 soc_pinctrl: pin-controller {
394 compatible = " 394 compatible = "marvell,berlin2cd-soc-pinctrl";
395 395
396 uart0_pmux: ua 396 uart0_pmux: uart0-pmux {
397 groups 397 groups = "G6";
398 functi 398 function = "uart0";
399 }; 399 };
400 }; 400 };
401 401
402 chip_rst: reset { 402 chip_rst: reset {
403 compatible = " 403 compatible = "marvell,berlin2-reset";
404 #reset-cells = 404 #reset-cells = <2>;
405 }; 405 };
406 }; 406 };
407 407
408 usb0: usb@ed0000 { 408 usb0: usb@ed0000 {
409 compatible = "chipidea 409 compatible = "chipidea,usb2";
410 reg = <0xed0000 0x200> 410 reg = <0xed0000 0x200>;
411 interrupts = <GIC_SPI 411 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
412 clocks = <&chip_clk CL 412 clocks = <&chip_clk CLKID_USB0>;
413 phys = <&usb_phy0>; 413 phys = <&usb_phy0>;
414 phy-names = "usb-phy"; 414 phy-names = "usb-phy";
415 status = "disabled"; 415 status = "disabled";
416 }; 416 };
417 417
418 usb1: usb@ee0000 { 418 usb1: usb@ee0000 {
419 compatible = "chipidea 419 compatible = "chipidea,usb2";
420 reg = <0xee0000 0x200> 420 reg = <0xee0000 0x200>;
421 interrupts = <GIC_SPI 421 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
422 clocks = <&chip_clk CL 422 clocks = <&chip_clk CLKID_USB1>;
423 phys = <&usb_phy1>; 423 phys = <&usb_phy1>;
424 phy-names = "usb-phy"; 424 phy-names = "usb-phy";
425 status = "disabled"; 425 status = "disabled";
426 }; 426 };
427 427
428 pwm: pwm@f20000 { 428 pwm: pwm@f20000 {
429 compatible = "marvell, 429 compatible = "marvell,berlin-pwm";
430 reg = <0xf20000 0x40>; 430 reg = <0xf20000 0x40>;
431 clocks = <&chip_clk CL 431 clocks = <&chip_clk CLKID_CFG>;
432 #pwm-cells = <3>; 432 #pwm-cells = <3>;
433 }; 433 };
434 434
435 apb@fc0000 { 435 apb@fc0000 {
436 compatible = "simple-b 436 compatible = "simple-bus";
437 #address-cells = <1>; 437 #address-cells = <1>;
438 #size-cells = <1>; 438 #size-cells = <1>;
439 439
440 ranges = <0 0xfc0000 0 440 ranges = <0 0xfc0000 0x10000>;
441 interrupt-parent = <&s 441 interrupt-parent = <&sic>;
442 442
443 wdt0: watchdog@1000 { 443 wdt0: watchdog@1000 {
444 compatible = " 444 compatible = "snps,dw-wdt";
445 reg = <0x1000 445 reg = <0x1000 0x100>;
446 clocks = <&ref 446 clocks = <&refclk>;
447 interrupts = < 447 interrupts = <0>;
448 }; 448 };
449 449
450 wdt1: watchdog@2000 { 450 wdt1: watchdog@2000 {
451 compatible = " 451 compatible = "snps,dw-wdt";
452 reg = <0x2000 452 reg = <0x2000 0x100>;
453 clocks = <&ref 453 clocks = <&refclk>;
454 interrupts = < 454 interrupts = <1>;
455 status = "disa 455 status = "disabled";
456 }; 456 };
457 457
458 wdt2: watchdog@3000 { 458 wdt2: watchdog@3000 {
459 compatible = " 459 compatible = "snps,dw-wdt";
460 reg = <0x3000 460 reg = <0x3000 0x100>;
461 clocks = <&ref 461 clocks = <&refclk>;
462 interrupts = < 462 interrupts = <2>;
463 status = "disa 463 status = "disabled";
464 }; 464 };
465 465
466 sm_gpio1: gpio@5000 { 466 sm_gpio1: gpio@5000 {
467 compatible = " 467 compatible = "snps,dw-apb-gpio";
468 reg = <0x5000 468 reg = <0x5000 0x400>;
469 #address-cells 469 #address-cells = <1>;
470 #size-cells = 470 #size-cells = <0>;
471 471
472 portf: gpio-po 472 portf: gpio-port@5 {
473 compat 473 compatible = "snps,dw-apb-gpio-port";
474 gpio-c 474 gpio-controller;
475 #gpio- 475 #gpio-cells = <2>;
476 ngpios 476 ngpios = <8>;
477 reg = 477 reg = <0>;
478 }; 478 };
479 }; 479 };
480 480
481 spi1: spi@6000 { 481 spi1: spi@6000 {
482 compatible = " 482 compatible = "snps,dw-apb-ssi";
483 #address-cells 483 #address-cells = <1>;
484 #size-cells = 484 #size-cells = <0>;
485 reg = <0x6000 485 reg = <0x6000 0x100>;
486 clocks = <&ref 486 clocks = <&refclk>;
487 interrupts = < 487 interrupts = <5>;
488 status = "disa 488 status = "disabled";
489 }; 489 };
490 490
491 i2c2: i2c@7000 { 491 i2c2: i2c@7000 {
492 compatible = " 492 compatible = "snps,designware-i2c";
493 #address-cells 493 #address-cells = <1>;
494 #size-cells = 494 #size-cells = <0>;
495 reg = <0x7000 495 reg = <0x7000 0x100>;
496 interrupts = < 496 interrupts = <6>;
497 clocks = <&ref 497 clocks = <&refclk>;
498 status = "disa 498 status = "disabled";
499 }; 499 };
500 500
501 i2c3: i2c@8000 { 501 i2c3: i2c@8000 {
502 compatible = " 502 compatible = "snps,designware-i2c";
503 #address-cells 503 #address-cells = <1>;
504 #size-cells = 504 #size-cells = <0>;
505 reg = <0x8000 505 reg = <0x8000 0x100>;
506 interrupts = < 506 interrupts = <7>;
507 clocks = <&ref 507 clocks = <&refclk>;
508 status = "disa 508 status = "disabled";
509 }; 509 };
510 510
511 sm_gpio0: gpio@c000 { 511 sm_gpio0: gpio@c000 {
512 compatible = " 512 compatible = "snps,dw-apb-gpio";
513 reg = <0xc000 513 reg = <0xc000 0x400>;
514 #address-cells 514 #address-cells = <1>;
515 #size-cells = 515 #size-cells = <0>;
516 516
517 porte: gpio-po 517 porte: gpio-port@4 {
518 compat 518 compatible = "snps,dw-apb-gpio-port";
519 gpio-c 519 gpio-controller;
520 #gpio- 520 #gpio-cells = <2>;
521 ngpios 521 ngpios = <8>;
522 reg = 522 reg = <0>;
523 }; 523 };
524 }; 524 };
525 525
526 uart0: serial@9000 { 526 uart0: serial@9000 {
527 compatible = " 527 compatible = "snps,dw-apb-uart";
528 reg = <0x9000 528 reg = <0x9000 0x100>;
529 reg-shift = <2 529 reg-shift = <2>;
530 reg-io-width = 530 reg-io-width = <1>;
531 interrupts = < 531 interrupts = <8>;
532 clocks = <&ref 532 clocks = <&refclk>;
533 pinctrl-0 = <& 533 pinctrl-0 = <&uart0_pmux>;
534 pinctrl-names 534 pinctrl-names = "default";
535 status = "disa 535 status = "disabled";
536 }; 536 };
537 537
538 uart1: serial@a000 { 538 uart1: serial@a000 {
539 compatible = " 539 compatible = "snps,dw-apb-uart";
540 reg = <0xa000 540 reg = <0xa000 0x100>;
541 reg-shift = <2 541 reg-shift = <2>;
542 reg-io-width = 542 reg-io-width = <1>;
543 interrupts = < 543 interrupts = <9>;
544 clocks = <&ref 544 clocks = <&refclk>;
545 status = "disa 545 status = "disabled";
546 }; 546 };
547 547
548 uart2: serial@b000 { 548 uart2: serial@b000 {
549 compatible = " 549 compatible = "snps,dw-apb-uart";
550 reg = <0xb000 550 reg = <0xb000 0x100>;
551 reg-shift = <2 551 reg-shift = <2>;
552 reg-io-width = 552 reg-io-width = <1>;
553 interrupts = < 553 interrupts = <10>;
554 clocks = <&ref 554 clocks = <&refclk>;
555 status = "disa 555 status = "disabled";
556 }; 556 };
557 557
558 sysctrl: system-contro 558 sysctrl: system-controller@d000 {
559 compatible = " 559 compatible = "simple-mfd", "syscon";
560 reg = <0xd000 560 reg = <0xd000 0x100>;
561 561
562 sys_pinctrl: p 562 sys_pinctrl: pin-controller {
563 compat 563 compatible = "marvell,berlin2cd-system-pinctrl";
564 }; 564 };
565 565
566 adc: adc { 566 adc: adc {
567 compat 567 compatible = "marvell,berlin2-adc";
568 interr 568 interrupts = <12>, <14>;
569 interr 569 interrupt-names = "adc", "tsen";
570 }; 570 };
571 }; 571 };
572 572
573 sic: interrupt-control 573 sic: interrupt-controller@e000 {
574 compatible = " 574 compatible = "snps,dw-apb-ictl";
575 reg = <0xe000 575 reg = <0xe000 0x400>;
576 interrupt-cont 576 interrupt-controller;
577 #interrupt-cel 577 #interrupt-cells = <1>;
578 interrupt-pare 578 interrupt-parent = <&gic>;
579 interrupts = < 579 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
580 }; 580 };
581 }; 581 };
582 }; 582 };
583 }; 583 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.