1 // SPDX-License-Identifier: GPL-2.0-or-later 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* 2 /*
3 * Copyright 2012 DENX Software Engineering Gm 3 * Copyright 2012 DENX Software Engineering GmbH
4 * Heiko Schocher <hs@denx.de> 4 * Heiko Schocher <hs@denx.de>
5 */ 5 */
6 #include <dt-bindings/interrupt-controller/irq 6 #include <dt-bindings/interrupt-controller/irq.h>
7 7
8 / { 8 / {
9 #address-cells = <1>; 9 #address-cells = <1>;
10 #size-cells = <1>; 10 #size-cells = <1>;
11 chosen { }; 11 chosen { };
12 aliases { }; 12 aliases { };
13 13
14 memory@c0000000 { 14 memory@c0000000 {
15 device_type = "memory"; 15 device_type = "memory";
16 reg = <0xc0000000 0x0>; 16 reg = <0xc0000000 0x0>;
17 }; 17 };
18 18
19 cpus { 19 cpus {
20 #address-cells = <1>; 20 #address-cells = <1>;
21 #size-cells = <0>; 21 #size-cells = <0>;
22 22
23 cpu: cpu@0 { 23 cpu: cpu@0 {
24 compatible = "arm,arm9 24 compatible = "arm,arm926ej-s";
25 device_type = "cpu"; 25 device_type = "cpu";
26 reg = <0>; 26 reg = <0>;
27 clocks = <&psc0 14>; 27 clocks = <&psc0 14>;
28 operating-points-v2 = 28 operating-points-v2 = <&opp_table>;
29 }; 29 };
30 }; 30 };
31 31
32 opp_table: opp-table { 32 opp_table: opp-table {
33 compatible = "operating-points 33 compatible = "operating-points-v2";
34 34
35 opp_100: opp100-100000000 { 35 opp_100: opp100-100000000 {
36 opp-hz = /bits/ 64 <10 36 opp-hz = /bits/ 64 <100000000>;
37 opp-microvolt = <10000 37 opp-microvolt = <1000000 950000 1050000>;
38 }; 38 };
39 39
40 opp_200: opp110-200000000 { 40 opp_200: opp110-200000000 {
41 opp-hz = /bits/ 64 <20 41 opp-hz = /bits/ 64 <200000000>;
42 opp-microvolt = <11000 42 opp-microvolt = <1100000 1050000 1160000>;
43 }; 43 };
44 44
45 opp_300: opp120-300000000 { 45 opp_300: opp120-300000000 {
46 opp-hz = /bits/ 64 <30 46 opp-hz = /bits/ 64 <300000000>;
47 opp-microvolt = <12000 47 opp-microvolt = <1200000 1140000 1320000>;
48 }; 48 };
49 49
50 /* 50 /*
51 * Original silicon was 300MHz 51 * Original silicon was 300MHz max, so higher frequencies
52 * need to be enabled on a per 52 * need to be enabled on a per-board basis if the chip is
53 * capable. 53 * capable.
54 */ 54 */
55 55
56 opp_375: opp120-375000000 { 56 opp_375: opp120-375000000 {
57 status = "disabled"; 57 status = "disabled";
58 opp-hz = /bits/ 64 <37 58 opp-hz = /bits/ 64 <375000000>;
59 opp-microvolt = <12000 59 opp-microvolt = <1200000 1140000 1320000>;
60 }; 60 };
61 61
62 opp_456: opp130-456000000 { 62 opp_456: opp130-456000000 {
63 status = "disabled"; 63 status = "disabled";
64 opp-hz = /bits/ 64 <45 64 opp-hz = /bits/ 64 <456000000>;
65 opp-microvolt = <13000 65 opp-microvolt = <1300000 1250000 1350000>;
66 }; 66 };
67 }; 67 };
68 68
69 arm { 69 arm {
70 #address-cells = <1>; 70 #address-cells = <1>;
71 #size-cells = <1>; 71 #size-cells = <1>;
72 ranges; 72 ranges;
73 intc: interrupt-controller@fff 73 intc: interrupt-controller@fffee000 {
74 compatible = "ti,cp-in 74 compatible = "ti,cp-intc";
75 interrupt-controller; 75 interrupt-controller;
76 #interrupt-cells = <1> 76 #interrupt-cells = <1>;
77 ti,intc-size = <101>; 77 ti,intc-size = <101>;
78 reg = <0xfffee000 0x20 78 reg = <0xfffee000 0x2000>;
79 }; 79 };
80 }; 80 };
81 clocks: clocks { 81 clocks: clocks {
82 ref_clk: ref_clk { 82 ref_clk: ref_clk {
83 compatible = "fixed-cl 83 compatible = "fixed-clock";
84 #clock-cells = <0>; 84 #clock-cells = <0>;
85 clock-output-names = " 85 clock-output-names = "ref_clk";
86 }; 86 };
87 sata_refclk: sata_refclk { 87 sata_refclk: sata_refclk {
88 compatible = "fixed-cl 88 compatible = "fixed-clock";
89 #clock-cells = <0>; 89 #clock-cells = <0>;
90 clock-output-names = " 90 clock-output-names = "sata_refclk";
91 status = "disabled"; 91 status = "disabled";
92 }; 92 };
93 usb_refclkin: usb_refclkin { 93 usb_refclkin: usb_refclkin {
94 compatible = "fixed-cl 94 compatible = "fixed-clock";
95 #clock-cells = <0>; 95 #clock-cells = <0>;
96 clock-output-names = " 96 clock-output-names = "usb_refclkin";
97 status = "disabled"; 97 status = "disabled";
98 }; 98 };
99 }; 99 };
100 dsp: dsp@11800000 { 100 dsp: dsp@11800000 {
101 compatible = "ti,da850-dsp"; 101 compatible = "ti,da850-dsp";
102 reg = <0x11800000 0x40000>, 102 reg = <0x11800000 0x40000>,
103 <0x11e00000 0x8000>, 103 <0x11e00000 0x8000>,
104 <0x11f00000 0x8000>, 104 <0x11f00000 0x8000>,
105 <0x01c14044 0x4>, 105 <0x01c14044 0x4>,
106 <0x01c14174 0x8>; 106 <0x01c14174 0x8>;
107 reg-names = "l2sram", "l1pram" 107 reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig";
108 interrupt-parent = <&intc>; 108 interrupt-parent = <&intc>;
109 interrupts = <28>; 109 interrupts = <28>;
110 clocks = <&psc0 15>; 110 clocks = <&psc0 15>;
111 resets = <&psc0 15>; 111 resets = <&psc0 15>;
112 status = "disabled"; 112 status = "disabled";
113 }; 113 };
114 soc@1c00000 { 114 soc@1c00000 {
115 compatible = "simple-bus"; 115 compatible = "simple-bus";
116 model = "da850"; 116 model = "da850";
117 #address-cells = <1>; 117 #address-cells = <1>;
118 #size-cells = <1>; 118 #size-cells = <1>;
119 ranges = <0x0 0x01c00000 0x400 119 ranges = <0x0 0x01c00000 0x400000>;
120 interrupt-parent = <&intc>; 120 interrupt-parent = <&intc>;
121 121
122 psc0: clock-controller@10000 { 122 psc0: clock-controller@10000 {
123 compatible = "ti,da850 123 compatible = "ti,da850-psc0";
124 reg = <0x10000 0x1000> 124 reg = <0x10000 0x1000>;
125 #clock-cells = <1>; 125 #clock-cells = <1>;
126 #reset-cells = <1>; 126 #reset-cells = <1>;
127 #power-domain-cells = 127 #power-domain-cells = <1>;
128 clocks = <&pll0_sysclk 128 clocks = <&pll0_sysclk 1>, <&pll0_sysclk 2>,
129 <&pll0_sysclk 129 <&pll0_sysclk 4>, <&pll0_sysclk 6>,
130 <&async1_clk> 130 <&async1_clk>;
131 clock-names = "pll0_sy 131 clock-names = "pll0_sysclk1", "pll0_sysclk2",
132 "pll0_sy 132 "pll0_sysclk4", "pll0_sysclk6",
133 "async1" 133 "async1";
134 }; 134 };
135 pll0: clock-controller@11000 { 135 pll0: clock-controller@11000 {
136 compatible = "ti,da850 136 compatible = "ti,da850-pll0";
137 reg = <0x11000 0x1000> 137 reg = <0x11000 0x1000>;
138 clocks = <&ref_clk>, < 138 clocks = <&ref_clk>, <&pll1_sysclk 3>;
139 clock-names = "clksrc" 139 clock-names = "clksrc", "extclksrc";
140 140
141 pll0_pllout: pllout { 141 pll0_pllout: pllout {
142 #clock-cells = 142 #clock-cells = <0>;
143 }; 143 };
144 pll0_sysclk: sysclk { 144 pll0_sysclk: sysclk {
145 #clock-cells = 145 #clock-cells = <1>;
146 }; 146 };
147 pll0_auxclk: auxclk { 147 pll0_auxclk: auxclk {
148 #clock-cells = 148 #clock-cells = <0>;
149 }; 149 };
150 pll0_obsclk: obsclk { 150 pll0_obsclk: obsclk {
151 #clock-cells = 151 #clock-cells = <0>;
152 }; 152 };
153 }; 153 };
154 pmx_core: pinmux@14120 { 154 pmx_core: pinmux@14120 {
155 compatible = "pinctrl- 155 compatible = "pinctrl-single";
156 reg = <0x14120 0x50>; 156 reg = <0x14120 0x50>;
157 #pinctrl-cells = <2>; 157 #pinctrl-cells = <2>;
158 pinctrl-single,bit-per 158 pinctrl-single,bit-per-mux;
159 pinctrl-single,registe 159 pinctrl-single,register-width = <32>;
160 pinctrl-single,functio 160 pinctrl-single,function-mask = <0xf>;
161 /* pin base, nr pins & 161 /* pin base, nr pins & gpio function */
162 pinctrl-single,gpio-ra 162 pinctrl-single,gpio-range = <&range 0 17 0x8>,
163 163 <&range 17 8 0x4>,
164 164 <&range 26 8 0x4>,
165 165 <&range 34 80 0x8>,
166 166 <&range 129 31 0x8>;
167 status = "disabled"; 167 status = "disabled";
168 168
169 range: gpio-range { 169 range: gpio-range {
170 #pinctrl-singl 170 #pinctrl-single,gpio-range-cells = <3>;
171 }; 171 };
172 172
173 serial0_rtscts_pins: s 173 serial0_rtscts_pins: serial0-rtscts-pins {
174 pinctrl-single 174 pinctrl-single,bits = <
175 /* UAR 175 /* UART0_RTS UART0_CTS */
176 0x0c 0 176 0x0c 0x22000000 0xff000000
177 >; 177 >;
178 }; 178 };
179 serial0_rxtx_pins: ser 179 serial0_rxtx_pins: serial0-rxtx-pins {
180 pinctrl-single 180 pinctrl-single,bits = <
181 /* UAR 181 /* UART0_TXD UART0_RXD */
182 0x0c 0 182 0x0c 0x00220000 0x00ff0000
183 >; 183 >;
184 }; 184 };
185 serial1_rtscts_pins: s 185 serial1_rtscts_pins: serial1-rtscts-pins {
186 pinctrl-single 186 pinctrl-single,bits = <
187 /* UAR 187 /* UART1_CTS UART1_RTS */
188 0x00 0 188 0x00 0x00440000 0x00ff0000
189 >; 189 >;
190 }; 190 };
191 serial1_rxtx_pins: ser 191 serial1_rxtx_pins: serial1-rxtx-pins {
192 pinctrl-single 192 pinctrl-single,bits = <
193 /* UAR 193 /* UART1_TXD UART1_RXD */
194 0x10 0 194 0x10 0x22000000 0xff000000
195 >; 195 >;
196 }; 196 };
197 serial2_rtscts_pins: s 197 serial2_rtscts_pins: serial2-rtscts-pins {
198 pinctrl-single 198 pinctrl-single,bits = <
199 /* UAR 199 /* UART2_CTS UART2_RTS */
200 0x00 0 200 0x00 0x44000000 0xff000000
201 >; 201 >;
202 }; 202 };
203 serial2_rxtx_pins: ser 203 serial2_rxtx_pins: serial2-rxtx-pins {
204 pinctrl-single 204 pinctrl-single,bits = <
205 /* UAR 205 /* UART2_TXD UART2_RXD */
206 0x10 0 206 0x10 0x00220000 0x00ff0000
207 >; 207 >;
208 }; 208 };
209 i2c0_pins: i2c0-pins { 209 i2c0_pins: i2c0-pins {
210 pinctrl-single 210 pinctrl-single,bits = <
211 /* I2C 211 /* I2C0_SDA,I2C0_SCL */
212 0x10 0 212 0x10 0x00002200 0x0000ff00
213 >; 213 >;
214 }; 214 };
215 i2c1_pins: i2c1-pins { 215 i2c1_pins: i2c1-pins {
216 pinctrl-single 216 pinctrl-single,bits = <
217 /* I2C 217 /* I2C1_SDA, I2C1_SCL */
218 0x10 0 218 0x10 0x00440000 0x00ff0000
219 >; 219 >;
220 }; 220 };
221 mmc0_pins: mmc-pins { 221 mmc0_pins: mmc-pins {
222 pinctrl-single 222 pinctrl-single,bits = <
223 /* MMC 223 /* MMCSD0_DAT[3] MMCSD0_DAT[2]
224 * MMC 224 * MMCSD0_DAT[1] MMCSD0_DAT[0]
225 * MMC 225 * MMCSD0_CMD MMCSD0_CLK
226 */ 226 */
227 0x28 0 227 0x28 0x00222222 0x00ffffff
228 >; 228 >;
229 }; 229 };
230 ehrpwm0a_pins: ehrpwm0 230 ehrpwm0a_pins: ehrpwm0a-pins {
231 pinctrl-single 231 pinctrl-single,bits = <
232 /* EPW 232 /* EPWM0A */
233 0xc 0x 233 0xc 0x00000002 0x0000000f
234 >; 234 >;
235 }; 235 };
236 ehrpwm0b_pins: ehrpwm0 236 ehrpwm0b_pins: ehrpwm0b-pins {
237 pinctrl-single 237 pinctrl-single,bits = <
238 /* EPW 238 /* EPWM0B */
239 0xc 0x 239 0xc 0x00000020 0x000000f0
240 >; 240 >;
241 }; 241 };
242 ehrpwm1a_pins: ehrpwm1 242 ehrpwm1a_pins: ehrpwm1a-pins {
243 pinctrl-single 243 pinctrl-single,bits = <
244 /* EPW 244 /* EPWM1A */
245 0x14 0 245 0x14 0x00000002 0x0000000f
246 >; 246 >;
247 }; 247 };
248 ehrpwm1b_pins: ehrpwm1 248 ehrpwm1b_pins: ehrpwm1b-pins {
249 pinctrl-single 249 pinctrl-single,bits = <
250 /* EPW 250 /* EPWM1B */
251 0x14 0 251 0x14 0x00000020 0x000000f0
252 >; 252 >;
253 }; 253 };
254 ecap0_pins: ecap0-pins 254 ecap0_pins: ecap0-pins {
255 pinctrl-single 255 pinctrl-single,bits = <
256 /* ECA 256 /* ECAP0_APWM0 */
257 0x8 0x 257 0x8 0x20000000 0xf0000000
258 >; 258 >;
259 }; 259 };
260 ecap1_pins: ecap1-pins 260 ecap1_pins: ecap1-pins {
261 pinctrl-single 261 pinctrl-single,bits = <
262 /* ECA 262 /* ECAP1_APWM1 */
263 0x4 0x 263 0x4 0x40000000 0xf0000000
264 >; 264 >;
265 }; 265 };
266 ecap2_pins: ecap2-pins 266 ecap2_pins: ecap2-pins {
267 pinctrl-single 267 pinctrl-single,bits = <
268 /* ECA 268 /* ECAP2_APWM2 */
269 0x4 0x 269 0x4 0x00000004 0x0000000f
270 >; 270 >;
271 }; 271 };
272 spi0_pins: spi0-pins { 272 spi0_pins: spi0-pins {
273 pinctrl-single 273 pinctrl-single,bits = <
274 /* SIM 274 /* SIMO, SOMI, CLK */
275 0xc 0x 275 0xc 0x00001101 0x0000ff0f
276 >; 276 >;
277 }; 277 };
278 spi0_cs0_pin: spi0-cs0 278 spi0_cs0_pin: spi0-cs0-pins {
279 pinctrl-single 279 pinctrl-single,bits = <
280 /* CS0 280 /* CS0 */
281 0x10 0 281 0x10 0x00000010 0x000000f0
282 >; 282 >;
283 }; 283 };
284 spi0_cs3_pin: spi0-cs3 284 spi0_cs3_pin: spi0-cs3-pins {
285 pinctrl-single 285 pinctrl-single,bits = <
286 /* CS3 286 /* CS3 */
287 0xc 0x 287 0xc 0x01000000 0x0f000000
288 >; 288 >;
289 }; 289 };
290 spi1_pins: spi1-pins { 290 spi1_pins: spi1-pins {
291 pinctrl-single 291 pinctrl-single,bits = <
292 /* SIM 292 /* SIMO, SOMI, CLK */
293 0x14 0 293 0x14 0x00110100 0x00ff0f00
294 >; 294 >;
295 }; 295 };
296 spi1_cs0_pin: spi1-cs0 296 spi1_cs0_pin: spi1-cs0-pins {
297 pinctrl-single 297 pinctrl-single,bits = <
298 /* CS0 298 /* CS0 */
299 0x14 0 299 0x14 0x00000010 0x000000f0
300 >; 300 >;
301 }; 301 };
302 mdio_pins: mdio-pins { 302 mdio_pins: mdio-pins {
303 pinctrl-single 303 pinctrl-single,bits = <
304 /* MDI 304 /* MDIO_CLK, MDIO_D */
305 0x10 0 305 0x10 0x00000088 0x000000ff
306 >; 306 >;
307 }; 307 };
308 mii_pins: mii-pins { 308 mii_pins: mii-pins {
309 pinctrl-single 309 pinctrl-single,bits = <
310 /* 310 /*
311 * MII 311 * MII_TXEN, MII_TXCLK, MII_COL
312 * MII 312 * MII_TXD_3, MII_TXD_2, MII_TXD_1
313 * MII 313 * MII_TXD_0
314 */ 314 */
315 0x8 0x 315 0x8 0x88888880 0xfffffff0
316 /* 316 /*
317 * MII 317 * MII_RXER, MII_CRS, MII_RXCLK
318 * MII 318 * MII_RXDV, MII_RXD_3, MII_RXD_2
319 * MII 319 * MII_RXD_1, MII_RXD_0
320 */ 320 */
321 0xc 0x 321 0xc 0x88888888 0xffffffff
322 >; 322 >;
323 }; 323 };
324 lcd_pins: lcd-pins { 324 lcd_pins: lcd-pins {
325 pinctrl-single 325 pinctrl-single,bits = <
326 /* 326 /*
327 * LCD 327 * LCD_D[2], LCD_D[3], LCD_D[4], LCD_D[5],
328 * LCD 328 * LCD_D[6], LCD_D[7]
329 */ 329 */
330 0x40 0 330 0x40 0x22222200 0xffffff00
331 /* 331 /*
332 * LCD 332 * LCD_D[10], LCD_D[11], LCD_D[12], LCD_D[13],
333 * LCD 333 * LCD_D[14], LCD_D[15], LCD_D[0], LCD_D[1]
334 */ 334 */
335 0x44 0 335 0x44 0x22222222 0xffffffff
336 /* LCD 336 /* LCD_D[8], LCD_D[9] */
337 0x48 0 337 0x48 0x00000022 0x000000ff
338 338
339 /* LCD 339 /* LCD_PCLK */
340 0x48 0 340 0x48 0x02000000 0x0f000000
341 /* LCD 341 /* LCD_AC_ENB_CS, LCD_VSYNC, LCD_HSYNC */
342 0x4c 0 342 0x4c 0x02000022 0x0f0000ff
343 >; 343 >;
344 }; 344 };
345 vpif_capture_pins: vpi 345 vpif_capture_pins: vpif-capture-pins {
346 pinctrl-single 346 pinctrl-single,bits = <
347 /* VP_ 347 /* VP_DIN[2..7], VP_CLKIN1, VP_CLKIN0 */
348 0x38 0 348 0x38 0x11111111 0xffffffff
349 /* VP_ 349 /* VP_DIN[10..15,0..1] */
350 0x3c 0 350 0x3c 0x11111111 0xffffffff
351 /* VP_ 351 /* VP_DIN[8..9] */
352 0x40 0 352 0x40 0x00000011 0x000000ff
353 >; 353 >;
354 }; 354 };
355 vpif_display_pins: vpi 355 vpif_display_pins: vpif-display-pins {
356 pinctrl-single 356 pinctrl-single,bits = <
357 /* VP_ 357 /* VP_DOUT[2..7] */
358 0x40 0 358 0x40 0x11111100 0xffffff00
359 /* VP_ 359 /* VP_DOUT[10..15,0..1] */
360 0x44 0 360 0x44 0x11111111 0xffffffff
361 /* VP 361 /* VP_DOUT[8..9] */
362 0x48 0 362 0x48 0x00000011 0x000000ff
363 /* 363 /*
364 * VP_ 364 * VP_CLKOUT3, VP_CLKIN3,
365 * VP_ 365 * VP_CLKOUT2, VP_CLKIN2
366 */ 366 */
367 0x4c 0 367 0x4c 0x00111100 0x00ffff00
368 >; 368 >;
369 }; 369 };
370 }; 370 };
371 prictrl: priority-controller@1 371 prictrl: priority-controller@14110 {
372 compatible = "ti,da850 372 compatible = "ti,da850-mstpri";
373 reg = <0x14110 0x0c>; 373 reg = <0x14110 0x0c>;
374 status = "disabled"; 374 status = "disabled";
375 }; 375 };
376 cfgchip: chip-controller@1417c 376 cfgchip: chip-controller@1417c {
377 compatible = "ti,da830 377 compatible = "ti,da830-cfgchip", "syscon", "simple-mfd";
378 reg = <0x1417c 0x14>; 378 reg = <0x1417c 0x14>;
379 379
380 usb_phy: usb-phy { 380 usb_phy: usb-phy {
381 compatible = " 381 compatible = "ti,da830-usb-phy";
382 #phy-cells = < 382 #phy-cells = <1>;
383 clocks = <&usb 383 clocks = <&usb_phy_clk 0>, <&usb_phy_clk 1>;
384 clock-names = 384 clock-names = "usb0_clk48", "usb1_clk48";
385 status = "disa 385 status = "disabled";
386 }; 386 };
387 usb_phy_clk: usb-phy-c 387 usb_phy_clk: usb-phy-clocks {
388 compatible = " 388 compatible = "ti,da830-usb-phy-clocks";
389 #clock-cells = 389 #clock-cells = <1>;
390 clocks = <&psc 390 clocks = <&psc1 1>, <&usb_refclkin>,
391 <&pll 391 <&pll0_auxclk>;
392 clock-names = 392 clock-names = "fck", "usb_refclkin", "auxclk";
393 }; 393 };
394 ehrpwm_tbclk: ehrpwm_t 394 ehrpwm_tbclk: ehrpwm_tbclk {
395 compatible = " 395 compatible = "ti,da830-tbclksync";
396 #clock-cells = 396 #clock-cells = <0>;
397 clocks = <&psc 397 clocks = <&psc1 17>;
398 clock-names = 398 clock-names = "fck";
399 }; 399 };
400 div4p5_clk: div4.5 { 400 div4p5_clk: div4.5 {
401 compatible = " 401 compatible = "ti,da830-div4p5ena";
402 #clock-cells = 402 #clock-cells = <0>;
403 clocks = <&pll 403 clocks = <&pll0_pllout>;
404 clock-names = 404 clock-names = "pll0_pllout";
405 }; 405 };
406 async1_clk: async1 { 406 async1_clk: async1 {
407 compatible = " 407 compatible = "ti,da850-async1-clksrc";
408 #clock-cells = 408 #clock-cells = <0>;
409 clocks = <&pll 409 clocks = <&pll0_sysclk 3>, <&div4p5_clk>;
410 clock-names = 410 clock-names = "pll0_sysclk3", "div4.5";
411 }; 411 };
412 async3_clk: async3 { 412 async3_clk: async3 {
413 compatible = " 413 compatible = "ti,da850-async3-clksrc";
414 #clock-cells = 414 #clock-cells = <0>;
415 clocks = <&pll 415 clocks = <&pll0_sysclk 2>, <&pll1_sysclk 2>;
416 clock-names = 416 clock-names = "pll0_sysclk2", "pll1_sysclk2";
417 }; 417 };
418 }; 418 };
419 edma0: edma@0 { 419 edma0: edma@0 {
420 compatible = "ti,edma3 420 compatible = "ti,edma3-tpcc";
421 /* eDMA3 CC0: 0x01c0 0 421 /* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */
422 reg = <0x0 0x8000>; 422 reg = <0x0 0x8000>;
423 reg-names = "edma3_cc" 423 reg-names = "edma3_cc";
424 interrupts = <11>, <12 424 interrupts = <11>, <12>;
425 interrupt-names = "edm 425 interrupt-names = "edma3_ccint", "edma3_ccerrint";
426 #dma-cells = <2>; 426 #dma-cells = <2>;
427 427
428 ti,tptcs = <&edma0_tpt 428 ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>;
429 power-domains = <&psc0 429 power-domains = <&psc0 0>;
430 }; 430 };
431 edma0_tptc0: tptc@8000 { 431 edma0_tptc0: tptc@8000 {
432 compatible = "ti,edma3 432 compatible = "ti,edma3-tptc";
433 reg = <0x8000 0x400>; 433 reg = <0x8000 0x400>;
434 interrupts = <13>; 434 interrupts = <13>;
435 interrupt-names = "edm 435 interrupt-names = "edm3_tcerrint";
436 power-domains = <&psc0 436 power-domains = <&psc0 1>;
437 }; 437 };
438 edma0_tptc1: tptc@8400 { 438 edma0_tptc1: tptc@8400 {
439 compatible = "ti,edma3 439 compatible = "ti,edma3-tptc";
440 reg = <0x8400 0x400>; 440 reg = <0x8400 0x400>;
441 interrupts = <32>; 441 interrupts = <32>;
442 interrupt-names = "edm 442 interrupt-names = "edm3_tcerrint";
443 power-domains = <&psc0 443 power-domains = <&psc0 2>;
444 }; 444 };
445 edma1: edma@230000 { 445 edma1: edma@230000 {
446 compatible = "ti,edma3 446 compatible = "ti,edma3-tpcc";
447 /* eDMA3 CC1: 0x01e3 0 447 /* eDMA3 CC1: 0x01e3 0000 - 0x01e3 7fff */
448 reg = <0x230000 0x8000 448 reg = <0x230000 0x8000>;
449 reg-names = "edma3_cc" 449 reg-names = "edma3_cc";
450 interrupts = <93>, <94 450 interrupts = <93>, <94>;
451 interrupt-names = "edm 451 interrupt-names = "edma3_ccint", "edma3_ccerrint";
452 #dma-cells = <2>; 452 #dma-cells = <2>;
453 453
454 ti,tptcs = <&edma1_tpt 454 ti,tptcs = <&edma1_tptc0 7>;
455 power-domains = <&psc1 455 power-domains = <&psc1 0>;
456 }; 456 };
457 edma1_tptc0: tptc@238000 { 457 edma1_tptc0: tptc@238000 {
458 compatible = "ti,edma3 458 compatible = "ti,edma3-tptc";
459 reg = <0x238000 0x400> 459 reg = <0x238000 0x400>;
460 interrupts = <95>; 460 interrupts = <95>;
461 interrupt-names = "edm 461 interrupt-names = "edm3_tcerrint";
462 power-domains = <&psc1 462 power-domains = <&psc1 21>;
463 }; 463 };
464 serial0: serial@42000 { 464 serial0: serial@42000 {
465 compatible = "ti,da830 465 compatible = "ti,da830-uart", "ns16550a";
466 reg = <0x42000 0x100>; 466 reg = <0x42000 0x100>;
467 reg-io-width = <4>; 467 reg-io-width = <4>;
468 reg-shift = <2>; 468 reg-shift = <2>;
469 interrupts = <25>; 469 interrupts = <25>;
470 clocks = <&psc0 9>; 470 clocks = <&psc0 9>;
471 power-domains = <&psc0 471 power-domains = <&psc0 9>;
472 status = "disabled"; 472 status = "disabled";
473 }; 473 };
474 serial1: serial@10c000 { 474 serial1: serial@10c000 {
475 compatible = "ti,da830 475 compatible = "ti,da830-uart", "ns16550a";
476 reg = <0x10c000 0x100> 476 reg = <0x10c000 0x100>;
477 reg-io-width = <4>; 477 reg-io-width = <4>;
478 reg-shift = <2>; 478 reg-shift = <2>;
479 interrupts = <53>; 479 interrupts = <53>;
480 clocks = <&psc1 12>; 480 clocks = <&psc1 12>;
481 power-domains = <&psc1 481 power-domains = <&psc1 12>;
482 status = "disabled"; 482 status = "disabled";
483 }; 483 };
484 serial2: serial@10d000 { 484 serial2: serial@10d000 {
485 compatible = "ti,da830 485 compatible = "ti,da830-uart", "ns16550a";
486 reg = <0x10d000 0x100> 486 reg = <0x10d000 0x100>;
487 reg-io-width = <4>; 487 reg-io-width = <4>;
488 reg-shift = <2>; 488 reg-shift = <2>;
489 interrupts = <61>; 489 interrupts = <61>;
490 clocks = <&psc1 13>; 490 clocks = <&psc1 13>;
491 power-domains = <&psc1 491 power-domains = <&psc1 13>;
492 status = "disabled"; 492 status = "disabled";
493 }; 493 };
494 rtc0: rtc@23000 { 494 rtc0: rtc@23000 {
495 compatible = "ti,da830 495 compatible = "ti,da830-rtc";
496 reg = <0x23000 0x1000> 496 reg = <0x23000 0x1000>;
497 interrupts = <19>, <19 497 interrupts = <19>, <19>;
498 clocks = <&pll0_auxclk 498 clocks = <&pll0_auxclk>;
499 clock-names = "int-clk 499 clock-names = "int-clk";
500 status = "disabled"; 500 status = "disabled";
501 }; 501 };
502 i2c0: i2c@22000 { 502 i2c0: i2c@22000 {
503 compatible = "ti,davin 503 compatible = "ti,davinci-i2c";
504 reg = <0x22000 0x1000> 504 reg = <0x22000 0x1000>;
505 interrupts = <15>; 505 interrupts = <15>;
506 #address-cells = <1>; 506 #address-cells = <1>;
507 #size-cells = <0>; 507 #size-cells = <0>;
508 clocks = <&pll0_auxclk 508 clocks = <&pll0_auxclk>;
509 status = "disabled"; 509 status = "disabled";
510 }; 510 };
511 i2c1: i2c@228000 { 511 i2c1: i2c@228000 {
512 compatible = "ti,davin 512 compatible = "ti,davinci-i2c";
513 reg = <0x228000 0x1000 513 reg = <0x228000 0x1000>;
514 interrupts = <51>; 514 interrupts = <51>;
515 #address-cells = <1>; 515 #address-cells = <1>;
516 #size-cells = <0>; 516 #size-cells = <0>;
517 clocks = <&psc1 11>; 517 clocks = <&psc1 11>;
518 power-domains = <&psc1 518 power-domains = <&psc1 11>;
519 status = "disabled"; 519 status = "disabled";
520 }; 520 };
521 clocksource: timer@20000 { 521 clocksource: timer@20000 {
522 compatible = "ti,da830 522 compatible = "ti,da830-timer";
523 reg = <0x20000 0x1000> 523 reg = <0x20000 0x1000>;
524 interrupts = <21>, <22 524 interrupts = <21>, <22>;
525 interrupt-names = "tin 525 interrupt-names = "tint12", "tint34";
526 clocks = <&pll0_auxclk 526 clocks = <&pll0_auxclk>;
527 }; 527 };
528 wdt: wdt@21000 { 528 wdt: wdt@21000 {
529 compatible = "ti,davin 529 compatible = "ti,davinci-wdt";
530 reg = <0x21000 0x1000> 530 reg = <0x21000 0x1000>;
531 clocks = <&pll0_auxclk 531 clocks = <&pll0_auxclk>;
532 status = "disabled"; 532 status = "disabled";
533 }; 533 };
534 mmc0: mmc@40000 { 534 mmc0: mmc@40000 {
535 compatible = "ti,da830 535 compatible = "ti,da830-mmc";
536 reg = <0x40000 0x1000> 536 reg = <0x40000 0x1000>;
537 cap-sd-highspeed; 537 cap-sd-highspeed;
538 cap-mmc-highspeed; 538 cap-mmc-highspeed;
539 interrupts = <16>, <17 539 interrupts = <16>, <17>;
540 dmas = <&edma0 16 0>, 540 dmas = <&edma0 16 0>, <&edma0 17 0>;
541 dma-names = "rx", "tx" 541 dma-names = "rx", "tx";
542 clocks = <&psc0 5>; 542 clocks = <&psc0 5>;
543 status = "disabled"; 543 status = "disabled";
544 }; 544 };
545 vpif: video@217000 { 545 vpif: video@217000 {
546 compatible = "ti,da850 546 compatible = "ti,da850-vpif";
547 reg = <0x217000 0x1000 547 reg = <0x217000 0x1000>;
548 interrupts = <92>; 548 interrupts = <92>;
549 power-domains = <&psc1 549 power-domains = <&psc1 9>;
550 status = "disabled"; 550 status = "disabled";
551 551
552 /* VPIF capture port * 552 /* VPIF capture port */
553 port@0 { 553 port@0 {
554 #address-cells 554 #address-cells = <1>;
555 #size-cells = 555 #size-cells = <0>;
556 }; 556 };
557 557
558 /* VPIF display port * 558 /* VPIF display port */
559 port@1 { 559 port@1 {
560 #address-cells 560 #address-cells = <1>;
561 #size-cells = 561 #size-cells = <0>;
562 }; 562 };
563 }; 563 };
564 mmc1: mmc@21b000 { 564 mmc1: mmc@21b000 {
565 compatible = "ti,da830 565 compatible = "ti,da830-mmc";
566 reg = <0x21b000 0x1000 566 reg = <0x21b000 0x1000>;
567 cap-sd-highspeed; 567 cap-sd-highspeed;
568 cap-mmc-highspeed; 568 cap-mmc-highspeed;
569 interrupts = <72>, <73 569 interrupts = <72>, <73>;
570 dmas = <&edma1 28 0>, 570 dmas = <&edma1 28 0>, <&edma1 29 0>;
571 dma-names = "rx", "tx" 571 dma-names = "rx", "tx";
572 clocks = <&psc1 18>; 572 clocks = <&psc1 18>;
573 status = "disabled"; 573 status = "disabled";
574 }; 574 };
575 ehrpwm0: pwm@300000 { 575 ehrpwm0: pwm@300000 {
576 compatible = "ti,da850 576 compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm";
577 #pwm-cells = <3>; 577 #pwm-cells = <3>;
578 reg = <0x300000 0x2000 578 reg = <0x300000 0x2000>;
579 clocks = <&psc1 17>, < 579 clocks = <&psc1 17>, <&ehrpwm_tbclk>;
580 clock-names = "fck", " 580 clock-names = "fck", "tbclk";
581 power-domains = <&psc1 581 power-domains = <&psc1 17>;
582 status = "disabled"; 582 status = "disabled";
583 }; 583 };
584 ehrpwm1: pwm@302000 { 584 ehrpwm1: pwm@302000 {
585 compatible = "ti,da850 585 compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm";
586 #pwm-cells = <3>; 586 #pwm-cells = <3>;
587 reg = <0x302000 0x2000 587 reg = <0x302000 0x2000>;
588 clocks = <&psc1 17>, < 588 clocks = <&psc1 17>, <&ehrpwm_tbclk>;
589 clock-names = "fck", " 589 clock-names = "fck", "tbclk";
590 power-domains = <&psc1 590 power-domains = <&psc1 17>;
591 status = "disabled"; 591 status = "disabled";
592 }; 592 };
593 ecap0: pwm@306000 { 593 ecap0: pwm@306000 {
594 compatible = "ti,da850 594 compatible = "ti,da850-ecap", "ti,am3352-ecap";
595 #pwm-cells = <3>; 595 #pwm-cells = <3>;
596 reg = <0x306000 0x80>; 596 reg = <0x306000 0x80>;
597 clocks = <&psc1 20>; 597 clocks = <&psc1 20>;
598 clock-names = "fck"; 598 clock-names = "fck";
599 power-domains = <&psc1 599 power-domains = <&psc1 20>;
600 status = "disabled"; 600 status = "disabled";
601 }; 601 };
602 ecap1: pwm@307000 { 602 ecap1: pwm@307000 {
603 compatible = "ti,da850 603 compatible = "ti,da850-ecap", "ti,am3352-ecap";
604 #pwm-cells = <3>; 604 #pwm-cells = <3>;
605 reg = <0x307000 0x80>; 605 reg = <0x307000 0x80>;
606 clocks = <&psc1 20>; 606 clocks = <&psc1 20>;
607 clock-names = "fck"; 607 clock-names = "fck";
608 power-domains = <&psc1 608 power-domains = <&psc1 20>;
609 status = "disabled"; 609 status = "disabled";
610 }; 610 };
611 ecap2: pwm@308000 { 611 ecap2: pwm@308000 {
612 compatible = "ti,da850 612 compatible = "ti,da850-ecap", "ti,am3352-ecap";
613 #pwm-cells = <3>; 613 #pwm-cells = <3>;
614 reg = <0x308000 0x80>; 614 reg = <0x308000 0x80>;
615 clocks = <&psc1 20>; 615 clocks = <&psc1 20>;
616 clock-names = "fck"; 616 clock-names = "fck";
617 power-domains = <&psc1 617 power-domains = <&psc1 20>;
618 status = "disabled"; 618 status = "disabled";
619 }; 619 };
620 spi0: spi@41000 { 620 spi0: spi@41000 {
621 #address-cells = <1>; 621 #address-cells = <1>;
622 #size-cells = <0>; 622 #size-cells = <0>;
623 compatible = "ti,da830 623 compatible = "ti,da830-spi";
624 reg = <0x41000 0x1000> 624 reg = <0x41000 0x1000>;
625 num-cs = <6>; 625 num-cs = <6>;
626 ti,davinci-spi-intr-li 626 ti,davinci-spi-intr-line = <1>;
627 interrupts = <20>; 627 interrupts = <20>;
628 dmas = <&edma0 14 0>, 628 dmas = <&edma0 14 0>, <&edma0 15 0>;
629 dma-names = "rx", "tx" 629 dma-names = "rx", "tx";
630 clocks = <&psc0 4>; 630 clocks = <&psc0 4>;
631 power-domains = <&psc0 631 power-domains = <&psc0 4>;
632 status = "disabled"; 632 status = "disabled";
633 }; 633 };
634 spi1: spi@30e000 { 634 spi1: spi@30e000 {
635 #address-cells = <1>; 635 #address-cells = <1>;
636 #size-cells = <0>; 636 #size-cells = <0>;
637 compatible = "ti,da830 637 compatible = "ti,da830-spi";
638 reg = <0x30e000 0x1000 638 reg = <0x30e000 0x1000>;
639 num-cs = <4>; 639 num-cs = <4>;
640 ti,davinci-spi-intr-li 640 ti,davinci-spi-intr-line = <1>;
641 interrupts = <56>; 641 interrupts = <56>;
642 dmas = <&edma0 18 0>, 642 dmas = <&edma0 18 0>, <&edma0 19 0>;
643 dma-names = "rx", "tx" 643 dma-names = "rx", "tx";
644 clocks = <&psc1 10>; 644 clocks = <&psc1 10>;
645 power-domains = <&psc1 645 power-domains = <&psc1 10>;
646 status = "disabled"; 646 status = "disabled";
647 }; 647 };
648 usb0: usb@200000 { 648 usb0: usb@200000 {
649 compatible = "ti,da830 649 compatible = "ti,da830-musb";
650 reg = <0x200000 0x1000 650 reg = <0x200000 0x1000>;
651 ranges; 651 ranges;
652 interrupts = <58>; 652 interrupts = <58>;
653 interrupt-names = "mc" 653 interrupt-names = "mc";
654 dr_mode = "otg"; 654 dr_mode = "otg";
655 phys = <&usb_phy 0>; 655 phys = <&usb_phy 0>;
656 phy-names = "usb-phy"; 656 phy-names = "usb-phy";
657 clocks = <&psc1 1>; 657 clocks = <&psc1 1>;
658 clock-ranges; 658 clock-ranges;
659 status = "disabled"; 659 status = "disabled";
660 660
661 #address-cells = <1>; 661 #address-cells = <1>;
662 #size-cells = <1>; 662 #size-cells = <1>;
663 663
664 dmas = <&cppi41dma 0 0 664 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
665 &cppi41dma 2 0 665 &cppi41dma 2 0 &cppi41dma 3 0
666 &cppi41dma 0 1 666 &cppi41dma 0 1 &cppi41dma 1 1
667 &cppi41dma 2 1 667 &cppi41dma 2 1 &cppi41dma 3 1>;
668 dma-names = 668 dma-names =
669 "rx1", "rx2", 669 "rx1", "rx2", "rx3", "rx4",
670 "tx1", "tx2", 670 "tx1", "tx2", "tx3", "tx4";
671 671
672 cppi41dma: dma-control 672 cppi41dma: dma-controller@201000 {
673 compatible = " 673 compatible = "ti,da830-cppi41";
674 reg = <0x20100 674 reg = <0x201000 0x1000
675 0x2020 675 0x202000 0x1000
676 0x2040 676 0x204000 0x4000>;
677 reg-names = "c 677 reg-names = "controller",
678 "s 678 "scheduler", "queuemgr";
679 interrupts = < 679 interrupts = <58>;
680 #dma-cells = < 680 #dma-cells = <2>;
681 /* For backwar 681 /* For backwards compatibility: */
682 #dma-channels 682 #dma-channels = <4>;
683 dma-channels = 683 dma-channels = <4>;
684 power-domains 684 power-domains = <&psc1 1>;
685 status = "okay 685 status = "okay";
686 }; 686 };
687 }; 687 };
688 sata: sata@218000 { 688 sata: sata@218000 {
689 compatible = "ti,da850 689 compatible = "ti,da850-ahci";
690 reg = <0x218000 0x2000 690 reg = <0x218000 0x2000>, <0x22c018 0x4>;
691 interrupts = <67>; 691 interrupts = <67>;
692 clocks = <&psc1 8>, <& 692 clocks = <&psc1 8>, <&sata_refclk>;
693 clock-names = "fck", " 693 clock-names = "fck", "refclk";
694 status = "disabled"; 694 status = "disabled";
695 }; 695 };
696 pll1: clock-controller@21a000 696 pll1: clock-controller@21a000 {
697 compatible = "ti,da850 697 compatible = "ti,da850-pll1";
698 reg = <0x21a000 0x1000 698 reg = <0x21a000 0x1000>;
699 clocks = <&ref_clk>; 699 clocks = <&ref_clk>;
700 clock-names = "clksrc" 700 clock-names = "clksrc";
701 701
702 pll1_sysclk: sysclk { 702 pll1_sysclk: sysclk {
703 #clock-cells = 703 #clock-cells = <1>;
704 }; 704 };
705 pll1_obsclk: obsclk { 705 pll1_obsclk: obsclk {
706 #clock-cells = 706 #clock-cells = <0>;
707 }; 707 };
708 }; 708 };
709 mdio: mdio@224000 { 709 mdio: mdio@224000 {
710 compatible = "ti,davin 710 compatible = "ti,davinci_mdio";
711 #address-cells = <1>; 711 #address-cells = <1>;
712 #size-cells = <0>; 712 #size-cells = <0>;
713 reg = <0x224000 0x1000 713 reg = <0x224000 0x1000>;
714 clocks = <&psc1 5>; 714 clocks = <&psc1 5>;
715 clock-names = "fck"; 715 clock-names = "fck";
716 power-domains = <&psc1 716 power-domains = <&psc1 5>;
717 status = "disabled"; 717 status = "disabled";
718 }; 718 };
719 eth0: ethernet@220000 { 719 eth0: ethernet@220000 {
720 compatible = "ti,davin 720 compatible = "ti,davinci-dm6467-emac";
721 reg = <0x220000 0x4000 721 reg = <0x220000 0x4000>;
722 ti,davinci-ctrl-reg-of 722 ti,davinci-ctrl-reg-offset = <0x3000>;
723 ti,davinci-ctrl-mod-re 723 ti,davinci-ctrl-mod-reg-offset = <0x2000>;
724 ti,davinci-ctrl-ram-of 724 ti,davinci-ctrl-ram-offset = <0>;
725 ti,davinci-ctrl-ram-si 725 ti,davinci-ctrl-ram-size = <0x2000>;
726 local-mac-address = [ 726 local-mac-address = [ 00 00 00 00 00 00 ];
727 interrupts = <33>, <34 727 interrupts = <33>, <34>, <35>,<36>;
728 clocks = <&psc1 5>; 728 clocks = <&psc1 5>;
729 power-domains = <&psc1 729 power-domains = <&psc1 5>;
730 status = "disabled"; 730 status = "disabled";
731 }; 731 };
732 usb1: usb@225000 { 732 usb1: usb@225000 {
733 compatible = "ti,da830 733 compatible = "ti,da830-ohci";
734 reg = <0x225000 0x1000 734 reg = <0x225000 0x1000>;
735 interrupts = <59>; 735 interrupts = <59>;
736 phys = <&usb_phy 1>; 736 phys = <&usb_phy 1>;
737 phy-names = "usb-phy"; 737 phy-names = "usb-phy";
738 clocks = <&psc1 2>; 738 clocks = <&psc1 2>;
739 status = "disabled"; 739 status = "disabled";
740 }; 740 };
741 gpio: gpio@226000 { 741 gpio: gpio@226000 {
742 compatible = "ti,dm644 742 compatible = "ti,dm6441-gpio";
743 gpio-controller; 743 gpio-controller;
744 #gpio-cells = <2>; 744 #gpio-cells = <2>;
745 reg = <0x226000 0x1000 745 reg = <0x226000 0x1000>;
746 interrupts = <42>, <43 746 interrupts = <42>, <43>, <44>, <45>, <46>, <47>, <48>, <49>, <50>;
747 ti,ngpio = <144>; 747 ti,ngpio = <144>;
748 ti,davinci-gpio-unbank 748 ti,davinci-gpio-unbanked = <0>;
749 clocks = <&psc1 3>; 749 clocks = <&psc1 3>;
750 clock-names = "gpio"; 750 clock-names = "gpio";
751 status = "disabled"; 751 status = "disabled";
752 interrupt-controller; 752 interrupt-controller;
753 #interrupt-cells = <2> 753 #interrupt-cells = <2>;
754 gpio-ranges = <&pmx_co 754 gpio-ranges = <&pmx_core 0 15 1>,
755 <&pmx_co 755 <&pmx_core 1 14 1>,
756 <&pmx_co 756 <&pmx_core 2 13 1>,
757 <&pmx_co 757 <&pmx_core 3 12 1>,
758 <&pmx_co 758 <&pmx_core 4 11 1>,
759 <&pmx_co 759 <&pmx_core 5 10 1>,
760 <&pmx_co 760 <&pmx_core 6 9 1>,
761 <&pmx_co 761 <&pmx_core 7 8 1>,
762 <&pmx_co 762 <&pmx_core 8 7 1>,
763 <&pmx_co 763 <&pmx_core 9 6 1>,
764 <&pmx_co 764 <&pmx_core 10 5 1>,
765 <&pmx_co 765 <&pmx_core 11 4 1>,
766 <&pmx_co 766 <&pmx_core 12 3 1>,
767 <&pmx_co 767 <&pmx_core 13 2 1>,
768 <&pmx_co 768 <&pmx_core 14 1 1>,
769 <&pmx_co 769 <&pmx_core 15 0 1>,
770 <&pmx_co 770 <&pmx_core 16 39 1>,
771 <&pmx_co 771 <&pmx_core 17 38 1>,
772 <&pmx_co 772 <&pmx_core 18 37 1>,
773 <&pmx_co 773 <&pmx_core 19 36 1>,
774 <&pmx_co 774 <&pmx_core 20 35 1>,
775 <&pmx_co 775 <&pmx_core 21 34 1>,
776 <&pmx_co 776 <&pmx_core 22 33 1>,
777 <&pmx_co 777 <&pmx_core 23 32 1>,
778 <&pmx_co 778 <&pmx_core 24 24 1>,
779 <&pmx_co 779 <&pmx_core 25 22 1>,
780 <&pmx_co 780 <&pmx_core 26 21 1>,
781 <&pmx_co 781 <&pmx_core 27 20 1>,
782 <&pmx_co 782 <&pmx_core 28 19 1>,
783 <&pmx_co 783 <&pmx_core 29 18 1>,
784 <&pmx_co 784 <&pmx_core 30 17 1>,
785 <&pmx_co 785 <&pmx_core 31 16 1>,
786 <&pmx_co 786 <&pmx_core 32 55 1>,
787 <&pmx_co 787 <&pmx_core 33 54 1>,
788 <&pmx_co 788 <&pmx_core 34 53 1>,
789 <&pmx_co 789 <&pmx_core 35 52 1>,
790 <&pmx_co 790 <&pmx_core 36 51 1>,
791 <&pmx_co 791 <&pmx_core 37 50 1>,
792 <&pmx_co 792 <&pmx_core 38 49 1>,
793 <&pmx_co 793 <&pmx_core 39 48 1>,
794 <&pmx_co 794 <&pmx_core 40 47 1>,
795 <&pmx_co 795 <&pmx_core 41 46 1>,
796 <&pmx_co 796 <&pmx_core 42 45 1>,
797 <&pmx_co 797 <&pmx_core 43 44 1>,
798 <&pmx_co 798 <&pmx_core 44 43 1>,
799 <&pmx_co 799 <&pmx_core 45 42 1>,
800 <&pmx_co 800 <&pmx_core 46 41 1>,
801 <&pmx_co 801 <&pmx_core 47 40 1>,
802 <&pmx_co 802 <&pmx_core 48 71 1>,
803 <&pmx_co 803 <&pmx_core 49 70 1>,
804 <&pmx_co 804 <&pmx_core 50 69 1>,
805 <&pmx_co 805 <&pmx_core 51 68 1>,
806 <&pmx_co 806 <&pmx_core 52 67 1>,
807 <&pmx_co 807 <&pmx_core 53 66 1>,
808 <&pmx_co 808 <&pmx_core 54 65 1>,
809 <&pmx_co 809 <&pmx_core 55 64 1>,
810 <&pmx_co 810 <&pmx_core 56 63 1>,
811 <&pmx_co 811 <&pmx_core 57 62 1>,
812 <&pmx_co 812 <&pmx_core 58 61 1>,
813 <&pmx_co 813 <&pmx_core 59 60 1>,
814 <&pmx_co 814 <&pmx_core 60 59 1>,
815 <&pmx_co 815 <&pmx_core 61 58 1>,
816 <&pmx_co 816 <&pmx_core 62 57 1>,
817 <&pmx_co 817 <&pmx_core 63 56 1>,
818 <&pmx_co 818 <&pmx_core 64 87 1>,
819 <&pmx_co 819 <&pmx_core 65 86 1>,
820 <&pmx_co 820 <&pmx_core 66 85 1>,
821 <&pmx_co 821 <&pmx_core 67 84 1>,
822 <&pmx_co 822 <&pmx_core 68 83 1>,
823 <&pmx_co 823 <&pmx_core 69 82 1>,
824 <&pmx_co 824 <&pmx_core 70 81 1>,
825 <&pmx_co 825 <&pmx_core 71 80 1>,
826 <&pmx_co 826 <&pmx_core 72 70 1>,
827 <&pmx_co 827 <&pmx_core 73 78 1>,
828 <&pmx_co 828 <&pmx_core 74 77 1>,
829 <&pmx_co 829 <&pmx_core 75 76 1>,
830 <&pmx_co 830 <&pmx_core 76 75 1>,
831 <&pmx_co 831 <&pmx_core 77 74 1>,
832 <&pmx_co 832 <&pmx_core 78 73 1>,
833 <&pmx_co 833 <&pmx_core 79 72 1>,
834 <&pmx_co 834 <&pmx_core 80 103 1>,
835 <&pmx_co 835 <&pmx_core 81 102 1>,
836 <&pmx_co 836 <&pmx_core 82 101 1>,
837 <&pmx_co 837 <&pmx_core 83 100 1>,
838 <&pmx_co 838 <&pmx_core 84 99 1>,
839 <&pmx_co 839 <&pmx_core 85 98 1>,
840 <&pmx_co 840 <&pmx_core 86 97 1>,
841 <&pmx_co 841 <&pmx_core 87 96 1>,
842 <&pmx_co 842 <&pmx_core 88 95 1>,
843 <&pmx_co 843 <&pmx_core 89 94 1>,
844 <&pmx_co 844 <&pmx_core 90 93 1>,
845 <&pmx_co 845 <&pmx_core 91 92 1>,
846 <&pmx_co 846 <&pmx_core 92 91 1>,
847 <&pmx_co 847 <&pmx_core 93 90 1>,
848 <&pmx_co 848 <&pmx_core 94 89 1>,
849 <&pmx_co 849 <&pmx_core 95 88 1>,
850 <&pmx_co 850 <&pmx_core 96 158 1>,
851 <&pmx_co 851 <&pmx_core 97 157 1>,
852 <&pmx_co 852 <&pmx_core 98 156 1>,
853 <&pmx_co 853 <&pmx_core 99 155 1>,
854 <&pmx_co 854 <&pmx_core 100 154 1>,
855 <&pmx_co 855 <&pmx_core 101 129 1>,
856 <&pmx_co 856 <&pmx_core 102 113 1>,
857 <&pmx_co 857 <&pmx_core 103 112 1>,
858 <&pmx_co 858 <&pmx_core 104 111 1>,
859 <&pmx_co 859 <&pmx_core 105 110 1>,
860 <&pmx_co 860 <&pmx_core 106 109 1>,
861 <&pmx_co 861 <&pmx_core 107 108 1>,
862 <&pmx_co 862 <&pmx_core 108 107 1>,
863 <&pmx_co 863 <&pmx_core 109 106 1>,
864 <&pmx_co 864 <&pmx_core 110 105 1>,
865 <&pmx_co 865 <&pmx_core 111 104 1>,
866 <&pmx_co 866 <&pmx_core 112 145 1>,
867 <&pmx_co 867 <&pmx_core 113 144 1>,
868 <&pmx_co 868 <&pmx_core 114 143 1>,
869 <&pmx_co 869 <&pmx_core 115 142 1>,
870 <&pmx_co 870 <&pmx_core 116 141 1>,
871 <&pmx_co 871 <&pmx_core 117 140 1>,
872 <&pmx_co 872 <&pmx_core 118 139 1>,
873 <&pmx_co 873 <&pmx_core 119 138 1>,
874 <&pmx_co 874 <&pmx_core 120 137 1>,
875 <&pmx_co 875 <&pmx_core 121 136 1>,
876 <&pmx_co 876 <&pmx_core 122 135 1>,
877 <&pmx_co 877 <&pmx_core 123 134 1>,
878 <&pmx_co 878 <&pmx_core 124 133 1>,
879 <&pmx_co 879 <&pmx_core 125 132 1>,
880 <&pmx_co 880 <&pmx_core 126 131 1>,
881 <&pmx_co 881 <&pmx_core 127 130 1>,
882 <&pmx_co 882 <&pmx_core 128 159 1>,
883 <&pmx_co 883 <&pmx_core 129 31 1>,
884 <&pmx_co 884 <&pmx_core 130 30 1>,
885 <&pmx_co 885 <&pmx_core 131 20 1>,
886 <&pmx_co 886 <&pmx_core 132 28 1>,
887 <&pmx_co 887 <&pmx_core 133 27 1>,
888 <&pmx_co 888 <&pmx_core 134 26 1>,
889 <&pmx_co 889 <&pmx_core 135 23 1>,
890 <&pmx_co 890 <&pmx_core 136 153 1>,
891 <&pmx_co 891 <&pmx_core 137 152 1>,
892 <&pmx_co 892 <&pmx_core 138 151 1>,
893 <&pmx_co 893 <&pmx_core 139 150 1>,
894 <&pmx_co 894 <&pmx_core 140 149 1>,
895 <&pmx_co 895 <&pmx_core 141 148 1>,
896 <&pmx_co 896 <&pmx_core 142 147 1>,
897 <&pmx_co 897 <&pmx_core 143 146 1>;
898 }; 898 };
899 psc1: clock-controller@227000 899 psc1: clock-controller@227000 {
900 compatible = "ti,da850 900 compatible = "ti,da850-psc1";
901 reg = <0x227000 0x1000 901 reg = <0x227000 0x1000>;
902 #clock-cells = <1>; 902 #clock-cells = <1>;
903 #power-domain-cells = 903 #power-domain-cells = <1>;
904 clocks = <&pll0_sysclk 904 clocks = <&pll0_sysclk 2>, <&pll0_sysclk 4>,
905 <&async3_clk> 905 <&async3_clk>;
906 clock-names = "pll0_sy 906 clock-names = "pll0_sysclk2", "pll0_sysclk4", "async3";
907 assigned-clocks = <&as 907 assigned-clocks = <&async3_clk>;
908 assigned-clock-parents 908 assigned-clock-parents = <&pll1_sysclk 2>;
909 }; 909 };
910 pinconf: pin-controller@22c00c 910 pinconf: pin-controller@22c00c {
911 compatible = "ti,da850 911 compatible = "ti,da850-pupd";
912 reg = <0x22c00c 0x8>; 912 reg = <0x22c00c 0x8>;
913 status = "disabled"; 913 status = "disabled";
914 }; 914 };
915 915
916 mcasp0: mcasp@100000 { 916 mcasp0: mcasp@100000 {
917 compatible = "ti,da830 917 compatible = "ti,da830-mcasp-audio";
918 reg = <0x100000 0x2000 918 reg = <0x100000 0x2000>,
919 <0x102000 0x4000 919 <0x102000 0x400000>;
920 reg-names = "mpu", "da 920 reg-names = "mpu", "dat";
921 interrupts = <54>; 921 interrupts = <54>;
922 interrupt-names = "com 922 interrupt-names = "common";
923 power-domains = <&psc1 923 power-domains = <&psc1 7>;
924 status = "disabled"; 924 status = "disabled";
925 dmas = <&edma0 1 1>, 925 dmas = <&edma0 1 1>,
926 <&edma0 0 1>; 926 <&edma0 0 1>;
927 dma-names = "tx", "rx" 927 dma-names = "tx", "rx";
928 }; 928 };
929 929
930 lcdc: display@213000 { 930 lcdc: display@213000 {
931 compatible = "ti,da850 931 compatible = "ti,da850-tilcdc";
932 reg = <0x213000 0x1000 932 reg = <0x213000 0x1000>;
933 interrupts = <52>; 933 interrupts = <52>;
934 max-pixelclock = <3750 934 max-pixelclock = <37500>;
935 clocks = <&psc1 16>; 935 clocks = <&psc1 16>;
936 clock-names = "fck"; 936 clock-names = "fck";
937 power-domains = <&psc1 937 power-domains = <&psc1 16>;
938 status = "disabled"; 938 status = "disabled";
939 }; 939 };
940 }; 940 };
941 aemif: aemif@68000000 { 941 aemif: aemif@68000000 {
942 compatible = "ti,da850-aemif"; 942 compatible = "ti,da850-aemif";
943 #address-cells = <2>; 943 #address-cells = <2>;
944 #size-cells = <1>; 944 #size-cells = <1>;
945 945
946 reg = <0x68000000 0x00008000>; 946 reg = <0x68000000 0x00008000>;
947 ranges = <0 0 0x60000000 0x080 947 ranges = <0 0 0x60000000 0x08000000
948 1 0 0x68000000 0x000 948 1 0 0x68000000 0x00008000>;
949 clocks = <&psc0 3>; 949 clocks = <&psc0 3>;
950 clock-names = "aemif"; 950 clock-names = "aemif";
951 clock-ranges; 951 clock-ranges;
952 status = "disabled"; 952 status = "disabled";
953 }; 953 };
954 memctrl: memory-controller@b0000000 { 954 memctrl: memory-controller@b0000000 {
955 compatible = "ti,da850-ddr-con 955 compatible = "ti,da850-ddr-controller";
956 reg = <0xb0000000 0xe8>; 956 reg = <0xb0000000 0xe8>;
957 status = "disabled"; 957 status = "disabled";
958 }; 958 };
959 }; 959 };
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