1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * Device Tree Source for AM33XX SoC 3 * Device Tree Source for AM33XX SoC
4 * 4 *
5 * Copyright (C) 2012 Texas Instruments Incorp 5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
6 */ 6 */
7 7
8 #include <dt-bindings/bus/ti-sysc.h> 8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/pinctrl/am33xx.h> 10 #include <dt-bindings/pinctrl/am33xx.h>
11 #include <dt-bindings/clock/am3.h> 11 #include <dt-bindings/clock/am3.h>
12 12
13 / { 13 / {
14 compatible = "ti,am33xx"; 14 compatible = "ti,am33xx";
15 interrupt-parent = <&intc>; 15 interrupt-parent = <&intc>;
16 #address-cells = <1>; 16 #address-cells = <1>;
17 #size-cells = <1>; 17 #size-cells = <1>;
18 chosen { }; 18 chosen { };
19 19
20 aliases { 20 aliases {
21 i2c0 = &i2c0; 21 i2c0 = &i2c0;
22 i2c1 = &i2c1; 22 i2c1 = &i2c1;
23 i2c2 = &i2c2; 23 i2c2 = &i2c2;
24 serial0 = &uart0; 24 serial0 = &uart0;
25 serial1 = &uart1; 25 serial1 = &uart1;
26 serial2 = &uart2; 26 serial2 = &uart2;
27 serial3 = &uart3; 27 serial3 = &uart3;
28 serial4 = &uart4; 28 serial4 = &uart4;
29 serial5 = &uart5; 29 serial5 = &uart5;
30 d-can0 = &dcan0; 30 d-can0 = &dcan0;
31 d-can1 = &dcan1; 31 d-can1 = &dcan1;
32 usb0 = &usb0; 32 usb0 = &usb0;
33 usb1 = &usb1; 33 usb1 = &usb1;
34 phy0 = &usb0_phy; 34 phy0 = &usb0_phy;
35 phy1 = &usb1_phy; 35 phy1 = &usb1_phy;
36 ethernet0 = &cpsw_port1; 36 ethernet0 = &cpsw_port1;
37 ethernet1 = &cpsw_port2; 37 ethernet1 = &cpsw_port2;
38 spi0 = &spi0; 38 spi0 = &spi0;
39 spi1 = &spi1; 39 spi1 = &spi1;
40 mmc0 = &mmc1; 40 mmc0 = &mmc1;
41 mmc1 = &mmc2; 41 mmc1 = &mmc2;
42 mmc2 = &mmc3; 42 mmc2 = &mmc3;
43 }; 43 };
44 44
45 cpus { 45 cpus {
46 #address-cells = <1>; 46 #address-cells = <1>;
47 #size-cells = <0>; 47 #size-cells = <0>;
48 cpu@0 { 48 cpu@0 {
49 compatible = "arm,cort 49 compatible = "arm,cortex-a8";
50 enable-method = "ti,am 50 enable-method = "ti,am3352";
51 device_type = "cpu"; 51 device_type = "cpu";
52 reg = <0>; 52 reg = <0>;
53 53
54 operating-points-v2 = 54 operating-points-v2 = <&cpu0_opp_table>;
55 55
56 clocks = <&dpll_mpu_ck 56 clocks = <&dpll_mpu_ck>;
57 clock-names = "cpu"; 57 clock-names = "cpu";
58 58
59 clock-latency = <30000 59 clock-latency = <300000>; /* From omap-cpufreq driver */
60 cpu-idle-states = <&mp 60 cpu-idle-states = <&mpu_gate>;
61 }; 61 };
62 62
63 idle-states { 63 idle-states {
64 mpu_gate: mpu_gate { 64 mpu_gate: mpu_gate {
65 compatible = " 65 compatible = "arm,idle-state";
66 entry-latency- 66 entry-latency-us = <40>;
67 exit-latency-u 67 exit-latency-us = <90>;
68 min-residency- 68 min-residency-us = <300>;
69 ti,idle-wkup-m 69 ti,idle-wkup-m3;
70 }; 70 };
71 }; 71 };
72 }; 72 };
73 73
74 cpu0_opp_table: opp-table { 74 cpu0_opp_table: opp-table {
75 compatible = "operating-points 75 compatible = "operating-points-v2-ti-cpu";
76 syscon = <&scm_conf>; 76 syscon = <&scm_conf>;
77 77
78 /* 78 /*
79 * The three following nodes a 79 * The three following nodes are marked with opp-suspend
80 * because the can not be enab 80 * because the can not be enabled simultaneously on a
81 * single SoC. 81 * single SoC.
82 */ 82 */
83 opp-50-300000000 { 83 opp-50-300000000 {
84 /* OPP50 */ 84 /* OPP50 */
85 opp-hz = /bits/ 64 <30 85 opp-hz = /bits/ 64 <300000000>;
86 opp-microvolt = <95000 86 opp-microvolt = <950000 931000 969000>;
87 opp-supported-hw = <0x 87 opp-supported-hw = <0x06 0x0010>;
88 opp-suspend; 88 opp-suspend;
89 }; 89 };
90 90
91 opp-100-275000000 { 91 opp-100-275000000 {
92 /* OPP100-1 */ 92 /* OPP100-1 */
93 opp-hz = /bits/ 64 <27 93 opp-hz = /bits/ 64 <275000000>;
94 opp-microvolt = <11000 94 opp-microvolt = <1100000 1078000 1122000>;
95 opp-supported-hw = <0x 95 opp-supported-hw = <0x01 0x00FF>;
96 opp-suspend; 96 opp-suspend;
97 }; 97 };
98 98
99 opp-100-300000000 { 99 opp-100-300000000 {
100 /* OPP100-2 */ 100 /* OPP100-2 */
101 opp-hz = /bits/ 64 <30 101 opp-hz = /bits/ 64 <300000000>;
102 opp-microvolt = <11000 102 opp-microvolt = <1100000 1078000 1122000>;
103 opp-supported-hw = <0x 103 opp-supported-hw = <0x06 0x0020>;
104 opp-suspend; 104 opp-suspend;
105 }; 105 };
106 106
107 opp-100-500000000 { 107 opp-100-500000000 {
108 /* OPP100-3 */ 108 /* OPP100-3 */
109 opp-hz = /bits/ 64 <50 109 opp-hz = /bits/ 64 <500000000>;
110 opp-microvolt = <11000 110 opp-microvolt = <1100000 1078000 1122000>;
111 opp-supported-hw = <0x 111 opp-supported-hw = <0x01 0xFFFF>;
112 }; 112 };
113 113
114 opp-100-600000000 { 114 opp-100-600000000 {
115 /* OPP100-4 */ 115 /* OPP100-4 */
116 opp-hz = /bits/ 64 <60 116 opp-hz = /bits/ 64 <600000000>;
117 opp-microvolt = <11000 117 opp-microvolt = <1100000 1078000 1122000>;
118 opp-supported-hw = <0x 118 opp-supported-hw = <0x06 0x0040>;
119 }; 119 };
120 120
121 opp-120-600000000 { 121 opp-120-600000000 {
122 /* OPP120-1 */ 122 /* OPP120-1 */
123 opp-hz = /bits/ 64 <60 123 opp-hz = /bits/ 64 <600000000>;
124 opp-microvolt = <12000 124 opp-microvolt = <1200000 1176000 1224000>;
125 opp-supported-hw = <0x 125 opp-supported-hw = <0x01 0xFFFF>;
126 }; 126 };
127 127
128 opp-120-720000000 { 128 opp-120-720000000 {
129 /* OPP120-2 */ 129 /* OPP120-2 */
130 opp-hz = /bits/ 64 <72 130 opp-hz = /bits/ 64 <720000000>;
131 opp-microvolt = <12000 131 opp-microvolt = <1200000 1176000 1224000>;
132 opp-supported-hw = <0x 132 opp-supported-hw = <0x06 0x0080>;
133 }; 133 };
134 134
135 opp-720000000 { 135 opp-720000000 {
136 /* OPP Turbo-1 */ 136 /* OPP Turbo-1 */
137 opp-hz = /bits/ 64 <72 137 opp-hz = /bits/ 64 <720000000>;
138 opp-microvolt = <12600 138 opp-microvolt = <1260000 1234800 1285200>;
139 opp-supported-hw = <0x 139 opp-supported-hw = <0x01 0xFFFF>;
140 }; 140 };
141 141
142 opp-800000000 { 142 opp-800000000 {
143 /* OPP Turbo-2 */ 143 /* OPP Turbo-2 */
144 opp-hz = /bits/ 64 <80 144 opp-hz = /bits/ 64 <800000000>;
145 opp-microvolt = <12600 145 opp-microvolt = <1260000 1234800 1285200>;
146 opp-supported-hw = <0x 146 opp-supported-hw = <0x06 0x0100>;
147 }; 147 };
148 148
149 opp-1000000000 { 149 opp-1000000000 {
150 /* OPP Nitro */ 150 /* OPP Nitro */
151 opp-hz = /bits/ 64 <10 151 opp-hz = /bits/ 64 <1000000000>;
152 opp-microvolt = <13250 152 opp-microvolt = <1325000 1298500 1351500>;
153 opp-supported-hw = <0x 153 opp-supported-hw = <0x04 0x0200>;
154 }; 154 };
155 }; 155 };
156 156
157 target-module@4b000000 { 157 target-module@4b000000 {
158 compatible = "ti,sysc-omap4-si 158 compatible = "ti,sysc-omap4-simple", "ti,sysc";
159 clocks = <&l3_clkctrl AM3_L3_L 159 clocks = <&l3_clkctrl AM3_L3_L3_INSTR_CLKCTRL 0>;
160 clock-names = "fck"; 160 clock-names = "fck";
161 ti,no-idle; 161 ti,no-idle;
162 #address-cells = <1>; 162 #address-cells = <1>;
163 #size-cells = <1>; 163 #size-cells = <1>;
164 ranges = <0x0 0x4b000000 0x100 164 ranges = <0x0 0x4b000000 0x1000000>;
165 165
166 target-module@140000 { 166 target-module@140000 {
167 compatible = "ti,sysc- 167 compatible = "ti,sysc-omap4-simple", "ti,sysc";
168 clocks = <&l3_aon_clkc 168 clocks = <&l3_aon_clkctrl AM3_L3_AON_DEBUGSS_CLKCTRL 0>;
169 clock-names = "fck"; 169 clock-names = "fck";
170 #address-cells = <1>; 170 #address-cells = <1>;
171 #size-cells = <1>; 171 #size-cells = <1>;
172 ranges = <0x0 0x140000 172 ranges = <0x0 0x140000 0xec0000>;
173 173
174 pmu@0 { 174 pmu@0 {
175 compatible = " 175 compatible = "arm,cortex-a8-pmu";
176 interrupts = < 176 interrupts = <3>;
177 }; 177 };
178 }; 178 };
179 }; 179 };
180 180
181 /* 181 /*
182 * The soc node represents the soc top 182 * The soc node represents the soc top level view. It is used for IPs
183 * that are not memory mapped in the M 183 * that are not memory mapped in the MPU view or for the MPU itself.
184 */ 184 */
185 soc { 185 soc {
186 compatible = "ti,omap-infra"; 186 compatible = "ti,omap-infra";
187 }; 187 };
188 188
189 /* 189 /*
190 * XXX: Use a flat representation of t 190 * XXX: Use a flat representation of the AM33XX interconnect.
191 * The real AM33XX interconnect networ 191 * The real AM33XX interconnect network is quite complex. Since
192 * it will not bring real advantage to 192 * it will not bring real advantage to represent that in DT
193 * for the moment, just use a fake OCP 193 * for the moment, just use a fake OCP bus entry to represent
194 * the whole bus hierarchy. 194 * the whole bus hierarchy.
195 */ 195 */
196 ocp: ocp { 196 ocp: ocp {
197 compatible = "simple-pm-bus"; 197 compatible = "simple-pm-bus";
198 power-domains = <&prm_per>; 198 power-domains = <&prm_per>;
199 clocks = <&l3_clkctrl AM3_L3_L 199 clocks = <&l3_clkctrl AM3_L3_L3_MAIN_CLKCTRL 0>;
200 clock-names = "fck"; 200 clock-names = "fck";
201 #address-cells = <1>; 201 #address-cells = <1>;
202 #size-cells = <1>; 202 #size-cells = <1>;
203 ranges; 203 ranges;
204 204
205 l4_wkup: interconnect@44c00000 205 l4_wkup: interconnect@44c00000 {
206 }; 206 };
207 l4_per: interconnect@48000000 207 l4_per: interconnect@48000000 {
208 }; 208 };
209 l4_fw: interconnect@47c00000 { 209 l4_fw: interconnect@47c00000 {
210 }; 210 };
211 l4_fast: interconnect@4a000000 211 l4_fast: interconnect@4a000000 {
212 }; 212 };
213 l4_mpuss: interconnect@4b14000 213 l4_mpuss: interconnect@4b140000 {
214 }; 214 };
215 215
216 intc: interrupt-controller@482 216 intc: interrupt-controller@48200000 {
217 compatible = "ti,am33x 217 compatible = "ti,am33xx-intc";
218 interrupt-controller; 218 interrupt-controller;
219 #interrupt-cells = <1> 219 #interrupt-cells = <1>;
220 reg = <0x48200000 0x10 220 reg = <0x48200000 0x1000>;
221 }; 221 };
222 222
223 target-module@49000000 { 223 target-module@49000000 {
224 compatible = "ti,sysc- 224 compatible = "ti,sysc-omap4", "ti,sysc";
225 reg = <0x49000000 0x4> 225 reg = <0x49000000 0x4>;
226 reg-names = "rev"; 226 reg-names = "rev";
227 clocks = <&l3_clkctrl 227 clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>;
228 clock-names = "fck"; 228 clock-names = "fck";
229 #address-cells = <1>; 229 #address-cells = <1>;
230 #size-cells = <1>; 230 #size-cells = <1>;
231 ranges = <0x0 0x490000 231 ranges = <0x0 0x49000000 0x10000>;
232 232
233 edma: dma@0 { 233 edma: dma@0 {
234 compatible = " 234 compatible = "ti,edma3-tpcc";
235 reg = <0 0x100 235 reg = <0 0x10000>;
236 reg-names = "e 236 reg-names = "edma3_cc";
237 interrupts = < 237 interrupts = <12 13 14>;
238 interrupt-name 238 interrupt-names = "edma3_ccint", "edma3_mperr",
239 239 "edma3_ccerrint";
240 dma-requests = 240 dma-requests = <64>;
241 #dma-cells = < 241 #dma-cells = <2>;
242 242
243 ti,tptcs = <&e 243 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
244 <&e 244 <&edma_tptc2 0>;
245 245
246 ti,edma-memcpy 246 ti,edma-memcpy-channels = <20 21>;
247 }; 247 };
248 }; 248 };
249 249
250 target-module@49800000 { 250 target-module@49800000 {
251 compatible = "ti,sysc- 251 compatible = "ti,sysc-omap4", "ti,sysc";
252 reg = <0x49800000 0x4> 252 reg = <0x49800000 0x4>,
253 <0x49800010 0x4> 253 <0x49800010 0x4>;
254 reg-names = "rev", "sy 254 reg-names = "rev", "sysc";
255 ti,sysc-mask = <SYSC_O 255 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
256 ti,sysc-midle = <SYSC_ 256 ti,sysc-midle = <SYSC_IDLE_FORCE>;
257 ti,sysc-sidle = <SYSC_ 257 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
258 <SYSC_ 258 <SYSC_IDLE_SMART>;
259 clocks = <&l3_clkctrl 259 clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>;
260 clock-names = "fck"; 260 clock-names = "fck";
261 #address-cells = <1>; 261 #address-cells = <1>;
262 #size-cells = <1>; 262 #size-cells = <1>;
263 ranges = <0x0 0x498000 263 ranges = <0x0 0x49800000 0x100000>;
264 264
265 edma_tptc0: dma@0 { 265 edma_tptc0: dma@0 {
266 compatible = " 266 compatible = "ti,edma3-tptc";
267 reg = <0 0x100 267 reg = <0 0x100000>;
268 interrupts = < 268 interrupts = <112>;
269 interrupt-name 269 interrupt-names = "edma3_tcerrint";
270 }; 270 };
271 }; 271 };
272 272
273 target-module@49900000 { 273 target-module@49900000 {
274 compatible = "ti,sysc- 274 compatible = "ti,sysc-omap4", "ti,sysc";
275 reg = <0x49900000 0x4> 275 reg = <0x49900000 0x4>,
276 <0x49900010 0x4> 276 <0x49900010 0x4>;
277 reg-names = "rev", "sy 277 reg-names = "rev", "sysc";
278 ti,sysc-mask = <SYSC_O 278 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
279 ti,sysc-midle = <SYSC_ 279 ti,sysc-midle = <SYSC_IDLE_FORCE>;
280 ti,sysc-sidle = <SYSC_ 280 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
281 <SYSC_ 281 <SYSC_IDLE_SMART>;
282 clocks = <&l3_clkctrl 282 clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>;
283 clock-names = "fck"; 283 clock-names = "fck";
284 #address-cells = <1>; 284 #address-cells = <1>;
285 #size-cells = <1>; 285 #size-cells = <1>;
286 ranges = <0x0 0x499000 286 ranges = <0x0 0x49900000 0x100000>;
287 287
288 edma_tptc1: dma@0 { 288 edma_tptc1: dma@0 {
289 compatible = " 289 compatible = "ti,edma3-tptc";
290 reg = <0 0x100 290 reg = <0 0x100000>;
291 interrupts = < 291 interrupts = <113>;
292 interrupt-name 292 interrupt-names = "edma3_tcerrint";
293 }; 293 };
294 }; 294 };
295 295
296 target-module@49a00000 { 296 target-module@49a00000 {
297 compatible = "ti,sysc- 297 compatible = "ti,sysc-omap4", "ti,sysc";
298 reg = <0x49a00000 0x4> 298 reg = <0x49a00000 0x4>,
299 <0x49a00010 0x4> 299 <0x49a00010 0x4>;
300 reg-names = "rev", "sy 300 reg-names = "rev", "sysc";
301 ti,sysc-mask = <SYSC_O 301 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
302 ti,sysc-midle = <SYSC_ 302 ti,sysc-midle = <SYSC_IDLE_FORCE>;
303 ti,sysc-sidle = <SYSC_ 303 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
304 <SYSC_ 304 <SYSC_IDLE_SMART>;
305 clocks = <&l3_clkctrl 305 clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>;
306 clock-names = "fck"; 306 clock-names = "fck";
307 #address-cells = <1>; 307 #address-cells = <1>;
308 #size-cells = <1>; 308 #size-cells = <1>;
309 ranges = <0x0 0x49a000 309 ranges = <0x0 0x49a00000 0x100000>;
310 310
311 edma_tptc2: dma@0 { 311 edma_tptc2: dma@0 {
312 compatible = " 312 compatible = "ti,edma3-tptc";
313 reg = <0 0x100 313 reg = <0 0x100000>;
314 interrupts = < 314 interrupts = <114>;
315 interrupt-name 315 interrupt-names = "edma3_tcerrint";
316 }; 316 };
317 }; 317 };
318 318
319 target-module@47810000 { 319 target-module@47810000 {
320 compatible = "ti,sysc- 320 compatible = "ti,sysc-omap2", "ti,sysc";
321 reg = <0x478102fc 0x4> 321 reg = <0x478102fc 0x4>,
322 <0x47810110 0x4> 322 <0x47810110 0x4>,
323 <0x47810114 0x4> 323 <0x47810114 0x4>;
324 reg-names = "rev", "sy 324 reg-names = "rev", "sysc", "syss";
325 ti,sysc-mask = <(SYSC_ 325 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
326 SYSC_ 326 SYSC_OMAP2_ENAWAKEUP |
327 SYSC_ 327 SYSC_OMAP2_SOFTRESET |
328 SYSC_ 328 SYSC_OMAP2_AUTOIDLE)>;
329 ti,sysc-sidle = <SYSC_ 329 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
330 <SYSC_ 330 <SYSC_IDLE_NO>,
331 <SYSC_ 331 <SYSC_IDLE_SMART>;
332 ti,syss-mask = <1>; 332 ti,syss-mask = <1>;
333 clocks = <&l3s_clkctrl 333 clocks = <&l3s_clkctrl AM3_L3S_MMC3_CLKCTRL 0>;
334 clock-names = "fck"; 334 clock-names = "fck";
335 #address-cells = <1>; 335 #address-cells = <1>;
336 #size-cells = <1>; 336 #size-cells = <1>;
337 ranges = <0x0 0x478100 337 ranges = <0x0 0x47810000 0x1000>;
338 338
339 mmc3: mmc@0 { 339 mmc3: mmc@0 {
340 compatible = " 340 compatible = "ti,am335-sdhci";
341 ti,needs-speci 341 ti,needs-special-reset;
342 interrupts = < 342 interrupts = <29>;
343 reg = <0x0 0x1 343 reg = <0x0 0x1000>;
344 status = "disa 344 status = "disabled";
345 }; 345 };
346 }; 346 };
347 347
348 usb: target-module@47400000 { 348 usb: target-module@47400000 {
349 compatible = "ti,sysc- 349 compatible = "ti,sysc-omap4", "ti,sysc";
350 reg = <0x47400000 0x4> 350 reg = <0x47400000 0x4>,
351 <0x47400010 0x4> 351 <0x47400010 0x4>;
352 reg-names = "rev", "sy 352 reg-names = "rev", "sysc";
353 ti,sysc-mask = <(SYSC_ 353 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
354 SYSC_ 354 SYSC_OMAP4_SOFTRESET)>;
355 ti,sysc-midle = <SYSC_ 355 ti,sysc-midle = <SYSC_IDLE_FORCE>,
356 <SYSC_ 356 <SYSC_IDLE_NO>,
357 <SYSC_ 357 <SYSC_IDLE_SMART>;
358 ti,sysc-sidle = <SYSC_ 358 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
359 <SYSC_ 359 <SYSC_IDLE_NO>,
360 <SYSC_ 360 <SYSC_IDLE_SMART>,
361 <SYSC_ 361 <SYSC_IDLE_SMART_WKUP>;
362 ti,sysc-delay-us = <2> 362 ti,sysc-delay-us = <2>;
363 clocks = <&l3s_clkctrl 363 clocks = <&l3s_clkctrl AM3_L3S_USB_OTG_HS_CLKCTRL 0>;
364 clock-names = "fck"; 364 clock-names = "fck";
365 #address-cells = <1>; 365 #address-cells = <1>;
366 #size-cells = <1>; 366 #size-cells = <1>;
367 ranges = <0x0 0x474000 367 ranges = <0x0 0x47400000 0x8000>;
368 368
369 usb0_phy: usb-phy@1300 369 usb0_phy: usb-phy@1300 {
370 compatible = " 370 compatible = "ti,am335x-usb-phy";
371 reg = <0x1300 371 reg = <0x1300 0x100>;
372 reg-names = "p 372 reg-names = "phy";
373 ti,ctrl_mod = 373 ti,ctrl_mod = <&usb_ctrl_mod>;
374 #phy-cells = < 374 #phy-cells = <0>;
375 }; 375 };
376 376
377 usb0: usb@1400 { 377 usb0: usb@1400 {
378 compatible = " 378 compatible = "ti,musb-am33xx";
379 reg = <0x1400 379 reg = <0x1400 0x400>,
380 <0x1000 380 <0x1000 0x200>;
381 reg-names = "m 381 reg-names = "mc", "control";
382 382
383 interrupts = < 383 interrupts = <18>;
384 interrupt-name 384 interrupt-names = "mc";
385 dr_mode = "otg 385 dr_mode = "otg";
386 mentor,multipo 386 mentor,multipoint = <1>;
387 mentor,num-eps 387 mentor,num-eps = <16>;
388 mentor,ram-bit 388 mentor,ram-bits = <12>;
389 mentor,power = 389 mentor,power = <500>;
390 phys = <&usb0_ 390 phys = <&usb0_phy>;
391 391
392 dmas = <&cppi4 392 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
393 &cppi4 393 &cppi41dma 2 0 &cppi41dma 3 0
394 &cppi4 394 &cppi41dma 4 0 &cppi41dma 5 0
395 &cppi4 395 &cppi41dma 6 0 &cppi41dma 7 0
396 &cppi4 396 &cppi41dma 8 0 &cppi41dma 9 0
397 &cppi4 397 &cppi41dma 10 0 &cppi41dma 11 0
398 &cppi4 398 &cppi41dma 12 0 &cppi41dma 13 0
399 &cppi4 399 &cppi41dma 14 0 &cppi41dma 0 1
400 &cppi4 400 &cppi41dma 1 1 &cppi41dma 2 1
401 &cppi4 401 &cppi41dma 3 1 &cppi41dma 4 1
402 &cppi4 402 &cppi41dma 5 1 &cppi41dma 6 1
403 &cppi4 403 &cppi41dma 7 1 &cppi41dma 8 1
404 &cppi4 404 &cppi41dma 9 1 &cppi41dma 10 1
405 &cppi4 405 &cppi41dma 11 1 &cppi41dma 12 1
406 &cppi4 406 &cppi41dma 13 1 &cppi41dma 14 1>;
407 dma-names = 407 dma-names =
408 "rx1", 408 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
409 "rx8", 409 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
410 "rx14" 410 "rx14", "rx15",
411 "tx1", 411 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
412 "tx8", 412 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
413 "tx14" 413 "tx14", "tx15";
414 }; 414 };
415 415
416 usb1_phy: usb-phy@1b00 416 usb1_phy: usb-phy@1b00 {
417 compatible = " 417 compatible = "ti,am335x-usb-phy";
418 reg = <0x1b00 418 reg = <0x1b00 0x100>;
419 reg-names = "p 419 reg-names = "phy";
420 ti,ctrl_mod = 420 ti,ctrl_mod = <&usb_ctrl_mod>;
421 #phy-cells = < 421 #phy-cells = <0>;
422 }; 422 };
423 423
424 usb1: usb@1800 { 424 usb1: usb@1800 {
425 compatible = " 425 compatible = "ti,musb-am33xx";
426 reg = <0x1c00 426 reg = <0x1c00 0x400>,
427 <0x1800 427 <0x1800 0x200>;
428 reg-names = "m 428 reg-names = "mc", "control";
429 interrupts = < 429 interrupts = <19>;
430 interrupt-name 430 interrupt-names = "mc";
431 dr_mode = "otg 431 dr_mode = "otg";
432 mentor,multipo 432 mentor,multipoint = <1>;
433 mentor,num-eps 433 mentor,num-eps = <16>;
434 mentor,ram-bit 434 mentor,ram-bits = <12>;
435 mentor,power = 435 mentor,power = <500>;
436 phys = <&usb1_ 436 phys = <&usb1_phy>;
437 437
438 dmas = <&cppi4 438 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
439 &cppi4 439 &cppi41dma 17 0 &cppi41dma 18 0
440 &cppi4 440 &cppi41dma 19 0 &cppi41dma 20 0
441 &cppi4 441 &cppi41dma 21 0 &cppi41dma 22 0
442 &cppi4 442 &cppi41dma 23 0 &cppi41dma 24 0
443 &cppi4 443 &cppi41dma 25 0 &cppi41dma 26 0
444 &cppi4 444 &cppi41dma 27 0 &cppi41dma 28 0
445 &cppi4 445 &cppi41dma 29 0 &cppi41dma 15 1
446 &cppi4 446 &cppi41dma 16 1 &cppi41dma 17 1
447 &cppi4 447 &cppi41dma 18 1 &cppi41dma 19 1
448 &cppi4 448 &cppi41dma 20 1 &cppi41dma 21 1
449 &cppi4 449 &cppi41dma 22 1 &cppi41dma 23 1
450 &cppi4 450 &cppi41dma 24 1 &cppi41dma 25 1
451 &cppi4 451 &cppi41dma 26 1 &cppi41dma 27 1
452 &cppi4 452 &cppi41dma 28 1 &cppi41dma 29 1>;
453 dma-names = 453 dma-names =
454 "rx1", 454 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
455 "rx8", 455 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
456 "rx14" 456 "rx14", "rx15",
457 "tx1", 457 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
458 "tx8", 458 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
459 "tx14" 459 "tx14", "tx15";
460 }; 460 };
461 461
462 cppi41dma: dma-control 462 cppi41dma: dma-controller@2000 {
463 compatible = " 463 compatible = "ti,am3359-cppi41";
464 reg = <0x0000 464 reg = <0x0000 0x1000>,
465 <0x2000 465 <0x2000 0x1000>,
466 <0x3000 466 <0x3000 0x1000>,
467 <0x4000 467 <0x4000 0x4000>;
468 reg-names = "g 468 reg-names = "glue", "controller", "scheduler", "queuemgr";
469 interrupts = < 469 interrupts = <17>;
470 interrupt-name 470 interrupt-names = "glue";
471 #dma-cells = < 471 #dma-cells = <2>;
472 /* For backwar 472 /* For backwards compatibility: */
473 #dma-channels 473 #dma-channels = <30>;
474 dma-channels = 474 dma-channels = <30>;
475 #dma-requests 475 #dma-requests = <256>;
476 dma-requests = 476 dma-requests = <256>;
477 }; 477 };
478 }; 478 };
479 479
480 target-module@40300000 { 480 target-module@40300000 {
481 compatible = "ti,sysc- 481 compatible = "ti,sysc-omap4-simple", "ti,sysc";
482 clocks = <&l3_clkctrl 482 clocks = <&l3_clkctrl AM3_L3_OCMCRAM_CLKCTRL 0>;
483 clock-names = "fck"; 483 clock-names = "fck";
484 ti,no-idle; 484 ti,no-idle;
485 #address-cells = <1>; 485 #address-cells = <1>;
486 #size-cells = <1>; 486 #size-cells = <1>;
487 ranges = <0 0x40300000 487 ranges = <0 0x40300000 0x10000>;
488 488
489 ocmcram: sram@0 { 489 ocmcram: sram@0 {
490 compatible = " 490 compatible = "mmio-sram";
491 reg = <0 0x100 491 reg = <0 0x10000>; /* 64k */
492 ranges = <0 0 492 ranges = <0 0 0x10000>;
493 #address-cells 493 #address-cells = <1>;
494 #size-cells = 494 #size-cells = <1>;
495 495
496 pm_sram_code: 496 pm_sram_code: pm-code-sram@0 {
497 compat 497 compatible = "ti,sram";
498 reg = 498 reg = <0x0 0x1000>;
499 protec 499 protect-exec;
500 }; 500 };
501 501
502 pm_sram_data: 502 pm_sram_data: pm-data-sram@1000 {
503 compat 503 compatible = "ti,sram";
504 reg = 504 reg = <0x1000 0x1000>;
505 pool; 505 pool;
506 }; 506 };
507 }; 507 };
508 }; 508 };
509 509
510 target-module@4c000000 { 510 target-module@4c000000 {
511 compatible = "ti,sysc- 511 compatible = "ti,sysc-omap4-simple", "ti,sysc";
512 reg = <0x4c000000 0x4> 512 reg = <0x4c000000 0x4>;
513 reg-names = "rev"; 513 reg-names = "rev";
514 clocks = <&l3_clkctrl 514 clocks = <&l3_clkctrl AM3_L3_EMIF_CLKCTRL 0>;
515 clock-names = "fck"; 515 clock-names = "fck";
516 ti,no-idle; 516 ti,no-idle;
517 #address-cells = <1>; 517 #address-cells = <1>;
518 #size-cells = <1>; 518 #size-cells = <1>;
519 ranges = <0x0 0x4c0000 519 ranges = <0x0 0x4c000000 0x1000000>;
520 520
521 emif: emif@0 { 521 emif: emif@0 {
522 compatible = " 522 compatible = "ti,emif-am3352";
523 reg = <0 0x100 523 reg = <0 0x1000000>;
524 interrupts = < 524 interrupts = <101>;
525 sram = <&pm_sr 525 sram = <&pm_sram_code
526 &pm_sr 526 &pm_sram_data>;
527 }; 527 };
528 }; 528 };
529 529
530 target-module@50000000 { 530 target-module@50000000 {
531 compatible = "ti,sysc- 531 compatible = "ti,sysc-omap2", "ti,sysc";
532 reg = <0x50000000 4>, 532 reg = <0x50000000 4>,
533 <0x50000010 4>, 533 <0x50000010 4>,
534 <0x50000014 4>; 534 <0x50000014 4>;
535 reg-names = "rev", "sy 535 reg-names = "rev", "sysc", "syss";
536 ti,sysc-sidle = <SYSC_ 536 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
537 <SYSC_ 537 <SYSC_IDLE_NO>,
538 <SYSC_ 538 <SYSC_IDLE_SMART>;
539 ti,syss-mask = <1>; 539 ti,syss-mask = <1>;
540 clocks = <&l3s_clkctrl 540 clocks = <&l3s_clkctrl AM3_L3S_GPMC_CLKCTRL 0>;
541 clock-names = "fck"; 541 clock-names = "fck";
542 #address-cells = <1>; 542 #address-cells = <1>;
543 #size-cells = <1>; 543 #size-cells = <1>;
544 ranges = <0x50000000 0 544 ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
545 <0x00000000 0 545 <0x00000000 0x00000000 0x40000000>; /* data */
546 546
547 gpmc: gpmc@50000000 { 547 gpmc: gpmc@50000000 {
548 compatible = " 548 compatible = "ti,am3352-gpmc";
549 reg = <0x50000 549 reg = <0x50000000 0x2000>;
550 interrupts = < 550 interrupts = <100>;
551 dmas = <&edma 551 dmas = <&edma 52 0>;
552 dma-names = "r 552 dma-names = "rxtx";
553 gpmc,num-cs = 553 gpmc,num-cs = <7>;
554 gpmc,num-waitp 554 gpmc,num-waitpins = <2>;
555 #address-cells 555 #address-cells = <2>;
556 #size-cells = 556 #size-cells = <1>;
557 interrupt-cont 557 interrupt-controller;
558 #interrupt-cel 558 #interrupt-cells = <2>;
559 gpio-controlle 559 gpio-controller;
560 #gpio-cells = 560 #gpio-cells = <2>;
561 status = "disa 561 status = "disabled";
562 }; 562 };
563 }; 563 };
564 564
565 sham_target: target-module@531 565 sham_target: target-module@53100000 {
566 compatible = "ti,sysc- 566 compatible = "ti,sysc-omap3-sham", "ti,sysc";
567 reg = <0x53100100 0x4> 567 reg = <0x53100100 0x4>,
568 <0x53100110 0x4> 568 <0x53100110 0x4>,
569 <0x53100114 0x4> 569 <0x53100114 0x4>;
570 reg-names = "rev", "sy 570 reg-names = "rev", "sysc", "syss";
571 ti,sysc-mask = <(SYSC_ 571 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
572 SYSC_ 572 SYSC_OMAP2_AUTOIDLE)>;
573 ti,sysc-sidle = <SYSC_ 573 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
574 <SYSC_ 574 <SYSC_IDLE_NO>,
575 <SYSC_ 575 <SYSC_IDLE_SMART>;
576 ti,syss-mask = <1>; 576 ti,syss-mask = <1>;
577 /* Domains (P, C): per 577 /* Domains (P, C): per_pwrdm, l3_clkdm */
578 clocks = <&l3_clkctrl 578 clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>;
579 clock-names = "fck"; 579 clock-names = "fck";
580 #address-cells = <1>; 580 #address-cells = <1>;
581 #size-cells = <1>; 581 #size-cells = <1>;
582 ranges = <0x0 0x531000 582 ranges = <0x0 0x53100000 0x1000>;
583 583
584 sham: sham@0 { 584 sham: sham@0 {
585 compatible = " 585 compatible = "ti,omap4-sham";
586 reg = <0 0x200 586 reg = <0 0x200>;
587 interrupts = < 587 interrupts = <109>;
588 dmas = <&edma 588 dmas = <&edma 36 0>;
589 dma-names = "r 589 dma-names = "rx";
590 }; 590 };
591 }; 591 };
592 592
593 aes_target: target-module@5350 593 aes_target: target-module@53500000 {
594 compatible = "ti,sysc- 594 compatible = "ti,sysc-omap2", "ti,sysc";
595 reg = <0x53500080 0x4> 595 reg = <0x53500080 0x4>,
596 <0x53500084 0x4> 596 <0x53500084 0x4>,
597 <0x53500088 0x4> 597 <0x53500088 0x4>;
598 reg-names = "rev", "sy 598 reg-names = "rev", "sysc", "syss";
599 ti,sysc-mask = <(SYSC_ 599 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
600 SYSC_ 600 SYSC_OMAP2_AUTOIDLE)>;
601 ti,sysc-sidle = <SYSC_ 601 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
602 <SYSC_ 602 <SYSC_IDLE_NO>,
603 <SYSC_ 603 <SYSC_IDLE_SMART>,
604 <SYSC_ 604 <SYSC_IDLE_SMART_WKUP>;
605 ti,syss-mask = <1>; 605 ti,syss-mask = <1>;
606 /* Domains (P, C): per 606 /* Domains (P, C): per_pwrdm, l3_clkdm */
607 clocks = <&l3_clkctrl 607 clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>;
608 clock-names = "fck"; 608 clock-names = "fck";
609 #address-cells = <1>; 609 #address-cells = <1>;
610 #size-cells = <1>; 610 #size-cells = <1>;
611 ranges = <0x0 0x535000 611 ranges = <0x0 0x53500000 0x1000>;
612 612
613 aes: aes@0 { 613 aes: aes@0 {
614 compatible = " 614 compatible = "ti,omap4-aes";
615 reg = <0 0xa0> 615 reg = <0 0xa0>;
616 interrupts = < 616 interrupts = <103>;
617 dmas = <&edma 617 dmas = <&edma 6 0>,
618 <&edma 618 <&edma 5 0>;
619 dma-names = "t 619 dma-names = "tx", "rx";
620 }; 620 };
621 }; 621 };
622 622
623 target-module@56000000 { 623 target-module@56000000 {
624 compatible = "ti,sysc- 624 compatible = "ti,sysc-omap4", "ti,sysc";
625 reg = <0x5600fe00 0x4> 625 reg = <0x5600fe00 0x4>,
626 <0x5600fe10 0x4> 626 <0x5600fe10 0x4>;
627 reg-names = "rev", "sy 627 reg-names = "rev", "sysc";
628 ti,sysc-midle = <SYSC_ 628 ti,sysc-midle = <SYSC_IDLE_FORCE>,
629 <SYSC_ 629 <SYSC_IDLE_NO>,
630 <SYSC_ 630 <SYSC_IDLE_SMART>;
631 ti,sysc-sidle = <SYSC_ 631 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
632 <SYSC_ 632 <SYSC_IDLE_NO>,
633 <SYSC_ 633 <SYSC_IDLE_SMART>;
634 clocks = <&gfx_l3_clkc 634 clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>;
635 clock-names = "fck"; 635 clock-names = "fck";
636 power-domains = <&prm_ 636 power-domains = <&prm_gfx>;
637 resets = <&prm_gfx 0>; 637 resets = <&prm_gfx 0>;
638 reset-names = "rstctrl 638 reset-names = "rstctrl";
639 #address-cells = <1>; 639 #address-cells = <1>;
640 #size-cells = <1>; 640 #size-cells = <1>;
641 ranges = <0 0x56000000 641 ranges = <0 0x56000000 0x1000000>;
642 642
643 gpu@0 { 643 gpu@0 {
644 compatible = " 644 compatible = "ti,omap3630-gpu", "img,powervr-sgx530";
645 reg = <0x0 0x1 645 reg = <0x0 0x10000>; /* 64kB */
646 interrupts = < 646 interrupts = <37>;
647 }; 647 };
648 }; 648 };
649 }; 649 };
650 }; 650 };
651 651
652 #include "am33xx-l4.dtsi" 652 #include "am33xx-l4.dtsi"
653 #include "am33xx-clocks.dtsi" 653 #include "am33xx-clocks.dtsi"
654 654
655 &prcm { 655 &prcm {
656 prm_per: prm@c00 { 656 prm_per: prm@c00 {
657 compatible = "ti,am3-prm-inst" 657 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
658 reg = <0xc00 0x100>; 658 reg = <0xc00 0x100>;
659 #reset-cells = <1>; 659 #reset-cells = <1>;
660 #power-domain-cells = <0>; 660 #power-domain-cells = <0>;
661 }; 661 };
662 662
663 prm_wkup: prm@d00 { 663 prm_wkup: prm@d00 {
664 compatible = "ti,am3-prm-inst" 664 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
665 reg = <0xd00 0x100>; 665 reg = <0xd00 0x100>;
666 #reset-cells = <1>; 666 #reset-cells = <1>;
667 #power-domain-cells = <0>; 667 #power-domain-cells = <0>;
668 }; 668 };
669 669
670 prm_mpu: prm@e00 { 670 prm_mpu: prm@e00 {
671 compatible = "ti,am3-prm-inst" 671 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
672 reg = <0xe00 0x100>; 672 reg = <0xe00 0x100>;
673 #power-domain-cells = <0>; 673 #power-domain-cells = <0>;
674 }; 674 };
675 675
676 prm_device: prm@f00 { 676 prm_device: prm@f00 {
677 compatible = "ti,am3-prm-inst" 677 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
678 reg = <0xf00 0x100>; 678 reg = <0xf00 0x100>;
679 #reset-cells = <1>; 679 #reset-cells = <1>;
680 }; 680 };
681 681
682 prm_rtc: prm@1000 { 682 prm_rtc: prm@1000 {
683 compatible = "ti,am3-prm-inst" 683 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
684 reg = <0x1000 0x100>; 684 reg = <0x1000 0x100>;
685 #power-domain-cells = <0>; 685 #power-domain-cells = <0>;
686 }; 686 };
687 687
688 prm_gfx: prm@1100 { 688 prm_gfx: prm@1100 {
689 compatible = "ti,am3-prm-inst" 689 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
690 reg = <0x1100 0x100>; 690 reg = <0x1100 0x100>;
691 #power-domain-cells = <0>; 691 #power-domain-cells = <0>;
692 #reset-cells = <1>; 692 #reset-cells = <1>;
693 }; 693 };
694 694
695 prm_cefuse: prm@1200 { 695 prm_cefuse: prm@1200 {
696 compatible = "ti,am3-prm-inst" 696 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
697 reg = <0x1200 0x100>; 697 reg = <0x1200 0x100>;
698 #power-domain-cells = <0>; 698 #power-domain-cells = <0>;
699 }; 699 };
700 }; 700 };
701 701
702 /* Preferred always-on timer for clocksource * 702 /* Preferred always-on timer for clocksource */
703 &timer1_target { 703 &timer1_target {
704 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP 704 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>,
705 <&l4_wkup_clkctrl AM3_L4_WKUP 705 <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>;
706 clock-names = "fck", "ick"; 706 clock-names = "fck", "ick";
707 ti,no-reset-on-init; 707 ti,no-reset-on-init;
708 ti,no-idle; 708 ti,no-idle;
709 timer@0 { 709 timer@0 {
710 assigned-clocks = <&timer1_fck 710 assigned-clocks = <&timer1_fck>;
711 assigned-clock-parents = <&sys 711 assigned-clock-parents = <&sys_clkin_ck>;
712 }; 712 };
713 }; 713 };
714 714
715 /* Preferred timer for clockevent */ 715 /* Preferred timer for clockevent */
716 &timer2_target { 716 &timer2_target {
717 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER 717 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>,
718 <&l4ls_clkctrl AM3_L4LS_L4_LS 718 <&l4ls_clkctrl AM3_L4LS_L4_LS_CLKCTRL 0>;
719 clock-names = "fck", "ick"; 719 clock-names = "fck", "ick";
720 ti,no-reset-on-init; 720 ti,no-reset-on-init;
721 ti,no-idle; 721 ti,no-idle;
722 timer@0 { 722 timer@0 {
723 assigned-clocks = <&timer2_fck 723 assigned-clocks = <&timer2_fck>;
724 assigned-clock-parents = <&sys 724 assigned-clock-parents = <&sys_clkin_ck>;
725 }; 725 };
726 }; 726 };
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