1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 2
3 &scrm { 3 &scrm {
4 main_fapll: main_fapll { 4 main_fapll: main_fapll {
5 #clock-cells = <1>; 5 #clock-cells = <1>;
6 compatible = "ti,dm816-fapll-c 6 compatible = "ti,dm816-fapll-clock";
7 reg = <0x400 0x40>; 7 reg = <0x400 0x40>;
8 clocks = <&sys_clkin_ck &sys_c 8 clocks = <&sys_clkin_ck &sys_clkin_ck>;
9 clock-indices = <1>, <2>, <3>, 9 clock-indices = <1>, <2>, <3>, <4>, <5>,
10 <6>, <7>; 10 <6>, <7>;
11 clock-output-names = "main_pll 11 clock-output-names = "main_pll_clk1",
12 "main_pll 12 "main_pll_clk2",
13 "main_pll 13 "main_pll_clk3",
14 "main_pll 14 "main_pll_clk4",
15 "main_pll 15 "main_pll_clk5",
16 "main_pll 16 "main_pll_clk6",
17 "main_pll 17 "main_pll_clk7";
18 }; 18 };
19 19
20 ddr_fapll: ddr_fapll { 20 ddr_fapll: ddr_fapll {
21 #clock-cells = <1>; 21 #clock-cells = <1>;
22 compatible = "ti,dm816-fapll-c 22 compatible = "ti,dm816-fapll-clock";
23 reg = <0x440 0x30>; 23 reg = <0x440 0x30>;
24 clocks = <&sys_clkin_ck &sys_c 24 clocks = <&sys_clkin_ck &sys_clkin_ck>;
25 clock-indices = <1>, <2>, <3>, 25 clock-indices = <1>, <2>, <3>, <4>;
26 clock-output-names = "ddr_pll_ 26 clock-output-names = "ddr_pll_clk1",
27 "ddr_pll_ 27 "ddr_pll_clk2",
28 "ddr_pll_ 28 "ddr_pll_clk3",
29 "ddr_pll_ 29 "ddr_pll_clk4";
30 }; 30 };
31 31
32 video_fapll: video_fapll { 32 video_fapll: video_fapll {
33 #clock-cells = <1>; 33 #clock-cells = <1>;
34 compatible = "ti,dm816-fapll-c 34 compatible = "ti,dm816-fapll-clock";
35 reg = <0x470 0x30>; 35 reg = <0x470 0x30>;
36 clocks = <&sys_clkin_ck &sys_c 36 clocks = <&sys_clkin_ck &sys_clkin_ck>;
37 clock-indices = <1>, <2>, <3>; 37 clock-indices = <1>, <2>, <3>;
38 clock-output-names = "video_pl 38 clock-output-names = "video_pll_clk1",
39 "video_pl 39 "video_pll_clk2",
40 "video_pl 40 "video_pll_clk3";
41 }; 41 };
42 42
43 audio_fapll: audio_fapll { 43 audio_fapll: audio_fapll {
44 #clock-cells = <1>; 44 #clock-cells = <1>;
45 compatible = "ti,dm816-fapll-c 45 compatible = "ti,dm816-fapll-clock";
46 reg = <0x4a0 0x30>; 46 reg = <0x4a0 0x30>;
47 clocks = <&main_fapll 7>, < &s 47 clocks = <&main_fapll 7>, < &sys_clkin_ck>;
48 clock-indices = <1>, <2>, <3>, 48 clock-indices = <1>, <2>, <3>, <4>, <5>;
49 clock-output-names = "audio_pl 49 clock-output-names = "audio_pll_clk1",
50 "audio_pl 50 "audio_pll_clk2",
51 "audio_pl 51 "audio_pll_clk3",
52 "audio_pl 52 "audio_pll_clk4",
53 "audio_pl 53 "audio_pll_clk5";
54 }; 54 };
55 }; 55 };
56 56
57 &scrm_clocks { 57 &scrm_clocks {
58 secure_32k_ck: secure_32k_ck { 58 secure_32k_ck: secure_32k_ck {
59 #clock-cells = <0>; 59 #clock-cells = <0>;
60 compatible = "fixed-clock"; 60 compatible = "fixed-clock";
61 clock-frequency = <32768>; 61 clock-frequency = <32768>;
62 }; 62 };
63 63
64 sys_32k_ck: sys_32k_ck { 64 sys_32k_ck: sys_32k_ck {
65 #clock-cells = <0>; 65 #clock-cells = <0>;
66 compatible = "fixed-clock"; 66 compatible = "fixed-clock";
67 clock-frequency = <32768>; 67 clock-frequency = <32768>;
68 }; 68 };
69 69
70 tclkin_ck: tclkin_ck { 70 tclkin_ck: tclkin_ck {
71 #clock-cells = <0>; 71 #clock-cells = <0>;
72 compatible = "fixed-clock"; 72 compatible = "fixed-clock";
73 clock-frequency = <32768>; 73 clock-frequency = <32768>;
74 }; 74 };
75 75
76 sys_clkin_ck: sys_clkin_ck { 76 sys_clkin_ck: sys_clkin_ck {
77 #clock-cells = <0>; 77 #clock-cells = <0>;
78 compatible = "fixed-clock"; 78 compatible = "fixed-clock";
79 clock-frequency = <27000000>; 79 clock-frequency = <27000000>;
80 }; 80 };
81 }; 81 };
82 82
83 /* 0x48180000 */ 83 /* 0x48180000 */
84 &prcm_clocks { 84 &prcm_clocks {
85 clkout_pre_ck: clkout_pre_ck@100 { 85 clkout_pre_ck: clkout_pre_ck@100 {
86 #clock-cells = <0>; 86 #clock-cells = <0>;
87 compatible = "ti,mux-clock"; 87 compatible = "ti,mux-clock";
88 clocks = <&main_fapll 5 &ddr_f 88 clocks = <&main_fapll 5 &ddr_fapll 1 &video_fapll 1
89 &audio_fapll 1>; 89 &audio_fapll 1>;
90 reg = <0x100>; 90 reg = <0x100>;
91 }; 91 };
92 92
93 clkout_div_ck: clkout_div_ck@100 { 93 clkout_div_ck: clkout_div_ck@100 {
94 #clock-cells = <0>; 94 #clock-cells = <0>;
95 compatible = "ti,divider-clock 95 compatible = "ti,divider-clock";
96 clocks = <&clkout_pre_ck>; 96 clocks = <&clkout_pre_ck>;
97 ti,bit-shift = <3>; 97 ti,bit-shift = <3>;
98 ti,max-div = <8>; 98 ti,max-div = <8>;
99 reg = <0x100>; 99 reg = <0x100>;
100 }; 100 };
101 101
102 clkout_ck: clkout_ck@100 { 102 clkout_ck: clkout_ck@100 {
103 #clock-cells = <0>; 103 #clock-cells = <0>;
104 compatible = "ti,gate-clock"; 104 compatible = "ti,gate-clock";
105 clocks = <&clkout_div_ck>; 105 clocks = <&clkout_div_ck>;
106 ti,bit-shift = <7>; 106 ti,bit-shift = <7>;
107 reg = <0x100>; 107 reg = <0x100>;
108 }; 108 };
109 109
110 /* CM_DPLL clocks p1795 */ 110 /* CM_DPLL clocks p1795 */
111 sysclk1_ck: sysclk1_ck@300 { 111 sysclk1_ck: sysclk1_ck@300 {
112 #clock-cells = <0>; 112 #clock-cells = <0>;
113 compatible = "ti,divider-clock 113 compatible = "ti,divider-clock";
114 clocks = <&main_fapll 1>; 114 clocks = <&main_fapll 1>;
115 ti,max-div = <7>; 115 ti,max-div = <7>;
116 reg = <0x0300>; 116 reg = <0x0300>;
117 }; 117 };
118 118
119 sysclk2_ck: sysclk2_ck@304 { 119 sysclk2_ck: sysclk2_ck@304 {
120 #clock-cells = <0>; 120 #clock-cells = <0>;
121 compatible = "ti,divider-clock 121 compatible = "ti,divider-clock";
122 clocks = <&main_fapll 2>; 122 clocks = <&main_fapll 2>;
123 ti,max-div = <7>; 123 ti,max-div = <7>;
124 reg = <0x0304>; 124 reg = <0x0304>;
125 }; 125 };
126 126
127 sysclk3_ck: sysclk3_ck@308 { 127 sysclk3_ck: sysclk3_ck@308 {
128 #clock-cells = <0>; 128 #clock-cells = <0>;
129 compatible = "ti,divider-clock 129 compatible = "ti,divider-clock";
130 clocks = <&main_fapll 3>; 130 clocks = <&main_fapll 3>;
131 ti,max-div = <7>; 131 ti,max-div = <7>;
132 reg = <0x0308>; 132 reg = <0x0308>;
133 }; 133 };
134 134
135 sysclk4_ck: sysclk4_ck@30c { 135 sysclk4_ck: sysclk4_ck@30c {
136 #clock-cells = <0>; 136 #clock-cells = <0>;
137 compatible = "ti,divider-clock 137 compatible = "ti,divider-clock";
138 clocks = <&main_fapll 4>; 138 clocks = <&main_fapll 4>;
139 ti,max-div = <1>; 139 ti,max-div = <1>;
140 reg = <0x030c>; 140 reg = <0x030c>;
141 }; 141 };
142 142
143 sysclk5_ck: sysclk5_ck@310 { 143 sysclk5_ck: sysclk5_ck@310 {
144 #clock-cells = <0>; 144 #clock-cells = <0>;
145 compatible = "ti,divider-clock 145 compatible = "ti,divider-clock";
146 clocks = <&sysclk4_ck>; 146 clocks = <&sysclk4_ck>;
147 ti,max-div = <1>; 147 ti,max-div = <1>;
148 reg = <0x0310>; 148 reg = <0x0310>;
149 }; 149 };
150 150
151 sysclk6_ck: sysclk6_ck@314 { 151 sysclk6_ck: sysclk6_ck@314 {
152 #clock-cells = <0>; 152 #clock-cells = <0>;
153 compatible = "ti,divider-clock 153 compatible = "ti,divider-clock";
154 clocks = <&main_fapll 4>; 154 clocks = <&main_fapll 4>;
155 ti,dividers = <2>, <4>; 155 ti,dividers = <2>, <4>;
156 reg = <0x0314>; 156 reg = <0x0314>;
157 }; 157 };
158 158
159 sysclk10_ck: sysclk10_ck@324 { 159 sysclk10_ck: sysclk10_ck@324 {
160 #clock-cells = <0>; 160 #clock-cells = <0>;
161 compatible = "ti,divider-clock 161 compatible = "ti,divider-clock";
162 clocks = <&ddr_fapll 2>; 162 clocks = <&ddr_fapll 2>;
163 ti,max-div = <7>; 163 ti,max-div = <7>;
164 reg = <0x0324>; 164 reg = <0x0324>;
165 }; 165 };
166 166
167 sysclk24_ck: sysclk24_ck@3b4 { 167 sysclk24_ck: sysclk24_ck@3b4 {
168 #clock-cells = <0>; 168 #clock-cells = <0>;
169 compatible = "ti,divider-clock 169 compatible = "ti,divider-clock";
170 clocks = <&main_fapll 5>; 170 clocks = <&main_fapll 5>;
171 ti,max-div = <7>; 171 ti,max-div = <7>;
172 reg = <0x03b4>; 172 reg = <0x03b4>;
173 }; 173 };
174 174
175 mpu_ck: mpu_ck@15dc { 175 mpu_ck: mpu_ck@15dc {
176 #clock-cells = <0>; 176 #clock-cells = <0>;
177 compatible = "ti,gate-clock"; 177 compatible = "ti,gate-clock";
178 clocks = <&sysclk2_ck>; 178 clocks = <&sysclk2_ck>;
179 ti,bit-shift = <1>; 179 ti,bit-shift = <1>;
180 reg = <0x15dc>; 180 reg = <0x15dc>;
181 }; 181 };
182 182
183 audio_pll_a_ck: audio_pll_a_ck@35c { 183 audio_pll_a_ck: audio_pll_a_ck@35c {
184 #clock-cells = <0>; 184 #clock-cells = <0>;
185 compatible = "ti,divider-clock 185 compatible = "ti,divider-clock";
186 clocks = <&audio_fapll 1>; 186 clocks = <&audio_fapll 1>;
187 ti,max-div = <7>; 187 ti,max-div = <7>;
188 reg = <0x035c>; 188 reg = <0x035c>;
189 }; 189 };
190 190
191 sysclk18_ck: sysclk18_ck@378 { 191 sysclk18_ck: sysclk18_ck@378 {
192 #clock-cells = <0>; 192 #clock-cells = <0>;
193 compatible = "ti,mux-clock"; 193 compatible = "ti,mux-clock";
194 clocks = <&sys_32k_ck>, <&audi 194 clocks = <&sys_32k_ck>, <&audio_pll_a_ck>;
195 reg = <0x0378>; 195 reg = <0x0378>;
196 }; 196 };
197 197
198 timer1_fck: timer1_fck@390 { 198 timer1_fck: timer1_fck@390 {
199 #clock-cells = <0>; 199 #clock-cells = <0>;
200 compatible = "ti,mux-clock"; 200 compatible = "ti,mux-clock";
201 clocks = <&tclkin_ck>, <&syscl 201 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
202 reg = <0x0390>; 202 reg = <0x0390>;
203 }; 203 };
204 204
205 timer2_fck: timer2_fck@394 { 205 timer2_fck: timer2_fck@394 {
206 #clock-cells = <0>; 206 #clock-cells = <0>;
207 compatible = "ti,mux-clock"; 207 compatible = "ti,mux-clock";
208 clocks = <&tclkin_ck>, <&syscl 208 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
209 reg = <0x0394>; 209 reg = <0x0394>;
210 }; 210 };
211 211
212 timer3_fck: timer3_fck@398 { 212 timer3_fck: timer3_fck@398 {
213 #clock-cells = <0>; 213 #clock-cells = <0>;
214 compatible = "ti,mux-clock"; 214 compatible = "ti,mux-clock";
215 clocks = <&tclkin_ck>, <&syscl 215 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
216 reg = <0x0398>; 216 reg = <0x0398>;
217 }; 217 };
218 218
219 timer4_fck: timer4_fck@39c { 219 timer4_fck: timer4_fck@39c {
220 #clock-cells = <0>; 220 #clock-cells = <0>;
221 compatible = "ti,mux-clock"; 221 compatible = "ti,mux-clock";
222 clocks = <&tclkin_ck>, <&syscl 222 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
223 reg = <0x039c>; 223 reg = <0x039c>;
224 }; 224 };
225 225
226 timer5_fck: timer5_fck@3a0 { 226 timer5_fck: timer5_fck@3a0 {
227 #clock-cells = <0>; 227 #clock-cells = <0>;
228 compatible = "ti,mux-clock"; 228 compatible = "ti,mux-clock";
229 clocks = <&tclkin_ck>, <&syscl 229 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
230 reg = <0x03a0>; 230 reg = <0x03a0>;
231 }; 231 };
232 232
233 timer6_fck: timer6_fck@3a4 { 233 timer6_fck: timer6_fck@3a4 {
234 #clock-cells = <0>; 234 #clock-cells = <0>;
235 compatible = "ti,mux-clock"; 235 compatible = "ti,mux-clock";
236 clocks = <&tclkin_ck>, <&syscl 236 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
237 reg = <0x03a4>; 237 reg = <0x03a4>;
238 }; 238 };
239 239
240 timer7_fck: timer7_fck@3a8 { 240 timer7_fck: timer7_fck@3a8 {
241 #clock-cells = <0>; 241 #clock-cells = <0>;
242 compatible = "ti,mux-clock"; 242 compatible = "ti,mux-clock";
243 clocks = <&tclkin_ck>, <&syscl 243 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
244 reg = <0x03a8>; 244 reg = <0x03a8>;
245 }; 245 };
246 }; 246 };
247 247
248 &prcm { 248 &prcm {
249 default_cm: default_cm@500 { 249 default_cm: default_cm@500 {
250 compatible = "ti,omap4-cm"; 250 compatible = "ti,omap4-cm";
251 reg = <0x500 0x100>; 251 reg = <0x500 0x100>;
252 #address-cells = <1>; 252 #address-cells = <1>;
253 #size-cells = <1>; 253 #size-cells = <1>;
254 ranges = <0 0x500 0x100>; 254 ranges = <0 0x500 0x100>;
255 255
256 default_clkctrl: clk@0 { 256 default_clkctrl: clk@0 {
257 compatible = "ti,clkct 257 compatible = "ti,clkctrl";
258 reg = <0x0 0x5c>; 258 reg = <0x0 0x5c>;
259 #clock-cells = <2>; 259 #clock-cells = <2>;
260 }; 260 };
261 }; 261 };
262 262
263 alwon_cm: alwon_cm@1400 { 263 alwon_cm: alwon_cm@1400 {
264 compatible = "ti,omap4-cm"; 264 compatible = "ti,omap4-cm";
265 reg = <0x1400 0x300>; 265 reg = <0x1400 0x300>;
266 #address-cells = <1>; 266 #address-cells = <1>;
267 #size-cells = <1>; 267 #size-cells = <1>;
268 ranges = <0 0x1400 0x300>; 268 ranges = <0 0x1400 0x300>;
269 269
270 alwon_clkctrl: clk@0 { 270 alwon_clkctrl: clk@0 {
271 compatible = "ti,clkct 271 compatible = "ti,clkctrl";
272 reg = <0x0 0x208>; 272 reg = <0x0 0x208>;
273 #clock-cells = <2>; 273 #clock-cells = <2>;
274 }; 274 };
275 }; 275 };
276 }; 276 };
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