1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * Copyright (C) 2013 Texas Instruments Incorp 3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
4 * 4 *
5 * Based on "omap4.dtsi" 5 * Based on "omap4.dtsi"
6 */ 6 */
7 7
8 #include <dt-bindings/bus/ti-sysc.h> 8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/clock/dra7.h> 9 #include <dt-bindings/clock/dra7.h>
10 #include <dt-bindings/interrupt-controller/arm 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h> 11 #include <dt-bindings/pinctrl/dra.h>
12 #include <dt-bindings/clock/dra7.h> 12 #include <dt-bindings/clock/dra7.h>
13 13
14 #define MAX_SOURCES 400 14 #define MAX_SOURCES 400
15 15
16 / { 16 / {
17 #address-cells = <2>; 17 #address-cells = <2>;
18 #size-cells = <2>; 18 #size-cells = <2>;
19 19
20 compatible = "ti,dra7xx"; 20 compatible = "ti,dra7xx";
21 interrupt-parent = <&crossbar_mpu>; 21 interrupt-parent = <&crossbar_mpu>;
22 chosen { }; 22 chosen { };
23 23
24 aliases { 24 aliases {
25 i2c0 = &i2c1; 25 i2c0 = &i2c1;
26 i2c1 = &i2c2; 26 i2c1 = &i2c2;
27 i2c2 = &i2c3; 27 i2c2 = &i2c3;
28 i2c3 = &i2c4; 28 i2c3 = &i2c4;
29 i2c4 = &i2c5; 29 i2c4 = &i2c5;
30 serial0 = &uart1; 30 serial0 = &uart1;
31 serial1 = &uart2; 31 serial1 = &uart2;
32 serial2 = &uart3; 32 serial2 = &uart3;
33 serial3 = &uart4; 33 serial3 = &uart4;
34 serial4 = &uart5; 34 serial4 = &uart5;
35 serial5 = &uart6; 35 serial5 = &uart6;
36 serial6 = &uart7; 36 serial6 = &uart7;
37 serial7 = &uart8; 37 serial7 = &uart8;
38 serial8 = &uart9; 38 serial8 = &uart9;
39 serial9 = &uart10; 39 serial9 = &uart10;
40 ethernet0 = &cpsw_port1; 40 ethernet0 = &cpsw_port1;
41 ethernet1 = &cpsw_port2; 41 ethernet1 = &cpsw_port2;
42 d_can0 = &dcan1; 42 d_can0 = &dcan1;
43 d_can1 = &dcan2; 43 d_can1 = &dcan2;
44 spi0 = &qspi; 44 spi0 = &qspi;
45 }; 45 };
46 46
47 timer { 47 timer {
48 compatible = "arm,armv7-timer" 48 compatible = "arm,armv7-timer";
49 status = "disabled"; /* See 49 status = "disabled"; /* See ARM architected timer wrap erratum i940 */
50 interrupts = <GIC_PPI 13 (GIC_ 50 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 14 (GIC_ 51 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
52 <GIC_PPI 11 (GIC_ 52 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
53 <GIC_PPI 10 (GIC_ 53 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
54 interrupt-parent = <&gic>; 54 interrupt-parent = <&gic>;
55 }; 55 };
56 56
57 gic: interrupt-controller@48211000 { 57 gic: interrupt-controller@48211000 {
58 compatible = "arm,cortex-a15-g 58 compatible = "arm,cortex-a15-gic";
59 interrupt-controller; 59 interrupt-controller;
60 #interrupt-cells = <3>; 60 #interrupt-cells = <3>;
61 reg = <0x0 0x48211000 0x0 0x10 61 reg = <0x0 0x48211000 0x0 0x1000>,
62 <0x0 0x48212000 0x0 0x20 62 <0x0 0x48212000 0x0 0x2000>,
63 <0x0 0x48214000 0x0 0x20 63 <0x0 0x48214000 0x0 0x2000>,
64 <0x0 0x48216000 0x0 0x20 64 <0x0 0x48216000 0x0 0x2000>;
65 interrupts = <GIC_PPI 9 (GIC_C 65 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
66 interrupt-parent = <&gic>; 66 interrupt-parent = <&gic>;
67 }; 67 };
68 68
69 wakeupgen: interrupt-controller@482810 69 wakeupgen: interrupt-controller@48281000 {
70 compatible = "ti,omap5-wugen-m 70 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
71 interrupt-controller; 71 interrupt-controller;
72 #interrupt-cells = <3>; 72 #interrupt-cells = <3>;
73 reg = <0x0 0x48281000 0x0 0x10 73 reg = <0x0 0x48281000 0x0 0x1000>;
74 interrupt-parent = <&gic>; 74 interrupt-parent = <&gic>;
75 }; 75 };
76 76
77 cpus { 77 cpus {
78 #address-cells = <1>; 78 #address-cells = <1>;
79 #size-cells = <0>; 79 #size-cells = <0>;
80 80
81 cpu0: cpu@0 { 81 cpu0: cpu@0 {
82 device_type = "cpu"; 82 device_type = "cpu";
83 compatible = "arm,cort 83 compatible = "arm,cortex-a15";
84 reg = <0>; 84 reg = <0>;
85 85
86 operating-points-v2 = 86 operating-points-v2 = <&cpu0_opp_table>;
87 87
88 clocks = <&dpll_mpu_ck 88 clocks = <&dpll_mpu_ck>;
89 clock-names = "cpu"; 89 clock-names = "cpu";
90 90
91 clock-latency = <30000 91 clock-latency = <300000>; /* From omap-cpufreq driver */
92 92
93 /* cooling options */ 93 /* cooling options */
94 #cooling-cells = <2>; 94 #cooling-cells = <2>; /* min followed by max */
95 95
96 vbb-supply = <&abb_mpu 96 vbb-supply = <&abb_mpu>;
97 }; 97 };
98 }; 98 };
99 99
100 cpu0_opp_table: opp-table { 100 cpu0_opp_table: opp-table {
101 compatible = "operating-points 101 compatible = "operating-points-v2-ti-cpu";
102 syscon = <&scm_wkup>; 102 syscon = <&scm_wkup>;
103 103
104 opp-1000000000 { 104 opp-1000000000 {
105 /* OPP NOM */ 105 /* OPP NOM */
106 opp-hz = /bits/ 64 <10 106 opp-hz = /bits/ 64 <1000000000>;
107 opp-microvolt = <10600 107 opp-microvolt = <1060000 850000 1150000>,
108 <10600 108 <1060000 850000 1150000>;
109 opp-supported-hw = <0x 109 opp-supported-hw = <0xFF 0x01>;
110 opp-suspend; 110 opp-suspend;
111 }; 111 };
112 112
113 opp-1176000000 { 113 opp-1176000000 {
114 /* OPP OD */ 114 /* OPP OD */
115 opp-hz = /bits/ 64 <11 115 opp-hz = /bits/ 64 <1176000000>;
116 opp-microvolt = <11600 116 opp-microvolt = <1160000 885000 1160000>,
117 <11600 117 <1160000 885000 1160000>;
118 118
119 opp-supported-hw = <0x 119 opp-supported-hw = <0xFF 0x02>;
120 }; 120 };
121 121
122 opp-1500000000 { 122 opp-1500000000 {
123 /* OPP High */ 123 /* OPP High */
124 opp-hz = /bits/ 64 <15 124 opp-hz = /bits/ 64 <1500000000>;
125 opp-microvolt = <12100 125 opp-microvolt = <1210000 950000 1250000>,
126 <12100 126 <1210000 950000 1250000>;
127 opp-supported-hw = <0x 127 opp-supported-hw = <0xFF 0x04>;
128 }; 128 };
129 }; 129 };
130 130
131 /* 131 /*
132 * XXX: Use a flat representation of t 132 * XXX: Use a flat representation of the SOC interconnect.
133 * The real OMAP interconnect network 133 * The real OMAP interconnect network is quite complex.
134 * Since it will not bring real advant 134 * Since it will not bring real advantage to represent that in DT for
135 * the moment, just use a fake OCP bus 135 * the moment, just use a fake OCP bus entry to represent the whole bus
136 * hierarchy. 136 * hierarchy.
137 */ 137 */
138 ocp: ocp { 138 ocp: ocp {
139 compatible = "simple-pm-bus"; 139 compatible = "simple-pm-bus";
140 power-domains = <&prm_core>; 140 power-domains = <&prm_core>;
141 clocks = <&l3main1_clkctrl DRA 141 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL 0>,
142 <&l3instr_clkctrl DRA 142 <&l3instr_clkctrl DRA7_L3INSTR_L3_MAIN_2_CLKCTRL 0>;
143 #address-cells = <1>; 143 #address-cells = <1>;
144 #size-cells = <1>; 144 #size-cells = <1>;
145 ranges = <0x0 0x0 0x0 0xc00000 145 ranges = <0x0 0x0 0x0 0xc0000000>;
146 dma-ranges = <0x80000000 0x0 0 146 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
147 147
148 l3-noc@44000000 { 148 l3-noc@44000000 {
149 compatible = "ti,dra7- 149 compatible = "ti,dra7-l3-noc";
150 reg = <0x44000000 0x10 150 reg = <0x44000000 0x1000000>,
151 <0x45000000 0x10 151 <0x45000000 0x1000>;
152 interrupts-extended = 152 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
153 153 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
154 }; 154 };
155 155
156 l4_cfg: interconnect@4a000000 156 l4_cfg: interconnect@4a000000 {
157 }; 157 };
158 l4_wkup: interconnect@4ae00000 158 l4_wkup: interconnect@4ae00000 {
159 }; 159 };
160 l4_per1: interconnect@48000000 160 l4_per1: interconnect@48000000 {
161 }; 161 };
162 162
163 target-module@48210000 { 163 target-module@48210000 {
164 compatible = "ti,sysc- 164 compatible = "ti,sysc-omap4-simple", "ti,sysc";
165 power-domains = <&prm_ 165 power-domains = <&prm_mpu>;
166 clocks = <&mpu_clkctrl 166 clocks = <&mpu_clkctrl DRA7_MPU_MPU_CLKCTRL 0>;
167 clock-names = "fck"; 167 clock-names = "fck";
168 #address-cells = <1>; 168 #address-cells = <1>;
169 #size-cells = <1>; 169 #size-cells = <1>;
170 ranges = <0 0x48210000 170 ranges = <0 0x48210000 0x1f0000>;
171 171
172 mpu { 172 mpu {
173 compatible = " 173 compatible = "ti,omap5-mpu";
174 }; 174 };
175 }; 175 };
176 176
177 l4_per2: interconnect@48400000 177 l4_per2: interconnect@48400000 {
178 }; 178 };
179 l4_per3: interconnect@48800000 179 l4_per3: interconnect@48800000 {
180 }; 180 };
181 181
182 /* 182 /*
183 * Register access seems to ha 183 * Register access seems to have complex dependencies and also
184 * seems to need an enabled ph 184 * seems to need an enabled phy. See the TRM chapter for "Table
185 * 26-678. Main Sequence PCIe 185 * 26-678. Main Sequence PCIe Controller Global Initialization"
186 * and also dra7xx_pcie_probe( 186 * and also dra7xx_pcie_probe().
187 */ 187 */
188 axi0: target-module@51000000 { 188 axi0: target-module@51000000 {
189 compatible = "ti,sysc- 189 compatible = "ti,sysc-omap4", "ti,sysc";
190 power-domains = <&prm_ 190 power-domains = <&prm_l3init>;
191 resets = <&prm_l3init 191 resets = <&prm_l3init 0>;
192 reset-names = "rstctrl 192 reset-names = "rstctrl";
193 clocks = <&pcie_clkctr 193 clocks = <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 0>,
194 <&pcie_clkctr 194 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>,
195 <&pcie_clkctr 195 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>;
196 clock-names = "fck", " 196 clock-names = "fck", "phy-clk", "phy-clk-div";
197 #size-cells = <1>; 197 #size-cells = <1>;
198 #address-cells = <1>; 198 #address-cells = <1>;
199 ranges = <0x51000000 0 199 ranges = <0x51000000 0x51000000 0x3000>,
200 <0x20000000 0 200 <0x20000000 0x20000000 0x10000000>;
201 dma-ranges; 201 dma-ranges;
202 /** 202 /**
203 * To enable PCI endpo 203 * To enable PCI endpoint mode, disable the pcie1_rc
204 * node and enable pci 204 * node and enable pcie1_ep mode.
205 */ 205 */
206 pcie1_rc: pcie@5100000 206 pcie1_rc: pcie@51000000 {
207 reg = <0x51000 207 reg = <0x51000000 0x2000>,
208 <0x51002 208 <0x51002000 0x14c>,
209 <0x20001 209 <0x20001000 0x2000>;
210 reg-names = "r 210 reg-names = "rc_dbics", "ti_conf", "config";
211 interrupts = < 211 interrupts = <0 232 0x4>, <0 233 0x4>;
212 #address-cells 212 #address-cells = <3>;
213 #size-cells = 213 #size-cells = <2>;
214 device_type = 214 device_type = "pci";
215 ranges = <0x81 215 ranges = <0x81000000 0 0x00000000 0x20003000 0 0x00010000>,
216 <0x82 216 <0x82000000 0 0x20013000 0x20013000 0 0x0ffed000>;
217 bus-range = <0 217 bus-range = <0x00 0xff>;
218 #interrupt-cel 218 #interrupt-cells = <1>;
219 num-lanes = <1 219 num-lanes = <1>;
220 linux,pci-doma 220 linux,pci-domain = <0>;
221 phys = <&pcie1 221 phys = <&pcie1_phy>;
222 phy-names = "p 222 phy-names = "pcie-phy0";
223 ti,syscon-lane 223 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
224 interrupt-map- 224 interrupt-map-mask = <0 0 0 7>;
225 interrupt-map 225 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
226 226 <0 0 0 2 &pcie1_intc 2>,
227 227 <0 0 0 3 &pcie1_intc 3>,
228 228 <0 0 0 4 &pcie1_intc 4>;
229 ti,syscon-unal 229 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
230 status = "disa 230 status = "disabled";
231 pcie1_intc: in 231 pcie1_intc: interrupt-controller {
232 interr 232 interrupt-controller;
233 #addre 233 #address-cells = <0>;
234 #inter 234 #interrupt-cells = <1>;
235 }; 235 };
236 }; 236 };
237 237
238 pcie1_ep: pcie_ep@5100 238 pcie1_ep: pcie_ep@51000000 {
239 reg = <0x51000 239 reg = <0x51000000 0x28>,
240 <0x51002 240 <0x51002000 0x14c>,
241 <0x51001 241 <0x51001000 0x28>,
242 <0x20001 242 <0x20001000 0x10000000>;
243 reg-names = "e 243 reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
244 interrupts = < 244 interrupts = <0 232 0x4>;
245 num-lanes = <1 245 num-lanes = <1>;
246 num-ib-windows 246 num-ib-windows = <4>;
247 num-ob-windows 247 num-ob-windows = <16>;
248 phys = <&pcie1 248 phys = <&pcie1_phy>;
249 phy-names = "p 249 phy-names = "pcie-phy0";
250 ti,syscon-unal 250 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
251 ti,syscon-lane 251 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
252 status = "disa 252 status = "disabled";
253 }; 253 };
254 }; 254 };
255 255
256 /* 256 /*
257 * Register access seems to ha 257 * Register access seems to have complex dependencies and also
258 * seems to need an enabled ph 258 * seems to need an enabled phy. See the TRM chapter for "Table
259 * 26-678. Main Sequence PCIe 259 * 26-678. Main Sequence PCIe Controller Global Initialization"
260 * and also dra7xx_pcie_probe( 260 * and also dra7xx_pcie_probe().
261 */ 261 */
262 axi1: target-module@51800000 { 262 axi1: target-module@51800000 {
263 compatible = "ti,sysc- 263 compatible = "ti,sysc-omap4", "ti,sysc";
264 clocks = <&pcie_clkctr 264 clocks = <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 0>,
265 <&pcie_clkctr 265 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>,
266 <&pcie_clkctr 266 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>;
267 clock-names = "fck", " 267 clock-names = "fck", "phy-clk", "phy-clk-div";
268 power-domains = <&prm_ 268 power-domains = <&prm_l3init>;
269 resets = <&prm_l3init 269 resets = <&prm_l3init 1>;
270 reset-names = "rstctrl 270 reset-names = "rstctrl";
271 #size-cells = <1>; 271 #size-cells = <1>;
272 #address-cells = <1>; 272 #address-cells = <1>;
273 ranges = <0x51800000 0 273 ranges = <0x51800000 0x51800000 0x3000>,
274 <0x30000000 0 274 <0x30000000 0x30000000 0x10000000>;
275 dma-ranges; 275 dma-ranges;
276 status = "disabled"; 276 status = "disabled";
277 pcie2_rc: pcie@5180000 277 pcie2_rc: pcie@51800000 {
278 reg = <0x51800 278 reg = <0x51800000 0x2000>,
279 <0x51802 279 <0x51802000 0x14c>,
280 <0x30001 280 <0x30001000 0x2000>;
281 reg-names = "r 281 reg-names = "rc_dbics", "ti_conf", "config";
282 interrupts = < 282 interrupts = <0 355 0x4>, <0 356 0x4>;
283 #address-cells 283 #address-cells = <3>;
284 #size-cells = 284 #size-cells = <2>;
285 device_type = 285 device_type = "pci";
286 ranges = <0x81 286 ranges = <0x81000000 0 0x00000000 0x30003000 0 0x00010000>,
287 <0x82 287 <0x82000000 0 0x30013000 0x30013000 0 0x0ffed000>;
288 bus-range = <0 288 bus-range = <0x00 0xff>;
289 #interrupt-cel 289 #interrupt-cells = <1>;
290 num-lanes = <1 290 num-lanes = <1>;
291 linux,pci-doma 291 linux,pci-domain = <1>;
292 phys = <&pcie2 292 phys = <&pcie2_phy>;
293 phy-names = "p 293 phy-names = "pcie-phy0";
294 interrupt-map- 294 interrupt-map-mask = <0 0 0 7>;
295 interrupt-map 295 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
296 296 <0 0 0 2 &pcie2_intc 2>,
297 297 <0 0 0 3 &pcie2_intc 3>,
298 298 <0 0 0 4 &pcie2_intc 4>;
299 ti,syscon-unal 299 ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
300 pcie2_intc: in 300 pcie2_intc: interrupt-controller {
301 interr 301 interrupt-controller;
302 #addre 302 #address-cells = <0>;
303 #inter 303 #interrupt-cells = <1>;
304 }; 304 };
305 }; 305 };
306 }; 306 };
307 307
308 ocmcram1: ocmcram@40300000 { 308 ocmcram1: ocmcram@40300000 {
309 compatible = "mmio-sra 309 compatible = "mmio-sram";
310 reg = <0x40300000 0x80 310 reg = <0x40300000 0x80000>;
311 ranges = <0x0 0x403000 311 ranges = <0x0 0x40300000 0x80000>;
312 #address-cells = <1>; 312 #address-cells = <1>;
313 #size-cells = <1>; 313 #size-cells = <1>;
314 /* 314 /*
315 * This is a placehold 315 * This is a placeholder for an optional reserved
316 * region for use by s 316 * region for use by secure software. The size
317 * of this region is n 317 * of this region is not known until runtime so it
318 * is set as zero to e 318 * is set as zero to either be updated to reserve
319 * space or left uncha 319 * space or left unchanged to leave all SRAM for use.
320 * On HS parts that th 320 * On HS parts that that require the reserved region
321 * either the bootload 321 * either the bootloader can update the size to
322 * the required amount 322 * the required amount or the node can be overridden
323 * from the board dts 323 * from the board dts file for the secure platform.
324 */ 324 */
325 sram-hs@0 { 325 sram-hs@0 {
326 compatible = " 326 compatible = "ti,secure-ram";
327 reg = <0x0 0x0 327 reg = <0x0 0x0>;
328 }; 328 };
329 }; 329 };
330 330
331 /* 331 /*
332 * NOTE: ocmcram2 and ocmcram3 332 * NOTE: ocmcram2 and ocmcram3 are not available on all
333 * DRA7xx and AM57xx variants. 333 * DRA7xx and AM57xx variants. Confirm availability in
334 * the data manual for the exa 334 * the data manual for the exact part number in use
335 * before enabling these nodes 335 * before enabling these nodes in the board dts file.
336 */ 336 */
337 ocmcram2: ocmcram@40400000 { 337 ocmcram2: ocmcram@40400000 {
338 status = "disabled"; 338 status = "disabled";
339 compatible = "mmio-sra 339 compatible = "mmio-sram";
340 reg = <0x40400000 0x10 340 reg = <0x40400000 0x100000>;
341 ranges = <0x0 0x404000 341 ranges = <0x0 0x40400000 0x100000>;
342 #address-cells = <1>; 342 #address-cells = <1>;
343 #size-cells = <1>; 343 #size-cells = <1>;
344 }; 344 };
345 345
346 ocmcram3: ocmcram@40500000 { 346 ocmcram3: ocmcram@40500000 {
347 status = "disabled"; 347 status = "disabled";
348 compatible = "mmio-sra 348 compatible = "mmio-sram";
349 reg = <0x40500000 0x10 349 reg = <0x40500000 0x100000>;
350 ranges = <0x0 0x405000 350 ranges = <0x0 0x40500000 0x100000>;
351 #address-cells = <1>; 351 #address-cells = <1>;
352 #size-cells = <1>; 352 #size-cells = <1>;
353 }; 353 };
354 354
355 bandgap: bandgap@4a0021e0 { 355 bandgap: bandgap@4a0021e0 {
356 reg = <0x4a0021e0 0xc 356 reg = <0x4a0021e0 0xc
357 0x4a00232c 0xc 357 0x4a00232c 0xc
358 0x4a002380 0x2 358 0x4a002380 0x2c
359 0x4a0023C0 0x3 359 0x4a0023C0 0x3c
360 0x4a002564 0x8 360 0x4a002564 0x8
361 0x4a002574 0x5 361 0x4a002574 0x50>;
362 compatible = " 362 compatible = "ti,dra752-bandgap";
363 interrupts = < 363 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
364 #thermal-senso 364 #thermal-sensor-cells = <1>;
365 }; 365 };
366 366
367 dsp1_system: dsp_system@40d000 367 dsp1_system: dsp_system@40d00000 {
368 compatible = "syscon"; 368 compatible = "syscon";
369 reg = <0x40d00000 0x10 369 reg = <0x40d00000 0x100>;
370 }; 370 };
371 371
372 dra7_iodelay_core: padconf@484 372 dra7_iodelay_core: padconf@4844a000 {
373 compatible = "ti,dra7- 373 compatible = "ti,dra7-iodelay";
374 reg = <0x4844a000 0x0d 374 reg = <0x4844a000 0x0d1c>;
375 #address-cells = <1>; 375 #address-cells = <1>;
376 #size-cells = <0>; 376 #size-cells = <0>;
377 #pinctrl-cells = <2>; 377 #pinctrl-cells = <2>;
378 }; 378 };
379 379
380 target-module@43300000 { 380 target-module@43300000 {
381 compatible = "ti,sysc- 381 compatible = "ti,sysc-omap4", "ti,sysc";
382 reg = <0x43300000 0x4> 382 reg = <0x43300000 0x4>,
383 <0x43300010 0x4> 383 <0x43300010 0x4>;
384 reg-names = "rev", "sy 384 reg-names = "rev", "sysc";
385 ti,sysc-midle = <SYSC_ 385 ti,sysc-midle = <SYSC_IDLE_FORCE>,
386 <SYSC_ 386 <SYSC_IDLE_NO>,
387 <SYSC_ 387 <SYSC_IDLE_SMART>;
388 ti,sysc-sidle = <SYSC_ 388 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
389 <SYSC_ 389 <SYSC_IDLE_NO>,
390 <SYSC_ 390 <SYSC_IDLE_SMART>;
391 clocks = <&l3main1_clk 391 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPCC_CLKCTRL 0>;
392 clock-names = "fck"; 392 clock-names = "fck";
393 #address-cells = <1>; 393 #address-cells = <1>;
394 #size-cells = <1>; 394 #size-cells = <1>;
395 ranges = <0x0 0x433000 395 ranges = <0x0 0x43300000 0x100000>;
396 396
397 edma: dma@0 { 397 edma: dma@0 {
398 compatible = " 398 compatible = "ti,edma3-tpcc";
399 reg = <0 0x100 399 reg = <0 0x100000>;
400 reg-names = "e 400 reg-names = "edma3_cc";
401 interrupts = < 401 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
402 < 402 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
403 < 403 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
404 interrupt-name 404 interrupt-names = "edma3_ccint", "edma3_mperr",
405 405 "edma3_ccerrint";
406 dma-requests = 406 dma-requests = <64>;
407 #dma-cells = < 407 #dma-cells = <2>;
408 408
409 ti,tptcs = <&e 409 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
410 410
411 /* 411 /*
412 * memcpy is di 412 * memcpy is disabled, can be enabled with:
413 * ti,edma-memc 413 * ti,edma-memcpy-channels = <20 21>;
414 * for example. 414 * for example. Note that these channels need to be
415 * masked in th 415 * masked in the xbar as well.
416 */ 416 */
417 }; 417 };
418 }; 418 };
419 419
420 target-module@43400000 { 420 target-module@43400000 {
421 compatible = "ti,sysc- 421 compatible = "ti,sysc-omap4", "ti,sysc";
422 reg = <0x43400000 0x4> 422 reg = <0x43400000 0x4>,
423 <0x43400010 0x4> 423 <0x43400010 0x4>;
424 reg-names = "rev", "sy 424 reg-names = "rev", "sysc";
425 ti,sysc-midle = <SYSC_ 425 ti,sysc-midle = <SYSC_IDLE_FORCE>,
426 <SYSC_ 426 <SYSC_IDLE_NO>,
427 <SYSC_ 427 <SYSC_IDLE_SMART>;
428 ti,sysc-sidle = <SYSC_ 428 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
429 <SYSC_ 429 <SYSC_IDLE_NO>,
430 <SYSC_ 430 <SYSC_IDLE_SMART>;
431 clocks = <&l3main1_clk 431 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC0_CLKCTRL 0>;
432 clock-names = "fck"; 432 clock-names = "fck";
433 #address-cells = <1>; 433 #address-cells = <1>;
434 #size-cells = <1>; 434 #size-cells = <1>;
435 ranges = <0x0 0x434000 435 ranges = <0x0 0x43400000 0x100000>;
436 436
437 edma_tptc0: dma@0 { 437 edma_tptc0: dma@0 {
438 compatible = " 438 compatible = "ti,edma3-tptc";
439 reg = <0 0x100 439 reg = <0 0x100000>;
440 interrupts = < 440 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
441 interrupt-name 441 interrupt-names = "edma3_tcerrint";
442 }; 442 };
443 }; 443 };
444 444
445 target-module@43500000 { 445 target-module@43500000 {
446 compatible = "ti,sysc- 446 compatible = "ti,sysc-omap4", "ti,sysc";
447 reg = <0x43500000 0x4> 447 reg = <0x43500000 0x4>,
448 <0x43500010 0x4> 448 <0x43500010 0x4>;
449 reg-names = "rev", "sy 449 reg-names = "rev", "sysc";
450 ti,sysc-midle = <SYSC_ 450 ti,sysc-midle = <SYSC_IDLE_FORCE>,
451 <SYSC_ 451 <SYSC_IDLE_NO>,
452 <SYSC_ 452 <SYSC_IDLE_SMART>;
453 ti,sysc-sidle = <SYSC_ 453 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
454 <SYSC_ 454 <SYSC_IDLE_NO>,
455 <SYSC_ 455 <SYSC_IDLE_SMART>;
456 clocks = <&l3main1_clk 456 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC1_CLKCTRL 0>;
457 clock-names = "fck"; 457 clock-names = "fck";
458 #address-cells = <1>; 458 #address-cells = <1>;
459 #size-cells = <1>; 459 #size-cells = <1>;
460 ranges = <0x0 0x435000 460 ranges = <0x0 0x43500000 0x100000>;
461 461
462 edma_tptc1: dma@0 { 462 edma_tptc1: dma@0 {
463 compatible = " 463 compatible = "ti,edma3-tptc";
464 reg = <0 0x100 464 reg = <0 0x100000>;
465 interrupts = < 465 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
466 interrupt-name 466 interrupt-names = "edma3_tcerrint";
467 }; 467 };
468 }; 468 };
469 469
470 target-module@4e000000 { 470 target-module@4e000000 {
471 compatible = "ti,sysc- 471 compatible = "ti,sysc-omap2", "ti,sysc";
472 reg = <0x4e000000 0x4> 472 reg = <0x4e000000 0x4>,
473 <0x4e000010 0x4> 473 <0x4e000010 0x4>;
474 reg-names = "rev", "sy 474 reg-names = "rev", "sysc";
475 ti,sysc-sidle = <SYSC_ 475 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
476 <SYSC_ 476 <SYSC_IDLE_NO>,
477 <SYSC_ 477 <SYSC_IDLE_SMART>;
478 ranges = <0x0 0x4e0000 478 ranges = <0x0 0x4e000000 0x2000000>;
479 #size-cells = <1>; 479 #size-cells = <1>;
480 #address-cells = <1>; 480 #address-cells = <1>;
481 481
482 dmm@0 { 482 dmm@0 {
483 compatible = " 483 compatible = "ti,omap5-dmm";
484 reg = <0 0x800 484 reg = <0 0x800>;
485 interrupts = < 485 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
486 }; 486 };
487 }; 487 };
488 488
489 ipu1: ipu@58820000 { 489 ipu1: ipu@58820000 {
490 compatible = "ti,dra7- 490 compatible = "ti,dra7-ipu";
491 reg = <0x58820000 0x10 491 reg = <0x58820000 0x10000>;
492 reg-names = "l2ram"; 492 reg-names = "l2ram";
493 iommus = <&mmu_ipu1>; 493 iommus = <&mmu_ipu1>;
494 status = "disabled"; 494 status = "disabled";
495 resets = <&prm_ipu 0>, 495 resets = <&prm_ipu 0>, <&prm_ipu 1>;
496 clocks = <&ipu1_clkctr 496 clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
497 firmware-name = "dra7- 497 firmware-name = "dra7-ipu1-fw.xem4";
498 }; 498 };
499 499
500 ipu2: ipu@55020000 { 500 ipu2: ipu@55020000 {
501 compatible = "ti,dra7- 501 compatible = "ti,dra7-ipu";
502 reg = <0x55020000 0x10 502 reg = <0x55020000 0x10000>;
503 reg-names = "l2ram"; 503 reg-names = "l2ram";
504 iommus = <&mmu_ipu2>; 504 iommus = <&mmu_ipu2>;
505 status = "disabled"; 505 status = "disabled";
506 resets = <&prm_core 0> 506 resets = <&prm_core 0>, <&prm_core 1>;
507 clocks = <&ipu2_clkctr 507 clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
508 firmware-name = "dra7- 508 firmware-name = "dra7-ipu2-fw.xem4";
509 }; 509 };
510 510
511 dsp1: dsp@40800000 { 511 dsp1: dsp@40800000 {
512 compatible = "ti,dra7- 512 compatible = "ti,dra7-dsp";
513 reg = <0x40800000 0x48 513 reg = <0x40800000 0x48000>,
514 <0x40e00000 0x80 514 <0x40e00000 0x8000>,
515 <0x40f00000 0x80 515 <0x40f00000 0x8000>;
516 reg-names = "l2ram", " 516 reg-names = "l2ram", "l1pram", "l1dram";
517 ti,bootreg = <&scm_con 517 ti,bootreg = <&scm_conf 0x55c 10>;
518 iommus = <&mmu0_dsp1>, 518 iommus = <&mmu0_dsp1>, <&mmu1_dsp1>;
519 status = "disabled"; 519 status = "disabled";
520 resets = <&prm_dsp1 0> 520 resets = <&prm_dsp1 0>;
521 clocks = <&dsp1_clkctr 521 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
522 firmware-name = "dra7- 522 firmware-name = "dra7-dsp1-fw.xe66";
523 }; 523 };
524 524
525 target-module@40d01000 { 525 target-module@40d01000 {
526 compatible = "ti,sysc- 526 compatible = "ti,sysc-omap2", "ti,sysc";
527 reg = <0x40d01000 0x4> 527 reg = <0x40d01000 0x4>,
528 <0x40d01010 0x4> 528 <0x40d01010 0x4>,
529 <0x40d01014 0x4> 529 <0x40d01014 0x4>;
530 reg-names = "rev", "sy 530 reg-names = "rev", "sysc", "syss";
531 ti,sysc-sidle = <SYSC_ 531 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
532 <SYSC_ 532 <SYSC_IDLE_NO>,
533 <SYSC_ 533 <SYSC_IDLE_SMART>;
534 ti,sysc-mask = <(SYSC_ 534 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
535 SYSC_ 535 SYSC_OMAP2_SOFTRESET |
536 SYSC_ 536 SYSC_OMAP2_AUTOIDLE)>;
537 clocks = <&dsp1_clkctr 537 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
538 clock-names = "fck"; 538 clock-names = "fck";
539 resets = <&prm_dsp1 1> 539 resets = <&prm_dsp1 1>;
540 reset-names = "rstctrl 540 reset-names = "rstctrl";
541 ranges = <0x0 0x40d010 541 ranges = <0x0 0x40d01000 0x1000>;
542 #size-cells = <1>; 542 #size-cells = <1>;
543 #address-cells = <1>; 543 #address-cells = <1>;
544 544
545 mmu0_dsp1: mmu@0 { 545 mmu0_dsp1: mmu@0 {
546 compatible = " 546 compatible = "ti,dra7-dsp-iommu";
547 reg = <0x0 0x1 547 reg = <0x0 0x100>;
548 interrupts = < 548 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
549 #iommu-cells = 549 #iommu-cells = <0>;
550 ti,syscon-mmuc 550 ti,syscon-mmuconfig = <&dsp1_system 0x0>;
551 }; 551 };
552 }; 552 };
553 553
554 target-module@40d02000 { 554 target-module@40d02000 {
555 compatible = "ti,sysc- 555 compatible = "ti,sysc-omap2", "ti,sysc";
556 reg = <0x40d02000 0x4> 556 reg = <0x40d02000 0x4>,
557 <0x40d02010 0x4> 557 <0x40d02010 0x4>,
558 <0x40d02014 0x4> 558 <0x40d02014 0x4>;
559 reg-names = "rev", "sy 559 reg-names = "rev", "sysc", "syss";
560 ti,sysc-sidle = <SYSC_ 560 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
561 <SYSC_ 561 <SYSC_IDLE_NO>,
562 <SYSC_ 562 <SYSC_IDLE_SMART>;
563 ti,sysc-mask = <(SYSC_ 563 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
564 SYSC_ 564 SYSC_OMAP2_SOFTRESET |
565 SYSC_ 565 SYSC_OMAP2_AUTOIDLE)>;
566 clocks = <&dsp1_clkctr 566 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
567 clock-names = "fck"; 567 clock-names = "fck";
568 resets = <&prm_dsp1 1> 568 resets = <&prm_dsp1 1>;
569 reset-names = "rstctrl 569 reset-names = "rstctrl";
570 ranges = <0x0 0x40d020 570 ranges = <0x0 0x40d02000 0x1000>;
571 #size-cells = <1>; 571 #size-cells = <1>;
572 #address-cells = <1>; 572 #address-cells = <1>;
573 573
574 mmu1_dsp1: mmu@0 { 574 mmu1_dsp1: mmu@0 {
575 compatible = " 575 compatible = "ti,dra7-dsp-iommu";
576 reg = <0x0 0x1 576 reg = <0x0 0x100>;
577 interrupts = < 577 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
578 #iommu-cells = 578 #iommu-cells = <0>;
579 ti,syscon-mmuc 579 ti,syscon-mmuconfig = <&dsp1_system 0x1>;
580 }; 580 };
581 }; 581 };
582 582
583 target-module@58882000 { 583 target-module@58882000 {
584 compatible = "ti,sysc- 584 compatible = "ti,sysc-omap2", "ti,sysc";
585 reg = <0x58882000 0x4> 585 reg = <0x58882000 0x4>,
586 <0x58882010 0x4> 586 <0x58882010 0x4>,
587 <0x58882014 0x4> 587 <0x58882014 0x4>;
588 reg-names = "rev", "sy 588 reg-names = "rev", "sysc", "syss";
589 ti,sysc-sidle = <SYSC_ 589 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
590 <SYSC_ 590 <SYSC_IDLE_NO>,
591 <SYSC_ 591 <SYSC_IDLE_SMART>;
592 ti,sysc-mask = <(SYSC_ 592 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
593 SYSC_ 593 SYSC_OMAP2_SOFTRESET |
594 SYSC_ 594 SYSC_OMAP2_AUTOIDLE)>;
595 clocks = <&ipu1_clkctr 595 clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
596 clock-names = "fck"; 596 clock-names = "fck";
597 resets = <&prm_ipu 2>; 597 resets = <&prm_ipu 2>;
598 reset-names = "rstctrl 598 reset-names = "rstctrl";
599 #address-cells = <1>; 599 #address-cells = <1>;
600 #size-cells = <1>; 600 #size-cells = <1>;
601 ranges = <0x0 0x588820 601 ranges = <0x0 0x58882000 0x100>;
602 602
603 mmu_ipu1: mmu@0 { 603 mmu_ipu1: mmu@0 {
604 compatible = " 604 compatible = "ti,dra7-iommu";
605 reg = <0x0 0x1 605 reg = <0x0 0x100>;
606 interrupts = < 606 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
607 #iommu-cells = 607 #iommu-cells = <0>;
608 ti,iommu-bus-e 608 ti,iommu-bus-err-back;
609 }; 609 };
610 }; 610 };
611 611
612 target-module@55082000 { 612 target-module@55082000 {
613 compatible = "ti,sysc- 613 compatible = "ti,sysc-omap2", "ti,sysc";
614 reg = <0x55082000 0x4> 614 reg = <0x55082000 0x4>,
615 <0x55082010 0x4> 615 <0x55082010 0x4>,
616 <0x55082014 0x4> 616 <0x55082014 0x4>;
617 reg-names = "rev", "sy 617 reg-names = "rev", "sysc", "syss";
618 ti,sysc-sidle = <SYSC_ 618 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
619 <SYSC_ 619 <SYSC_IDLE_NO>,
620 <SYSC_ 620 <SYSC_IDLE_SMART>;
621 ti,sysc-mask = <(SYSC_ 621 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
622 SYSC_ 622 SYSC_OMAP2_SOFTRESET |
623 SYSC_ 623 SYSC_OMAP2_AUTOIDLE)>;
624 clocks = <&ipu2_clkctr 624 clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
625 clock-names = "fck"; 625 clock-names = "fck";
626 resets = <&prm_core 2> 626 resets = <&prm_core 2>;
627 reset-names = "rstctrl 627 reset-names = "rstctrl";
628 #address-cells = <1>; 628 #address-cells = <1>;
629 #size-cells = <1>; 629 #size-cells = <1>;
630 ranges = <0x0 0x550820 630 ranges = <0x0 0x55082000 0x100>;
631 631
632 mmu_ipu2: mmu@0 { 632 mmu_ipu2: mmu@0 {
633 compatible = " 633 compatible = "ti,dra7-iommu";
634 reg = <0x0 0x1 634 reg = <0x0 0x100>;
635 interrupts = < 635 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
636 #iommu-cells = 636 #iommu-cells = <0>;
637 ti,iommu-bus-e 637 ti,iommu-bus-err-back;
638 }; 638 };
639 }; 639 };
640 640
641 abb_mpu: regulator-abb-mpu@4ae 641 abb_mpu: regulator-abb-mpu@4ae07ddc {
642 compatible = "ti,abb-v 642 compatible = "ti,abb-v3";
643 regulator-name = "abb_ 643 regulator-name = "abb_mpu";
644 #address-cells = <0>; 644 #address-cells = <0>;
645 #size-cells = <0>; 645 #size-cells = <0>;
646 clocks = <&sys_clkin1> 646 clocks = <&sys_clkin1>;
647 ti,settling-time = <50 647 ti,settling-time = <50>;
648 ti,clock-cycles = <16> 648 ti,clock-cycles = <16>;
649 649
650 reg = <0x4ae07ddc 0x4> 650 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
651 <0x4ae06014 0x4> 651 <0x4ae06014 0x4>, <0x4a003b20 0xc>,
652 <0x4ae0c158 0x4> 652 <0x4ae0c158 0x4>;
653 reg-names = "setup-add 653 reg-names = "setup-address", "control-address",
654 "int-addre 654 "int-address", "efuse-address",
655 "ldo-addre 655 "ldo-address";
656 ti,tranxdone-status-ma 656 ti,tranxdone-status-mask = <0x80>;
657 /* LDOVBBMPU_FBB_MUX_C 657 /* LDOVBBMPU_FBB_MUX_CTRL */
658 ti,ldovbb-override-mas 658 ti,ldovbb-override-mask = <0x400>;
659 /* LDOVBBMPU_FBB_VSET_ 659 /* LDOVBBMPU_FBB_VSET_OUT */
660 ti,ldovbb-vset-mask = 660 ti,ldovbb-vset-mask = <0x1F>;
661 661
662 /* 662 /*
663 * NOTE: only FBB mode 663 * NOTE: only FBB mode used but actual vset will
664 * determine final bia 664 * determine final biasing
665 */ 665 */
666 ti,abb_info = < 666 ti,abb_info = <
667 /*uV ABB 667 /*uV ABB efuse rbb_m fbb_m vset_m*/
668 1060000 0 668 1060000 0 0x0 0 0x02000000 0x01F00000
669 1160000 0 669 1160000 0 0x4 0 0x02000000 0x01F00000
670 1210000 0 670 1210000 0 0x8 0 0x02000000 0x01F00000
671 >; 671 >;
672 }; 672 };
673 673
674 abb_ivahd: regulator-abb-ivahd 674 abb_ivahd: regulator-abb-ivahd@4ae07e34 {
675 compatible = "ti,abb-v 675 compatible = "ti,abb-v3";
676 regulator-name = "abb_ 676 regulator-name = "abb_ivahd";
677 #address-cells = <0>; 677 #address-cells = <0>;
678 #size-cells = <0>; 678 #size-cells = <0>;
679 clocks = <&sys_clkin1> 679 clocks = <&sys_clkin1>;
680 ti,settling-time = <50 680 ti,settling-time = <50>;
681 ti,clock-cycles = <16> 681 ti,clock-cycles = <16>;
682 682
683 reg = <0x4ae07e34 0x4> 683 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
684 <0x4ae06010 0x4> 684 <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
685 <0x4a002470 0x4> 685 <0x4a002470 0x4>;
686 reg-names = "setup-add 686 reg-names = "setup-address", "control-address",
687 "int-addre 687 "int-address", "efuse-address",
688 "ldo-addre 688 "ldo-address";
689 ti,tranxdone-status-ma 689 ti,tranxdone-status-mask = <0x40000000>;
690 /* LDOVBBIVA_FBB_MUX_C 690 /* LDOVBBIVA_FBB_MUX_CTRL */
691 ti,ldovbb-override-mas 691 ti,ldovbb-override-mask = <0x400>;
692 /* LDOVBBIVA_FBB_VSET_ 692 /* LDOVBBIVA_FBB_VSET_OUT */
693 ti,ldovbb-vset-mask = 693 ti,ldovbb-vset-mask = <0x1F>;
694 694
695 /* 695 /*
696 * NOTE: only FBB mode 696 * NOTE: only FBB mode used but actual vset will
697 * determine final bia 697 * determine final biasing
698 */ 698 */
699 ti,abb_info = < 699 ti,abb_info = <
700 /*uV ABB 700 /*uV ABB efuse rbb_m fbb_m vset_m*/
701 1055000 0 701 1055000 0 0x0 0 0x02000000 0x01F00000
702 1150000 0 702 1150000 0 0x4 0 0x02000000 0x01F00000
703 1250000 0 703 1250000 0 0x8 0 0x02000000 0x01F00000
704 >; 704 >;
705 }; 705 };
706 706
707 abb_dspeve: regulator-abb-dspe 707 abb_dspeve: regulator-abb-dspeve@4ae07e30 {
708 compatible = "ti,abb-v 708 compatible = "ti,abb-v3";
709 regulator-name = "abb_ 709 regulator-name = "abb_dspeve";
710 #address-cells = <0>; 710 #address-cells = <0>;
711 #size-cells = <0>; 711 #size-cells = <0>;
712 clocks = <&sys_clkin1> 712 clocks = <&sys_clkin1>;
713 ti,settling-time = <50 713 ti,settling-time = <50>;
714 ti,clock-cycles = <16> 714 ti,clock-cycles = <16>;
715 715
716 reg = <0x4ae07e30 0x4> 716 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
717 <0x4ae06010 0x4> 717 <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
718 <0x4a00246c 0x4> 718 <0x4a00246c 0x4>;
719 reg-names = "setup-add 719 reg-names = "setup-address", "control-address",
720 "int-addre 720 "int-address", "efuse-address",
721 "ldo-addre 721 "ldo-address";
722 ti,tranxdone-status-ma 722 ti,tranxdone-status-mask = <0x20000000>;
723 /* LDOVBBDSPEVE_FBB_MU 723 /* LDOVBBDSPEVE_FBB_MUX_CTRL */
724 ti,ldovbb-override-mas 724 ti,ldovbb-override-mask = <0x400>;
725 /* LDOVBBDSPEVE_FBB_VS 725 /* LDOVBBDSPEVE_FBB_VSET_OUT */
726 ti,ldovbb-vset-mask = 726 ti,ldovbb-vset-mask = <0x1F>;
727 727
728 /* 728 /*
729 * NOTE: only FBB mode 729 * NOTE: only FBB mode used but actual vset will
730 * determine final bia 730 * determine final biasing
731 */ 731 */
732 ti,abb_info = < 732 ti,abb_info = <
733 /*uV ABB 733 /*uV ABB efuse rbb_m fbb_m vset_m*/
734 1055000 0 734 1055000 0 0x0 0 0x02000000 0x01F00000
735 1150000 0 735 1150000 0 0x4 0 0x02000000 0x01F00000
736 1250000 0 736 1250000 0 0x8 0 0x02000000 0x01F00000
737 >; 737 >;
738 }; 738 };
739 739
740 abb_gpu: regulator-abb-gpu@4ae 740 abb_gpu: regulator-abb-gpu@4ae07de4 {
741 compatible = "ti,abb-v 741 compatible = "ti,abb-v3";
742 regulator-name = "abb_ 742 regulator-name = "abb_gpu";
743 #address-cells = <0>; 743 #address-cells = <0>;
744 #size-cells = <0>; 744 #size-cells = <0>;
745 clocks = <&sys_clkin1> 745 clocks = <&sys_clkin1>;
746 ti,settling-time = <50 746 ti,settling-time = <50>;
747 ti,clock-cycles = <16> 747 ti,clock-cycles = <16>;
748 748
749 reg = <0x4ae07de4 0x4> 749 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
750 <0x4ae06010 0x4> 750 <0x4ae06010 0x4>, <0x4a003b08 0xc>,
751 <0x4ae0c154 0x4> 751 <0x4ae0c154 0x4>;
752 reg-names = "setup-add 752 reg-names = "setup-address", "control-address",
753 "int-addre 753 "int-address", "efuse-address",
754 "ldo-addre 754 "ldo-address";
755 ti,tranxdone-status-ma 755 ti,tranxdone-status-mask = <0x10000000>;
756 /* LDOVBBGPU_FBB_MUX_C 756 /* LDOVBBGPU_FBB_MUX_CTRL */
757 ti,ldovbb-override-mas 757 ti,ldovbb-override-mask = <0x400>;
758 /* LDOVBBGPU_FBB_VSET_ 758 /* LDOVBBGPU_FBB_VSET_OUT */
759 ti,ldovbb-vset-mask = 759 ti,ldovbb-vset-mask = <0x1F>;
760 760
761 /* 761 /*
762 * NOTE: only FBB mode 762 * NOTE: only FBB mode used but actual vset will
763 * determine final bia 763 * determine final biasing
764 */ 764 */
765 ti,abb_info = < 765 ti,abb_info = <
766 /*uV ABB 766 /*uV ABB efuse rbb_m fbb_m vset_m*/
767 1090000 0 767 1090000 0 0x0 0 0x02000000 0x01F00000
768 1210000 0 768 1210000 0 0x4 0 0x02000000 0x01F00000
769 1280000 0 769 1280000 0 0x8 0 0x02000000 0x01F00000
770 >; 770 >;
771 }; 771 };
772 772
773 target-module@4b300000 { 773 target-module@4b300000 {
774 compatible = "ti,sysc- 774 compatible = "ti,sysc-omap4", "ti,sysc";
775 reg = <0x4b300000 0x4> 775 reg = <0x4b300000 0x4>,
776 <0x4b300010 0x4> 776 <0x4b300010 0x4>;
777 reg-names = "rev", "sy 777 reg-names = "rev", "sysc";
778 ti,sysc-sidle = <SYSC_ 778 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
779 <SYSC_ 779 <SYSC_IDLE_NO>,
780 <SYSC_ 780 <SYSC_IDLE_SMART>,
781 <SYSC_ 781 <SYSC_IDLE_SMART_WKUP>;
782 clocks = <&l4per2_clkc 782 clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 0>;
783 clock-names = "fck"; 783 clock-names = "fck";
784 #address-cells = <1>; 784 #address-cells = <1>;
785 #size-cells = <1>; 785 #size-cells = <1>;
786 ranges = <0x0 0x4b3000 786 ranges = <0x0 0x4b300000 0x1000>,
787 <0x5c000000 0 787 <0x5c000000 0x5c000000 0x4000000>;
788 788
789 qspi: spi@0 { 789 qspi: spi@0 {
790 compatible = " 790 compatible = "ti,dra7xxx-qspi";
791 reg = <0 0x100 791 reg = <0 0x100>,
792 <0x5c000 792 <0x5c000000 0x4000000>;
793 reg-names = "q 793 reg-names = "qspi_base", "qspi_mmap";
794 syscon-chipsel 794 syscon-chipselects = <&scm_conf 0x558>;
795 #address-cells 795 #address-cells = <1>;
796 #size-cells = 796 #size-cells = <0>;
797 clocks = <&l4p 797 clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 25>;
798 clock-names = 798 clock-names = "fck";
799 num-cs = <4>; 799 num-cs = <4>;
800 interrupts = < 800 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
801 status = "disa 801 status = "disabled";
802 }; 802 };
803 }; 803 };
804 804
805 /* OCP2SCP1 */ 805 /* OCP2SCP1 */
806 /* IRQ for DWC3_3 and DWC3_4 n 806 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
807 807
808 target-module@50000000 { 808 target-module@50000000 {
809 compatible = "ti,sysc- 809 compatible = "ti,sysc-omap2", "ti,sysc";
810 reg = <0x50000000 4>, 810 reg = <0x50000000 4>,
811 <0x50000010 4>, 811 <0x50000010 4>,
812 <0x50000014 4>; 812 <0x50000014 4>;
813 reg-names = "rev", "sy 813 reg-names = "rev", "sysc", "syss";
814 ti,sysc-sidle = <SYSC_ 814 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
815 <SYSC_ 815 <SYSC_IDLE_NO>,
816 <SYSC_ 816 <SYSC_IDLE_SMART>;
817 ti,syss-mask = <1>; 817 ti,syss-mask = <1>;
818 clocks = <&l3main1_clk 818 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_GPMC_CLKCTRL 0>;
819 clock-names = "fck"; 819 clock-names = "fck";
820 #address-cells = <1>; 820 #address-cells = <1>;
821 #size-cells = <1>; 821 #size-cells = <1>;
822 ranges = <0x50000000 0 822 ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
823 <0x00000000 0 823 <0x00000000 0x00000000 0x40000000>; /* data */
824 824
825 gpmc: gpmc@50000000 { 825 gpmc: gpmc@50000000 {
826 compatible = " 826 compatible = "ti,am3352-gpmc";
827 reg = <0x50000 827 reg = <0x50000000 0x37c>; /* device IO registers */
828 interrupts = < 828 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
829 dmas = <&edma_ 829 dmas = <&edma_xbar 4 0>;
830 dma-names = "r 830 dma-names = "rxtx";
831 gpmc,num-cs = 831 gpmc,num-cs = <8>;
832 gpmc,num-waitp 832 gpmc,num-waitpins = <2>;
833 #address-cells 833 #address-cells = <2>;
834 #size-cells = 834 #size-cells = <1>;
835 interrupt-cont 835 interrupt-controller;
836 #interrupt-cel 836 #interrupt-cells = <2>;
837 gpio-controlle 837 gpio-controller;
838 #gpio-cells = 838 #gpio-cells = <2>;
839 status = "disa 839 status = "disabled";
840 }; 840 };
841 }; 841 };
842 842
843 target-module@56000000 { 843 target-module@56000000 {
844 compatible = "ti,sysc- 844 compatible = "ti,sysc-omap4", "ti,sysc";
845 reg = <0x5600fe00 0x4> 845 reg = <0x5600fe00 0x4>,
846 <0x5600fe10 0x4> 846 <0x5600fe10 0x4>;
847 reg-names = "rev", "sy 847 reg-names = "rev", "sysc";
848 ti,sysc-midle = <SYSC_ 848 ti,sysc-midle = <SYSC_IDLE_FORCE>,
849 <SYSC_ 849 <SYSC_IDLE_NO>,
850 <SYSC_ 850 <SYSC_IDLE_SMART>;
851 ti,sysc-sidle = <SYSC_ 851 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
852 <SYSC_ 852 <SYSC_IDLE_NO>,
853 <SYSC_ 853 <SYSC_IDLE_SMART>,
854 <SYSC_ 854 <SYSC_IDLE_SMART_WKUP>;
855 clocks = <&gpu_clkctrl 855 clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>;
856 clock-names = "fck"; 856 clock-names = "fck";
857 #address-cells = <1>; 857 #address-cells = <1>;
858 #size-cells = <1>; 858 #size-cells = <1>;
859 ranges = <0 0x56000000 859 ranges = <0 0x56000000 0x2000000>;
860 860
861 gpu@0 { 861 gpu@0 {
862 compatible = " 862 compatible = "ti,am5728-gpu", "img,powervr-sgx544";
863 reg = <0x0 0x1 863 reg = <0x0 0x10000>; /* 64kB */
864 interrupts = < 864 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
865 }; 865 };
866 }; 866 };
867 867
868 crossbar_mpu: crossbar@4a002a4 868 crossbar_mpu: crossbar@4a002a48 {
869 compatible = "ti,irq-c 869 compatible = "ti,irq-crossbar";
870 reg = <0x4a002a48 0x13 870 reg = <0x4a002a48 0x130>;
871 interrupt-controller; 871 interrupt-controller;
872 interrupt-parent = <&w 872 interrupt-parent = <&wakeupgen>;
873 #interrupt-cells = <3> 873 #interrupt-cells = <3>;
874 ti,max-irqs = <160>; 874 ti,max-irqs = <160>;
875 ti,max-crossbar-source 875 ti,max-crossbar-sources = <MAX_SOURCES>;
876 ti,reg-size = <2>; 876 ti,reg-size = <2>;
877 ti,irqs-reserved = <0 877 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
878 ti,irqs-skip = <10 133 878 ti,irqs-skip = <10 133 139 140>;
879 ti,irqs-safe-map = <0> 879 ti,irqs-safe-map = <0>;
880 }; 880 };
881 881
882 target-module@58000000 { 882 target-module@58000000 {
883 compatible = "ti,sysc- 883 compatible = "ti,sysc-omap2", "ti,sysc";
884 reg = <0x58000000 4>, 884 reg = <0x58000000 4>,
885 <0x58000014 4>; 885 <0x58000014 4>;
886 reg-names = "rev", "sy 886 reg-names = "rev", "syss";
887 ti,syss-mask = <1>; 887 ti,syss-mask = <1>;
888 clocks = <&dss_clkctrl 888 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 0>,
889 <&dss_clkctrl 889 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
890 <&dss_clkctrl 890 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>,
891 <&dss_clkctrl 891 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 11>;
892 clock-names = "fck", " 892 clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
893 #address-cells = <1>; 893 #address-cells = <1>;
894 #size-cells = <1>; 894 #size-cells = <1>;
895 ranges = <0 0x58000000 895 ranges = <0 0x58000000 0x800000>;
896 896
897 dss: dss@0 { 897 dss: dss@0 {
898 compatible = " 898 compatible = "ti,dra7-dss";
899 /* 'reg' defin 899 /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
900 /* 'clocks' de 900 /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
901 status = "disa 901 status = "disabled";
902 /* CTRL_CORE_D 902 /* CTRL_CORE_DSS_PLL_CONTROL */
903 syscon-pll-ctr 903 syscon-pll-ctrl = <&scm_conf 0x538>;
904 #address-cells 904 #address-cells = <1>;
905 #size-cells = 905 #size-cells = <1>;
906 ranges = <0 0 906 ranges = <0 0 0x800000>;
907 907
908 target-module@ 908 target-module@1000 {
909 compat 909 compatible = "ti,sysc-omap2", "ti,sysc";
910 reg = 910 reg = <0x1000 0x4>,
911 911 <0x1010 0x4>,
912 912 <0x1014 0x4>;
913 reg-na 913 reg-names = "rev", "sysc", "syss";
914 ti,sys 914 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
915 915 <SYSC_IDLE_NO>,
916 916 <SYSC_IDLE_SMART>;
917 ti,sys 917 ti,sysc-midle = <SYSC_IDLE_FORCE>,
918 918 <SYSC_IDLE_NO>,
919 919 <SYSC_IDLE_SMART>;
920 ti,sys 920 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
921 921 SYSC_OMAP2_ENAWAKEUP |
922 922 SYSC_OMAP2_SOFTRESET |
923 923 SYSC_OMAP2_AUTOIDLE)>;
924 ti,sys 924 ti,syss-mask = <1>;
925 clocks 925 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
926 clock- 926 clock-names = "fck";
927 #addre 927 #address-cells = <1>;
928 #size- 928 #size-cells = <1>;
929 ranges 929 ranges = <0 0x1000 0x1000>;
930 930
931 dispc@ 931 dispc@0 {
932 932 compatible = "ti,dra7-dispc";
933 933 reg = <0 0x1000>;
934 934 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
935 935 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
936 936 clock-names = "fck";
937 937 /* CTRL_CORE_SMA_SW_1 */
938 938 syscon-pol = <&scm_conf 0x534>;
939 }; 939 };
940 }; 940 };
941 941
942 target-module@ 942 target-module@40000 {
943 compat 943 compatible = "ti,sysc-omap4", "ti,sysc";
944 reg = 944 reg = <0x40000 0x4>,
945 945 <0x40010 0x4>;
946 reg-na 946 reg-names = "rev", "sysc";
947 ti,sys 947 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
948 948 <SYSC_IDLE_NO>,
949 949 <SYSC_IDLE_SMART>,
950 950 <SYSC_IDLE_SMART_WKUP>;
951 ti,sys 951 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
952 clocks 952 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
953 953 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
954 clock- 954 clock-names = "fck", "dss_clk";
955 #addre 955 #address-cells = <1>;
956 #size- 956 #size-cells = <1>;
957 ranges 957 ranges = <0 0x40000 0x40000>;
958 958
959 hdmi: 959 hdmi: encoder@0 {
960 960 compatible = "ti,dra7-hdmi";
961 961 reg = <0 0x200>,
962 962 <0x200 0x80>,
963 963 <0x300 0x80>,
964 964 <0x20000 0x19000>;
965 965 reg-names = "wp", "pll", "phy", "core";
966 966 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
967 967 status = "disabled";
968 968 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
969 969 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>;
970 970 clock-names = "fck", "sys_clk";
971 971 dmas = <&sdma_xbar 76>;
972 972 dma-names = "audio_tx";
973 }; 973 };
974 }; 974 };
975 }; 975 };
976 }; 976 };
977 977
978 target-module@59000000 { 978 target-module@59000000 {
979 compatible = "ti,sysc- 979 compatible = "ti,sysc-omap4", "ti,sysc";
980 reg = <0x59000020 0x4> 980 reg = <0x59000020 0x4>;
981 reg-names = "rev"; 981 reg-names = "rev";
982 clocks = <&dss_clkctrl 982 clocks = <&dss_clkctrl DRA7_DSS_BB2D_CLKCTRL 0>;
983 clock-names = "fck"; 983 clock-names = "fck";
984 #address-cells = <1>; 984 #address-cells = <1>;
985 #size-cells = <1>; 985 #size-cells = <1>;
986 ranges = <0x0 0x590000 986 ranges = <0x0 0x59000000 0x1000>;
987 987
988 bb2d: gpu@0 { 988 bb2d: gpu@0 {
989 compatible = " 989 compatible = "vivante,gc";
990 reg = <0x0 0x7 990 reg = <0x0 0x700>;
991 interrupts = < 991 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
992 clocks = <&dss 992 clocks = <&dss_clkctrl DRA7_DSS_BB2D_CLKCTRL 0>;
993 clock-names = 993 clock-names = "core";
994 }; 994 };
995 }; 995 };
996 996
997 aes1_target: target-module@4b5 997 aes1_target: target-module@4b500000 {
998 compatible = "ti,sysc- 998 compatible = "ti,sysc-omap2", "ti,sysc";
999 reg = <0x4b500080 0x4> 999 reg = <0x4b500080 0x4>,
1000 <0x4b500084 0x4 1000 <0x4b500084 0x4>,
1001 <0x4b500088 0x4 1001 <0x4b500088 0x4>;
1002 reg-names = "rev", "s 1002 reg-names = "rev", "sysc", "syss";
1003 ti,sysc-mask = <(SYSC 1003 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
1004 SYSC 1004 SYSC_OMAP2_AUTOIDLE)>;
1005 ti,sysc-sidle = <SYSC 1005 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1006 <SYSC 1006 <SYSC_IDLE_NO>,
1007 <SYSC 1007 <SYSC_IDLE_SMART>,
1008 <SYSC 1008 <SYSC_IDLE_SMART_WKUP>;
1009 ti,syss-mask = <1>; 1009 ti,syss-mask = <1>;
1010 /* Domains (P, C): pe 1010 /* Domains (P, C): per_pwrdm, l4sec_clkdm */
1011 clocks = <&l4sec_clkc 1011 clocks = <&l4sec_clkctrl DRA7_L4SEC_AES1_CLKCTRL 0>;
1012 clock-names = "fck"; 1012 clock-names = "fck";
1013 #address-cells = <1>; 1013 #address-cells = <1>;
1014 #size-cells = <1>; 1014 #size-cells = <1>;
1015 ranges = <0x0 0x4b500 1015 ranges = <0x0 0x4b500000 0x1000>;
1016 1016
1017 aes1: aes@0 { 1017 aes1: aes@0 {
1018 compatible = 1018 compatible = "ti,omap4-aes";
1019 reg = <0 0xa0 1019 reg = <0 0xa0>;
1020 interrupts = 1020 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1021 dmas = <&edma 1021 dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
1022 dma-names = " 1022 dma-names = "tx", "rx";
1023 clocks = <&l3 1023 clocks = <&l3_iclk_div>;
1024 clock-names = 1024 clock-names = "fck";
1025 }; 1025 };
1026 }; 1026 };
1027 1027
1028 aes2_target: target-module@4b 1028 aes2_target: target-module@4b700000 {
1029 compatible = "ti,sysc 1029 compatible = "ti,sysc-omap2", "ti,sysc";
1030 reg = <0x4b700080 0x4 1030 reg = <0x4b700080 0x4>,
1031 <0x4b700084 0x4 1031 <0x4b700084 0x4>,
1032 <0x4b700088 0x4 1032 <0x4b700088 0x4>;
1033 reg-names = "rev", "s 1033 reg-names = "rev", "sysc", "syss";
1034 ti,sysc-mask = <(SYSC 1034 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
1035 SYSC 1035 SYSC_OMAP2_AUTOIDLE)>;
1036 ti,sysc-sidle = <SYSC 1036 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1037 <SYSC 1037 <SYSC_IDLE_NO>,
1038 <SYSC 1038 <SYSC_IDLE_SMART>,
1039 <SYSC 1039 <SYSC_IDLE_SMART_WKUP>;
1040 ti,syss-mask = <1>; 1040 ti,syss-mask = <1>;
1041 /* Domains (P, C): pe 1041 /* Domains (P, C): per_pwrdm, l4sec_clkdm */
1042 clocks = <&l4sec_clkc 1042 clocks = <&l4sec_clkctrl DRA7_L4SEC_AES2_CLKCTRL 0>;
1043 clock-names = "fck"; 1043 clock-names = "fck";
1044 #address-cells = <1>; 1044 #address-cells = <1>;
1045 #size-cells = <1>; 1045 #size-cells = <1>;
1046 ranges = <0x0 0x4b700 1046 ranges = <0x0 0x4b700000 0x1000>;
1047 1047
1048 aes2: aes@0 { 1048 aes2: aes@0 {
1049 compatible = 1049 compatible = "ti,omap4-aes";
1050 reg = <0 0xa0 1050 reg = <0 0xa0>;
1051 interrupts = 1051 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1052 dmas = <&edma 1052 dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
1053 dma-names = " 1053 dma-names = "tx", "rx";
1054 clocks = <&l3 1054 clocks = <&l3_iclk_div>;
1055 clock-names = 1055 clock-names = "fck";
1056 }; 1056 };
1057 }; 1057 };
1058 1058
1059 sham1_target: target-module@4 1059 sham1_target: target-module@4b101000 {
1060 compatible = "ti,sysc 1060 compatible = "ti,sysc-omap3-sham", "ti,sysc";
1061 reg = <0x4b101100 0x4 1061 reg = <0x4b101100 0x4>,
1062 <0x4b101110 0x4 1062 <0x4b101110 0x4>,
1063 <0x4b101114 0x4 1063 <0x4b101114 0x4>;
1064 reg-names = "rev", "s 1064 reg-names = "rev", "sysc", "syss";
1065 ti,sysc-mask = <(SYSC 1065 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
1066 SYSC 1066 SYSC_OMAP2_AUTOIDLE)>;
1067 ti,sysc-sidle = <SYSC 1067 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1068 <SYSC 1068 <SYSC_IDLE_NO>,
1069 <SYSC 1069 <SYSC_IDLE_SMART>;
1070 ti,syss-mask = <1>; 1070 ti,syss-mask = <1>;
1071 /* Domains (P, C): l4 1071 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
1072 clocks = <&l4sec_clkc 1072 clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM_CLKCTRL 0>;
1073 clock-names = "fck"; 1073 clock-names = "fck";
1074 #address-cells = <1>; 1074 #address-cells = <1>;
1075 #size-cells = <1>; 1075 #size-cells = <1>;
1076 ranges = <0x0 0x4b101 1076 ranges = <0x0 0x4b101000 0x1000>;
1077 1077
1078 sham1: sham@0 { 1078 sham1: sham@0 {
1079 compatible = 1079 compatible = "ti,omap5-sham";
1080 reg = <0 0x30 1080 reg = <0 0x300>;
1081 interrupts = 1081 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1082 dmas = <&edma 1082 dmas = <&edma_xbar 119 0>;
1083 dma-names = " 1083 dma-names = "rx";
1084 clocks = <&l3 1084 clocks = <&l3_iclk_div>;
1085 clock-names = 1085 clock-names = "fck";
1086 }; 1086 };
1087 }; 1087 };
1088 1088
1089 sham2_target: target-module@4 1089 sham2_target: target-module@42701000 {
1090 compatible = "ti,sysc 1090 compatible = "ti,sysc-omap3-sham", "ti,sysc";
1091 reg = <0x42701100 0x4 1091 reg = <0x42701100 0x4>,
1092 <0x42701110 0x4 1092 <0x42701110 0x4>,
1093 <0x42701114 0x4 1093 <0x42701114 0x4>;
1094 reg-names = "rev", "s 1094 reg-names = "rev", "sysc", "syss";
1095 ti,sysc-mask = <(SYSC 1095 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
1096 SYSC 1096 SYSC_OMAP2_AUTOIDLE)>;
1097 ti,sysc-sidle = <SYSC 1097 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1098 <SYSC 1098 <SYSC_IDLE_NO>,
1099 <SYSC 1099 <SYSC_IDLE_SMART>;
1100 ti,syss-mask = <1>; 1100 ti,syss-mask = <1>;
1101 /* Domains (P, C): l4 1101 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
1102 clocks = <&l4sec_clkc 1102 clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM2_CLKCTRL 0>;
1103 clock-names = "fck"; 1103 clock-names = "fck";
1104 #address-cells = <1>; 1104 #address-cells = <1>;
1105 #size-cells = <1>; 1105 #size-cells = <1>;
1106 ranges = <0x0 0x42701 1106 ranges = <0x0 0x42701000 0x1000>;
1107 1107
1108 sham2: sham@0 { 1108 sham2: sham@0 {
1109 compatible = 1109 compatible = "ti,omap5-sham";
1110 reg = <0 0x30 1110 reg = <0 0x300>;
1111 interrupts = 1111 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
1112 dmas = <&edma 1112 dmas = <&edma_xbar 165 0>;
1113 dma-names = " 1113 dma-names = "rx";
1114 clocks = <&l3 1114 clocks = <&l3_iclk_div>;
1115 clock-names = 1115 clock-names = "fck";
1116 }; 1116 };
1117 }; 1117 };
1118 1118
1119 iva_hd_target: target-module@ 1119 iva_hd_target: target-module@5a000000 {
1120 compatible = "ti,sysc 1120 compatible = "ti,sysc-omap4", "ti,sysc";
1121 reg = <0x5a05a400 0x4 1121 reg = <0x5a05a400 0x4>,
1122 <0x5a05a410 0x4 1122 <0x5a05a410 0x4>;
1123 reg-names = "rev", "s 1123 reg-names = "rev", "sysc";
1124 ti,sysc-midle = <SYSC 1124 ti,sysc-midle = <SYSC_IDLE_FORCE>,
1125 <SYSC 1125 <SYSC_IDLE_NO>,
1126 <SYSC 1126 <SYSC_IDLE_SMART>;
1127 ti,sysc-sidle = <SYSC 1127 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1128 <SYSC 1128 <SYSC_IDLE_NO>,
1129 <SYSC 1129 <SYSC_IDLE_SMART>;
1130 power-domains = <&prm 1130 power-domains = <&prm_iva>;
1131 resets = <&prm_iva 2> 1131 resets = <&prm_iva 2>;
1132 reset-names = "rstctr 1132 reset-names = "rstctrl";
1133 clocks = <&iva_clkctr 1133 clocks = <&iva_clkctrl DRA7_IVA_CLKCTRL 0>;
1134 clock-names = "fck"; 1134 clock-names = "fck";
1135 #address-cells = <1>; 1135 #address-cells = <1>;
1136 #size-cells = <1>; 1136 #size-cells = <1>;
1137 ranges = <0x5a000000 1137 ranges = <0x5a000000 0x5a000000 0x1000000>,
1138 <0x5b000000 1138 <0x5b000000 0x5b000000 0x1000000>;
1139 1139
1140 iva { 1140 iva {
1141 compatible = 1141 compatible = "ti,ivahd";
1142 }; 1142 };
1143 }; 1143 };
1144 1144
1145 opp_supply_mpu: opp-supply@4a 1145 opp_supply_mpu: opp-supply@4a003b20 {
1146 compatible = "ti,omap 1146 compatible = "ti,omap5-opp-supply";
1147 reg = <0x4a003b20 0xc 1147 reg = <0x4a003b20 0xc>;
1148 ti,efuse-settings = < 1148 ti,efuse-settings = <
1149 /* uV offset */ 1149 /* uV offset */
1150 1060000 0x0 1150 1060000 0x0
1151 1160000 0x4 1151 1160000 0x4
1152 1210000 0x8 1152 1210000 0x8
1153 >; 1153 >;
1154 ti,absolute-max-volta 1154 ti,absolute-max-voltage-uv = <1500000>;
1155 }; 1155 };
1156 1156
1157 }; 1157 };
1158 1158
1159 thermal_zones: thermal-zones { 1159 thermal_zones: thermal-zones {
1160 #include "omap4-cpu-thermal.d 1160 #include "omap4-cpu-thermal.dtsi"
1161 #include "omap5-gpu-thermal.d 1161 #include "omap5-gpu-thermal.dtsi"
1162 #include "omap5-core-thermal. 1162 #include "omap5-core-thermal.dtsi"
1163 #include "dra7-dspeve-thermal 1163 #include "dra7-dspeve-thermal.dtsi"
1164 #include "dra7-iva-thermal.dt 1164 #include "dra7-iva-thermal.dtsi"
1165 }; 1165 };
1166 1166
1167 }; 1167 };
1168 1168
1169 &cpu_thermal { 1169 &cpu_thermal {
1170 polling-delay = <500>; /* millisecond 1170 polling-delay = <500>; /* milliseconds */
1171 coefficients = <0 2000>; 1171 coefficients = <0 2000>;
1172 }; 1172 };
1173 1173
1174 &gpu_thermal { 1174 &gpu_thermal {
1175 coefficients = <0 2000>; 1175 coefficients = <0 2000>;
1176 }; 1176 };
1177 1177
1178 &core_thermal { 1178 &core_thermal {
1179 coefficients = <0 2000>; 1179 coefficients = <0 2000>;
1180 }; 1180 };
1181 1181
1182 &dspeve_thermal { 1182 &dspeve_thermal {
1183 coefficients = <0 2000>; 1183 coefficients = <0 2000>;
1184 }; 1184 };
1185 1185
1186 &iva_thermal { 1186 &iva_thermal {
1187 coefficients = <0 2000>; 1187 coefficients = <0 2000>;
1188 }; 1188 };
1189 1189
1190 &cpu_crit { 1190 &cpu_crit {
1191 temperature = <120000>; /* milli Cels 1191 temperature = <120000>; /* milli Celsius */
1192 }; 1192 };
1193 1193
1194 &core_crit { 1194 &core_crit {
1195 temperature = <120000>; /* milli Cels 1195 temperature = <120000>; /* milli Celsius */
1196 }; 1196 };
1197 1197
1198 &gpu_crit { 1198 &gpu_crit {
1199 temperature = <120000>; /* milli Cels 1199 temperature = <120000>; /* milli Celsius */
1200 }; 1200 };
1201 1201
1202 &dspeve_crit { 1202 &dspeve_crit {
1203 temperature = <120000>; /* milli Cels 1203 temperature = <120000>; /* milli Celsius */
1204 }; 1204 };
1205 1205
1206 &iva_crit { 1206 &iva_crit {
1207 temperature = <120000>; /* milli Cels 1207 temperature = <120000>; /* milli Celsius */
1208 }; 1208 };
1209 1209
1210 #include "dra7-l4.dtsi" 1210 #include "dra7-l4.dtsi"
1211 #include "dra7xx-clocks.dtsi" 1211 #include "dra7xx-clocks.dtsi"
1212 1212
1213 &prm { 1213 &prm {
1214 prm_mpu: prm@300 { 1214 prm_mpu: prm@300 {
1215 compatible = "ti,dra7-prm-ins 1215 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1216 reg = <0x300 0x100>; 1216 reg = <0x300 0x100>;
1217 #power-domain-cells = <0>; 1217 #power-domain-cells = <0>;
1218 }; 1218 };
1219 1219
1220 prm_dsp1: prm@400 { 1220 prm_dsp1: prm@400 {
1221 compatible = "ti,dra7-prm-ins 1221 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1222 reg = <0x400 0x100>; 1222 reg = <0x400 0x100>;
1223 #reset-cells = <1>; 1223 #reset-cells = <1>;
1224 #power-domain-cells = <0>; 1224 #power-domain-cells = <0>;
1225 }; 1225 };
1226 1226
1227 prm_ipu: prm@500 { 1227 prm_ipu: prm@500 {
1228 compatible = "ti,dra7-prm-ins 1228 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1229 reg = <0x500 0x100>; 1229 reg = <0x500 0x100>;
1230 #reset-cells = <1>; 1230 #reset-cells = <1>;
1231 #power-domain-cells = <0>; 1231 #power-domain-cells = <0>;
1232 }; 1232 };
1233 1233
1234 prm_coreaon: prm@628 { 1234 prm_coreaon: prm@628 {
1235 compatible = "ti,dra7-prm-ins 1235 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1236 reg = <0x628 0xd8>; 1236 reg = <0x628 0xd8>;
1237 #power-domain-cells = <0>; 1237 #power-domain-cells = <0>;
1238 }; 1238 };
1239 1239
1240 prm_core: prm@700 { 1240 prm_core: prm@700 {
1241 compatible = "ti,dra7-prm-ins 1241 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1242 reg = <0x700 0x100>; 1242 reg = <0x700 0x100>;
1243 #reset-cells = <1>; 1243 #reset-cells = <1>;
1244 #power-domain-cells = <0>; 1244 #power-domain-cells = <0>;
1245 }; 1245 };
1246 1246
1247 prm_iva: prm@f00 { 1247 prm_iva: prm@f00 {
1248 compatible = "ti,dra7-prm-ins 1248 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1249 reg = <0xf00 0x100>; 1249 reg = <0xf00 0x100>;
1250 #reset-cells = <1>; 1250 #reset-cells = <1>;
1251 #power-domain-cells = <0>; 1251 #power-domain-cells = <0>;
1252 }; 1252 };
1253 1253
1254 prm_cam: prm@1000 { 1254 prm_cam: prm@1000 {
1255 compatible = "ti,dra7-prm-ins 1255 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1256 reg = <0x1000 0x100>; 1256 reg = <0x1000 0x100>;
1257 #power-domain-cells = <0>; 1257 #power-domain-cells = <0>;
1258 }; 1258 };
1259 1259
1260 prm_dss: prm@1100 { 1260 prm_dss: prm@1100 {
1261 compatible = "ti,dra7-prm-ins 1261 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1262 reg = <0x1100 0x100>; 1262 reg = <0x1100 0x100>;
1263 #power-domain-cells = <0>; 1263 #power-domain-cells = <0>;
1264 }; 1264 };
1265 1265
1266 prm_gpu: prm@1200 { 1266 prm_gpu: prm@1200 {
1267 compatible = "ti,dra7-prm-ins 1267 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1268 reg = <0x1200 0x100>; 1268 reg = <0x1200 0x100>;
1269 #power-domain-cells = <0>; 1269 #power-domain-cells = <0>;
1270 }; 1270 };
1271 1271
1272 prm_l3init: prm@1300 { 1272 prm_l3init: prm@1300 {
1273 compatible = "ti,dra7-prm-ins 1273 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1274 reg = <0x1300 0x100>; 1274 reg = <0x1300 0x100>;
1275 #reset-cells = <1>; 1275 #reset-cells = <1>;
1276 #power-domain-cells = <0>; 1276 #power-domain-cells = <0>;
1277 }; 1277 };
1278 1278
1279 prm_l4per: prm@1400 { 1279 prm_l4per: prm@1400 {
1280 compatible = "ti,dra7-prm-ins 1280 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1281 reg = <0x1400 0x100>; 1281 reg = <0x1400 0x100>;
1282 #power-domain-cells = <0>; 1282 #power-domain-cells = <0>;
1283 }; 1283 };
1284 1284
1285 prm_custefuse: prm@1600 { 1285 prm_custefuse: prm@1600 {
1286 compatible = "ti,dra7-prm-ins 1286 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1287 reg = <0x1600 0x100>; 1287 reg = <0x1600 0x100>;
1288 #power-domain-cells = <0>; 1288 #power-domain-cells = <0>;
1289 }; 1289 };
1290 1290
1291 prm_wkupaon: prm@1724 { 1291 prm_wkupaon: prm@1724 {
1292 compatible = "ti,dra7-prm-ins 1292 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1293 reg = <0x1724 0x100>; 1293 reg = <0x1724 0x100>;
1294 #power-domain-cells = <0>; 1294 #power-domain-cells = <0>;
1295 }; 1295 };
1296 1296
1297 prm_dsp2: prm@1b00 { 1297 prm_dsp2: prm@1b00 {
1298 compatible = "ti,dra7-prm-ins 1298 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1299 reg = <0x1b00 0x40>; 1299 reg = <0x1b00 0x40>;
1300 #reset-cells = <1>; 1300 #reset-cells = <1>;
1301 #power-domain-cells = <0>; 1301 #power-domain-cells = <0>;
1302 }; 1302 };
1303 1303
1304 prm_eve1: prm@1b40 { 1304 prm_eve1: prm@1b40 {
1305 compatible = "ti,dra7-prm-ins 1305 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1306 reg = <0x1b40 0x40>; 1306 reg = <0x1b40 0x40>;
1307 #power-domain-cells = <0>; 1307 #power-domain-cells = <0>;
1308 }; 1308 };
1309 1309
1310 prm_eve2: prm@1b80 { 1310 prm_eve2: prm@1b80 {
1311 compatible = "ti,dra7-prm-ins 1311 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1312 reg = <0x1b80 0x40>; 1312 reg = <0x1b80 0x40>;
1313 #power-domain-cells = <0>; 1313 #power-domain-cells = <0>;
1314 }; 1314 };
1315 1315
1316 prm_eve3: prm@1bc0 { 1316 prm_eve3: prm@1bc0 {
1317 compatible = "ti,dra7-prm-ins 1317 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1318 reg = <0x1bc0 0x40>; 1318 reg = <0x1bc0 0x40>;
1319 #power-domain-cells = <0>; 1319 #power-domain-cells = <0>;
1320 }; 1320 };
1321 1321
1322 prm_eve4: prm@1c00 { 1322 prm_eve4: prm@1c00 {
1323 compatible = "ti,dra7-prm-ins 1323 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1324 reg = <0x1c00 0x60>; 1324 reg = <0x1c00 0x60>;
1325 #power-domain-cells = <0>; 1325 #power-domain-cells = <0>;
1326 }; 1326 };
1327 1327
1328 prm_rtc: prm@1c60 { 1328 prm_rtc: prm@1c60 {
1329 compatible = "ti,dra7-prm-ins 1329 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1330 reg = <0x1c60 0x20>; 1330 reg = <0x1c60 0x20>;
1331 #power-domain-cells = <0>; 1331 #power-domain-cells = <0>;
1332 }; 1332 };
1333 1333
1334 prm_vpe: prm@1c80 { 1334 prm_vpe: prm@1c80 {
1335 compatible = "ti,dra7-prm-ins 1335 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1336 reg = <0x1c80 0x80>; 1336 reg = <0x1c80 0x80>;
1337 #power-domain-cells = <0>; 1337 #power-domain-cells = <0>;
1338 }; 1338 };
1339 }; 1339 };
1340 1340
1341 /* Preferred always-on timer for clockevent * 1341 /* Preferred always-on timer for clockevent */
1342 &timer1_target { 1342 &timer1_target {
1343 ti,no-reset-on-init; 1343 ti,no-reset-on-init;
1344 ti,no-idle; 1344 ti,no-idle;
1345 timer@0 { 1345 timer@0 {
1346 assigned-clocks = <&wkupaon_c 1346 assigned-clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>;
1347 assigned-clock-parents = <&sy 1347 assigned-clock-parents = <&sys_32k_ck>;
1348 }; 1348 };
1349 }; 1349 };
1350 1350
1351 /* Local timers, see ARM architected timer wr 1351 /* Local timers, see ARM architected timer wrap erratum i940 */
1352 &timer15_target { 1352 &timer15_target {
1353 ti,no-reset-on-init; 1353 ti,no-reset-on-init;
1354 ti,no-idle; 1354 ti,no-idle;
1355 timer@0 { 1355 timer@0 {
1356 assigned-clocks = <&l4per3_cl 1356 assigned-clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>;
1357 assigned-clock-parents = <&ti 1357 assigned-clock-parents = <&timer_sys_clk_div>;
1358 }; 1358 };
1359 }; 1359 };
1360 1360
1361 &timer16_target { 1361 &timer16_target {
1362 ti,no-reset-on-init; 1362 ti,no-reset-on-init;
1363 ti,no-idle; 1363 ti,no-idle;
1364 timer@0 { 1364 timer@0 {
1365 assigned-clocks = <&l4per3_cl 1365 assigned-clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>;
1366 assigned-clock-parents = <&ti 1366 assigned-clock-parents = <&timer_sys_clk_div>;
1367 }; 1367 };
1368 }; 1368 };
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