1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * Device Tree Source for OMAP3430 ES1 clock d 3 * Device Tree Source for OMAP3430 ES1 clock data
4 * 4 *
5 * Copyright (C) 2013 Texas Instruments, Inc. 5 * Copyright (C) 2013 Texas Instruments, Inc.
6 */ 6 */
7 &cm_clocks { 7 &cm_clocks {
8 gfx_l3_ck: gfx_l3_ck@b10 { 8 gfx_l3_ck: gfx_l3_ck@b10 {
9 #clock-cells = <0>; 9 #clock-cells = <0>;
10 compatible = "ti,wait-gate-clo 10 compatible = "ti,wait-gate-clock";
11 clocks = <&l3_ick>; 11 clocks = <&l3_ick>;
12 reg = <0x0b10>; 12 reg = <0x0b10>;
13 ti,bit-shift = <0>; 13 ti,bit-shift = <0>;
14 }; 14 };
15 15
16 gfx_l3_fck: gfx_l3_fck@b40 { 16 gfx_l3_fck: gfx_l3_fck@b40 {
17 #clock-cells = <0>; 17 #clock-cells = <0>;
18 compatible = "ti,divider-clock 18 compatible = "ti,divider-clock";
19 clocks = <&l3_ick>; 19 clocks = <&l3_ick>;
20 ti,max-div = <7>; 20 ti,max-div = <7>;
21 reg = <0x0b40>; 21 reg = <0x0b40>;
22 ti,index-starts-at-one; 22 ti,index-starts-at-one;
23 }; 23 };
24 24
25 gfx_l3_ick: gfx_l3_ick { 25 gfx_l3_ick: gfx_l3_ick {
26 #clock-cells = <0>; 26 #clock-cells = <0>;
27 compatible = "fixed-factor-clo 27 compatible = "fixed-factor-clock";
28 clocks = <&gfx_l3_ck>; 28 clocks = <&gfx_l3_ck>;
29 clock-mult = <1>; 29 clock-mult = <1>;
30 clock-div = <1>; 30 clock-div = <1>;
31 }; 31 };
32 32
33 gfx_cg1_ck: gfx_cg1_ck@b00 { 33 gfx_cg1_ck: gfx_cg1_ck@b00 {
34 #clock-cells = <0>; 34 #clock-cells = <0>;
35 compatible = "ti,wait-gate-clo 35 compatible = "ti,wait-gate-clock";
36 clocks = <&gfx_l3_fck>; 36 clocks = <&gfx_l3_fck>;
37 reg = <0x0b00>; 37 reg = <0x0b00>;
38 ti,bit-shift = <1>; 38 ti,bit-shift = <1>;
39 }; 39 };
40 40
41 gfx_cg2_ck: gfx_cg2_ck@b00 { 41 gfx_cg2_ck: gfx_cg2_ck@b00 {
42 #clock-cells = <0>; 42 #clock-cells = <0>;
43 compatible = "ti,wait-gate-clo 43 compatible = "ti,wait-gate-clock";
44 clocks = <&gfx_l3_fck>; 44 clocks = <&gfx_l3_fck>;
45 reg = <0x0b00>; 45 reg = <0x0b00>;
46 ti,bit-shift = <2>; 46 ti,bit-shift = <2>;
47 }; 47 };
48 48
49 clock@a00 { 49 clock@a00 {
50 compatible = "ti,clksel"; 50 compatible = "ti,clksel";
51 reg = <0xa00>; 51 reg = <0xa00>;
52 #clock-cells = <2>; 52 #clock-cells = <2>;
53 #address-cells = <1>; 53 #address-cells = <1>;
54 #size-cells = <0>; 54 #size-cells = <0>;
55 55
56 d2d_26m_fck: clock-d2d-26m-fck 56 d2d_26m_fck: clock-d2d-26m-fck@3 {
57 reg = <3>; 57 reg = <3>;
58 #clock-cells = <0>; 58 #clock-cells = <0>;
59 compatible = "ti,wait- 59 compatible = "ti,wait-gate-clock";
60 clock-output-names = " 60 clock-output-names = "d2d_26m_fck";
61 clocks = <&sys_ck>; 61 clocks = <&sys_ck>;
62 }; 62 };
63 63
64 fshostusb_fck: clock-fshostusb 64 fshostusb_fck: clock-fshostusb-fck@5 {
65 reg = <5>; 65 reg = <5>;
66 #clock-cells = <0>; 66 #clock-cells = <0>;
67 compatible = "ti,wait- 67 compatible = "ti,wait-gate-clock";
68 clock-output-names = " 68 clock-output-names = "fshostusb_fck";
69 clocks = <&core_48m_fc 69 clocks = <&core_48m_fck>;
70 }; 70 };
71 71
72 ssi_ssr_gate_fck_3430es1: cloc 72 ssi_ssr_gate_fck_3430es1: clock-ssi-ssr-gate-fck-3430es1@0 {
73 reg = <0>; 73 reg = <0>;
74 #clock-cells = <0>; 74 #clock-cells = <0>;
75 compatible = "ti,compo 75 compatible = "ti,composite-no-wait-gate-clock";
76 clock-output-names = " 76 clock-output-names = "ssi_ssr_gate_fck_3430es1";
77 clocks = <&corex2_fck> 77 clocks = <&corex2_fck>;
78 }; 78 };
79 }; 79 };
80 80
81 clock@a40 { 81 clock@a40 {
82 compatible = "ti,clksel"; 82 compatible = "ti,clksel";
83 reg = <0xa40>; 83 reg = <0xa40>;
84 #clock-cells = <2>; 84 #clock-cells = <2>;
85 #address-cells = <1>; 85 #address-cells = <1>;
86 #size-cells = <0>; 86 #size-cells = <0>;
87 87
88 ssi_ssr_div_fck_3430es1: clock 88 ssi_ssr_div_fck_3430es1: clock-ssi-ssr-div-fck-3430es1@8 {
89 reg = <8>; 89 reg = <8>;
90 #clock-cells = <0>; 90 #clock-cells = <0>;
91 compatible = "ti,compo 91 compatible = "ti,composite-divider-clock";
92 clock-output-names = " 92 clock-output-names = "ssi_ssr_div_fck_3430es1";
93 clocks = <&corex2_fck> 93 clocks = <&corex2_fck>;
94 ti,dividers = <0>, <1> 94 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
95 }; 95 };
96 96
97 usb_l4_div_ick: clock-usb-l4-d 97 usb_l4_div_ick: clock-usb-l4-div-ick@4 {
98 reg = <4>; 98 reg = <4>;
99 #clock-cells = <0>; 99 #clock-cells = <0>;
100 compatible = "ti,compo 100 compatible = "ti,composite-divider-clock";
101 clock-output-names = " 101 clock-output-names = "usb_l4_div_ick";
102 clocks = <&l4_ick>; 102 clocks = <&l4_ick>;
103 ti,max-div = <1>; 103 ti,max-div = <1>;
104 ti,index-starts-at-one 104 ti,index-starts-at-one;
105 }; 105 };
106 }; 106 };
107 107
108 ssi_ssr_fck: ssi_ssr_fck_3430es1 { 108 ssi_ssr_fck: ssi_ssr_fck_3430es1 {
109 #clock-cells = <0>; 109 #clock-cells = <0>;
110 compatible = "ti,composite-clo 110 compatible = "ti,composite-clock";
111 clocks = <&ssi_ssr_gate_fck_34 111 clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>;
112 }; 112 };
113 113
114 ssi_sst_fck: ssi_sst_fck_3430es1 { 114 ssi_sst_fck: ssi_sst_fck_3430es1 {
115 #clock-cells = <0>; 115 #clock-cells = <0>;
116 compatible = "fixed-factor-clo 116 compatible = "fixed-factor-clock";
117 clocks = <&ssi_ssr_fck>; 117 clocks = <&ssi_ssr_fck>;
118 clock-mult = <1>; 118 clock-mult = <1>;
119 clock-div = <2>; 119 clock-div = <2>;
120 }; 120 };
121 121
122 clock@a10 { 122 clock@a10 {
123 compatible = "ti,clksel"; 123 compatible = "ti,clksel";
124 reg = <0xa10>; 124 reg = <0xa10>;
125 #clock-cells = <2>; 125 #clock-cells = <2>;
126 #address-cells = <1>; 126 #address-cells = <1>;
127 #size-cells = <0>; 127 #size-cells = <0>;
128 128
129 hsotgusb_ick_3430es1: clock-hs 129 hsotgusb_ick_3430es1: clock-hsotgusb-ick-3430es1@4 {
130 reg = <4>; 130 reg = <4>;
131 #clock-cells = <0>; 131 #clock-cells = <0>;
132 compatible = "ti,omap3 132 compatible = "ti,omap3-no-wait-interface-clock";
133 clock-output-names = " 133 clock-output-names = "hsotgusb_ick_3430es1";
134 clocks = <&core_l3_ick 134 clocks = <&core_l3_ick>;
135 }; 135 };
136 136
137 fac_ick: clock-fac-ick@8 { 137 fac_ick: clock-fac-ick@8 {
138 reg = <8>; 138 reg = <8>;
139 #clock-cells = <0>; 139 #clock-cells = <0>;
140 compatible = "ti,omap3 140 compatible = "ti,omap3-interface-clock";
141 clock-output-names = " 141 clock-output-names = "fac_ick";
142 clocks = <&core_l4_ick 142 clocks = <&core_l4_ick>;
143 }; 143 };
144 144
145 ssi_ick: clock-ssi-ick-3430es1 145 ssi_ick: clock-ssi-ick-3430es1@0 {
146 reg = <0>; 146 reg = <0>;
147 #clock-cells = <0>; 147 #clock-cells = <0>;
148 compatible = "ti,omap3 148 compatible = "ti,omap3-no-wait-interface-clock";
149 clock-output-names = " 149 clock-output-names = "ssi_ick_3430es1";
150 clocks = <&ssi_l4_ick> 150 clocks = <&ssi_l4_ick>;
151 }; 151 };
152 152
153 usb_l4_gate_ick: clock-usb-l4- 153 usb_l4_gate_ick: clock-usb-l4-gate-ick@5 {
154 reg = <5>; 154 reg = <5>;
155 #clock-cells = <0>; 155 #clock-cells = <0>;
156 compatible = "ti,compo 156 compatible = "ti,composite-interface-clock";
157 clock-output-names = " 157 clock-output-names = "usb_l4_gate_ick";
158 clocks = <&l4_ick>; 158 clocks = <&l4_ick>;
159 }; 159 };
160 }; 160 };
161 161
162 ssi_l4_ick: ssi_l4_ick { 162 ssi_l4_ick: ssi_l4_ick {
163 #clock-cells = <0>; 163 #clock-cells = <0>;
164 compatible = "fixed-factor-clo 164 compatible = "fixed-factor-clock";
165 clocks = <&l4_ick>; 165 clocks = <&l4_ick>;
166 clock-mult = <1>; 166 clock-mult = <1>;
167 clock-div = <1>; 167 clock-div = <1>;
168 }; 168 };
169 169
170 usb_l4_ick: usb_l4_ick { 170 usb_l4_ick: usb_l4_ick {
171 #clock-cells = <0>; 171 #clock-cells = <0>;
172 compatible = "ti,composite-clo 172 compatible = "ti,composite-clock";
173 clocks = <&usb_l4_gate_ick>, < 173 clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
174 }; 174 };
175 175
176 clock@e00 { 176 clock@e00 {
177 compatible = "ti,clksel"; 177 compatible = "ti,clksel";
178 reg = <0xe00>; 178 reg = <0xe00>;
179 #clock-cells = <2>; 179 #clock-cells = <2>;
180 #address-cells = <1>; 180 #address-cells = <1>;
181 #size-cells = <0>; 181 #size-cells = <0>;
182 182
183 dss1_alwon_fck: clock-dss1-alw 183 dss1_alwon_fck: clock-dss1-alwon-fck-3430es1@0 {
184 reg = <0>; 184 reg = <0>;
185 #clock-cells = <0>; 185 #clock-cells = <0>;
186 compatible = "ti,gate- 186 compatible = "ti,gate-clock";
187 clock-output-names = " 187 clock-output-names = "dss1_alwon_fck_3430es1";
188 clocks = <&dpll4_m4x2_ 188 clocks = <&dpll4_m4x2_ck>;
189 ti,set-rate-parent; 189 ti,set-rate-parent;
190 }; 190 };
191 }; 191 };
192 192
193 dss_ick: dss_ick_3430es1@e10 { 193 dss_ick: dss_ick_3430es1@e10 {
194 #clock-cells = <0>; 194 #clock-cells = <0>;
195 compatible = "ti,omap3-no-wait 195 compatible = "ti,omap3-no-wait-interface-clock";
196 clocks = <&l4_ick>; 196 clocks = <&l4_ick>;
197 reg = <0x0e10>; 197 reg = <0x0e10>;
198 ti,bit-shift = <0>; 198 ti,bit-shift = <0>;
199 }; 199 };
200 }; 200 };
201 201
202 &cm_clockdomains { 202 &cm_clockdomains {
203 core_l3_clkdm: core_l3_clkdm { 203 core_l3_clkdm: core_l3_clkdm {
204 compatible = "ti,clockdomain"; 204 compatible = "ti,clockdomain";
205 clocks = <&sdrc_ick>, <&hsotgu 205 clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es1>;
206 }; 206 };
207 207
208 gfx_3430es1_clkdm: gfx_3430es1_clkdm { 208 gfx_3430es1_clkdm: gfx_3430es1_clkdm {
209 compatible = "ti,clockdomain"; 209 compatible = "ti,clockdomain";
210 clocks = <&gfx_l3_ck>, <&gfx_c 210 clocks = <&gfx_l3_ck>, <&gfx_cg1_ck>, <&gfx_cg2_ck>;
211 }; 211 };
212 212
213 dss_clkdm: dss_clkdm { 213 dss_clkdm: dss_clkdm {
214 compatible = "ti,clockdomain"; 214 compatible = "ti,clockdomain";
215 clocks = <&dss_tv_fck>, <&dss_ 215 clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
216 <&dss1_alwon_fck>, <& 216 <&dss1_alwon_fck>, <&dss_ick>;
217 }; 217 };
218 218
219 d2d_clkdm: d2d_clkdm { 219 d2d_clkdm: d2d_clkdm {
220 compatible = "ti,clockdomain"; 220 compatible = "ti,clockdomain";
221 clocks = <&d2d_26m_fck>; 221 clocks = <&d2d_26m_fck>;
222 }; 222 };
223 223
224 core_l4_clkdm: core_l4_clkdm { 224 core_l4_clkdm: core_l4_clkdm {
225 compatible = "ti,clockdomain"; 225 compatible = "ti,clockdomain";
226 clocks = <&mmchs2_fck>, <&mmch 226 clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
227 <&i2c1_fck>, <&mcspi4 227 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
228 <&mcspi2_fck>, <&mcsp 228 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
229 <&uart1_fck>, <&hdq_f 229 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
230 <&hdq_ick>, <&mcspi4_ 230 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
231 <&mcspi2_ick>, <&mcsp 231 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
232 <&i2c1_ick>, <&uart2_ 232 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
233 <&gpt10_ick>, <&mcbsp 233 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
234 <&omapctrl_ick>, <&ae 234 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
235 <&fshostusb_fck>, <&f 235 <&fshostusb_fck>, <&fac_ick>, <&ssi_ick>;
236 }; 236 };
237 }; 237 };
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