1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * Device Tree Source for OMAP36xx clock data 3 * Device Tree Source for OMAP36xx clock data
4 * 4 *
5 * Copyright (C) 2013 Texas Instruments, Inc. 5 * Copyright (C) 2013 Texas Instruments, Inc.
6 */ 6 */
7 &cm_clocks { 7 &cm_clocks {
8 dpll4_ck: dpll4_ck@d00 { 8 dpll4_ck: dpll4_ck@d00 {
9 #clock-cells = <0>; 9 #clock-cells = <0>;
10 compatible = "ti,omap3-dpll-pe 10 compatible = "ti,omap3-dpll-per-j-type-clock";
11 clocks = <&sys_ck>, <&sys_ck>; 11 clocks = <&sys_ck>, <&sys_ck>;
12 reg = <0x0d00>, <0x0d20>, <0x0 12 reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
13 }; 13 };
14 14
15 dpll4_m5x2_ck: dpll4_m5x2_ck@d00 { 15 dpll4_m5x2_ck: dpll4_m5x2_ck@d00 {
16 #clock-cells = <0>; 16 #clock-cells = <0>;
17 compatible = "ti,hsdiv-gate-cl 17 compatible = "ti,hsdiv-gate-clock";
18 clocks = <&dpll4_m5x2_mul_ck>; 18 clocks = <&dpll4_m5x2_mul_ck>;
19 ti,bit-shift = <0x1e>; 19 ti,bit-shift = <0x1e>;
20 reg = <0x0d00>; 20 reg = <0x0d00>;
21 ti,set-rate-parent; 21 ti,set-rate-parent;
22 ti,set-bit-to-disable; 22 ti,set-bit-to-disable;
23 }; 23 };
24 24
25 dpll4_m2x2_ck: dpll4_m2x2_ck@d00 { 25 dpll4_m2x2_ck: dpll4_m2x2_ck@d00 {
26 #clock-cells = <0>; 26 #clock-cells = <0>;
27 compatible = "ti,hsdiv-gate-cl 27 compatible = "ti,hsdiv-gate-clock";
28 clocks = <&dpll4_m2x2_mul_ck>; 28 clocks = <&dpll4_m2x2_mul_ck>;
29 ti,bit-shift = <0x1b>; 29 ti,bit-shift = <0x1b>;
30 reg = <0x0d00>; 30 reg = <0x0d00>;
31 ti,set-bit-to-disable; 31 ti,set-bit-to-disable;
32 }; 32 };
33 33
34 dpll3_m3x2_ck: dpll3_m3x2_ck@d00 { 34 dpll3_m3x2_ck: dpll3_m3x2_ck@d00 {
35 #clock-cells = <0>; 35 #clock-cells = <0>;
36 compatible = "ti,hsdiv-gate-cl 36 compatible = "ti,hsdiv-gate-clock";
37 clocks = <&dpll3_m3x2_mul_ck>; 37 clocks = <&dpll3_m3x2_mul_ck>;
38 ti,bit-shift = <0xc>; 38 ti,bit-shift = <0xc>;
39 reg = <0x0d00>; 39 reg = <0x0d00>;
40 ti,set-bit-to-disable; 40 ti,set-bit-to-disable;
41 }; 41 };
42 42
43 dpll4_m3x2_ck: dpll4_m3x2_ck@d00 { 43 dpll4_m3x2_ck: dpll4_m3x2_ck@d00 {
44 #clock-cells = <0>; 44 #clock-cells = <0>;
45 compatible = "ti,hsdiv-gate-cl 45 compatible = "ti,hsdiv-gate-clock";
46 clocks = <&dpll4_m3x2_mul_ck>; 46 clocks = <&dpll4_m3x2_mul_ck>;
47 ti,bit-shift = <0x1c>; 47 ti,bit-shift = <0x1c>;
48 reg = <0x0d00>; 48 reg = <0x0d00>;
49 ti,set-bit-to-disable; 49 ti,set-bit-to-disable;
50 }; 50 };
51 51
52 dpll4_m6x2_ck: dpll4_m6x2_ck@d00 { 52 dpll4_m6x2_ck: dpll4_m6x2_ck@d00 {
53 #clock-cells = <0>; 53 #clock-cells = <0>;
54 compatible = "ti,hsdiv-gate-cl 54 compatible = "ti,hsdiv-gate-clock";
55 clocks = <&dpll4_m6x2_mul_ck>; 55 clocks = <&dpll4_m6x2_mul_ck>;
56 ti,bit-shift = <0x1f>; 56 ti,bit-shift = <0x1f>;
57 reg = <0x0d00>; 57 reg = <0x0d00>;
58 ti,set-bit-to-disable; 58 ti,set-bit-to-disable;
59 }; 59 };
60 60
61 clock@1000 { 61 clock@1000 {
62 compatible = "ti,clksel"; 62 compatible = "ti,clksel";
63 reg = <0x1000>; 63 reg = <0x1000>;
64 #clock-cells = <2>; 64 #clock-cells = <2>;
65 #address-cells = <1>; 65 #address-cells = <1>;
66 #size-cells = <0>; 66 #size-cells = <0>;
67 67
68 uart4_fck: clock-uart4-fck@18 68 uart4_fck: clock-uart4-fck@18 {
69 reg = <18>; 69 reg = <18>;
70 #clock-cells = <0>; 70 #clock-cells = <0>;
71 compatible = "ti,wait- 71 compatible = "ti,wait-gate-clock";
72 clock-output-names = " 72 clock-output-names = "uart4_fck";
73 clocks = <&per_48m_fck 73 clocks = <&per_48m_fck>;
74 }; 74 };
75 }; 75 };
76 }; 76 };
77 77
78 &dpll4_m2x2_mul_ck { 78 &dpll4_m2x2_mul_ck {
79 clock-mult = <1>; 79 clock-mult = <1>;
80 }; 80 };
81 81
82 &dpll4_m3x2_mul_ck { 82 &dpll4_m3x2_mul_ck {
83 clock-mult = <1>; 83 clock-mult = <1>;
84 }; 84 };
85 85
86 &dpll4_m4x2_mul_ck { 86 &dpll4_m4x2_mul_ck {
87 ti,clock-mult = <1>; 87 ti,clock-mult = <1>;
88 }; 88 };
89 89
90 &dpll4_m5x2_mul_ck { 90 &dpll4_m5x2_mul_ck {
91 ti,clock-mult = <1>; 91 ti,clock-mult = <1>;
92 }; 92 };
93 93
94 &dpll4_m6x2_mul_ck { 94 &dpll4_m6x2_mul_ck {
95 clock-mult = <1>; 95 clock-mult = <1>;
96 }; 96 };
97 97
98 &cm_clockdomains { 98 &cm_clockdomains {
99 dpll4_clkdm: dpll4_clkdm { 99 dpll4_clkdm: dpll4_clkdm {
100 compatible = "ti,clockdomain"; 100 compatible = "ti,clockdomain";
101 clocks = <&dpll4_ck>; 101 clocks = <&dpll4_ck>;
102 }; 102 };
103 103
104 per_clkdm: per_clkdm { 104 per_clkdm: per_clkdm {
105 compatible = "ti,clockdomain"; 105 compatible = "ti,clockdomain";
106 clocks = <&uart3_fck>, <&gpio6 106 clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
107 <&gpio4_dbck>, <&gpio 107 <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
108 <&wdt3_fck>, <&gpio6_ 108 <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
109 <&gpio3_ick>, <&gpio2 109 <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
110 <&uart4_ick>, <&gpt9_ 110 <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
111 <&gpt6_ick>, <&gpt5_i 111 <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
112 <&gpt2_ick>, <&mcbsp2 112 <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
113 <&mcbsp4_ick>, <&uart 113 <&mcbsp4_ick>, <&uart4_fck>;
114 }; 114 };
115 }; 115 };
116 116
117 &dpll4_m4_ck { 117 &dpll4_m4_ck {
118 ti,max-div = <31>; 118 ti,max-div = <31>;
119 }; 119 };
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