1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 &l4_cfg { 2 &l4_cfg { /* 0x4a000000 */
3 compatible = "ti,omap4-l4-cfg", "simpl 3 compatible = "ti,omap4-l4-cfg", "simple-pm-bus";
4 power-domains = <&prm_core>; 4 power-domains = <&prm_core>;
5 clocks = <&l4_cfg_clkctrl OMAP4_L4_CFG 5 clocks = <&l4_cfg_clkctrl OMAP4_L4_CFG_CLKCTRL 0>;
6 clock-names = "fck"; 6 clock-names = "fck";
7 reg = <0x4a000000 0x800>, 7 reg = <0x4a000000 0x800>,
8 <0x4a000800 0x800>, 8 <0x4a000800 0x800>,
9 <0x4a001000 0x1000>; 9 <0x4a001000 0x1000>;
10 reg-names = "ap", "la", "ia0"; 10 reg-names = "ap", "la", "ia0";
11 #address-cells = <1>; 11 #address-cells = <1>;
12 #size-cells = <1>; 12 #size-cells = <1>;
13 ranges = <0x00000000 0x4a000000 0x0800 13 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
14 <0x00080000 0x4a080000 0x0800 14 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
15 <0x00100000 0x4a100000 0x0800 15 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
16 <0x00180000 0x4a180000 0x0800 16 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
17 <0x00200000 0x4a200000 0x0800 17 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
18 <0x00280000 0x4a280000 0x0800 18 <0x00280000 0x4a280000 0x080000>, /* segment 5 */
19 <0x00300000 0x4a300000 0x0800 19 <0x00300000 0x4a300000 0x080000>; /* segment 6 */
20 20
21 segment@0 { 21 segment@0 { /* 0x4a000000 */
22 compatible = "simple-pm-bus"; 22 compatible = "simple-pm-bus";
23 #address-cells = <1>; 23 #address-cells = <1>;
24 #size-cells = <1>; 24 #size-cells = <1>;
25 ranges = <0x00000000 0x0000000 25 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
26 <0x00001000 0x0000100 26 <0x00001000 0x00001000 0x001000>, /* ap 1 */
27 <0x00000800 0x0000080 27 <0x00000800 0x00000800 0x000800>, /* ap 2 */
28 <0x00002000 0x0000200 28 <0x00002000 0x00002000 0x001000>, /* ap 3 */
29 <0x00003000 0x0000300 29 <0x00003000 0x00003000 0x001000>, /* ap 4 */
30 <0x00004000 0x0000400 30 <0x00004000 0x00004000 0x001000>, /* ap 5 */
31 <0x00005000 0x0000500 31 <0x00005000 0x00005000 0x001000>, /* ap 6 */
32 <0x00056000 0x0005600 32 <0x00056000 0x00056000 0x001000>, /* ap 7 */
33 <0x00057000 0x0005700 33 <0x00057000 0x00057000 0x001000>, /* ap 8 */
34 <0x0005c000 0x0005c00 34 <0x0005c000 0x0005c000 0x001000>, /* ap 9 */
35 <0x00058000 0x0005800 35 <0x00058000 0x00058000 0x004000>, /* ap 10 */
36 <0x00062000 0x0006200 36 <0x00062000 0x00062000 0x001000>, /* ap 11 */
37 <0x00063000 0x0006300 37 <0x00063000 0x00063000 0x001000>, /* ap 12 */
38 <0x00008000 0x0000800 38 <0x00008000 0x00008000 0x002000>, /* ap 23 */
39 <0x0000a000 0x0000a00 39 <0x0000a000 0x0000a000 0x001000>, /* ap 24 */
40 <0x00066000 0x0006600 40 <0x00066000 0x00066000 0x001000>, /* ap 25 */
41 <0x00067000 0x0006700 41 <0x00067000 0x00067000 0x001000>, /* ap 26 */
42 <0x0005e000 0x0005e00 42 <0x0005e000 0x0005e000 0x002000>, /* ap 80 */
43 <0x00060000 0x0006000 43 <0x00060000 0x00060000 0x001000>, /* ap 81 */
44 <0x00064000 0x0006400 44 <0x00064000 0x00064000 0x001000>, /* ap 86 */
45 <0x00065000 0x0006500 45 <0x00065000 0x00065000 0x001000>; /* ap 87 */
46 46
47 target-module@2000 { 47 target-module@2000 { /* 0x4a002000, ap 3 06.0 */
48 compatible = "ti,sysc- 48 compatible = "ti,sysc-omap4", "ti,sysc";
49 reg = <0x2000 0x4>, 49 reg = <0x2000 0x4>,
50 <0x2010 0x4>; 50 <0x2010 0x4>;
51 reg-names = "rev", "sy 51 reg-names = "rev", "sysc";
52 ti,sysc-sidle = <SYSC_ 52 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
53 <SYSC_ 53 <SYSC_IDLE_NO>,
54 <SYSC_ 54 <SYSC_IDLE_SMART>,
55 <SYSC_ 55 <SYSC_IDLE_SMART_WKUP>;
56 /* Domains (V, P, C): 56 /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */
57 #address-cells = <1>; 57 #address-cells = <1>;
58 #size-cells = <1>; 58 #size-cells = <1>;
59 ranges = <0x0 0x2000 0 59 ranges = <0x0 0x2000 0x1000>;
60 60
61 omap4_scm_core: scm@0 61 omap4_scm_core: scm@0 {
62 compatible = " 62 compatible = "ti,omap4-scm-core", "simple-bus";
63 reg = <0x0 0x1 63 reg = <0x0 0x1000>;
64 #address-cells 64 #address-cells = <1>;
65 #size-cells = 65 #size-cells = <1>;
66 ranges = <0 0 66 ranges = <0 0 0x1000>;
67 67
68 scm_conf: scm_ 68 scm_conf: scm_conf@0 {
69 compat 69 compatible = "syscon";
70 reg = 70 reg = <0x0 0x800>;
71 #addre 71 #address-cells = <1>;
72 #size- 72 #size-cells = <1>;
73 }; 73 };
74 74
75 omap_control_u 75 omap_control_usb2phy: control-phy@300 {
76 compat 76 compatible = "ti,control-phy-usb2";
77 reg = 77 reg = <0x300 0x4>;
78 reg-na 78 reg-names = "power";
79 }; 79 };
80 80
81 omap_control_u 81 omap_control_usbotg: control-phy@33c {
82 compat 82 compatible = "ti,control-phy-otghs";
83 reg = 83 reg = <0x33c 0x4>;
84 reg-na 84 reg-names = "otghs_control";
85 }; 85 };
86 }; 86 };
87 }; 87 };
88 88
89 target-module@4000 { 89 target-module@4000 { /* 0x4a004000, ap 5 02.0 */
90 compatible = "ti,sysc- 90 compatible = "ti,sysc-omap4", "ti,sysc";
91 reg = <0x4000 0x4>; 91 reg = <0x4000 0x4>;
92 reg-names = "rev"; 92 reg-names = "rev";
93 #address-cells = <1>; 93 #address-cells = <1>;
94 #size-cells = <1>; 94 #size-cells = <1>;
95 ranges = <0x0 0x4000 0 95 ranges = <0x0 0x4000 0x1000>;
96 96
97 cm1: cm1@0 { 97 cm1: cm1@0 {
98 compatible = " 98 compatible = "ti,omap4-cm1", "simple-bus";
99 reg = <0x0 0x2 99 reg = <0x0 0x2000>;
100 #address-cells 100 #address-cells = <1>;
101 #size-cells = 101 #size-cells = <1>;
102 ranges = <0 0 102 ranges = <0 0 0x2000>;
103 103
104 cm1_clocks: cl 104 cm1_clocks: clocks {
105 #addre 105 #address-cells = <1>;
106 #size- 106 #size-cells = <0>;
107 }; 107 };
108 108
109 cm1_clockdomai 109 cm1_clockdomains: clockdomains {
110 }; 110 };
111 }; 111 };
112 }; 112 };
113 113
114 target-module@8000 { 114 target-module@8000 { /* 0x4a008000, ap 23 32.0 */
115 compatible = "ti,sysc- 115 compatible = "ti,sysc-omap4", "ti,sysc";
116 reg = <0x8000 0x4>; 116 reg = <0x8000 0x4>;
117 reg-names = "rev"; 117 reg-names = "rev";
118 #address-cells = <1>; 118 #address-cells = <1>;
119 #size-cells = <1>; 119 #size-cells = <1>;
120 ranges = <0x0 0x8000 0 120 ranges = <0x0 0x8000 0x2000>;
121 121
122 cm2: cm2@0 { 122 cm2: cm2@0 {
123 compatible = " 123 compatible = "ti,omap4-cm2", "simple-bus";
124 reg = <0x0 0x2 124 reg = <0x0 0x2000>;
125 #address-cells 125 #address-cells = <1>;
126 #size-cells = 126 #size-cells = <1>;
127 ranges = <0 0 127 ranges = <0 0 0x2000>;
128 128
129 cm2_clocks: cl 129 cm2_clocks: clocks {
130 #addre 130 #address-cells = <1>;
131 #size- 131 #size-cells = <0>;
132 }; 132 };
133 133
134 cm2_clockdomai 134 cm2_clockdomains: clockdomains {
135 }; 135 };
136 }; 136 };
137 }; 137 };
138 138
139 target-module@56000 { 139 target-module@56000 { /* 0x4a056000, ap 7 0a.0 */
140 compatible = "ti,sysc- 140 compatible = "ti,sysc-omap2", "ti,sysc";
141 reg = <0x56000 0x4>, 141 reg = <0x56000 0x4>,
142 <0x5602c 0x4>, 142 <0x5602c 0x4>,
143 <0x56028 0x4>; 143 <0x56028 0x4>;
144 reg-names = "rev", "sy 144 reg-names = "rev", "sysc", "syss";
145 ti,sysc-mask = <(SYSC_ 145 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
146 SYSC_ 146 SYSC_OMAP2_EMUFREE |
147 SYSC_ 147 SYSC_OMAP2_SOFTRESET |
148 SYSC_ 148 SYSC_OMAP2_AUTOIDLE)>;
149 ti,sysc-midle = <SYSC_ 149 ti,sysc-midle = <SYSC_IDLE_FORCE>,
150 <SYSC_ 150 <SYSC_IDLE_NO>,
151 <SYSC_ 151 <SYSC_IDLE_SMART>;
152 ti,sysc-sidle = <SYSC_ 152 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
153 <SYSC_ 153 <SYSC_IDLE_NO>,
154 <SYSC_ 154 <SYSC_IDLE_SMART>;
155 ti,syss-mask = <1>; 155 ti,syss-mask = <1>;
156 /* Domains (V, P, C): 156 /* Domains (V, P, C): core, core_pwrdm, l3_dma_clkdm */
157 clocks = <&l3_dma_clkc 157 clocks = <&l3_dma_clkctrl OMAP4_DMA_SYSTEM_CLKCTRL 0>;
158 clock-names = "fck"; 158 clock-names = "fck";
159 #address-cells = <1>; 159 #address-cells = <1>;
160 #size-cells = <1>; 160 #size-cells = <1>;
161 ranges = <0x0 0x56000 161 ranges = <0x0 0x56000 0x1000>;
162 162
163 sdma: dma-controller@0 163 sdma: dma-controller@0 {
164 compatible = " 164 compatible = "ti,omap4430-sdma", "ti,omap-sdma";
165 reg = <0x0 0x1 165 reg = <0x0 0x1000>;
166 interrupts = < 166 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
167 < 167 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
168 < 168 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
169 < 169 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
170 #dma-cells = < 170 #dma-cells = <1>;
171 dma-channels = 171 dma-channels = <32>;
172 dma-requests = 172 dma-requests = <127>;
173 }; 173 };
174 }; 174 };
175 175
176 target-module@58000 { 176 target-module@58000 { /* 0x4a058000, ap 10 0e.0 */
177 compatible = "ti,sysc- 177 compatible = "ti,sysc-omap2", "ti,sysc";
178 reg = <0x58000 0x4>, 178 reg = <0x58000 0x4>,
179 <0x58010 0x4>, 179 <0x58010 0x4>,
180 <0x58014 0x4>; 180 <0x58014 0x4>;
181 reg-names = "rev", "sy 181 reg-names = "rev", "sysc", "syss";
182 ti,sysc-mask = <(SYSC_ 182 ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
183 SYSC_ 183 SYSC_OMAP2_SOFTRESET |
184 SYSC_ 184 SYSC_OMAP2_AUTOIDLE)>;
185 ti,sysc-midle = <SYSC_ 185 ti,sysc-midle = <SYSC_IDLE_FORCE>,
186 <SYSC_ 186 <SYSC_IDLE_NO>,
187 <SYSC_ 187 <SYSC_IDLE_SMART>,
188 <SYSC_ 188 <SYSC_IDLE_SMART_WKUP>;
189 ti,sysc-sidle = <SYSC_ 189 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
190 <SYSC_ 190 <SYSC_IDLE_NO>,
191 <SYSC_ 191 <SYSC_IDLE_SMART>,
192 <SYSC_ 192 <SYSC_IDLE_SMART_WKUP>;
193 ti,syss-mask = <1>; 193 ti,syss-mask = <1>;
194 /* Domains (V, P, C): 194 /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
195 clocks = <&l3_init_clk 195 clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>;
196 clock-names = "fck"; 196 clock-names = "fck";
197 #address-cells = <1>; 197 #address-cells = <1>;
198 #size-cells = <1>; 198 #size-cells = <1>;
199 ranges = <0x0 0x58000 199 ranges = <0x0 0x58000 0x5000>;
200 200
201 hsi: hsi@0 { 201 hsi: hsi@0 {
202 compatible = " 202 compatible = "ti,omap4-hsi";
203 reg = <0x0 0x4 203 reg = <0x0 0x4000>,
204 <0x5000 204 <0x5000 0x1000>;
205 reg-names = "s 205 reg-names = "sys", "gdd";
206 206
207 clocks = <&l3_ 207 clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>;
208 clock-names = 208 clock-names = "hsi_fck";
209 209
210 interrupts = < 210 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
211 interrupt-name 211 interrupt-names = "gdd_mpu";
212 212
213 #address-cells 213 #address-cells = <1>;
214 #size-cells = 214 #size-cells = <1>;
215 ranges = <0 0 215 ranges = <0 0 0x4000>;
216 216
217 hsi_port1: hsi 217 hsi_port1: hsi-port@2000 {
218 compat 218 compatible = "ti,omap4-hsi-port";
219 reg = 219 reg = <0x2000 0x800>,
220 220 <0x2800 0x800>;
221 reg-na 221 reg-names = "tx", "rx";
222 interr 222 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
223 }; 223 };
224 224
225 hsi_port2: hsi 225 hsi_port2: hsi-port@3000 {
226 compat 226 compatible = "ti,omap4-hsi-port";
227 reg = 227 reg = <0x3000 0x800>,
228 228 <0x3800 0x800>;
229 reg-na 229 reg-names = "tx", "rx";
230 interr 230 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
231 }; 231 };
232 }; 232 };
233 }; 233 };
234 234
235 target-module@5e000 { 235 target-module@5e000 { /* 0x4a05e000, ap 80 68.0 */
236 compatible = "ti,sysc" 236 compatible = "ti,sysc";
237 status = "disabled"; 237 status = "disabled";
238 #address-cells = <1>; 238 #address-cells = <1>;
239 #size-cells = <1>; 239 #size-cells = <1>;
240 ranges = <0x0 0x5e000 240 ranges = <0x0 0x5e000 0x2000>;
241 }; 241 };
242 242
243 target-module@62000 { 243 target-module@62000 { /* 0x4a062000, ap 11 16.0 */
244 compatible = "ti,sysc- 244 compatible = "ti,sysc-omap2", "ti,sysc";
245 reg = <0x62000 0x4>, 245 reg = <0x62000 0x4>,
246 <0x62010 0x4>, 246 <0x62010 0x4>,
247 <0x62014 0x4>; 247 <0x62014 0x4>;
248 reg-names = "rev", "sy 248 reg-names = "rev", "sysc", "syss";
249 ti,sysc-mask = <(SYSC_ 249 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
250 SYSC_ 250 SYSC_OMAP2_ENAWAKEUP |
251 SYSC_ 251 SYSC_OMAP2_SOFTRESET |
252 SYSC_ 252 SYSC_OMAP2_AUTOIDLE)>;
253 ti,sysc-sidle = <SYSC_ 253 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
254 <SYSC_ 254 <SYSC_IDLE_NO>,
255 <SYSC_ 255 <SYSC_IDLE_SMART>;
256 /* Domains (V, P, C): 256 /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
257 clocks = <&l3_init_clk 257 clocks = <&l3_init_clkctrl OMAP4_USB_TLL_HS_CLKCTRL 0>;
258 clock-names = "fck"; 258 clock-names = "fck";
259 #address-cells = <1>; 259 #address-cells = <1>;
260 #size-cells = <1>; 260 #size-cells = <1>;
261 ranges = <0x0 0x62000 261 ranges = <0x0 0x62000 0x1000>;
262 262
263 usbhstll: usbhstll@0 { 263 usbhstll: usbhstll@0 {
264 compatible = " 264 compatible = "ti,usbhs-tll";
265 reg = <0x0 0x1 265 reg = <0x0 0x1000>;
266 interrupts = < 266 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
267 }; 267 };
268 }; 268 };
269 269
270 target-module@64000 { 270 target-module@64000 { /* 0x4a064000, ap 86 1e.0 */
271 compatible = "ti,sysc- 271 compatible = "ti,sysc-omap4", "ti,sysc";
272 reg = <0x64000 0x4>, 272 reg = <0x64000 0x4>,
273 <0x64010 0x4>, 273 <0x64010 0x4>,
274 <0x64014 0x4>; 274 <0x64014 0x4>;
275 reg-names = "rev", "sy 275 reg-names = "rev", "sysc", "syss";
276 ti,sysc-mask = <SYSC_O 276 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
277 ti,sysc-midle = <SYSC_ 277 ti,sysc-midle = <SYSC_IDLE_FORCE>,
278 <SYSC_ 278 <SYSC_IDLE_NO>,
279 <SYSC_ 279 <SYSC_IDLE_SMART>,
280 <SYSC_ 280 <SYSC_IDLE_SMART_WKUP>;
281 ti,sysc-sidle = <SYSC_ 281 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
282 <SYSC_ 282 <SYSC_IDLE_NO>,
283 <SYSC_ 283 <SYSC_IDLE_SMART>,
284 <SYSC_ 284 <SYSC_IDLE_SMART_WKUP>;
285 /* Domains (V, P, C): 285 /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
286 clocks = <&l3_init_clk 286 clocks = <&l3_init_clkctrl OMAP4_USB_HOST_HS_CLKCTRL 0>;
287 clock-names = "fck"; 287 clock-names = "fck";
288 #address-cells = <1>; 288 #address-cells = <1>;
289 #size-cells = <1>; 289 #size-cells = <1>;
290 ranges = <0x0 0x64000 290 ranges = <0x0 0x64000 0x1000>;
291 291
292 usbhshost: usbhshost@0 292 usbhshost: usbhshost@0 {
293 compatible = " 293 compatible = "ti,usbhs-host";
294 reg = <0x0 0x8 294 reg = <0x0 0x800>;
295 #address-cells 295 #address-cells = <1>;
296 #size-cells = 296 #size-cells = <1>;
297 ranges = <0 0 297 ranges = <0 0 0x1000>;
298 clocks = <&ini 298 clocks = <&init_60m_fclk>,
299 <&xcl 299 <&xclk60mhsp1_ck>,
300 <&xcl 300 <&xclk60mhsp2_ck>;
301 clock-names = 301 clock-names = "refclk_60m_int",
302 302 "refclk_60m_ext_p1",
303 303 "refclk_60m_ext_p2";
304 304
305 usbhsohci: ohc 305 usbhsohci: ohci@800 {
306 compat 306 compatible = "ti,ohci-omap3";
307 reg = 307 reg = <0x800 0x400>;
308 interr 308 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
309 remote 309 remote-wakeup-connected;
310 }; 310 };
311 311
312 usbhsehci: ehc 312 usbhsehci: ehci@c00 {
313 compat 313 compatible = "ti,ehci-omap";
314 reg = 314 reg = <0xc00 0x400>;
315 interr 315 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
316 }; 316 };
317 }; 317 };
318 }; 318 };
319 319
320 target-module@66000 { 320 target-module@66000 { /* 0x4a066000, ap 25 26.0 */
321 compatible = "ti,sysc- 321 compatible = "ti,sysc-omap2", "ti,sysc";
322 reg = <0x66000 0x4>, 322 reg = <0x66000 0x4>,
323 <0x66010 0x4>, 323 <0x66010 0x4>,
324 <0x66014 0x4>; 324 <0x66014 0x4>;
325 reg-names = "rev", "sy 325 reg-names = "rev", "sysc", "syss";
326 ti,sysc-mask = <(SYSC_ 326 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
327 SYSC_ 327 SYSC_OMAP2_SOFTRESET |
328 SYSC_ 328 SYSC_OMAP2_AUTOIDLE)>;
329 ti,sysc-sidle = <SYSC_ 329 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
330 <SYSC_ 330 <SYSC_IDLE_NO>,
331 <SYSC_ 331 <SYSC_IDLE_SMART>;
332 /* Domains (V, P, C): 332 /* Domains (V, P, C): iva, tesla_pwrdm, tesla_clkdm */
333 clocks = <&tesla_clkct 333 clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
334 clock-names = "fck"; 334 clock-names = "fck";
335 power-domains = <&prm_ 335 power-domains = <&prm_tesla>;
336 resets = <&prm_tesla 1 336 resets = <&prm_tesla 1>;
337 reset-names = "rstctrl 337 reset-names = "rstctrl";
338 #address-cells = <1>; 338 #address-cells = <1>;
339 #size-cells = <1>; 339 #size-cells = <1>;
340 ranges = <0x0 0x66000 340 ranges = <0x0 0x66000 0x1000>;
341 341
342 mmu_dsp: mmu@0 { 342 mmu_dsp: mmu@0 {
343 compatible = " 343 compatible = "ti,omap4-iommu";
344 reg = <0x0 0x1 344 reg = <0x0 0x100>;
345 interrupts = < 345 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
346 #iommu-cells = 346 #iommu-cells = <0>;
347 }; 347 };
348 }; 348 };
349 }; 349 };
350 350
351 segment@80000 { 351 segment@80000 { /* 0x4a080000 */
352 compatible = "simple-pm-bus"; 352 compatible = "simple-pm-bus";
353 #address-cells = <1>; 353 #address-cells = <1>;
354 #size-cells = <1>; 354 #size-cells = <1>;
355 ranges = <0x00059000 0x000d900 355 ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */
356 <0x0005a000 0x000da00 356 <0x0005a000 0x000da000 0x001000>, /* ap 14 */
357 <0x0005b000 0x000db00 357 <0x0005b000 0x000db000 0x001000>, /* ap 15 */
358 <0x0005c000 0x000dc00 358 <0x0005c000 0x000dc000 0x001000>, /* ap 16 */
359 <0x0005d000 0x000dd00 359 <0x0005d000 0x000dd000 0x001000>, /* ap 17 */
360 <0x0005e000 0x000de00 360 <0x0005e000 0x000de000 0x001000>, /* ap 18 */
361 <0x00060000 0x000e000 361 <0x00060000 0x000e0000 0x001000>, /* ap 19 */
362 <0x00061000 0x000e100 362 <0x00061000 0x000e1000 0x001000>, /* ap 20 */
363 <0x00074000 0x000f400 363 <0x00074000 0x000f4000 0x001000>, /* ap 27 */
364 <0x00075000 0x000f500 364 <0x00075000 0x000f5000 0x001000>, /* ap 28 */
365 <0x00076000 0x000f600 365 <0x00076000 0x000f6000 0x001000>, /* ap 29 */
366 <0x00077000 0x000f700 366 <0x00077000 0x000f7000 0x001000>, /* ap 30 */
367 <0x00036000 0x000b600 367 <0x00036000 0x000b6000 0x001000>, /* ap 69 */
368 <0x00037000 0x000b700 368 <0x00037000 0x000b7000 0x001000>, /* ap 70 */
369 <0x0004d000 0x000cd00 369 <0x0004d000 0x000cd000 0x001000>, /* ap 78 */
370 <0x0004e000 0x000ce00 370 <0x0004e000 0x000ce000 0x001000>, /* ap 79 */
371 <0x00029000 0x000a900 371 <0x00029000 0x000a9000 0x001000>, /* ap 82 */
372 <0x0002a000 0x000aa00 372 <0x0002a000 0x000aa000 0x001000>, /* ap 83 */
373 <0x0002b000 0x000ab00 373 <0x0002b000 0x000ab000 0x001000>, /* ap 84 */
374 <0x0002c000 0x000ac00 374 <0x0002c000 0x000ac000 0x001000>, /* ap 85 */
375 <0x0002d000 0x000ad00 375 <0x0002d000 0x000ad000 0x001000>, /* ap 88 */
376 <0x0002e000 0x000ae00 376 <0x0002e000 0x000ae000 0x001000>; /* ap 89 */
377 377
378 target-module@29000 { 378 target-module@29000 { /* 0x4a0a9000, ap 82 04.0 */
379 compatible = "ti,sysc" 379 compatible = "ti,sysc";
380 status = "disabled"; 380 status = "disabled";
381 #address-cells = <1>; 381 #address-cells = <1>;
382 #size-cells = <1>; 382 #size-cells = <1>;
383 ranges = <0x0 0x29000 383 ranges = <0x0 0x29000 0x1000>;
384 }; 384 };
385 385
386 target-module@2b000 { 386 target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */
387 compatible = "ti,sysc- 387 compatible = "ti,sysc-omap2", "ti,sysc";
388 reg = <0x2b400 0x4>, 388 reg = <0x2b400 0x4>,
389 <0x2b404 0x4>, 389 <0x2b404 0x4>,
390 <0x2b408 0x4>; 390 <0x2b408 0x4>;
391 reg-names = "rev", "sy 391 reg-names = "rev", "sysc", "syss";
392 ti,sysc-mask = <(SYSC_ 392 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
393 SYSC_ 393 SYSC_OMAP2_SOFTRESET |
394 SYSC_ 394 SYSC_OMAP2_AUTOIDLE)>;
395 ti,sysc-midle = <SYSC_ 395 ti,sysc-midle = <SYSC_IDLE_FORCE>,
396 <SYSC_ 396 <SYSC_IDLE_NO>,
397 <SYSC_ 397 <SYSC_IDLE_SMART>;
398 ti,sysc-sidle = <SYSC_ 398 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
399 <SYSC_ 399 <SYSC_IDLE_NO>,
400 <SYSC_ 400 <SYSC_IDLE_SMART>,
401 <SYSC_ 401 <SYSC_IDLE_SMART_WKUP>;
402 ti,syss-mask = <1>; 402 ti,syss-mask = <1>;
403 /* Domains (V, P, C): 403 /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
404 clocks = <&l3_init_clk 404 clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>;
405 clock-names = "fck"; 405 clock-names = "fck";
406 #address-cells = <1>; 406 #address-cells = <1>;
407 #size-cells = <1>; 407 #size-cells = <1>;
408 ranges = <0x0 0x2b000 408 ranges = <0x0 0x2b000 0x1000>;
409 409
410 usb_otg_hs: usb_otg_hs 410 usb_otg_hs: usb_otg_hs@0 {
411 compatible = " 411 compatible = "ti,omap4-musb";
412 reg = <0x0 0x7 412 reg = <0x0 0x7ff>;
413 interrupts = < 413 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
414 interrupt-name 414 interrupt-names = "mc", "dma";
415 usb-phy = <&us 415 usb-phy = <&usb2_phy>;
416 phys = <&usb2_ 416 phys = <&usb2_phy>;
417 phy-names = "u 417 phy-names = "usb2-phy";
418 multipoint = < 418 multipoint = <1>;
419 num-eps = <16> 419 num-eps = <16>;
420 ram-bits = <12 420 ram-bits = <12>;
421 ctrl-module = 421 ctrl-module = <&omap_control_usbotg>;
422 }; 422 };
423 }; 423 };
424 424
425 target-module@2d000 { 425 target-module@2d000 { /* 0x4a0ad000, ap 88 0c.0 */
426 compatible = "ti,sysc- 426 compatible = "ti,sysc-omap2", "ti,sysc";
427 reg = <0x2d000 0x4>, 427 reg = <0x2d000 0x4>,
428 <0x2d010 0x4>, 428 <0x2d010 0x4>,
429 <0x2d014 0x4>; 429 <0x2d014 0x4>;
430 reg-names = "rev", "sy 430 reg-names = "rev", "sysc", "syss";
431 ti,sysc-mask = <(SYSC_ 431 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
432 SYSC_ 432 SYSC_OMAP2_AUTOIDLE)>;
433 ti,sysc-sidle = <SYSC_ 433 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
434 <SYSC_ 434 <SYSC_IDLE_NO>,
435 <SYSC_ 435 <SYSC_IDLE_SMART>;
436 ti,syss-mask = <1>; 436 ti,syss-mask = <1>;
437 /* Domains (V, P, C): 437 /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
438 clocks = <&l3_init_clk 438 clocks = <&l3_init_clkctrl OMAP4_OCP2SCP_USB_PHY_CLKCTRL 0>;
439 clock-names = "fck"; 439 clock-names = "fck";
440 #address-cells = <1>; 440 #address-cells = <1>;
441 #size-cells = <1>; 441 #size-cells = <1>;
442 ranges = <0x0 0x2d000 442 ranges = <0x0 0x2d000 0x1000>;
443 443
444 ocp2scp@0 { 444 ocp2scp@0 {
445 compatible = " 445 compatible = "ti,omap-ocp2scp";
446 reg = <0x0 0x1 446 reg = <0x0 0x1f>;
447 #address-cells 447 #address-cells = <1>;
448 #size-cells = 448 #size-cells = <1>;
449 ranges = <0 0 449 ranges = <0 0 0x1000>;
450 usb2_phy: usb2 450 usb2_phy: usb2phy@80 {
451 compat 451 compatible = "ti,omap-usb2";
452 reg = 452 reg = <0x80 0x58>;
453 ctrl-m 453 ctrl-module = <&omap_control_usb2phy>;
454 clocks 454 clocks = <&usb_phy_cm_clk32k>;
455 clock- 455 clock-names = "wkupclk";
456 #phy-c 456 #phy-cells = <0>;
457 }; 457 };
458 }; 458 };
459 }; 459 };
460 460
461 /* d2d mdm */ 461 /* d2d mdm */
462 target-module@36000 { 462 target-module@36000 { /* 0x4a0b6000, ap 69 60.0 */
463 compatible = "ti,sysc- 463 compatible = "ti,sysc-omap2", "ti,sysc";
464 reg = <0x36000 0x4>, 464 reg = <0x36000 0x4>,
465 <0x36010 0x4>, 465 <0x36010 0x4>,
466 <0x36014 0x4>; 466 <0x36014 0x4>;
467 reg-names = "rev", "sy 467 reg-names = "rev", "sysc", "syss";
468 ti,sysc-mask = <(SYSC_ 468 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>;
469 ti,sysc-sidle = <SYSC_ 469 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
470 <SYSC_ 470 <SYSC_IDLE_NO>,
471 <SYSC_ 471 <SYSC_IDLE_SMART>,
472 <SYSC_ 472 <SYSC_IDLE_SMART_WKUP>;
473 ti,syss-mask = <1>; 473 ti,syss-mask = <1>;
474 /* Domains (V, P, C): 474 /* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */
475 clocks = <&d2d_clkctrl 475 clocks = <&d2d_clkctrl OMAP4_C2C_CLKCTRL 0>;
476 clock-names = "fck"; 476 clock-names = "fck";
477 #address-cells = <1>; 477 #address-cells = <1>;
478 #size-cells = <1>; 478 #size-cells = <1>;
479 ranges = <0x0 0x36000 479 ranges = <0x0 0x36000 0x1000>;
480 }; 480 };
481 481
482 /* d2d mpu */ 482 /* d2d mpu */
483 target-module@4d000 { 483 target-module@4d000 { /* 0x4a0cd000, ap 78 58.0 */
484 compatible = "ti,sysc- 484 compatible = "ti,sysc-omap2", "ti,sysc";
485 reg = <0x4d000 0x4>, 485 reg = <0x4d000 0x4>,
486 <0x4d010 0x4>, 486 <0x4d010 0x4>,
487 <0x4d014 0x4>; 487 <0x4d014 0x4>;
488 reg-names = "rev", "sy 488 reg-names = "rev", "sysc", "syss";
489 ti,sysc-mask = <(SYSC_ 489 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>;
490 ti,sysc-sidle = <SYSC_ 490 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
491 <SYSC_ 491 <SYSC_IDLE_NO>,
492 <SYSC_ 492 <SYSC_IDLE_SMART>,
493 <SYSC_ 493 <SYSC_IDLE_SMART_WKUP>;
494 ti,syss-mask = <1>; 494 ti,syss-mask = <1>;
495 /* Domains (V, P, C): 495 /* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */
496 clocks = <&d2d_clkctrl 496 clocks = <&d2d_clkctrl OMAP4_C2C_CLKCTRL 0>;
497 clock-names = "fck"; 497 clock-names = "fck";
498 #address-cells = <1>; 498 #address-cells = <1>;
499 #size-cells = <1>; 499 #size-cells = <1>;
500 ranges = <0x0 0x4d000 500 ranges = <0x0 0x4d000 0x1000>;
501 }; 501 };
502 502
503 target-module@59000 { 503 target-module@59000 { /* 0x4a0d9000, ap 13 1a.0 */
504 compatible = "ti,sysc- 504 compatible = "ti,sysc-omap4-sr", "ti,sysc";
505 reg = <0x59038 0x4>; 505 reg = <0x59038 0x4>;
506 reg-names = "sysc"; 506 reg-names = "sysc";
507 ti,sysc-mask = <SYSC_O 507 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
508 ti,sysc-sidle = <SYSC_ 508 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
509 <SYSC_ 509 <SYSC_IDLE_NO>,
510 <SYSC_ 510 <SYSC_IDLE_SMART>,
511 <SYSC_ 511 <SYSC_IDLE_SMART_WKUP>;
512 /* Domains (V, P, C): 512 /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */
513 clocks = <&l4_ao_clkct 513 clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_MPU_CLKCTRL 0>;
514 clock-names = "fck"; 514 clock-names = "fck";
515 #address-cells = <1>; 515 #address-cells = <1>;
516 #size-cells = <1>; 516 #size-cells = <1>;
517 ranges = <0x0 0x59000 517 ranges = <0x0 0x59000 0x1000>;
518 518
519 smartreflex_mpu: smart 519 smartreflex_mpu: smartreflex@0 {
520 compatible = " 520 compatible = "ti,omap4-smartreflex-mpu";
521 reg = <0x0 0x8 521 reg = <0x0 0x80>;
522 interrupts = < 522 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
523 }; 523 };
524 }; 524 };
525 525
526 target-module@5b000 { 526 target-module@5b000 { /* 0x4a0db000, ap 15 08.0 */
527 compatible = "ti,sysc- 527 compatible = "ti,sysc-omap4-sr", "ti,sysc";
528 reg = <0x5b038 0x4>; 528 reg = <0x5b038 0x4>;
529 reg-names = "sysc"; 529 reg-names = "sysc";
530 ti,sysc-mask = <SYSC_O 530 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
531 ti,sysc-sidle = <SYSC_ 531 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
532 <SYSC_ 532 <SYSC_IDLE_NO>,
533 <SYSC_ 533 <SYSC_IDLE_SMART>,
534 <SYSC_ 534 <SYSC_IDLE_SMART_WKUP>;
535 /* Domains (V, P, C): 535 /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */
536 clocks = <&l4_ao_clkct 536 clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_IVA_CLKCTRL 0>;
537 clock-names = "fck"; 537 clock-names = "fck";
538 #address-cells = <1>; 538 #address-cells = <1>;
539 #size-cells = <1>; 539 #size-cells = <1>;
540 ranges = <0x0 0x5b000 540 ranges = <0x0 0x5b000 0x1000>;
541 541
542 smartreflex_iva: smart 542 smartreflex_iva: smartreflex@0 {
543 compatible = " 543 compatible = "ti,omap4-smartreflex-iva";
544 reg = <0x0 0x8 544 reg = <0x0 0x80>;
545 interrupts = < 545 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
546 }; 546 };
547 }; 547 };
548 548
549 target-module@5d000 { 549 target-module@5d000 { /* 0x4a0dd000, ap 17 22.0 */
550 compatible = "ti,sysc- 550 compatible = "ti,sysc-omap4-sr", "ti,sysc";
551 reg = <0x5d038 0x4>; 551 reg = <0x5d038 0x4>;
552 reg-names = "sysc"; 552 reg-names = "sysc";
553 ti,sysc-mask = <SYSC_O 553 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
554 ti,sysc-sidle = <SYSC_ 554 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
555 <SYSC_ 555 <SYSC_IDLE_NO>,
556 <SYSC_ 556 <SYSC_IDLE_SMART>,
557 <SYSC_ 557 <SYSC_IDLE_SMART_WKUP>;
558 /* Domains (V, P, C): 558 /* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */
559 clocks = <&l4_ao_clkct 559 clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_CORE_CLKCTRL 0>;
560 clock-names = "fck"; 560 clock-names = "fck";
561 #address-cells = <1>; 561 #address-cells = <1>;
562 #size-cells = <1>; 562 #size-cells = <1>;
563 ranges = <0x0 0x5d000 563 ranges = <0x0 0x5d000 0x1000>;
564 564
565 smartreflex_core: smar 565 smartreflex_core: smartreflex@0 {
566 compatible = " 566 compatible = "ti,omap4-smartreflex-core";
567 reg = <0x0 0x8 567 reg = <0x0 0x80>;
568 interrupts = < 568 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
569 }; 569 };
570 }; 570 };
571 571
572 target-module@60000 { 572 target-module@60000 { /* 0x4a0e0000, ap 19 1c.0 */
573 compatible = "ti,sysc" 573 compatible = "ti,sysc";
574 status = "disabled"; 574 status = "disabled";
575 #address-cells = <1>; 575 #address-cells = <1>;
576 #size-cells = <1>; 576 #size-cells = <1>;
577 ranges = <0x0 0x60000 577 ranges = <0x0 0x60000 0x1000>;
578 }; 578 };
579 579
580 target-module@74000 { 580 target-module@74000 { /* 0x4a0f4000, ap 27 24.0 */
581 compatible = "ti,sysc- 581 compatible = "ti,sysc-omap4", "ti,sysc";
582 reg = <0x74000 0x4>, 582 reg = <0x74000 0x4>,
583 <0x74010 0x4>; 583 <0x74010 0x4>;
584 reg-names = "rev", "sy 584 reg-names = "rev", "sysc";
585 ti,sysc-mask = <SYSC_O 585 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
586 ti,sysc-sidle = <SYSC_ 586 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
587 <SYSC_ 587 <SYSC_IDLE_NO>,
588 <SYSC_ 588 <SYSC_IDLE_SMART>;
589 /* Domains (V, P, C): 589 /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */
590 clocks = <&l4_cfg_clkc 590 clocks = <&l4_cfg_clkctrl OMAP4_MAILBOX_CLKCTRL 0>;
591 clock-names = "fck"; 591 clock-names = "fck";
592 #address-cells = <1>; 592 #address-cells = <1>;
593 #size-cells = <1>; 593 #size-cells = <1>;
594 ranges = <0x0 0x74000 594 ranges = <0x0 0x74000 0x1000>;
595 595
596 mailbox: mailbox@0 { 596 mailbox: mailbox@0 {
597 compatible = " 597 compatible = "ti,omap4-mailbox";
598 reg = <0x0 0x2 598 reg = <0x0 0x200>;
599 interrupts = < 599 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
600 #mbox-cells = 600 #mbox-cells = <1>;
601 ti,mbox-num-us 601 ti,mbox-num-users = <3>;
602 ti,mbox-num-fi 602 ti,mbox-num-fifos = <8>;
603 mbox_ipu: mbox 603 mbox_ipu: mbox-ipu {
604 ti,mbo 604 ti,mbox-tx = <0 0 0>;
605 ti,mbo 605 ti,mbox-rx = <1 0 0>;
606 }; 606 };
607 mbox_dsp: mbox 607 mbox_dsp: mbox-dsp {
608 ti,mbo 608 ti,mbox-tx = <3 0 0>;
609 ti,mbo 609 ti,mbox-rx = <2 0 0>;
610 }; 610 };
611 }; 611 };
612 }; 612 };
613 613
614 target-module@76000 { 614 target-module@76000 { /* 0x4a0f6000, ap 29 3a.0 */
615 compatible = "ti,sysc- 615 compatible = "ti,sysc-omap2", "ti,sysc";
616 reg = <0x76000 0x4>, 616 reg = <0x76000 0x4>,
617 <0x76010 0x4>, 617 <0x76010 0x4>,
618 <0x76014 0x4>; 618 <0x76014 0x4>;
619 reg-names = "rev", "sy 619 reg-names = "rev", "sysc", "syss";
620 ti,sysc-mask = <(SYSC_ 620 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
621 SYSC_ 621 SYSC_OMAP2_ENAWAKEUP |
622 SYSC_ 622 SYSC_OMAP2_SOFTRESET |
623 SYSC_ 623 SYSC_OMAP2_AUTOIDLE)>;
624 ti,sysc-sidle = <SYSC_ 624 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
625 <SYSC_ 625 <SYSC_IDLE_NO>,
626 <SYSC_ 626 <SYSC_IDLE_SMART>;
627 ti,syss-mask = <1>; 627 ti,syss-mask = <1>;
628 /* Domains (V, P, C): 628 /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */
629 clocks = <&l4_cfg_clkc 629 clocks = <&l4_cfg_clkctrl OMAP4_SPINLOCK_CLKCTRL 0>;
630 clock-names = "fck"; 630 clock-names = "fck";
631 #address-cells = <1>; 631 #address-cells = <1>;
632 #size-cells = <1>; 632 #size-cells = <1>;
633 ranges = <0x0 0x76000 633 ranges = <0x0 0x76000 0x1000>;
634 634
635 hwspinlock: spinlock@0 635 hwspinlock: spinlock@0 {
636 compatible = " 636 compatible = "ti,omap4-hwspinlock";
637 reg = <0x0 0x1 637 reg = <0x0 0x1000>;
638 #hwlock-cells 638 #hwlock-cells = <1>;
639 }; 639 };
640 }; 640 };
641 }; 641 };
642 642
643 segment@100000 { 643 segment@100000 { /* 0x4a100000 */
644 compatible = "simple-pm-bus"; 644 compatible = "simple-pm-bus";
645 #address-cells = <1>; 645 #address-cells = <1>;
646 #size-cells = <1>; 646 #size-cells = <1>;
647 ranges = <0x00000000 0x0010000 647 ranges = <0x00000000 0x00100000 0x001000>, /* ap 21 */
648 <0x00001000 0x0010100 648 <0x00001000 0x00101000 0x001000>, /* ap 22 */
649 <0x00002000 0x0010200 649 <0x00002000 0x00102000 0x001000>, /* ap 61 */
650 <0x00003000 0x0010300 650 <0x00003000 0x00103000 0x001000>, /* ap 62 */
651 <0x00008000 0x0010800 651 <0x00008000 0x00108000 0x001000>, /* ap 63 */
652 <0x00009000 0x0010900 652 <0x00009000 0x00109000 0x001000>, /* ap 64 */
653 <0x0000a000 0x0010a00 653 <0x0000a000 0x0010a000 0x001000>, /* ap 65 */
654 <0x0000b000 0x0010b00 654 <0x0000b000 0x0010b000 0x001000>; /* ap 66 */
655 655
656 target-module@0 { 656 target-module@0 { /* 0x4a100000, ap 21 2a.0 */
657 compatible = "ti,sysc- 657 compatible = "ti,sysc-omap4", "ti,sysc";
658 reg = <0x0 0x4>, 658 reg = <0x0 0x4>,
659 <0x10 0x4>; 659 <0x10 0x4>;
660 reg-names = "rev", "sy 660 reg-names = "rev", "sysc";
661 ti,sysc-sidle = <SYSC_ 661 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
662 <SYSC_ 662 <SYSC_IDLE_NO>,
663 <SYSC_ 663 <SYSC_IDLE_SMART>,
664 <SYSC_ 664 <SYSC_IDLE_SMART_WKUP>;
665 /* Domains (V, P, C): 665 /* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */
666 #address-cells = <1>; 666 #address-cells = <1>;
667 #size-cells = <1>; 667 #size-cells = <1>;
668 ranges = <0x0 0x0 0x10 668 ranges = <0x0 0x0 0x1000>;
669 669
670 omap4_pmx_core: pinmux 670 omap4_pmx_core: pinmux@40 {
671 compatible = " 671 compatible = "ti,omap4-padconf",
672 " 672 "pinctrl-single";
673 reg = <0x40 0x 673 reg = <0x40 0x0196>;
674 #address-cells 674 #address-cells = <1>;
675 #size-cells = 675 #size-cells = <0>;
676 #pinctrl-cells 676 #pinctrl-cells = <1>;
677 #interrupt-cel 677 #interrupt-cells = <1>;
678 interrupt-cont 678 interrupt-controller;
679 pinctrl-single 679 pinctrl-single,register-width = <16>;
680 pinctrl-single 680 pinctrl-single,function-mask = <0x7fff>;
681 }; 681 };
682 682
683 omap4_padconf_global: 683 omap4_padconf_global: omap4_padconf_global@5a0 {
684 compatible = " 684 compatible = "syscon",
685 " 685 "simple-bus";
686 reg = <0x5a0 0 686 reg = <0x5a0 0x170>;
687 #address-cells 687 #address-cells = <1>;
688 #size-cells = 688 #size-cells = <1>;
689 ranges = <0 0x 689 ranges = <0 0x5a0 0x170>;
690 690
691 pbias_regulato 691 pbias_regulator: pbias_regulator@60 {
692 compat 692 compatible = "ti,pbias-omap4", "ti,pbias-omap";
693 reg = 693 reg = <0x60 0x4>;
694 syscon 694 syscon = <&omap4_padconf_global>;
695 pbias_ 695 pbias_mmc_reg: pbias_mmc_omap4 {
696 696 regulator-name = "pbias_mmc_omap4";
697 697 regulator-min-microvolt = <1800000>;
698 698 regulator-max-microvolt = <3000000>;
699 }; 699 };
700 }; 700 };
701 }; 701 };
702 }; 702 };
703 703
704 target-module@2000 { 704 target-module@2000 { /* 0x4a102000, ap 61 3c.0 */
705 compatible = "ti,sysc" 705 compatible = "ti,sysc";
706 status = "disabled"; 706 status = "disabled";
707 #address-cells = <1>; 707 #address-cells = <1>;
708 #size-cells = <1>; 708 #size-cells = <1>;
709 ranges = <0x0 0x2000 0 709 ranges = <0x0 0x2000 0x1000>;
710 }; 710 };
711 711
712 target-module@8000 { 712 target-module@8000 { /* 0x4a108000, ap 63 62.0 */
713 compatible = "ti,sysc" 713 compatible = "ti,sysc";
714 status = "disabled"; 714 status = "disabled";
715 #address-cells = <1>; 715 #address-cells = <1>;
716 #size-cells = <1>; 716 #size-cells = <1>;
717 ranges = <0x0 0x8000 0 717 ranges = <0x0 0x8000 0x1000>;
718 }; 718 };
719 719
720 target-module@a000 { 720 target-module@a000 { /* 0x4a10a000, ap 65 50.0 */
721 compatible = "ti,sysc- 721 compatible = "ti,sysc-omap4", "ti,sysc";
722 reg = <0xa000 0x4>, 722 reg = <0xa000 0x4>,
723 <0xa010 0x4>; 723 <0xa010 0x4>;
724 reg-names = "rev", "sy 724 reg-names = "rev", "sysc";
725 ti,sysc-mask = <SYSC_O 725 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
726 ti,sysc-midle = <SYSC_ 726 ti,sysc-midle = <SYSC_IDLE_FORCE>,
727 <SYSC_ 727 <SYSC_IDLE_NO>,
728 <SYSC_ 728 <SYSC_IDLE_SMART>;
729 ti,sysc-sidle = <SYSC_ 729 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
730 <SYSC_ 730 <SYSC_IDLE_NO>,
731 <SYSC_ 731 <SYSC_IDLE_SMART>;
732 ti,sysc-delay-us = <2> 732 ti,sysc-delay-us = <2>;
733 /* Domains (V, P, C): 733 /* Domains (V, P, C): core, cam_pwrdm, iss_clkdm */
734 clocks = <&iss_clkctrl 734 clocks = <&iss_clkctrl OMAP4_FDIF_CLKCTRL 0>;
735 clock-names = "fck"; 735 clock-names = "fck";
736 #address-cells = <1>; 736 #address-cells = <1>;
737 #size-cells = <1>; 737 #size-cells = <1>;
738 ranges = <0x0 0xa000 0 738 ranges = <0x0 0xa000 0x1000>;
739 739
740 /* No child device bin 740 /* No child device binding or driver in mainline */
741 }; 741 };
742 }; 742 };
743 743
744 segment@180000 { 744 segment@180000 { /* 0x4a180000 */
745 compatible = "simple-pm-bus"; 745 compatible = "simple-pm-bus";
746 #address-cells = <1>; 746 #address-cells = <1>;
747 #size-cells = <1>; 747 #size-cells = <1>;
748 }; 748 };
749 749
750 segment@200000 { 750 segment@200000 { /* 0x4a200000 */
751 compatible = "simple-pm-bus"; 751 compatible = "simple-pm-bus";
752 #address-cells = <1>; 752 #address-cells = <1>;
753 #size-cells = <1>; 753 #size-cells = <1>;
754 ranges = <0x0001e000 0x0021e00 754 ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 31 */
755 <0x0001f000 0x0021f00 755 <0x0001f000 0x0021f000 0x001000>, /* ap 32 */
756 <0x0000a000 0x0020a00 756 <0x0000a000 0x0020a000 0x001000>, /* ap 33 */
757 <0x0000b000 0x0020b00 757 <0x0000b000 0x0020b000 0x001000>, /* ap 34 */
758 <0x00004000 0x0020400 758 <0x00004000 0x00204000 0x001000>, /* ap 35 */
759 <0x00005000 0x0020500 759 <0x00005000 0x00205000 0x001000>, /* ap 36 */
760 <0x00006000 0x0020600 760 <0x00006000 0x00206000 0x001000>, /* ap 37 */
761 <0x00007000 0x0020700 761 <0x00007000 0x00207000 0x001000>, /* ap 38 */
762 <0x00012000 0x0021200 762 <0x00012000 0x00212000 0x001000>, /* ap 39 */
763 <0x00013000 0x0021300 763 <0x00013000 0x00213000 0x001000>, /* ap 40 */
764 <0x0000c000 0x0020c00 764 <0x0000c000 0x0020c000 0x001000>, /* ap 41 */
765 <0x0000d000 0x0020d00 765 <0x0000d000 0x0020d000 0x001000>, /* ap 42 */
766 <0x00010000 0x0021000 766 <0x00010000 0x00210000 0x001000>, /* ap 43 */
767 <0x00011000 0x0021100 767 <0x00011000 0x00211000 0x001000>, /* ap 44 */
768 <0x00016000 0x0021600 768 <0x00016000 0x00216000 0x001000>, /* ap 45 */
769 <0x00017000 0x0021700 769 <0x00017000 0x00217000 0x001000>, /* ap 46 */
770 <0x00014000 0x0021400 770 <0x00014000 0x00214000 0x001000>, /* ap 47 */
771 <0x00015000 0x0021500 771 <0x00015000 0x00215000 0x001000>, /* ap 48 */
772 <0x00018000 0x0021800 772 <0x00018000 0x00218000 0x001000>, /* ap 49 */
773 <0x00019000 0x0021900 773 <0x00019000 0x00219000 0x001000>, /* ap 50 */
774 <0x00020000 0x0022000 774 <0x00020000 0x00220000 0x001000>, /* ap 51 */
775 <0x00021000 0x0022100 775 <0x00021000 0x00221000 0x001000>, /* ap 52 */
776 <0x00026000 0x0022600 776 <0x00026000 0x00226000 0x001000>, /* ap 53 */
777 <0x00027000 0x0022700 777 <0x00027000 0x00227000 0x001000>, /* ap 54 */
778 <0x00028000 0x0022800 778 <0x00028000 0x00228000 0x001000>, /* ap 55 */
779 <0x00029000 0x0022900 779 <0x00029000 0x00229000 0x001000>, /* ap 56 */
780 <0x0002a000 0x0022a00 780 <0x0002a000 0x0022a000 0x001000>, /* ap 57 */
781 <0x0002b000 0x0022b00 781 <0x0002b000 0x0022b000 0x001000>, /* ap 58 */
782 <0x0001c000 0x0021c00 782 <0x0001c000 0x0021c000 0x001000>, /* ap 59 */
783 <0x0001d000 0x0021d00 783 <0x0001d000 0x0021d000 0x001000>; /* ap 60 */
784 784
785 target-module@4000 { 785 target-module@4000 { /* 0x4a204000, ap 35 42.0 */
786 compatible = "ti,sysc" 786 compatible = "ti,sysc";
787 status = "disabled"; 787 status = "disabled";
788 #address-cells = <1>; 788 #address-cells = <1>;
789 #size-cells = <1>; 789 #size-cells = <1>;
790 ranges = <0x0 0x4000 0 790 ranges = <0x0 0x4000 0x1000>;
791 }; 791 };
792 792
793 target-module@6000 { 793 target-module@6000 { /* 0x4a206000, ap 37 4a.0 */
794 compatible = "ti,sysc" 794 compatible = "ti,sysc";
795 status = "disabled"; 795 status = "disabled";
796 #address-cells = <1>; 796 #address-cells = <1>;
797 #size-cells = <1>; 797 #size-cells = <1>;
798 ranges = <0x0 0x6000 0 798 ranges = <0x0 0x6000 0x1000>;
799 }; 799 };
800 800
801 target-module@a000 { 801 target-module@a000 { /* 0x4a20a000, ap 33 2c.0 */
802 compatible = "ti,sysc" 802 compatible = "ti,sysc";
803 status = "disabled"; 803 status = "disabled";
804 #address-cells = <1>; 804 #address-cells = <1>;
805 #size-cells = <1>; 805 #size-cells = <1>;
806 ranges = <0x0 0xa000 0 806 ranges = <0x0 0xa000 0x1000>;
807 }; 807 };
808 808
809 target-module@c000 { 809 target-module@c000 { /* 0x4a20c000, ap 41 20.0 */
810 compatible = "ti,sysc" 810 compatible = "ti,sysc";
811 status = "disabled"; 811 status = "disabled";
812 #address-cells = <1>; 812 #address-cells = <1>;
813 #size-cells = <1>; 813 #size-cells = <1>;
814 ranges = <0x0 0xc000 0 814 ranges = <0x0 0xc000 0x1000>;
815 }; 815 };
816 816
817 target-module@10000 { 817 target-module@10000 { /* 0x4a210000, ap 43 52.0 */
818 compatible = "ti,sysc" 818 compatible = "ti,sysc";
819 status = "disabled"; 819 status = "disabled";
820 #address-cells = <1>; 820 #address-cells = <1>;
821 #size-cells = <1>; 821 #size-cells = <1>;
822 ranges = <0x0 0x10000 822 ranges = <0x0 0x10000 0x1000>;
823 }; 823 };
824 824
825 target-module@12000 { 825 target-module@12000 { /* 0x4a212000, ap 39 18.0 */
826 compatible = "ti,sysc" 826 compatible = "ti,sysc";
827 status = "disabled"; 827 status = "disabled";
828 #address-cells = <1>; 828 #address-cells = <1>;
829 #size-cells = <1>; 829 #size-cells = <1>;
830 ranges = <0x0 0x12000 830 ranges = <0x0 0x12000 0x1000>;
831 }; 831 };
832 832
833 target-module@14000 { 833 target-module@14000 { /* 0x4a214000, ap 47 30.0 */
834 compatible = "ti,sysc" 834 compatible = "ti,sysc";
835 status = "disabled"; 835 status = "disabled";
836 #address-cells = <1>; 836 #address-cells = <1>;
837 #size-cells = <1>; 837 #size-cells = <1>;
838 ranges = <0x0 0x14000 838 ranges = <0x0 0x14000 0x1000>;
839 }; 839 };
840 840
841 target-module@16000 { 841 target-module@16000 { /* 0x4a216000, ap 45 28.0 */
842 compatible = "ti,sysc" 842 compatible = "ti,sysc";
843 status = "disabled"; 843 status = "disabled";
844 #address-cells = <1>; 844 #address-cells = <1>;
845 #size-cells = <1>; 845 #size-cells = <1>;
846 ranges = <0x0 0x16000 846 ranges = <0x0 0x16000 0x1000>;
847 }; 847 };
848 848
849 target-module@18000 { 849 target-module@18000 { /* 0x4a218000, ap 49 38.0 */
850 compatible = "ti,sysc" 850 compatible = "ti,sysc";
851 status = "disabled"; 851 status = "disabled";
852 #address-cells = <1>; 852 #address-cells = <1>;
853 #size-cells = <1>; 853 #size-cells = <1>;
854 ranges = <0x0 0x18000 854 ranges = <0x0 0x18000 0x1000>;
855 }; 855 };
856 856
857 target-module@1c000 { 857 target-module@1c000 { /* 0x4a21c000, ap 59 5a.0 */
858 compatible = "ti,sysc" 858 compatible = "ti,sysc";
859 status = "disabled"; 859 status = "disabled";
860 #address-cells = <1>; 860 #address-cells = <1>;
861 #size-cells = <1>; 861 #size-cells = <1>;
862 ranges = <0x0 0x1c000 862 ranges = <0x0 0x1c000 0x1000>;
863 }; 863 };
864 864
865 target-module@1e000 { 865 target-module@1e000 { /* 0x4a21e000, ap 31 10.0 */
866 compatible = "ti,sysc" 866 compatible = "ti,sysc";
867 status = "disabled"; 867 status = "disabled";
868 #address-cells = <1>; 868 #address-cells = <1>;
869 #size-cells = <1>; 869 #size-cells = <1>;
870 ranges = <0x0 0x1e000 870 ranges = <0x0 0x1e000 0x1000>;
871 }; 871 };
872 872
873 target-module@20000 { 873 target-module@20000 { /* 0x4a220000, ap 51 40.0 */
874 compatible = "ti,sysc" 874 compatible = "ti,sysc";
875 status = "disabled"; 875 status = "disabled";
876 #address-cells = <1>; 876 #address-cells = <1>;
877 #size-cells = <1>; 877 #size-cells = <1>;
878 ranges = <0x0 0x20000 878 ranges = <0x0 0x20000 0x1000>;
879 }; 879 };
880 880
881 target-module@26000 { 881 target-module@26000 { /* 0x4a226000, ap 53 34.0 */
882 compatible = "ti,sysc" 882 compatible = "ti,sysc";
883 status = "disabled"; 883 status = "disabled";
884 #address-cells = <1>; 884 #address-cells = <1>;
885 #size-cells = <1>; 885 #size-cells = <1>;
886 ranges = <0x0 0x26000 886 ranges = <0x0 0x26000 0x1000>;
887 }; 887 };
888 888
889 target-module@28000 { 889 target-module@28000 { /* 0x4a228000, ap 55 2e.0 */
890 compatible = "ti,sysc" 890 compatible = "ti,sysc";
891 status = "disabled"; 891 status = "disabled";
892 #address-cells = <1>; 892 #address-cells = <1>;
893 #size-cells = <1>; 893 #size-cells = <1>;
894 ranges = <0x0 0x28000 894 ranges = <0x0 0x28000 0x1000>;
895 }; 895 };
896 896
897 target-module@2a000 { 897 target-module@2a000 { /* 0x4a22a000, ap 57 48.0 */
898 compatible = "ti,sysc" 898 compatible = "ti,sysc";
899 status = "disabled"; 899 status = "disabled";
900 #address-cells = <1>; 900 #address-cells = <1>;
901 #size-cells = <1>; 901 #size-cells = <1>;
902 ranges = <0x0 0x2a000 902 ranges = <0x0 0x2a000 0x1000>;
903 }; 903 };
904 }; 904 };
905 905
906 segment@280000 { 906 segment@280000 { /* 0x4a280000 */
907 compatible = "simple-pm-bus"; 907 compatible = "simple-pm-bus";
908 #address-cells = <1>; 908 #address-cells = <1>;
909 #size-cells = <1>; 909 #size-cells = <1>;
910 }; 910 };
911 911
912 l4_cfg_segment_300000: segment@300000 912 l4_cfg_segment_300000: segment@300000 { /* 0x4a300000 */
913 compatible = "simple-pm-bus"; 913 compatible = "simple-pm-bus";
914 #address-cells = <1>; 914 #address-cells = <1>;
915 #size-cells = <1>; 915 #size-cells = <1>;
916 ranges = <0x00000000 0x0030000 916 ranges = <0x00000000 0x00300000 0x020000>, /* ap 67 */
917 <0x00040000 0x0034000 917 <0x00040000 0x00340000 0x001000>, /* ap 68 */
918 <0x00020000 0x0032000 918 <0x00020000 0x00320000 0x004000>, /* ap 71 */
919 <0x00024000 0x0032400 919 <0x00024000 0x00324000 0x002000>, /* ap 72 */
920 <0x00026000 0x0032600 920 <0x00026000 0x00326000 0x001000>, /* ap 73 */
921 <0x00027000 0x0032700 921 <0x00027000 0x00327000 0x001000>, /* ap 74 */
922 <0x00028000 0x0032800 922 <0x00028000 0x00328000 0x001000>, /* ap 75 */
923 <0x00029000 0x0032900 923 <0x00029000 0x00329000 0x001000>, /* ap 76 */
924 <0x00030000 0x0033000 924 <0x00030000 0x00330000 0x010000>, /* ap 77 */
925 <0x0002a000 0x0032a00 925 <0x0002a000 0x0032a000 0x002000>, /* ap 90 */
926 <0x0002c000 0x0032c00 926 <0x0002c000 0x0032c000 0x004000>; /* ap 91 */
927 927
928 l4_cfg_target_0: target-module 928 l4_cfg_target_0: target-module@0 { /* 0x4a300000, ap 67 14.0 */
929 compatible = "ti,sysc" 929 compatible = "ti,sysc";
930 status = "disabled"; 930 status = "disabled";
931 #address-cells = <1>; 931 #address-cells = <1>;
932 #size-cells = <1>; 932 #size-cells = <1>;
933 ranges = <0x00000000 0 933 ranges = <0x00000000 0x00000000 0x00020000>,
934 <0x00020000 0 934 <0x00020000 0x00020000 0x00004000>,
935 <0x00024000 0 935 <0x00024000 0x00024000 0x00002000>,
936 <0x00026000 0 936 <0x00026000 0x00026000 0x00001000>,
937 <0x00027000 0 937 <0x00027000 0x00027000 0x00001000>,
938 <0x00028000 0 938 <0x00028000 0x00028000 0x00001000>,
939 <0x00029000 0 939 <0x00029000 0x00029000 0x00001000>,
940 <0x0002a000 0 940 <0x0002a000 0x0002a000 0x00002000>,
941 <0x0002c000 0 941 <0x0002c000 0x0002c000 0x00004000>,
942 <0x00030000 0 942 <0x00030000 0x00030000 0x00010000>;
943 }; 943 };
944 }; 944 };
945 }; 945 };
946 946
947 &l4_wkup { 947 &l4_wkup { /* 0x4a300000 */
948 compatible = "ti,omap4-l4-wkup", "simp 948 compatible = "ti,omap4-l4-wkup", "simple-pm-bus";
949 power-domains = <&prm_wkup>; 949 power-domains = <&prm_wkup>;
950 clocks = <&l4_wkup_clkctrl OMAP4_L4_WK 950 clocks = <&l4_wkup_clkctrl OMAP4_L4_WKUP_CLKCTRL 0>;
951 clock-names = "fck"; 951 clock-names = "fck";
952 reg = <0x4a300000 0x800>, 952 reg = <0x4a300000 0x800>,
953 <0x4a300800 0x800>, 953 <0x4a300800 0x800>,
954 <0x4a301000 0x1000>; 954 <0x4a301000 0x1000>;
955 reg-names = "ap", "la", "ia0"; 955 reg-names = "ap", "la", "ia0";
956 #address-cells = <1>; 956 #address-cells = <1>;
957 #size-cells = <1>; 957 #size-cells = <1>;
958 ranges = <0x00000000 0x4a300000 0x0100 958 ranges = <0x00000000 0x4a300000 0x010000>, /* segment 0 */
959 <0x00010000 0x4a310000 0x0100 959 <0x00010000 0x4a310000 0x010000>, /* segment 1 */
960 <0x00020000 0x4a320000 0x0100 960 <0x00020000 0x4a320000 0x010000>; /* segment 2 */
961 961
962 segment@0 { 962 segment@0 { /* 0x4a300000 */
963 compatible = "simple-pm-bus"; 963 compatible = "simple-pm-bus";
964 #address-cells = <1>; 964 #address-cells = <1>;
965 #size-cells = <1>; 965 #size-cells = <1>;
966 ranges = <0x00000000 0x0000000 966 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
967 <0x00001000 0x0000100 967 <0x00001000 0x00001000 0x001000>, /* ap 1 */
968 <0x00000800 0x0000080 968 <0x00000800 0x00000800 0x000800>, /* ap 2 */
969 <0x00006000 0x0000600 969 <0x00006000 0x00006000 0x002000>, /* ap 3 */
970 <0x00008000 0x0000800 970 <0x00008000 0x00008000 0x001000>, /* ap 4 */
971 <0x0000a000 0x0000a00 971 <0x0000a000 0x0000a000 0x001000>, /* ap 15 */
972 <0x0000b000 0x0000b00 972 <0x0000b000 0x0000b000 0x001000>, /* ap 16 */
973 <0x00004000 0x0000400 973 <0x00004000 0x00004000 0x001000>, /* ap 17 */
974 <0x00005000 0x0000500 974 <0x00005000 0x00005000 0x001000>, /* ap 18 */
975 <0x0000c000 0x0000c00 975 <0x0000c000 0x0000c000 0x001000>, /* ap 19 */
976 <0x0000d000 0x0000d00 976 <0x0000d000 0x0000d000 0x001000>; /* ap 20 */
977 977
978 target-module@4000 { 978 target-module@4000 { /* 0x4a304000, ap 17 24.0 */
979 compatible = "ti,sysc- 979 compatible = "ti,sysc-omap2", "ti,sysc";
980 reg = <0x4000 0x4>, 980 reg = <0x4000 0x4>,
981 <0x4004 0x4>; 981 <0x4004 0x4>;
982 reg-names = "rev", "sy 982 reg-names = "rev", "sysc";
983 ti,sysc-sidle = <SYSC_ 983 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
984 <SYSC_ 984 <SYSC_IDLE_NO>;
985 /* Domains (V, P, C): 985 /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */
986 clocks = <&l4_wkup_clk 986 clocks = <&l4_wkup_clkctrl OMAP4_COUNTER_32K_CLKCTRL 0>;
987 clock-names = "fck"; 987 clock-names = "fck";
988 #address-cells = <1>; 988 #address-cells = <1>;
989 #size-cells = <1>; 989 #size-cells = <1>;
990 ranges = <0x0 0x4000 0 990 ranges = <0x0 0x4000 0x1000>;
991 991
992 counter32k: counter@0 992 counter32k: counter@0 {
993 compatible = " 993 compatible = "ti,omap-counter32k";
994 reg = <0x0 0x2 994 reg = <0x0 0x20>;
995 }; 995 };
996 }; 996 };
997 997
998 target-module@6000 { 998 target-module@6000 { /* 0x4a306000, ap 3 08.0 */
999 compatible = "ti,sysc- 999 compatible = "ti,sysc-omap4", "ti,sysc";
1000 reg = <0x6000 0x4>; 1000 reg = <0x6000 0x4>;
1001 reg-names = "rev"; 1001 reg-names = "rev";
1002 #address-cells = <1>; 1002 #address-cells = <1>;
1003 #size-cells = <1>; 1003 #size-cells = <1>;
1004 ranges = <0x0 0x6000 1004 ranges = <0x0 0x6000 0x2000>;
1005 1005
1006 prm: prm@0 { 1006 prm: prm@0 {
1007 compatible = 1007 compatible = "ti,omap4-prm", "simple-bus";
1008 reg = <0x0 0x 1008 reg = <0x0 0x2000>;
1009 interrupts = 1009 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1010 #address-cell 1010 #address-cells = <1>;
1011 #size-cells = 1011 #size-cells = <1>;
1012 ranges = <0 0 1012 ranges = <0 0 0x2000>;
1013 1013
1014 prm_clocks: c 1014 prm_clocks: clocks {
1015 #addr 1015 #address-cells = <1>;
1016 #size 1016 #size-cells = <0>;
1017 }; 1017 };
1018 1018
1019 prm_clockdoma 1019 prm_clockdomains: clockdomains {
1020 }; 1020 };
1021 }; 1021 };
1022 }; 1022 };
1023 1023
1024 target-module@a000 { 1024 target-module@a000 { /* 0x4a30a000, ap 15 34.0 */
1025 compatible = "ti,sysc 1025 compatible = "ti,sysc-omap4", "ti,sysc";
1026 reg = <0xa000 0x4>; 1026 reg = <0xa000 0x4>;
1027 reg-names = "rev"; 1027 reg-names = "rev";
1028 #address-cells = <1>; 1028 #address-cells = <1>;
1029 #size-cells = <1>; 1029 #size-cells = <1>;
1030 ranges = <0x0 0xa000 1030 ranges = <0x0 0xa000 0x1000>;
1031 1031
1032 scrm: scrm@0 { 1032 scrm: scrm@0 {
1033 compatible = 1033 compatible = "ti,omap4-scrm";
1034 reg = <0x0 0x 1034 reg = <0x0 0x2000>;
1035 1035
1036 scrm_clocks: 1036 scrm_clocks: clocks {
1037 #addr 1037 #address-cells = <1>;
1038 #size 1038 #size-cells = <0>;
1039 }; 1039 };
1040 1040
1041 scrm_clockdom 1041 scrm_clockdomains: clockdomains {
1042 }; 1042 };
1043 }; 1043 };
1044 }; 1044 };
1045 1045
1046 target-module@c000 { 1046 target-module@c000 { /* 0x4a30c000, ap 19 2c.0 */
1047 compatible = "ti,sysc 1047 compatible = "ti,sysc-omap4", "ti,sysc";
1048 reg = <0xc000 0x4>, 1048 reg = <0xc000 0x4>,
1049 <0xc010 0x4>; 1049 <0xc010 0x4>;
1050 reg-names = "rev", "s 1050 reg-names = "rev", "sysc";
1051 ti,sysc-sidle = <SYSC 1051 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1052 <SYSC 1052 <SYSC_IDLE_NO>,
1053 <SYSC 1053 <SYSC_IDLE_SMART>,
1054 <SYSC 1054 <SYSC_IDLE_SMART_WKUP>;
1055 /* Domains (V, P, C): 1055 /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */
1056 #address-cells = <1>; 1056 #address-cells = <1>;
1057 #size-cells = <1>; 1057 #size-cells = <1>;
1058 ranges = <0x0 0xc000 1058 ranges = <0x0 0xc000 0x1000>;
1059 1059
1060 omap4_scm_wkup: scm@c 1060 omap4_scm_wkup: scm@c000 {
1061 compatible = 1061 compatible = "ti,omap4-scm-wkup";
1062 reg = <0xc000 1062 reg = <0xc000 0x1000>;
1063 }; 1063 };
1064 }; 1064 };
1065 }; 1065 };
1066 1066
1067 segment@10000 { 1067 segment@10000 { /* 0x4a310000 */
1068 compatible = "simple-pm-bus"; 1068 compatible = "simple-pm-bus";
1069 #address-cells = <1>; 1069 #address-cells = <1>;
1070 #size-cells = <1>; 1070 #size-cells = <1>;
1071 ranges = <0x00000000 0x000100 1071 ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */
1072 <0x00001000 0x000110 1072 <0x00001000 0x00011000 0x001000>, /* ap 6 */
1073 <0x00004000 0x000140 1073 <0x00004000 0x00014000 0x001000>, /* ap 7 */
1074 <0x00005000 0x000150 1074 <0x00005000 0x00015000 0x001000>, /* ap 8 */
1075 <0x00008000 0x000180 1075 <0x00008000 0x00018000 0x001000>, /* ap 9 */
1076 <0x00009000 0x000190 1076 <0x00009000 0x00019000 0x001000>, /* ap 10 */
1077 <0x0000c000 0x0001c0 1077 <0x0000c000 0x0001c000 0x001000>, /* ap 11 */
1078 <0x0000d000 0x0001d0 1078 <0x0000d000 0x0001d000 0x001000>, /* ap 12 */
1079 <0x0000e000 0x0001e0 1079 <0x0000e000 0x0001e000 0x001000>, /* ap 21 */
1080 <0x0000f000 0x0001f0 1080 <0x0000f000 0x0001f000 0x001000>; /* ap 22 */
1081 1081
1082 gpio1_target: target-module@0 1082 gpio1_target: target-module@0 { /* 0x4a310000, ap 5 14.0 */
1083 compatible = "ti,sysc 1083 compatible = "ti,sysc-omap2", "ti,sysc";
1084 reg = <0x0 0x4>, 1084 reg = <0x0 0x4>,
1085 <0x10 0x4>, 1085 <0x10 0x4>,
1086 <0x114 0x4>; 1086 <0x114 0x4>;
1087 reg-names = "rev", "s 1087 reg-names = "rev", "sysc", "syss";
1088 ti,sysc-mask = <(SYSC 1088 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1089 SYSC 1089 SYSC_OMAP2_SOFTRESET |
1090 SYSC 1090 SYSC_OMAP2_AUTOIDLE)>;
1091 ti,sysc-sidle = <SYSC 1091 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1092 <SYSC 1092 <SYSC_IDLE_NO>,
1093 <SYSC 1093 <SYSC_IDLE_SMART>,
1094 <SYSC 1094 <SYSC_IDLE_SMART_WKUP>;
1095 ti,syss-mask = <1>; 1095 ti,syss-mask = <1>;
1096 /* Domains (V, P, C): 1096 /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */
1097 clocks = <&l4_wkup_cl 1097 clocks = <&l4_wkup_clkctrl OMAP4_GPIO1_CLKCTRL 0>,
1098 <&l4_wkup_cl 1098 <&l4_wkup_clkctrl OMAP4_GPIO1_CLKCTRL 8>;
1099 clock-names = "fck", 1099 clock-names = "fck", "dbclk";
1100 #address-cells = <1>; 1100 #address-cells = <1>;
1101 #size-cells = <1>; 1101 #size-cells = <1>;
1102 ranges = <0x0 0x0 0x1 1102 ranges = <0x0 0x0 0x1000>;
1103 1103
1104 gpio1: gpio@0 { 1104 gpio1: gpio@0 {
1105 compatible = 1105 compatible = "ti,omap4-gpio";
1106 reg = <0x0 0x 1106 reg = <0x0 0x200>;
1107 interrupts = 1107 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1108 ti,gpio-alway 1108 ti,gpio-always-on;
1109 gpio-controll 1109 gpio-controller;
1110 #gpio-cells = 1110 #gpio-cells = <2>;
1111 interrupt-con 1111 interrupt-controller;
1112 #interrupt-ce 1112 #interrupt-cells = <2>;
1113 }; 1113 };
1114 }; 1114 };
1115 1115
1116 target-module@4000 { 1116 target-module@4000 { /* 0x4a314000, ap 7 18.0 */
1117 compatible = "ti,sysc 1117 compatible = "ti,sysc-omap2", "ti,sysc";
1118 reg = <0x4000 0x4>, 1118 reg = <0x4000 0x4>,
1119 <0x4010 0x4>, 1119 <0x4010 0x4>,
1120 <0x4014 0x4>; 1120 <0x4014 0x4>;
1121 reg-names = "rev", "s 1121 reg-names = "rev", "sysc", "syss";
1122 ti,sysc-mask = <(SYSC 1122 ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
1123 SYSC 1123 SYSC_OMAP2_SOFTRESET)>;
1124 ti,sysc-sidle = <SYSC 1124 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1125 <SYSC 1125 <SYSC_IDLE_NO>,
1126 <SYSC 1126 <SYSC_IDLE_SMART>,
1127 <SYSC 1127 <SYSC_IDLE_SMART_WKUP>;
1128 ti,syss-mask = <1>; 1128 ti,syss-mask = <1>;
1129 /* Domains (V, P, C): 1129 /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */
1130 clocks = <&l4_wkup_cl 1130 clocks = <&l4_wkup_clkctrl OMAP4_WD_TIMER2_CLKCTRL 0>;
1131 clock-names = "fck"; 1131 clock-names = "fck";
1132 #address-cells = <1>; 1132 #address-cells = <1>;
1133 #size-cells = <1>; 1133 #size-cells = <1>;
1134 ranges = <0x0 0x4000 1134 ranges = <0x0 0x4000 0x1000>;
1135 1135
1136 wdt2: wdt@0 { 1136 wdt2: wdt@0 {
1137 compatible = 1137 compatible = "ti,omap4-wdt", "ti,omap3-wdt";
1138 reg = <0x0 0x 1138 reg = <0x0 0x80>;
1139 interrupts = 1139 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1140 }; 1140 };
1141 }; 1141 };
1142 1142
1143 timer1_target: target-module@ 1143 timer1_target: target-module@8000 { /* 0x4a318000, ap 9 1c.0 */
1144 compatible = "ti,sysc 1144 compatible = "ti,sysc-omap2-timer", "ti,sysc";
1145 reg = <0x8000 0x4>, 1145 reg = <0x8000 0x4>,
1146 <0x8010 0x4>, 1146 <0x8010 0x4>,
1147 <0x8014 0x4>; 1147 <0x8014 0x4>;
1148 reg-names = "rev", "s 1148 reg-names = "rev", "sysc", "syss";
1149 ti,sysc-mask = <(SYSC 1149 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1150 SYSC 1150 SYSC_OMAP2_EMUFREE |
1151 SYSC 1151 SYSC_OMAP2_ENAWAKEUP |
1152 SYSC 1152 SYSC_OMAP2_SOFTRESET |
1153 SYSC 1153 SYSC_OMAP2_AUTOIDLE)>;
1154 ti,sysc-sidle = <SYSC 1154 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1155 <SYSC 1155 <SYSC_IDLE_NO>,
1156 <SYSC 1156 <SYSC_IDLE_SMART>;
1157 ti,syss-mask = <1>; 1157 ti,syss-mask = <1>;
1158 /* Domains (V, P, C): 1158 /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */
1159 clocks = <&l4_wkup_cl 1159 clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 0>;
1160 clock-names = "fck"; 1160 clock-names = "fck";
1161 #address-cells = <1>; 1161 #address-cells = <1>;
1162 #size-cells = <1>; 1162 #size-cells = <1>;
1163 ranges = <0x0 0x8000 1163 ranges = <0x0 0x8000 0x1000>;
1164 1164
1165 timer1: timer@0 { 1165 timer1: timer@0 {
1166 compatible = 1166 compatible = "ti,omap3430-timer";
1167 reg = <0x0 0x 1167 reg = <0x0 0x80>;
1168 clocks = <&l4 1168 clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>,
1169 <&sy 1169 <&sys_clkin_ck>;
1170 clock-names = 1170 clock-names = "fck", "timer_sys_ck";
1171 interrupts = 1171 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1172 ti,timer-alwo 1172 ti,timer-alwon;
1173 }; 1173 };
1174 }; 1174 };
1175 1175
1176 target-module@c000 { 1176 target-module@c000 { /* 0x4a31c000, ap 11 20.0 */
1177 compatible = "ti,sysc 1177 compatible = "ti,sysc-omap2", "ti,sysc";
1178 reg = <0xc000 0x4>, 1178 reg = <0xc000 0x4>,
1179 <0xc010 0x4>, 1179 <0xc010 0x4>,
1180 <0xc014 0x4>; 1180 <0xc014 0x4>;
1181 reg-names = "rev", "s 1181 reg-names = "rev", "sysc", "syss";
1182 ti,sysc-mask = <(SYSC 1182 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1183 SYSC 1183 SYSC_OMAP2_EMUFREE |
1184 SYSC 1184 SYSC_OMAP2_ENAWAKEUP |
1185 SYSC 1185 SYSC_OMAP2_SOFTRESET |
1186 SYSC 1186 SYSC_OMAP2_AUTOIDLE)>;
1187 ti,sysc-sidle = <SYSC 1187 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1188 <SYSC 1188 <SYSC_IDLE_NO>,
1189 <SYSC 1189 <SYSC_IDLE_SMART>;
1190 ti,syss-mask = <1>; 1190 ti,syss-mask = <1>;
1191 /* Domains (V, P, C): 1191 /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */
1192 clocks = <&l4_wkup_cl 1192 clocks = <&l4_wkup_clkctrl OMAP4_KBD_CLKCTRL 0>;
1193 clock-names = "fck"; 1193 clock-names = "fck";
1194 #address-cells = <1>; 1194 #address-cells = <1>;
1195 #size-cells = <1>; 1195 #size-cells = <1>;
1196 ranges = <0x0 0xc000 1196 ranges = <0x0 0xc000 0x1000>;
1197 1197
1198 keypad: keypad@0 { 1198 keypad: keypad@0 {
1199 compatible = 1199 compatible = "ti,omap4-keypad";
1200 reg = <0x0 0x 1200 reg = <0x0 0x80>;
1201 interrupts = 1201 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1202 reg-names = " 1202 reg-names = "mpu";
1203 }; 1203 };
1204 }; 1204 };
1205 1205
1206 target-module@e000 { 1206 target-module@e000 { /* 0x4a31e000, ap 21 30.0 */
1207 compatible = "ti,sysc 1207 compatible = "ti,sysc-omap4", "ti,sysc";
1208 reg = <0xe000 0x4>, 1208 reg = <0xe000 0x4>,
1209 <0xe010 0x4>; 1209 <0xe010 0x4>;
1210 reg-names = "rev", "s 1210 reg-names = "rev", "sysc";
1211 ti,sysc-sidle = <SYSC 1211 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1212 <SYSC 1212 <SYSC_IDLE_NO>,
1213 <SYSC 1213 <SYSC_IDLE_SMART>,
1214 <SYSC 1214 <SYSC_IDLE_SMART_WKUP>;
1215 /* Domains (V, P, C): 1215 /* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */
1216 #address-cells = <1>; 1216 #address-cells = <1>;
1217 #size-cells = <1>; 1217 #size-cells = <1>;
1218 ranges = <0x0 0xe000 1218 ranges = <0x0 0xe000 0x1000>;
1219 1219
1220 omap4_pmx_wkup: pinmu 1220 omap4_pmx_wkup: pinmux@40 {
1221 compatible = 1221 compatible = "ti,omap4-padconf",
1222 1222 "pinctrl-single";
1223 reg = <0x40 0 1223 reg = <0x40 0x0038>;
1224 #address-cell 1224 #address-cells = <1>;
1225 #size-cells = 1225 #size-cells = <0>;
1226 #pinctrl-cell 1226 #pinctrl-cells = <1>;
1227 #interrupt-ce 1227 #interrupt-cells = <1>;
1228 interrupt-con 1228 interrupt-controller;
1229 pinctrl-singl 1229 pinctrl-single,register-width = <16>;
1230 pinctrl-singl 1230 pinctrl-single,function-mask = <0x7fff>;
1231 }; 1231 };
1232 }; 1232 };
1233 }; 1233 };
1234 1234
1235 segment@20000 { 1235 segment@20000 { /* 0x4a320000 */
1236 compatible = "simple-pm-bus"; 1236 compatible = "simple-pm-bus";
1237 #address-cells = <1>; 1237 #address-cells = <1>;
1238 #size-cells = <1>; 1238 #size-cells = <1>;
1239 ranges = <0x00006000 0x000260 1239 ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */
1240 <0x0000a000 0x0002a0 1240 <0x0000a000 0x0002a000 0x001000>, /* ap 14 */
1241 <0x00000000 0x000200 1241 <0x00000000 0x00020000 0x001000>, /* ap 23 */
1242 <0x00001000 0x000210 1242 <0x00001000 0x00021000 0x001000>, /* ap 24 */
1243 <0x00002000 0x000220 1243 <0x00002000 0x00022000 0x001000>, /* ap 25 */
1244 <0x00003000 0x000230 1244 <0x00003000 0x00023000 0x001000>, /* ap 26 */
1245 <0x00004000 0x000240 1245 <0x00004000 0x00024000 0x001000>, /* ap 27 */
1246 <0x00005000 0x000250 1246 <0x00005000 0x00025000 0x001000>, /* ap 28 */
1247 <0x00007000 0x000270 1247 <0x00007000 0x00027000 0x000400>, /* ap 29 */
1248 <0x00008000 0x000280 1248 <0x00008000 0x00028000 0x000800>, /* ap 30 */
1249 <0x00009000 0x000290 1249 <0x00009000 0x00029000 0x000400>; /* ap 31 */
1250 1250
1251 target-module@0 { 1251 target-module@0 { /* 0x4a320000, ap 23 04.0 */
1252 compatible = "ti,sysc 1252 compatible = "ti,sysc";
1253 status = "disabled"; 1253 status = "disabled";
1254 #address-cells = <1>; 1254 #address-cells = <1>;
1255 #size-cells = <1>; 1255 #size-cells = <1>;
1256 ranges = <0x0 0x0 0x1 1256 ranges = <0x0 0x0 0x1000>;
1257 }; 1257 };
1258 1258
1259 target-module@2000 { 1259 target-module@2000 { /* 0x4a322000, ap 25 0c.0 */
1260 compatible = "ti,sysc 1260 compatible = "ti,sysc";
1261 status = "disabled"; 1261 status = "disabled";
1262 #address-cells = <1>; 1262 #address-cells = <1>;
1263 #size-cells = <1>; 1263 #size-cells = <1>;
1264 ranges = <0x0 0x2000 1264 ranges = <0x0 0x2000 0x1000>;
1265 }; 1265 };
1266 1266
1267 target-module@4000 { 1267 target-module@4000 { /* 0x4a324000, ap 27 10.0 */
1268 compatible = "ti,sysc 1268 compatible = "ti,sysc";
1269 status = "disabled"; 1269 status = "disabled";
1270 #address-cells = <1>; 1270 #address-cells = <1>;
1271 #size-cells = <1>; 1271 #size-cells = <1>;
1272 ranges = <0x0 0x4000 1272 ranges = <0x0 0x4000 0x1000>;
1273 }; 1273 };
1274 1274
1275 target-module@6000 { 1275 target-module@6000 { /* 0x4a326000, ap 13 28.0 */
1276 compatible = "ti,sysc 1276 compatible = "ti,sysc";
1277 status = "disabled"; 1277 status = "disabled";
1278 #address-cells = <1>; 1278 #address-cells = <1>;
1279 #size-cells = <1>; 1279 #size-cells = <1>;
1280 ranges = <0x00000000 1280 ranges = <0x00000000 0x00006000 0x00001000>,
1281 <0x00001000 1281 <0x00001000 0x00007000 0x00000400>,
1282 <0x00002000 1282 <0x00002000 0x00008000 0x00000800>,
1283 <0x00003000 1283 <0x00003000 0x00009000 0x00000400>;
1284 }; 1284 };
1285 }; 1285 };
1286 }; 1286 };
1287 1287
1288 &l4_per { 1288 &l4_per { /* 0x48000000 */
1289 compatible = "ti,omap4-l4-per", "simp 1289 compatible = "ti,omap4-l4-per", "simple-pm-bus";
1290 power-domains = <&prm_l4per>; 1290 power-domains = <&prm_l4per>;
1291 clocks = <&l4_per_clkctrl OMAP4_L4_PE 1291 clocks = <&l4_per_clkctrl OMAP4_L4_PER_CLKCTRL 0>;
1292 clock-names = "fck"; 1292 clock-names = "fck";
1293 reg = <0x48000000 0x800>, 1293 reg = <0x48000000 0x800>,
1294 <0x48000800 0x800>, 1294 <0x48000800 0x800>,
1295 <0x48001000 0x400>, 1295 <0x48001000 0x400>,
1296 <0x48001400 0x400>, 1296 <0x48001400 0x400>,
1297 <0x48001800 0x400>, 1297 <0x48001800 0x400>,
1298 <0x48001c00 0x400>; 1298 <0x48001c00 0x400>;
1299 reg-names = "ap", "la", "ia0", "ia1", 1299 reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
1300 #address-cells = <1>; 1300 #address-cells = <1>;
1301 #size-cells = <1>; 1301 #size-cells = <1>;
1302 ranges = <0x00000000 0x48000000 0x200 1302 ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */
1303 <0x00200000 0x48200000 0x200 1303 <0x00200000 0x48200000 0x200000>; /* segment 1 */
1304 1304
1305 segment@0 { 1305 segment@0 { /* 0x48000000 */
1306 compatible = "simple-pm-bus"; 1306 compatible = "simple-pm-bus";
1307 #address-cells = <1>; 1307 #address-cells = <1>;
1308 #size-cells = <1>; 1308 #size-cells = <1>;
1309 ranges = <0x00000000 0x000000 1309 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
1310 <0x00001000 0x000010 1310 <0x00001000 0x00001000 0x000400>, /* ap 1 */
1311 <0x00000800 0x000008 1311 <0x00000800 0x00000800 0x000800>, /* ap 2 */
1312 <0x00020000 0x000200 1312 <0x00020000 0x00020000 0x001000>, /* ap 3 */
1313 <0x00021000 0x000210 1313 <0x00021000 0x00021000 0x001000>, /* ap 4 */
1314 <0x00032000 0x000320 1314 <0x00032000 0x00032000 0x001000>, /* ap 5 */
1315 <0x00033000 0x000330 1315 <0x00033000 0x00033000 0x001000>, /* ap 6 */
1316 <0x00034000 0x000340 1316 <0x00034000 0x00034000 0x001000>, /* ap 7 */
1317 <0x00035000 0x000350 1317 <0x00035000 0x00035000 0x001000>, /* ap 8 */
1318 <0x00036000 0x000360 1318 <0x00036000 0x00036000 0x001000>, /* ap 9 */
1319 <0x00037000 0x000370 1319 <0x00037000 0x00037000 0x001000>, /* ap 10 */
1320 <0x0003e000 0x0003e0 1320 <0x0003e000 0x0003e000 0x001000>, /* ap 11 */
1321 <0x0003f000 0x0003f0 1321 <0x0003f000 0x0003f000 0x001000>, /* ap 12 */
1322 <0x00040000 0x000400 1322 <0x00040000 0x00040000 0x010000>, /* ap 13 */
1323 <0x00050000 0x000500 1323 <0x00050000 0x00050000 0x001000>, /* ap 14 */
1324 <0x00055000 0x000550 1324 <0x00055000 0x00055000 0x001000>, /* ap 15 */
1325 <0x00056000 0x000560 1325 <0x00056000 0x00056000 0x001000>, /* ap 16 */
1326 <0x00057000 0x000570 1326 <0x00057000 0x00057000 0x001000>, /* ap 17 */
1327 <0x00058000 0x000580 1327 <0x00058000 0x00058000 0x001000>, /* ap 18 */
1328 <0x00059000 0x000590 1328 <0x00059000 0x00059000 0x001000>, /* ap 19 */
1329 <0x0005a000 0x0005a0 1329 <0x0005a000 0x0005a000 0x001000>, /* ap 20 */
1330 <0x0005b000 0x0005b0 1330 <0x0005b000 0x0005b000 0x001000>, /* ap 21 */
1331 <0x0005c000 0x0005c0 1331 <0x0005c000 0x0005c000 0x001000>, /* ap 22 */
1332 <0x0005d000 0x0005d0 1332 <0x0005d000 0x0005d000 0x001000>, /* ap 23 */
1333 <0x0005e000 0x0005e0 1333 <0x0005e000 0x0005e000 0x001000>, /* ap 24 */
1334 <0x00060000 0x000600 1334 <0x00060000 0x00060000 0x001000>, /* ap 25 */
1335 <0x0006a000 0x0006a0 1335 <0x0006a000 0x0006a000 0x001000>, /* ap 26 */
1336 <0x0006b000 0x0006b0 1336 <0x0006b000 0x0006b000 0x001000>, /* ap 27 */
1337 <0x0006c000 0x0006c0 1337 <0x0006c000 0x0006c000 0x001000>, /* ap 28 */
1338 <0x0006d000 0x0006d0 1338 <0x0006d000 0x0006d000 0x001000>, /* ap 29 */
1339 <0x0006e000 0x0006e0 1339 <0x0006e000 0x0006e000 0x001000>, /* ap 30 */
1340 <0x0006f000 0x0006f0 1340 <0x0006f000 0x0006f000 0x001000>, /* ap 31 */
1341 <0x00070000 0x000700 1341 <0x00070000 0x00070000 0x001000>, /* ap 32 */
1342 <0x00071000 0x000710 1342 <0x00071000 0x00071000 0x001000>, /* ap 33 */
1343 <0x00072000 0x000720 1343 <0x00072000 0x00072000 0x001000>, /* ap 34 */
1344 <0x00073000 0x000730 1344 <0x00073000 0x00073000 0x001000>, /* ap 35 */
1345 <0x00061000 0x000610 1345 <0x00061000 0x00061000 0x001000>, /* ap 36 */
1346 <0x00096000 0x000960 1346 <0x00096000 0x00096000 0x001000>, /* ap 37 */
1347 <0x00097000 0x000970 1347 <0x00097000 0x00097000 0x001000>, /* ap 38 */
1348 <0x00076000 0x000760 1348 <0x00076000 0x00076000 0x001000>, /* ap 39 */
1349 <0x00077000 0x000770 1349 <0x00077000 0x00077000 0x001000>, /* ap 40 */
1350 <0x00078000 0x000780 1350 <0x00078000 0x00078000 0x001000>, /* ap 41 */
1351 <0x00079000 0x000790 1351 <0x00079000 0x00079000 0x001000>, /* ap 42 */
1352 <0x00086000 0x000860 1352 <0x00086000 0x00086000 0x001000>, /* ap 43 */
1353 <0x00087000 0x000870 1353 <0x00087000 0x00087000 0x001000>, /* ap 44 */
1354 <0x00088000 0x000880 1354 <0x00088000 0x00088000 0x001000>, /* ap 45 */
1355 <0x00089000 0x000890 1355 <0x00089000 0x00089000 0x001000>, /* ap 46 */
1356 <0x000b0000 0x000b00 1356 <0x000b0000 0x000b0000 0x001000>, /* ap 47 */
1357 <0x000b1000 0x000b10 1357 <0x000b1000 0x000b1000 0x001000>, /* ap 48 */
1358 <0x00098000 0x000980 1358 <0x00098000 0x00098000 0x001000>, /* ap 49 */
1359 <0x00099000 0x000990 1359 <0x00099000 0x00099000 0x001000>, /* ap 50 */
1360 <0x0009a000 0x0009a0 1360 <0x0009a000 0x0009a000 0x001000>, /* ap 51 */
1361 <0x0009b000 0x0009b0 1361 <0x0009b000 0x0009b000 0x001000>, /* ap 52 */
1362 <0x0009c000 0x0009c0 1362 <0x0009c000 0x0009c000 0x001000>, /* ap 53 */
1363 <0x0009d000 0x0009d0 1363 <0x0009d000 0x0009d000 0x001000>, /* ap 54 */
1364 <0x0009e000 0x0009e0 1364 <0x0009e000 0x0009e000 0x001000>, /* ap 55 */
1365 <0x0009f000 0x0009f0 1365 <0x0009f000 0x0009f000 0x001000>, /* ap 56 */
1366 <0x00090000 0x000900 1366 <0x00090000 0x00090000 0x002000>, /* ap 57 */
1367 <0x00092000 0x000920 1367 <0x00092000 0x00092000 0x001000>, /* ap 58 */
1368 <0x000a4000 0x000a40 1368 <0x000a4000 0x000a4000 0x001000>, /* ap 59 */
1369 <0x000a6000 0x000a60 1369 <0x000a6000 0x000a6000 0x001000>, /* ap 60 */
1370 <0x000a8000 0x000a80 1370 <0x000a8000 0x000a8000 0x004000>, /* ap 61 */
1371 <0x000ac000 0x000ac0 1371 <0x000ac000 0x000ac000 0x001000>, /* ap 62 */
1372 <0x000ad000 0x000ad0 1372 <0x000ad000 0x000ad000 0x001000>, /* ap 63 */
1373 <0x000ae000 0x000ae0 1373 <0x000ae000 0x000ae000 0x001000>, /* ap 64 */
1374 <0x000b2000 0x000b20 1374 <0x000b2000 0x000b2000 0x001000>, /* ap 65 */
1375 <0x000b3000 0x000b30 1375 <0x000b3000 0x000b3000 0x001000>, /* ap 66 */
1376 <0x000b4000 0x000b40 1376 <0x000b4000 0x000b4000 0x001000>, /* ap 67 */
1377 <0x000b5000 0x000b50 1377 <0x000b5000 0x000b5000 0x001000>, /* ap 68 */
1378 <0x000b8000 0x000b80 1378 <0x000b8000 0x000b8000 0x001000>, /* ap 69 */
1379 <0x000b9000 0x000b90 1379 <0x000b9000 0x000b9000 0x001000>, /* ap 70 */
1380 <0x000ba000 0x000ba0 1380 <0x000ba000 0x000ba000 0x001000>, /* ap 71 */
1381 <0x000bb000 0x000bb0 1381 <0x000bb000 0x000bb000 0x001000>, /* ap 72 */
1382 <0x000d1000 0x000d10 1382 <0x000d1000 0x000d1000 0x001000>, /* ap 73 */
1383 <0x000d2000 0x000d20 1383 <0x000d2000 0x000d2000 0x001000>, /* ap 74 */
1384 <0x000d5000 0x000d50 1384 <0x000d5000 0x000d5000 0x001000>, /* ap 75 */
1385 <0x000d6000 0x000d60 1385 <0x000d6000 0x000d6000 0x001000>, /* ap 76 */
1386 <0x000a2000 0x000a20 1386 <0x000a2000 0x000a2000 0x001000>, /* ap 79 */
1387 <0x000a3000 0x000a30 1387 <0x000a3000 0x000a3000 0x001000>, /* ap 80 */
1388 <0x00001400 0x000014 1388 <0x00001400 0x00001400 0x000400>, /* ap 81 */
1389 <0x00001800 0x000018 1389 <0x00001800 0x00001800 0x000400>, /* ap 82 */
1390 <0x00001c00 0x00001c 1390 <0x00001c00 0x00001c00 0x000400>, /* ap 83 */
1391 <0x000a5000 0x000a50 1391 <0x000a5000 0x000a5000 0x001000>; /* ap 84 */
1392 1392
1393 target-module@20000 { 1393 target-module@20000 { /* 0x48020000, ap 3 06.0 */
1394 compatible = "ti,sysc 1394 compatible = "ti,sysc-omap2", "ti,sysc";
1395 reg = <0x20050 0x4>, 1395 reg = <0x20050 0x4>,
1396 <0x20054 0x4>, 1396 <0x20054 0x4>,
1397 <0x20058 0x4>; 1397 <0x20058 0x4>;
1398 reg-names = "rev", "s 1398 reg-names = "rev", "sysc", "syss";
1399 ti,sysc-mask = <(SYSC 1399 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1400 SYSC 1400 SYSC_OMAP2_SOFTRESET |
1401 SYSC 1401 SYSC_OMAP2_AUTOIDLE)>;
1402 ti,sysc-sidle = <SYSC 1402 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1403 <SYSC 1403 <SYSC_IDLE_NO>,
1404 <SYSC 1404 <SYSC_IDLE_SMART>,
1405 <SYSC 1405 <SYSC_IDLE_SMART_WKUP>;
1406 ti,syss-mask = <1>; 1406 ti,syss-mask = <1>;
1407 /* Domains (V, P, C): 1407 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1408 clocks = <&l4_per_clk 1408 clocks = <&l4_per_clkctrl OMAP4_UART3_CLKCTRL 0>;
1409 clock-names = "fck"; 1409 clock-names = "fck";
1410 #address-cells = <1>; 1410 #address-cells = <1>;
1411 #size-cells = <1>; 1411 #size-cells = <1>;
1412 ranges = <0x0 0x20000 1412 ranges = <0x0 0x20000 0x1000>;
1413 1413
1414 uart3: serial@0 { 1414 uart3: serial@0 {
1415 compatible = 1415 compatible = "ti,omap4-uart";
1416 reg = <0x0 0x 1416 reg = <0x0 0x100>;
1417 interrupts = 1417 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1418 clock-frequen 1418 clock-frequency = <48000000>;
1419 }; 1419 };
1420 }; 1420 };
1421 1421
1422 target-module@32000 { 1422 target-module@32000 { /* 0x48032000, ap 5 02.0 */
1423 compatible = "ti,sysc 1423 compatible = "ti,sysc-omap2-timer", "ti,sysc";
1424 reg = <0x32000 0x4>, 1424 reg = <0x32000 0x4>,
1425 <0x32010 0x4>, 1425 <0x32010 0x4>,
1426 <0x32014 0x4>; 1426 <0x32014 0x4>;
1427 reg-names = "rev", "s 1427 reg-names = "rev", "sysc", "syss";
1428 ti,sysc-mask = <(SYSC 1428 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1429 SYSC 1429 SYSC_OMAP2_EMUFREE |
1430 SYSC 1430 SYSC_OMAP2_ENAWAKEUP |
1431 SYSC 1431 SYSC_OMAP2_SOFTRESET |
1432 SYSC 1432 SYSC_OMAP2_AUTOIDLE)>;
1433 ti,sysc-sidle = <SYSC 1433 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1434 <SYSC 1434 <SYSC_IDLE_NO>,
1435 <SYSC 1435 <SYSC_IDLE_SMART>;
1436 ti,syss-mask = <1>; 1436 ti,syss-mask = <1>;
1437 /* Domains (V, P, C): 1437 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1438 clocks = <&l4_per_clk 1438 clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 0>;
1439 clock-names = "fck"; 1439 clock-names = "fck";
1440 #address-cells = <1>; 1440 #address-cells = <1>;
1441 #size-cells = <1>; 1441 #size-cells = <1>;
1442 ranges = <0x0 0x32000 1442 ranges = <0x0 0x32000 0x1000>;
1443 1443
1444 timer2: timer@0 { 1444 timer2: timer@0 {
1445 compatible = 1445 compatible = "ti,omap3430-timer";
1446 reg = <0x0 0x 1446 reg = <0x0 0x80>;
1447 clocks = <&l4 1447 clocks = <&l4_per_clkctrl OMAP4_TIMER2_CLKCTRL 24>,
1448 <&sy 1448 <&sys_clkin_ck>;
1449 clock-names = 1449 clock-names = "fck", "timer_sys_ck";
1450 interrupts = 1450 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1451 }; 1451 };
1452 }; 1452 };
1453 1453
1454 target-module@34000 { 1454 target-module@34000 { /* 0x48034000, ap 7 04.0 */
1455 compatible = "ti,sysc 1455 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1456 reg = <0x34000 0x4>, 1456 reg = <0x34000 0x4>,
1457 <0x34010 0x4>; 1457 <0x34010 0x4>;
1458 reg-names = "rev", "s 1458 reg-names = "rev", "sysc";
1459 ti,sysc-mask = <(SYSC 1459 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1460 SYSC 1460 SYSC_OMAP4_SOFTRESET)>;
1461 ti,sysc-sidle = <SYSC 1461 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1462 <SYSC 1462 <SYSC_IDLE_NO>,
1463 <SYSC 1463 <SYSC_IDLE_SMART>,
1464 <SYSC 1464 <SYSC_IDLE_SMART_WKUP>;
1465 /* Domains (V, P, C): 1465 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1466 clocks = <&l4_per_clk 1466 clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 0>;
1467 clock-names = "fck"; 1467 clock-names = "fck";
1468 #address-cells = <1>; 1468 #address-cells = <1>;
1469 #size-cells = <1>; 1469 #size-cells = <1>;
1470 ranges = <0x0 0x34000 1470 ranges = <0x0 0x34000 0x1000>;
1471 1471
1472 timer3: timer@0 { 1472 timer3: timer@0 {
1473 compatible = 1473 compatible = "ti,omap4430-timer";
1474 reg = <0x0 0x 1474 reg = <0x0 0x80>;
1475 clocks = <&l4 1475 clocks = <&l4_per_clkctrl OMAP4_TIMER3_CLKCTRL 24>,
1476 <&sy 1476 <&sys_clkin_ck>;
1477 clock-names = 1477 clock-names = "fck", "timer_sys_ck";
1478 interrupts = 1478 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1479 }; 1479 };
1480 }; 1480 };
1481 1481
1482 target-module@36000 { 1482 target-module@36000 { /* 0x48036000, ap 9 0e.0 */
1483 compatible = "ti,sysc 1483 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1484 reg = <0x36000 0x4>, 1484 reg = <0x36000 0x4>,
1485 <0x36010 0x4>; 1485 <0x36010 0x4>;
1486 reg-names = "rev", "s 1486 reg-names = "rev", "sysc";
1487 ti,sysc-mask = <(SYSC 1487 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1488 SYSC 1488 SYSC_OMAP4_SOFTRESET)>;
1489 ti,sysc-sidle = <SYSC 1489 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1490 <SYSC 1490 <SYSC_IDLE_NO>,
1491 <SYSC 1491 <SYSC_IDLE_SMART>,
1492 <SYSC 1492 <SYSC_IDLE_SMART_WKUP>;
1493 /* Domains (V, P, C): 1493 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1494 clocks = <&l4_per_clk 1494 clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 0>;
1495 clock-names = "fck"; 1495 clock-names = "fck";
1496 #address-cells = <1>; 1496 #address-cells = <1>;
1497 #size-cells = <1>; 1497 #size-cells = <1>;
1498 ranges = <0x0 0x36000 1498 ranges = <0x0 0x36000 0x1000>;
1499 1499
1500 timer4: timer@0 { 1500 timer4: timer@0 {
1501 compatible = 1501 compatible = "ti,omap4430-timer";
1502 reg = <0x0 0x 1502 reg = <0x0 0x80>;
1503 clocks = <&l4 1503 clocks = <&l4_per_clkctrl OMAP4_TIMER4_CLKCTRL 24>,
1504 <&sy 1504 <&sys_clkin_ck>;
1505 clock-names = 1505 clock-names = "fck", "timer_sys_ck";
1506 interrupts = 1506 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1507 }; 1507 };
1508 }; 1508 };
1509 1509
1510 target-module@3e000 { 1510 target-module@3e000 { /* 0x4803e000, ap 11 08.0 */
1511 compatible = "ti,sysc 1511 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1512 reg = <0x3e000 0x4>, 1512 reg = <0x3e000 0x4>,
1513 <0x3e010 0x4>; 1513 <0x3e010 0x4>;
1514 reg-names = "rev", "s 1514 reg-names = "rev", "sysc";
1515 ti,sysc-mask = <(SYSC 1515 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1516 SYSC 1516 SYSC_OMAP4_SOFTRESET)>;
1517 ti,sysc-sidle = <SYSC 1517 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1518 <SYSC 1518 <SYSC_IDLE_NO>,
1519 <SYSC 1519 <SYSC_IDLE_SMART>,
1520 <SYSC 1520 <SYSC_IDLE_SMART_WKUP>;
1521 /* Domains (V, P, C): 1521 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1522 clocks = <&l4_per_clk 1522 clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 0>;
1523 clock-names = "fck"; 1523 clock-names = "fck";
1524 #address-cells = <1>; 1524 #address-cells = <1>;
1525 #size-cells = <1>; 1525 #size-cells = <1>;
1526 ranges = <0x0 0x3e000 1526 ranges = <0x0 0x3e000 0x1000>;
1527 1527
1528 timer9: timer@0 { 1528 timer9: timer@0 {
1529 compatible = 1529 compatible = "ti,omap4430-timer";
1530 reg = <0x0 0x 1530 reg = <0x0 0x80>;
1531 clocks = <&l4 1531 clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>,
1532 <&sy 1532 <&sys_clkin_ck>;
1533 clock-names = 1533 clock-names = "fck", "timer_sys_ck";
1534 interrupts = 1534 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1535 ti,timer-pwm; 1535 ti,timer-pwm;
1536 }; 1536 };
1537 }; 1537 };
1538 1538
1539 /* Unused DSS L4 access, see 1539 /* Unused DSS L4 access, see L3 instead */
1540 target-module@40000 { 1540 target-module@40000 { /* 0x48040000, ap 13 0a.0 */
1541 compatible = "ti,sysc 1541 compatible = "ti,sysc";
1542 status = "disabled"; 1542 status = "disabled";
1543 #address-cells = <1>; 1543 #address-cells = <1>;
1544 #size-cells = <1>; 1544 #size-cells = <1>;
1545 ranges = <0x0 0x40000 1545 ranges = <0x0 0x40000 0x10000>;
1546 }; 1546 };
1547 1547
1548 target-module@55000 { 1548 target-module@55000 { /* 0x48055000, ap 15 0c.0 */
1549 compatible = "ti,sysc 1549 compatible = "ti,sysc-omap2", "ti,sysc";
1550 reg = <0x55000 0x4>, 1550 reg = <0x55000 0x4>,
1551 <0x55010 0x4>, 1551 <0x55010 0x4>,
1552 <0x55114 0x4>; 1552 <0x55114 0x4>;
1553 reg-names = "rev", "s 1553 reg-names = "rev", "sysc", "syss";
1554 ti,sysc-mask = <(SYSC 1554 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1555 SYSC 1555 SYSC_OMAP2_SOFTRESET |
1556 SYSC 1556 SYSC_OMAP2_AUTOIDLE)>;
1557 ti,sysc-sidle = <SYSC 1557 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1558 <SYSC 1558 <SYSC_IDLE_NO>,
1559 <SYSC 1559 <SYSC_IDLE_SMART>,
1560 <SYSC 1560 <SYSC_IDLE_SMART_WKUP>;
1561 ti,syss-mask = <1>; 1561 ti,syss-mask = <1>;
1562 /* Domains (V, P, C): 1562 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1563 clocks = <&l4_per_clk 1563 clocks = <&l4_per_clkctrl OMAP4_GPIO2_CLKCTRL 0>,
1564 <&l4_per_clk 1564 <&l4_per_clkctrl OMAP4_GPIO2_CLKCTRL 8>;
1565 clock-names = "fck", 1565 clock-names = "fck", "dbclk";
1566 #address-cells = <1>; 1566 #address-cells = <1>;
1567 #size-cells = <1>; 1567 #size-cells = <1>;
1568 ranges = <0x0 0x55000 1568 ranges = <0x0 0x55000 0x1000>;
1569 1569
1570 gpio2: gpio@0 { 1570 gpio2: gpio@0 {
1571 compatible = 1571 compatible = "ti,omap4-gpio";
1572 reg = <0x0 0x 1572 reg = <0x0 0x200>;
1573 interrupts = 1573 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1574 gpio-controll 1574 gpio-controller;
1575 #gpio-cells = 1575 #gpio-cells = <2>;
1576 interrupt-con 1576 interrupt-controller;
1577 #interrupt-ce 1577 #interrupt-cells = <2>;
1578 }; 1578 };
1579 }; 1579 };
1580 1580
1581 target-module@57000 { 1581 target-module@57000 { /* 0x48057000, ap 17 16.0 */
1582 compatible = "ti,sysc 1582 compatible = "ti,sysc-omap2", "ti,sysc";
1583 reg = <0x57000 0x4>, 1583 reg = <0x57000 0x4>,
1584 <0x57010 0x4>, 1584 <0x57010 0x4>,
1585 <0x57114 0x4>; 1585 <0x57114 0x4>;
1586 reg-names = "rev", "s 1586 reg-names = "rev", "sysc", "syss";
1587 ti,sysc-mask = <(SYSC 1587 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1588 SYSC 1588 SYSC_OMAP2_SOFTRESET |
1589 SYSC 1589 SYSC_OMAP2_AUTOIDLE)>;
1590 ti,sysc-sidle = <SYSC 1590 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1591 <SYSC 1591 <SYSC_IDLE_NO>,
1592 <SYSC 1592 <SYSC_IDLE_SMART>,
1593 <SYSC 1593 <SYSC_IDLE_SMART_WKUP>;
1594 ti,syss-mask = <1>; 1594 ti,syss-mask = <1>;
1595 /* Domains (V, P, C): 1595 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1596 clocks = <&l4_per_clk 1596 clocks = <&l4_per_clkctrl OMAP4_GPIO3_CLKCTRL 0>,
1597 <&l4_per_clk 1597 <&l4_per_clkctrl OMAP4_GPIO3_CLKCTRL 8>;
1598 clock-names = "fck", 1598 clock-names = "fck", "dbclk";
1599 #address-cells = <1>; 1599 #address-cells = <1>;
1600 #size-cells = <1>; 1600 #size-cells = <1>;
1601 ranges = <0x0 0x57000 1601 ranges = <0x0 0x57000 0x1000>;
1602 1602
1603 gpio3: gpio@0 { 1603 gpio3: gpio@0 {
1604 compatible = 1604 compatible = "ti,omap4-gpio";
1605 reg = <0x0 0x 1605 reg = <0x0 0x200>;
1606 interrupts = 1606 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1607 gpio-controll 1607 gpio-controller;
1608 #gpio-cells = 1608 #gpio-cells = <2>;
1609 interrupt-con 1609 interrupt-controller;
1610 #interrupt-ce 1610 #interrupt-cells = <2>;
1611 }; 1611 };
1612 }; 1612 };
1613 1613
1614 target-module@59000 { 1614 target-module@59000 { /* 0x48059000, ap 19 10.0 */
1615 compatible = "ti,sysc 1615 compatible = "ti,sysc-omap2", "ti,sysc";
1616 reg = <0x59000 0x4>, 1616 reg = <0x59000 0x4>,
1617 <0x59010 0x4>, 1617 <0x59010 0x4>,
1618 <0x59114 0x4>; 1618 <0x59114 0x4>;
1619 reg-names = "rev", "s 1619 reg-names = "rev", "sysc", "syss";
1620 ti,sysc-mask = <(SYSC 1620 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1621 SYSC 1621 SYSC_OMAP2_SOFTRESET |
1622 SYSC 1622 SYSC_OMAP2_AUTOIDLE)>;
1623 ti,sysc-sidle = <SYSC 1623 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1624 <SYSC 1624 <SYSC_IDLE_NO>,
1625 <SYSC 1625 <SYSC_IDLE_SMART>,
1626 <SYSC 1626 <SYSC_IDLE_SMART_WKUP>;
1627 ti,syss-mask = <1>; 1627 ti,syss-mask = <1>;
1628 /* Domains (V, P, C): 1628 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1629 clocks = <&l4_per_clk 1629 clocks = <&l4_per_clkctrl OMAP4_GPIO4_CLKCTRL 0>,
1630 <&l4_per_clk 1630 <&l4_per_clkctrl OMAP4_GPIO4_CLKCTRL 8>;
1631 clock-names = "fck", 1631 clock-names = "fck", "dbclk";
1632 #address-cells = <1>; 1632 #address-cells = <1>;
1633 #size-cells = <1>; 1633 #size-cells = <1>;
1634 ranges = <0x0 0x59000 1634 ranges = <0x0 0x59000 0x1000>;
1635 1635
1636 gpio4: gpio@0 { 1636 gpio4: gpio@0 {
1637 compatible = 1637 compatible = "ti,omap4-gpio";
1638 reg = <0x0 0x 1638 reg = <0x0 0x200>;
1639 interrupts = 1639 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1640 gpio-controll 1640 gpio-controller;
1641 #gpio-cells = 1641 #gpio-cells = <2>;
1642 interrupt-con 1642 interrupt-controller;
1643 #interrupt-ce 1643 #interrupt-cells = <2>;
1644 }; 1644 };
1645 }; 1645 };
1646 1646
1647 target-module@5b000 { 1647 target-module@5b000 { /* 0x4805b000, ap 21 12.0 */
1648 compatible = "ti,sysc 1648 compatible = "ti,sysc-omap2", "ti,sysc";
1649 reg = <0x5b000 0x4>, 1649 reg = <0x5b000 0x4>,
1650 <0x5b010 0x4>, 1650 <0x5b010 0x4>,
1651 <0x5b114 0x4>; 1651 <0x5b114 0x4>;
1652 reg-names = "rev", "s 1652 reg-names = "rev", "sysc", "syss";
1653 ti,sysc-mask = <(SYSC 1653 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1654 SYSC 1654 SYSC_OMAP2_SOFTRESET |
1655 SYSC 1655 SYSC_OMAP2_AUTOIDLE)>;
1656 ti,sysc-sidle = <SYSC 1656 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1657 <SYSC 1657 <SYSC_IDLE_NO>,
1658 <SYSC 1658 <SYSC_IDLE_SMART>,
1659 <SYSC 1659 <SYSC_IDLE_SMART_WKUP>;
1660 ti,syss-mask = <1>; 1660 ti,syss-mask = <1>;
1661 /* Domains (V, P, C): 1661 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1662 clocks = <&l4_per_clk 1662 clocks = <&l4_per_clkctrl OMAP4_GPIO5_CLKCTRL 0>,
1663 <&l4_per_clk 1663 <&l4_per_clkctrl OMAP4_GPIO5_CLKCTRL 8>;
1664 clock-names = "fck", 1664 clock-names = "fck", "dbclk";
1665 #address-cells = <1>; 1665 #address-cells = <1>;
1666 #size-cells = <1>; 1666 #size-cells = <1>;
1667 ranges = <0x0 0x5b000 1667 ranges = <0x0 0x5b000 0x1000>;
1668 1668
1669 gpio5: gpio@0 { 1669 gpio5: gpio@0 {
1670 compatible = 1670 compatible = "ti,omap4-gpio";
1671 reg = <0x0 0x 1671 reg = <0x0 0x200>;
1672 interrupts = 1672 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1673 gpio-controll 1673 gpio-controller;
1674 #gpio-cells = 1674 #gpio-cells = <2>;
1675 interrupt-con 1675 interrupt-controller;
1676 #interrupt-ce 1676 #interrupt-cells = <2>;
1677 }; 1677 };
1678 }; 1678 };
1679 1679
1680 target-module@5d000 { 1680 target-module@5d000 { /* 0x4805d000, ap 23 14.0 */
1681 compatible = "ti,sysc 1681 compatible = "ti,sysc-omap2", "ti,sysc";
1682 reg = <0x5d000 0x4>, 1682 reg = <0x5d000 0x4>,
1683 <0x5d010 0x4>, 1683 <0x5d010 0x4>,
1684 <0x5d114 0x4>; 1684 <0x5d114 0x4>;
1685 reg-names = "rev", "s 1685 reg-names = "rev", "sysc", "syss";
1686 ti,sysc-mask = <(SYSC 1686 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1687 SYSC 1687 SYSC_OMAP2_SOFTRESET |
1688 SYSC 1688 SYSC_OMAP2_AUTOIDLE)>;
1689 ti,sysc-sidle = <SYSC 1689 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1690 <SYSC 1690 <SYSC_IDLE_NO>,
1691 <SYSC 1691 <SYSC_IDLE_SMART>,
1692 <SYSC 1692 <SYSC_IDLE_SMART_WKUP>;
1693 ti,syss-mask = <1>; 1693 ti,syss-mask = <1>;
1694 /* Domains (V, P, C): 1694 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1695 clocks = <&l4_per_clk 1695 clocks = <&l4_per_clkctrl OMAP4_GPIO6_CLKCTRL 0>,
1696 <&l4_per_clk 1696 <&l4_per_clkctrl OMAP4_GPIO6_CLKCTRL 8>;
1697 clock-names = "fck", 1697 clock-names = "fck", "dbclk";
1698 #address-cells = <1>; 1698 #address-cells = <1>;
1699 #size-cells = <1>; 1699 #size-cells = <1>;
1700 ranges = <0x0 0x5d000 1700 ranges = <0x0 0x5d000 0x1000>;
1701 1701
1702 gpio6: gpio@0 { 1702 gpio6: gpio@0 {
1703 compatible = 1703 compatible = "ti,omap4-gpio";
1704 reg = <0x0 0x 1704 reg = <0x0 0x200>;
1705 interrupts = 1705 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
1706 gpio-controll 1706 gpio-controller;
1707 #gpio-cells = 1707 #gpio-cells = <2>;
1708 interrupt-con 1708 interrupt-controller;
1709 #interrupt-ce 1709 #interrupt-cells = <2>;
1710 }; 1710 };
1711 }; 1711 };
1712 1712
1713 target-module@60000 { 1713 target-module@60000 { /* 0x48060000, ap 25 1e.0 */
1714 compatible = "ti,sysc 1714 compatible = "ti,sysc-omap2", "ti,sysc";
1715 reg = <0x60000 0x8>, 1715 reg = <0x60000 0x8>,
1716 <0x60010 0x8>, 1716 <0x60010 0x8>,
1717 <0x60090 0x8>; 1717 <0x60090 0x8>;
1718 reg-names = "rev", "s 1718 reg-names = "rev", "sysc", "syss";
1719 ti,sysc-mask = <(SYSC 1719 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1720 SYSC 1720 SYSC_OMAP2_ENAWAKEUP |
1721 SYSC 1721 SYSC_OMAP2_SOFTRESET |
1722 SYSC 1722 SYSC_OMAP2_AUTOIDLE)>;
1723 ti,sysc-sidle = <SYSC 1723 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1724 <SYSC 1724 <SYSC_IDLE_NO>,
1725 <SYSC 1725 <SYSC_IDLE_SMART>,
1726 <SYSC 1726 <SYSC_IDLE_SMART_WKUP>;
1727 ti,syss-mask = <1>; 1727 ti,syss-mask = <1>;
1728 /* Domains (V, P, C): 1728 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1729 clocks = <&l4_per_clk 1729 clocks = <&l4_per_clkctrl OMAP4_I2C3_CLKCTRL 0>;
1730 clock-names = "fck"; 1730 clock-names = "fck";
1731 #address-cells = <1>; 1731 #address-cells = <1>;
1732 #size-cells = <1>; 1732 #size-cells = <1>;
1733 ranges = <0x0 0x60000 1733 ranges = <0x0 0x60000 0x1000>;
1734 1734
1735 i2c3: i2c@0 { 1735 i2c3: i2c@0 {
1736 compatible = 1736 compatible = "ti,omap4-i2c";
1737 reg = <0x0 0x 1737 reg = <0x0 0x100>;
1738 interrupts = 1738 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1739 #address-cell 1739 #address-cells = <1>;
1740 #size-cells = 1740 #size-cells = <0>;
1741 }; 1741 };
1742 }; 1742 };
1743 1743
1744 target-module@6a000 { 1744 target-module@6a000 { /* 0x4806a000, ap 26 18.0 */
1745 compatible = "ti,sysc 1745 compatible = "ti,sysc-omap2", "ti,sysc";
1746 reg = <0x6a050 0x4>, 1746 reg = <0x6a050 0x4>,
1747 <0x6a054 0x4>, 1747 <0x6a054 0x4>,
1748 <0x6a058 0x4>; 1748 <0x6a058 0x4>;
1749 reg-names = "rev", "s 1749 reg-names = "rev", "sysc", "syss";
1750 ti,sysc-mask = <(SYSC 1750 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1751 SYSC 1751 SYSC_OMAP2_SOFTRESET |
1752 SYSC 1752 SYSC_OMAP2_AUTOIDLE)>;
1753 ti,sysc-sidle = <SYSC 1753 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1754 <SYSC 1754 <SYSC_IDLE_NO>,
1755 <SYSC 1755 <SYSC_IDLE_SMART>,
1756 <SYSC 1756 <SYSC_IDLE_SMART_WKUP>;
1757 ti,syss-mask = <1>; 1757 ti,syss-mask = <1>;
1758 /* Domains (V, P, C): 1758 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1759 clocks = <&l4_per_clk 1759 clocks = <&l4_per_clkctrl OMAP4_UART1_CLKCTRL 0>;
1760 clock-names = "fck"; 1760 clock-names = "fck";
1761 #address-cells = <1>; 1761 #address-cells = <1>;
1762 #size-cells = <1>; 1762 #size-cells = <1>;
1763 ranges = <0x0 0x6a000 1763 ranges = <0x0 0x6a000 0x1000>;
1764 1764
1765 uart1: serial@0 { 1765 uart1: serial@0 {
1766 compatible = 1766 compatible = "ti,omap4-uart";
1767 reg = <0x0 0x 1767 reg = <0x0 0x100>;
1768 interrupts = 1768 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1769 clock-frequen 1769 clock-frequency = <48000000>;
1770 }; 1770 };
1771 }; 1771 };
1772 1772
1773 target-module@6c000 { 1773 target-module@6c000 { /* 0x4806c000, ap 28 20.0 */
1774 compatible = "ti,sysc 1774 compatible = "ti,sysc-omap2", "ti,sysc";
1775 reg = <0x6c050 0x4>, 1775 reg = <0x6c050 0x4>,
1776 <0x6c054 0x4>, 1776 <0x6c054 0x4>,
1777 <0x6c058 0x4>; 1777 <0x6c058 0x4>;
1778 reg-names = "rev", "s 1778 reg-names = "rev", "sysc", "syss";
1779 ti,sysc-mask = <(SYSC 1779 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1780 SYSC 1780 SYSC_OMAP2_SOFTRESET |
1781 SYSC 1781 SYSC_OMAP2_AUTOIDLE)>;
1782 ti,sysc-sidle = <SYSC 1782 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1783 <SYSC 1783 <SYSC_IDLE_NO>,
1784 <SYSC 1784 <SYSC_IDLE_SMART>,
1785 <SYSC 1785 <SYSC_IDLE_SMART_WKUP>;
1786 ti,syss-mask = <1>; 1786 ti,syss-mask = <1>;
1787 /* Domains (V, P, C): 1787 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1788 clocks = <&l4_per_clk 1788 clocks = <&l4_per_clkctrl OMAP4_UART2_CLKCTRL 0>;
1789 clock-names = "fck"; 1789 clock-names = "fck";
1790 #address-cells = <1>; 1790 #address-cells = <1>;
1791 #size-cells = <1>; 1791 #size-cells = <1>;
1792 ranges = <0x0 0x6c000 1792 ranges = <0x0 0x6c000 0x1000>;
1793 1793
1794 uart2: serial@0 { 1794 uart2: serial@0 {
1795 compatible = 1795 compatible = "ti,omap4-uart";
1796 reg = <0x0 0x 1796 reg = <0x0 0x100>;
1797 interrupts = 1797 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1798 clock-frequen 1798 clock-frequency = <48000000>;
1799 }; 1799 };
1800 }; 1800 };
1801 1801
1802 target-module@6e000 { 1802 target-module@6e000 { /* 0x4806e000, ap 30 1c.1 */
1803 compatible = "ti,sysc 1803 compatible = "ti,sysc-omap2", "ti,sysc";
1804 reg = <0x6e050 0x4>, 1804 reg = <0x6e050 0x4>,
1805 <0x6e054 0x4>, 1805 <0x6e054 0x4>,
1806 <0x6e058 0x4>; 1806 <0x6e058 0x4>;
1807 reg-names = "rev", "s 1807 reg-names = "rev", "sysc", "syss";
1808 ti,sysc-mask = <(SYSC 1808 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1809 SYSC 1809 SYSC_OMAP2_SOFTRESET |
1810 SYSC 1810 SYSC_OMAP2_AUTOIDLE)>;
1811 ti,sysc-sidle = <SYSC 1811 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1812 <SYSC 1812 <SYSC_IDLE_NO>,
1813 <SYSC 1813 <SYSC_IDLE_SMART>,
1814 <SYSC 1814 <SYSC_IDLE_SMART_WKUP>;
1815 ti,syss-mask = <1>; 1815 ti,syss-mask = <1>;
1816 /* Domains (V, P, C): 1816 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1817 clocks = <&l4_per_clk 1817 clocks = <&l4_per_clkctrl OMAP4_UART4_CLKCTRL 0>;
1818 clock-names = "fck"; 1818 clock-names = "fck";
1819 #address-cells = <1>; 1819 #address-cells = <1>;
1820 #size-cells = <1>; 1820 #size-cells = <1>;
1821 ranges = <0x0 0x6e000 1821 ranges = <0x0 0x6e000 0x1000>;
1822 1822
1823 uart4: serial@0 { 1823 uart4: serial@0 {
1824 compatible = 1824 compatible = "ti,omap4-uart";
1825 reg = <0x0 0x 1825 reg = <0x0 0x100>;
1826 interrupts = 1826 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1827 clock-frequen 1827 clock-frequency = <48000000>;
1828 }; 1828 };
1829 }; 1829 };
1830 1830
1831 target-module@70000 { 1831 target-module@70000 { /* 0x48070000, ap 32 28.0 */
1832 compatible = "ti,sysc 1832 compatible = "ti,sysc-omap2", "ti,sysc";
1833 reg = <0x70000 0x8>, 1833 reg = <0x70000 0x8>,
1834 <0x70010 0x8>, 1834 <0x70010 0x8>,
1835 <0x70090 0x8>; 1835 <0x70090 0x8>;
1836 reg-names = "rev", "s 1836 reg-names = "rev", "sysc", "syss";
1837 ti,sysc-mask = <(SYSC 1837 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1838 SYSC 1838 SYSC_OMAP2_ENAWAKEUP |
1839 SYSC 1839 SYSC_OMAP2_SOFTRESET |
1840 SYSC 1840 SYSC_OMAP2_AUTOIDLE)>;
1841 ti,sysc-sidle = <SYSC 1841 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1842 <SYSC 1842 <SYSC_IDLE_NO>,
1843 <SYSC 1843 <SYSC_IDLE_SMART>,
1844 <SYSC 1844 <SYSC_IDLE_SMART_WKUP>;
1845 ti,syss-mask = <1>; 1845 ti,syss-mask = <1>;
1846 /* Domains (V, P, C): 1846 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1847 clocks = <&l4_per_clk 1847 clocks = <&l4_per_clkctrl OMAP4_I2C1_CLKCTRL 0>;
1848 clock-names = "fck"; 1848 clock-names = "fck";
1849 #address-cells = <1>; 1849 #address-cells = <1>;
1850 #size-cells = <1>; 1850 #size-cells = <1>;
1851 ranges = <0x0 0x70000 1851 ranges = <0x0 0x70000 0x1000>;
1852 1852
1853 i2c1: i2c@0 { 1853 i2c1: i2c@0 {
1854 compatible = 1854 compatible = "ti,omap4-i2c";
1855 reg = <0x0 0x 1855 reg = <0x0 0x100>;
1856 interrupts = 1856 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1857 #address-cell 1857 #address-cells = <1>;
1858 #size-cells = 1858 #size-cells = <0>;
1859 }; 1859 };
1860 }; 1860 };
1861 1861
1862 target-module@72000 { 1862 target-module@72000 { /* 0x48072000, ap 34 30.0 */
1863 compatible = "ti,sysc 1863 compatible = "ti,sysc-omap2", "ti,sysc";
1864 reg = <0x72000 0x8>, 1864 reg = <0x72000 0x8>,
1865 <0x72010 0x8>, 1865 <0x72010 0x8>,
1866 <0x72090 0x8>; 1866 <0x72090 0x8>;
1867 reg-names = "rev", "s 1867 reg-names = "rev", "sysc", "syss";
1868 ti,sysc-mask = <(SYSC 1868 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1869 SYSC 1869 SYSC_OMAP2_ENAWAKEUP |
1870 SYSC 1870 SYSC_OMAP2_SOFTRESET |
1871 SYSC 1871 SYSC_OMAP2_AUTOIDLE)>;
1872 ti,sysc-sidle = <SYSC 1872 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1873 <SYSC 1873 <SYSC_IDLE_NO>,
1874 <SYSC 1874 <SYSC_IDLE_SMART>,
1875 <SYSC 1875 <SYSC_IDLE_SMART_WKUP>;
1876 ti,syss-mask = <1>; 1876 ti,syss-mask = <1>;
1877 /* Domains (V, P, C): 1877 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1878 clocks = <&l4_per_clk 1878 clocks = <&l4_per_clkctrl OMAP4_I2C2_CLKCTRL 0>;
1879 clock-names = "fck"; 1879 clock-names = "fck";
1880 #address-cells = <1>; 1880 #address-cells = <1>;
1881 #size-cells = <1>; 1881 #size-cells = <1>;
1882 ranges = <0x0 0x72000 1882 ranges = <0x0 0x72000 0x1000>;
1883 1883
1884 i2c2: i2c@0 { 1884 i2c2: i2c@0 {
1885 compatible = 1885 compatible = "ti,omap4-i2c";
1886 reg = <0x0 0x 1886 reg = <0x0 0x100>;
1887 interrupts = 1887 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1888 #address-cell 1888 #address-cells = <1>;
1889 #size-cells = 1889 #size-cells = <0>;
1890 }; 1890 };
1891 }; 1891 };
1892 1892
1893 target-module@76000 { 1893 target-module@76000 { /* 0x48076000, ap 39 38.0 */
1894 compatible = "ti,sysc 1894 compatible = "ti,sysc-omap4", "ti,sysc";
1895 reg = <0x76000 0x4>, 1895 reg = <0x76000 0x4>,
1896 <0x76010 0x4>; 1896 <0x76010 0x4>;
1897 reg-names = "rev", "s 1897 reg-names = "rev", "sysc";
1898 ti,sysc-mask = <SYSC_ 1898 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
1899 ti,sysc-sidle = <SYSC 1899 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1900 <SYSC 1900 <SYSC_IDLE_NO>,
1901 <SYSC 1901 <SYSC_IDLE_SMART>,
1902 <SYSC 1902 <SYSC_IDLE_SMART_WKUP>;
1903 /* Domains (V, P, C): 1903 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1904 clocks = <&l4_per_clk 1904 clocks = <&l4_per_clkctrl OMAP4_SLIMBUS2_CLKCTRL 0>;
1905 clock-names = "fck"; 1905 clock-names = "fck";
1906 #address-cells = <1>; 1906 #address-cells = <1>;
1907 #size-cells = <1>; 1907 #size-cells = <1>;
1908 ranges = <0x0 0x76000 1908 ranges = <0x0 0x76000 0x1000>;
1909 1909
1910 /* No child device bi 1910 /* No child device binding or driver in mainline */
1911 }; 1911 };
1912 1912
1913 target-module@78000 { 1913 target-module@78000 { /* 0x48078000, ap 41 1a.0 */
1914 compatible = "ti,sysc 1914 compatible = "ti,sysc-omap2", "ti,sysc";
1915 reg = <0x78000 0x4>, 1915 reg = <0x78000 0x4>,
1916 <0x78010 0x4>, 1916 <0x78010 0x4>,
1917 <0x78014 0x4>; 1917 <0x78014 0x4>;
1918 reg-names = "rev", "s 1918 reg-names = "rev", "sysc", "syss";
1919 ti,sysc-mask = <(SYSC 1919 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1920 SYSC 1920 SYSC_OMAP2_SOFTRESET |
1921 SYSC 1921 SYSC_OMAP2_AUTOIDLE)>;
1922 ti,sysc-sidle = <SYSC 1922 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1923 <SYSC 1923 <SYSC_IDLE_NO>,
1924 <SYSC 1924 <SYSC_IDLE_SMART>;
1925 ti,syss-mask = <1>; 1925 ti,syss-mask = <1>;
1926 /* Domains (V, P, C): 1926 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1927 clocks = <&l4_per_clk 1927 clocks = <&l4_per_clkctrl OMAP4_ELM_CLKCTRL 0>;
1928 clock-names = "fck"; 1928 clock-names = "fck";
1929 #address-cells = <1>; 1929 #address-cells = <1>;
1930 #size-cells = <1>; 1930 #size-cells = <1>;
1931 ranges = <0x0 0x78000 1931 ranges = <0x0 0x78000 0x1000>;
1932 1932
1933 elm: elm@0 { 1933 elm: elm@0 {
1934 compatible = 1934 compatible = "ti,am3352-elm";
1935 reg = <0x0 0x 1935 reg = <0x0 0x2000>;
1936 interrupts = 1936 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1937 status = "dis 1937 status = "disabled";
1938 }; 1938 };
1939 }; 1939 };
1940 1940
1941 target-module@86000 { 1941 target-module@86000 { /* 0x48086000, ap 43 24.0 */
1942 compatible = "ti,sysc 1942 compatible = "ti,sysc-omap2-timer", "ti,sysc";
1943 reg = <0x86000 0x4>, 1943 reg = <0x86000 0x4>,
1944 <0x86010 0x4>, 1944 <0x86010 0x4>,
1945 <0x86014 0x4>; 1945 <0x86014 0x4>;
1946 reg-names = "rev", "s 1946 reg-names = "rev", "sysc", "syss";
1947 ti,sysc-mask = <(SYSC 1947 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1948 SYSC 1948 SYSC_OMAP2_EMUFREE |
1949 SYSC 1949 SYSC_OMAP2_ENAWAKEUP |
1950 SYSC 1950 SYSC_OMAP2_SOFTRESET |
1951 SYSC 1951 SYSC_OMAP2_AUTOIDLE)>;
1952 ti,sysc-sidle = <SYSC 1952 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1953 <SYSC 1953 <SYSC_IDLE_NO>,
1954 <SYSC 1954 <SYSC_IDLE_SMART>;
1955 ti,syss-mask = <1>; 1955 ti,syss-mask = <1>;
1956 /* Domains (V, P, C): 1956 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1957 clocks = <&l4_per_clk 1957 clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 0>;
1958 clock-names = "fck"; 1958 clock-names = "fck";
1959 #address-cells = <1>; 1959 #address-cells = <1>;
1960 #size-cells = <1>; 1960 #size-cells = <1>;
1961 ranges = <0x0 0x86000 1961 ranges = <0x0 0x86000 0x1000>;
1962 1962
1963 timer10: timer@0 { 1963 timer10: timer@0 {
1964 compatible = 1964 compatible = "ti,omap3430-timer";
1965 reg = <0x0 0x 1965 reg = <0x0 0x80>;
1966 clocks = <&l4 1966 clocks = <&l4_per_clkctrl OMAP4_TIMER10_CLKCTRL 24>,
1967 <&sy 1967 <&sys_clkin_ck>;
1968 clock-names = 1968 clock-names = "fck", "timer_sys_ck";
1969 interrupts = 1969 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1970 ti,timer-pwm; 1970 ti,timer-pwm;
1971 }; 1971 };
1972 }; 1972 };
1973 1973
1974 target-module@88000 { 1974 target-module@88000 { /* 0x48088000, ap 45 2e.0 */
1975 compatible = "ti,sysc 1975 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1976 reg = <0x88000 0x4>, 1976 reg = <0x88000 0x4>,
1977 <0x88010 0x4>; 1977 <0x88010 0x4>;
1978 reg-names = "rev", "s 1978 reg-names = "rev", "sysc";
1979 ti,sysc-mask = <(SYSC 1979 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1980 SYSC 1980 SYSC_OMAP4_SOFTRESET)>;
1981 ti,sysc-sidle = <SYSC 1981 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1982 <SYSC 1982 <SYSC_IDLE_NO>,
1983 <SYSC 1983 <SYSC_IDLE_SMART>,
1984 <SYSC 1984 <SYSC_IDLE_SMART_WKUP>;
1985 /* Domains (V, P, C): 1985 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
1986 clocks = <&l4_per_clk 1986 clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 0>;
1987 clock-names = "fck"; 1987 clock-names = "fck";
1988 #address-cells = <1>; 1988 #address-cells = <1>;
1989 #size-cells = <1>; 1989 #size-cells = <1>;
1990 ranges = <0x0 0x88000 1990 ranges = <0x0 0x88000 0x1000>;
1991 1991
1992 timer11: timer@0 { 1992 timer11: timer@0 {
1993 compatible = 1993 compatible = "ti,omap4430-timer";
1994 reg = <0x0 0x 1994 reg = <0x0 0x80>;
1995 clocks = <&l4 1995 clocks = <&l4_per_clkctrl OMAP4_TIMER11_CLKCTRL 24>,
1996 <&sy 1996 <&sys_clkin_ck>;
1997 clock-names = 1997 clock-names = "fck", "timer_sys_ck";
1998 interrupts = 1998 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1999 ti,timer-pwm; 1999 ti,timer-pwm;
2000 }; 2000 };
2001 }; 2001 };
2002 2002
2003 rng_target: target-module@900 2003 rng_target: target-module@90000 { /* 0x48090000, ap 57 2a.0 */
2004 compatible = "ti,sysc 2004 compatible = "ti,sysc-omap2", "ti,sysc";
2005 reg = <0x91fe0 0x4>, 2005 reg = <0x91fe0 0x4>,
2006 <0x91fe4 0x4>; 2006 <0x91fe4 0x4>;
2007 reg-names = "rev", "s 2007 reg-names = "rev", "sysc";
2008 ti,sysc-mask = <(SYSC 2008 ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
2009 ti,sysc-sidle = <SYSC 2009 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2010 <SYSC 2010 <SYSC_IDLE_NO>;
2011 /* Domains (P, C): l4 2011 /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
2012 clocks = <&l4_secure_ 2012 clocks = <&l4_secure_clkctrl OMAP4_RNG_CLKCTRL 0>;
2013 clock-names = "fck"; 2013 clock-names = "fck";
2014 #address-cells = <1>; 2014 #address-cells = <1>;
2015 #size-cells = <1>; 2015 #size-cells = <1>;
2016 ranges = <0x0 0x90000 2016 ranges = <0x0 0x90000 0x2000>;
2017 2017
2018 rng: rng@0 { 2018 rng: rng@0 {
2019 compatible = 2019 compatible = "ti,omap4-rng";
2020 reg = <0x0 0x 2020 reg = <0x0 0x2000>;
2021 interrupts = 2021 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
2022 }; 2022 };
2023 }; 2023 };
2024 2024
2025 target-module@96000 { 2025 target-module@96000 { /* 0x48096000, ap 37 26.0 */
2026 compatible = "ti,sysc 2026 compatible = "ti,sysc-omap2", "ti,sysc";
2027 reg = <0x9608c 0x4>; 2027 reg = <0x9608c 0x4>;
2028 reg-names = "sysc"; 2028 reg-names = "sysc";
2029 ti,sysc-mask = <(SYSC 2029 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
2030 SYSC 2030 SYSC_OMAP2_ENAWAKEUP |
2031 SYSC 2031 SYSC_OMAP2_SOFTRESET)>;
2032 ti,sysc-sidle = <SYSC 2032 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2033 <SYSC 2033 <SYSC_IDLE_NO>,
2034 <SYSC 2034 <SYSC_IDLE_SMART>;
2035 /* Domains (V, P, C): 2035 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
2036 clocks = <&l4_per_clk 2036 clocks = <&l4_per_clkctrl OMAP4_MCBSP4_CLKCTRL 0>;
2037 clock-names = "fck"; 2037 clock-names = "fck";
2038 #address-cells = <1>; 2038 #address-cells = <1>;
2039 #size-cells = <1>; 2039 #size-cells = <1>;
2040 ranges = <0x0 0x96000 2040 ranges = <0x0 0x96000 0x1000>;
2041 2041
2042 mcbsp4: mcbsp@0 { 2042 mcbsp4: mcbsp@0 {
2043 compatible = 2043 compatible = "ti,omap4-mcbsp";
2044 reg = <0x0 0x 2044 reg = <0x0 0xff>; /* L4 Interconnect */
2045 reg-names = " 2045 reg-names = "mpu";
2046 clocks = <&l4 2046 clocks = <&l4_per_clkctrl OMAP4_MCBSP4_CLKCTRL 24>;
2047 clock-names = 2047 clock-names = "fck";
2048 interrupts = 2048 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
2049 interrupt-nam 2049 interrupt-names = "common";
2050 ti,buffer-siz 2050 ti,buffer-size = <128>;
2051 dmas = <&sdma 2051 dmas = <&sdma 31>,
2052 <&sdma 2052 <&sdma 32>;
2053 dma-names = " 2053 dma-names = "tx", "rx";
2054 status = "dis 2054 status = "disabled";
2055 }; 2055 };
2056 }; 2056 };
2057 2057
2058 target-module@98000 { 2058 target-module@98000 { /* 0x48098000, ap 49 22.0 */
2059 compatible = "ti,sysc 2059 compatible = "ti,sysc-omap4", "ti,sysc";
2060 reg = <0x98000 0x4>, 2060 reg = <0x98000 0x4>,
2061 <0x98010 0x4>; 2061 <0x98010 0x4>;
2062 reg-names = "rev", "s 2062 reg-names = "rev", "sysc";
2063 ti,sysc-mask = <(SYSC 2063 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2064 SYSC 2064 SYSC_OMAP4_SOFTRESET)>;
2065 ti,sysc-sidle = <SYSC 2065 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2066 <SYSC 2066 <SYSC_IDLE_NO>,
2067 <SYSC 2067 <SYSC_IDLE_SMART>,
2068 <SYSC 2068 <SYSC_IDLE_SMART_WKUP>;
2069 /* Domains (V, P, C): 2069 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
2070 clocks = <&l4_per_clk 2070 clocks = <&l4_per_clkctrl OMAP4_MCSPI1_CLKCTRL 0>;
2071 clock-names = "fck"; 2071 clock-names = "fck";
2072 #address-cells = <1>; 2072 #address-cells = <1>;
2073 #size-cells = <1>; 2073 #size-cells = <1>;
2074 ranges = <0x0 0x98000 2074 ranges = <0x0 0x98000 0x1000>;
2075 2075
2076 mcspi1: spi@0 { 2076 mcspi1: spi@0 {
2077 compatible = 2077 compatible = "ti,omap4-mcspi";
2078 reg = <0x0 0x 2078 reg = <0x0 0x200>;
2079 interrupts = 2079 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
2080 #address-cell 2080 #address-cells = <1>;
2081 #size-cells = 2081 #size-cells = <0>;
2082 ti,spi-num-cs 2082 ti,spi-num-cs = <4>;
2083 dmas = <&sdma 2083 dmas = <&sdma 35>,
2084 <&sdma 2084 <&sdma 36>,
2085 <&sdma 2085 <&sdma 37>,
2086 <&sdma 2086 <&sdma 38>,
2087 <&sdma 2087 <&sdma 39>,
2088 <&sdma 2088 <&sdma 40>,
2089 <&sdma 2089 <&sdma 41>,
2090 <&sdma 2090 <&sdma 42>;
2091 dma-names = " 2091 dma-names = "tx0", "rx0", "tx1", "rx1",
2092 " 2092 "tx2", "rx2", "tx3", "rx3";
2093 }; 2093 };
2094 }; 2094 };
2095 2095
2096 target-module@9a000 { 2096 target-module@9a000 { /* 0x4809a000, ap 51 2c.0 */
2097 compatible = "ti,sysc 2097 compatible = "ti,sysc-omap4", "ti,sysc";
2098 reg = <0x9a000 0x4>, 2098 reg = <0x9a000 0x4>,
2099 <0x9a010 0x4>; 2099 <0x9a010 0x4>;
2100 reg-names = "rev", "s 2100 reg-names = "rev", "sysc";
2101 ti,sysc-mask = <(SYSC 2101 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2102 SYSC 2102 SYSC_OMAP4_SOFTRESET)>;
2103 ti,sysc-sidle = <SYSC 2103 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2104 <SYSC 2104 <SYSC_IDLE_NO>,
2105 <SYSC 2105 <SYSC_IDLE_SMART>,
2106 <SYSC 2106 <SYSC_IDLE_SMART_WKUP>;
2107 /* Domains (V, P, C): 2107 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
2108 clocks = <&l4_per_clk 2108 clocks = <&l4_per_clkctrl OMAP4_MCSPI2_CLKCTRL 0>;
2109 clock-names = "fck"; 2109 clock-names = "fck";
2110 #address-cells = <1>; 2110 #address-cells = <1>;
2111 #size-cells = <1>; 2111 #size-cells = <1>;
2112 ranges = <0x0 0x9a000 2112 ranges = <0x0 0x9a000 0x1000>;
2113 2113
2114 mcspi2: spi@0 { 2114 mcspi2: spi@0 {
2115 compatible = 2115 compatible = "ti,omap4-mcspi";
2116 reg = <0x0 0x 2116 reg = <0x0 0x200>;
2117 interrupts = 2117 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
2118 #address-cell 2118 #address-cells = <1>;
2119 #size-cells = 2119 #size-cells = <0>;
2120 ti,spi-num-cs 2120 ti,spi-num-cs = <2>;
2121 dmas = <&sdma 2121 dmas = <&sdma 43>,
2122 <&sdma 2122 <&sdma 44>,
2123 <&sdma 2123 <&sdma 45>,
2124 <&sdma 2124 <&sdma 46>;
2125 dma-names = " 2125 dma-names = "tx0", "rx0", "tx1", "rx1";
2126 }; 2126 };
2127 }; 2127 };
2128 2128
2129 target-module@9c000 { 2129 target-module@9c000 { /* 0x4809c000, ap 53 36.0 */
2130 compatible = "ti,sysc 2130 compatible = "ti,sysc-omap4", "ti,sysc";
2131 reg = <0x9c000 0x4>, 2131 reg = <0x9c000 0x4>,
2132 <0x9c010 0x4>; 2132 <0x9c010 0x4>;
2133 reg-names = "rev", "s 2133 reg-names = "rev", "sysc";
2134 ti,sysc-mask = <(SYSC 2134 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2135 SYSC 2135 SYSC_OMAP4_SOFTRESET)>;
2136 ti,sysc-midle = <SYSC 2136 ti,sysc-midle = <SYSC_IDLE_FORCE>,
2137 <SYSC 2137 <SYSC_IDLE_NO>,
2138 <SYSC 2138 <SYSC_IDLE_SMART>,
2139 <SYSC 2139 <SYSC_IDLE_SMART_WKUP>;
2140 ti,sysc-sidle = <SYSC 2140 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2141 <SYSC 2141 <SYSC_IDLE_NO>,
2142 <SYSC 2142 <SYSC_IDLE_SMART>,
2143 <SYSC 2143 <SYSC_IDLE_SMART_WKUP>;
2144 /* Domains (V, P, C): 2144 /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
2145 clocks = <&l3_init_cl 2145 clocks = <&l3_init_clkctrl OMAP4_MMC1_CLKCTRL 0>;
2146 clock-names = "fck"; 2146 clock-names = "fck";
2147 #address-cells = <1>; 2147 #address-cells = <1>;
2148 #size-cells = <1>; 2148 #size-cells = <1>;
2149 ranges = <0x0 0x9c000 2149 ranges = <0x0 0x9c000 0x1000>;
2150 2150
2151 mmc1: mmc@0 { 2151 mmc1: mmc@0 {
2152 compatible = 2152 compatible = "ti,omap4-hsmmc";
2153 reg = <0x0 0x 2153 reg = <0x0 0x400>;
2154 interrupts = 2154 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2155 ti,dual-volt; 2155 ti,dual-volt;
2156 ti,needs-spec 2156 ti,needs-special-reset;
2157 dmas = <&sdma 2157 dmas = <&sdma 61>, <&sdma 62>;
2158 dma-names = " 2158 dma-names = "tx", "rx";
2159 pbias-supply 2159 pbias-supply = <&pbias_mmc_reg>;
2160 }; 2160 };
2161 }; 2161 };
2162 2162
2163 target-module@9e000 { 2163 target-module@9e000 { /* 0x4809e000, ap 55 48.0 */
2164 compatible = "ti,sysc 2164 compatible = "ti,sysc";
2165 status = "disabled"; 2165 status = "disabled";
2166 #address-cells = <1>; 2166 #address-cells = <1>;
2167 #size-cells = <1>; 2167 #size-cells = <1>;
2168 ranges = <0x0 0x9e000 2168 ranges = <0x0 0x9e000 0x1000>;
2169 }; 2169 };
2170 2170
2171 target-module@a2000 { 2171 target-module@a2000 { /* 0x480a2000, ap 79 3a.0 */
2172 compatible = "ti,sysc 2172 compatible = "ti,sysc";
2173 status = "disabled"; 2173 status = "disabled";
2174 #address-cells = <1>; 2174 #address-cells = <1>;
2175 #size-cells = <1>; 2175 #size-cells = <1>;
2176 ranges = <0x0 0xa2000 2176 ranges = <0x0 0xa2000 0x1000>;
2177 }; 2177 };
2178 2178
2179 target-module@a4000 { 2179 target-module@a4000 { /* 0x480a4000, ap 59 34.0 */
2180 compatible = "ti,sysc 2180 compatible = "ti,sysc";
2181 status = "disabled"; 2181 status = "disabled";
2182 #address-cells = <1>; 2182 #address-cells = <1>;
2183 #size-cells = <1>; 2183 #size-cells = <1>;
2184 ranges = <0x00000000 2184 ranges = <0x00000000 0x000a4000 0x00001000>,
2185 <0x00001000 2185 <0x00001000 0x000a5000 0x00001000>;
2186 }; 2186 };
2187 2187
2188 des_target: target-module@a50 2188 des_target: target-module@a5000 { /* 0x480a5000 */
2189 compatible = "ti,sysc 2189 compatible = "ti,sysc-omap2", "ti,sysc";
2190 reg = <0xa5030 0x4>, 2190 reg = <0xa5030 0x4>,
2191 <0xa5034 0x4>, 2191 <0xa5034 0x4>,
2192 <0xa5038 0x4>; 2192 <0xa5038 0x4>;
2193 reg-names = "rev", "s 2193 reg-names = "rev", "sysc", "syss";
2194 ti,sysc-mask = <(SYSC 2194 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
2195 SYSC 2195 SYSC_OMAP2_AUTOIDLE)>;
2196 ti,sysc-sidle = <SYSC 2196 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2197 <SYSC 2197 <SYSC_IDLE_NO>,
2198 <SYSC 2198 <SYSC_IDLE_SMART>,
2199 <SYSC 2199 <SYSC_IDLE_SMART_WKUP>;
2200 ti,syss-mask = <1>; 2200 ti,syss-mask = <1>;
2201 /* Domains (P, C): l4 2201 /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
2202 clocks = <&l4_secure_ 2202 clocks = <&l4_secure_clkctrl OMAP4_DES3DES_CLKCTRL 0>;
2203 clock-names = "fck"; 2203 clock-names = "fck";
2204 #address-cells = <1>; 2204 #address-cells = <1>;
2205 #size-cells = <1>; 2205 #size-cells = <1>;
2206 ranges = <0 0xa5000 0 2206 ranges = <0 0xa5000 0x00001000>;
2207 2207
2208 des: des@0 { 2208 des: des@0 {
2209 compatible = 2209 compatible = "ti,omap4-des";
2210 reg = <0 0xa0 2210 reg = <0 0xa0>;
2211 interrupts = 2211 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
2212 dmas = <&sdma 2212 dmas = <&sdma 117>, <&sdma 116>;
2213 dma-names = " 2213 dma-names = "tx", "rx";
2214 }; 2214 };
2215 }; 2215 };
2216 2216
2217 target-module@a8000 { 2217 target-module@a8000 { /* 0x480a8000, ap 61 3e.0 */
2218 compatible = "ti,sysc 2218 compatible = "ti,sysc";
2219 status = "disabled"; 2219 status = "disabled";
2220 #address-cells = <1>; 2220 #address-cells = <1>;
2221 #size-cells = <1>; 2221 #size-cells = <1>;
2222 ranges = <0x0 0xa8000 2222 ranges = <0x0 0xa8000 0x4000>;
2223 }; 2223 };
2224 2224
2225 target-module@ad000 { 2225 target-module@ad000 { /* 0x480ad000, ap 63 50.0 */
2226 compatible = "ti,sysc 2226 compatible = "ti,sysc-omap4", "ti,sysc";
2227 reg = <0xad000 0x4>, 2227 reg = <0xad000 0x4>,
2228 <0xad010 0x4>; 2228 <0xad010 0x4>;
2229 reg-names = "rev", "s 2229 reg-names = "rev", "sysc";
2230 ti,sysc-mask = <(SYSC 2230 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2231 SYSC 2231 SYSC_OMAP4_SOFTRESET)>;
2232 ti,sysc-midle = <SYSC 2232 ti,sysc-midle = <SYSC_IDLE_FORCE>,
2233 <SYSC 2233 <SYSC_IDLE_NO>,
2234 <SYSC 2234 <SYSC_IDLE_SMART>,
2235 <SYSC 2235 <SYSC_IDLE_SMART_WKUP>;
2236 ti,sysc-sidle = <SYSC 2236 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2237 <SYSC 2237 <SYSC_IDLE_NO>,
2238 <SYSC 2238 <SYSC_IDLE_SMART>,
2239 <SYSC 2239 <SYSC_IDLE_SMART_WKUP>;
2240 /* Domains (V, P, C): 2240 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
2241 clocks = <&l4_per_clk 2241 clocks = <&l4_per_clkctrl OMAP4_MMC3_CLKCTRL 0>;
2242 clock-names = "fck"; 2242 clock-names = "fck";
2243 #address-cells = <1>; 2243 #address-cells = <1>;
2244 #size-cells = <1>; 2244 #size-cells = <1>;
2245 ranges = <0x0 0xad000 2245 ranges = <0x0 0xad000 0x1000>;
2246 2246
2247 mmc3: mmc@0 { 2247 mmc3: mmc@0 {
2248 compatible = 2248 compatible = "ti,omap4-hsmmc";
2249 reg = <0x0 0x 2249 reg = <0x0 0x400>;
2250 interrupts = 2250 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
2251 ti,needs-spec 2251 ti,needs-special-reset;
2252 dmas = <&sdma 2252 dmas = <&sdma 77>, <&sdma 78>;
2253 dma-names = " 2253 dma-names = "tx", "rx";
2254 }; 2254 };
2255 }; 2255 };
2256 2256
2257 target-module@b0000 { 2257 target-module@b0000 { /* 0x480b0000, ap 47 40.0 */
2258 compatible = "ti,sysc 2258 compatible = "ti,sysc";
2259 status = "disabled"; 2259 status = "disabled";
2260 #address-cells = <1>; 2260 #address-cells = <1>;
2261 #size-cells = <1>; 2261 #size-cells = <1>;
2262 ranges = <0x0 0xb0000 2262 ranges = <0x0 0xb0000 0x1000>;
2263 }; 2263 };
2264 2264
2265 target-module@b2000 { 2265 target-module@b2000 { /* 0x480b2000, ap 65 3c.0 */
2266 compatible = "ti,sysc 2266 compatible = "ti,sysc-omap2", "ti,sysc";
2267 reg = <0xb2000 0x4>, 2267 reg = <0xb2000 0x4>,
2268 <0xb2014 0x4>, 2268 <0xb2014 0x4>,
2269 <0xb2018 0x4>; 2269 <0xb2018 0x4>;
2270 reg-names = "rev", "s 2270 reg-names = "rev", "sysc", "syss";
2271 ti,sysc-mask = <(SYSC 2271 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
2272 SYSC 2272 SYSC_OMAP2_AUTOIDLE)>;
2273 ti,syss-mask = <1>; 2273 ti,syss-mask = <1>;
2274 ti,no-reset-on-init; 2274 ti,no-reset-on-init;
2275 /* Domains (V, P, C): 2275 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
2276 clocks = <&l4_per_clk 2276 clocks = <&l4_per_clkctrl OMAP4_HDQ1W_CLKCTRL 0>;
2277 clock-names = "fck"; 2277 clock-names = "fck";
2278 #address-cells = <1>; 2278 #address-cells = <1>;
2279 #size-cells = <1>; 2279 #size-cells = <1>;
2280 ranges = <0x0 0xb2000 2280 ranges = <0x0 0xb2000 0x1000>;
2281 2281
2282 hdqw1w: 1w@0 { 2282 hdqw1w: 1w@0 {
2283 compatible = 2283 compatible = "ti,omap3-1w";
2284 reg = <0x0 0x 2284 reg = <0x0 0x1000>;
2285 interrupts = 2285 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
2286 }; 2286 };
2287 }; 2287 };
2288 2288
2289 target-module@b4000 { 2289 target-module@b4000 { /* 0x480b4000, ap 67 46.0 */
2290 compatible = "ti,sysc 2290 compatible = "ti,sysc-omap4", "ti,sysc";
2291 reg = <0xb4000 0x4>, 2291 reg = <0xb4000 0x4>,
2292 <0xb4010 0x4>; 2292 <0xb4010 0x4>;
2293 reg-names = "rev", "s 2293 reg-names = "rev", "sysc";
2294 ti,sysc-mask = <(SYSC 2294 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2295 SYSC 2295 SYSC_OMAP4_SOFTRESET)>;
2296 ti,sysc-midle = <SYSC 2296 ti,sysc-midle = <SYSC_IDLE_FORCE>,
2297 <SYSC 2297 <SYSC_IDLE_NO>,
2298 <SYSC 2298 <SYSC_IDLE_SMART>,
2299 <SYSC 2299 <SYSC_IDLE_SMART_WKUP>;
2300 ti,sysc-sidle = <SYSC 2300 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2301 <SYSC 2301 <SYSC_IDLE_NO>,
2302 <SYSC 2302 <SYSC_IDLE_SMART>,
2303 <SYSC 2303 <SYSC_IDLE_SMART_WKUP>;
2304 /* Domains (V, P, C): 2304 /* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
2305 clocks = <&l3_init_cl 2305 clocks = <&l3_init_clkctrl OMAP4_MMC2_CLKCTRL 0>;
2306 clock-names = "fck"; 2306 clock-names = "fck";
2307 #address-cells = <1>; 2307 #address-cells = <1>;
2308 #size-cells = <1>; 2308 #size-cells = <1>;
2309 ranges = <0x0 0xb4000 2309 ranges = <0x0 0xb4000 0x1000>;
2310 2310
2311 mmc2: mmc@0 { 2311 mmc2: mmc@0 {
2312 compatible = 2312 compatible = "ti,omap4-hsmmc";
2313 reg = <0x0 0x 2313 reg = <0x0 0x400>;
2314 interrupts = 2314 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
2315 ti,needs-spec 2315 ti,needs-special-reset;
2316 dmas = <&sdma 2316 dmas = <&sdma 47>, <&sdma 48>;
2317 dma-names = " 2317 dma-names = "tx", "rx";
2318 }; 2318 };
2319 }; 2319 };
2320 2320
2321 target-module@b8000 { 2321 target-module@b8000 { /* 0x480b8000, ap 69 58.0 */
2322 compatible = "ti,sysc 2322 compatible = "ti,sysc-omap4", "ti,sysc";
2323 reg = <0xb8000 0x4>, 2323 reg = <0xb8000 0x4>,
2324 <0xb8010 0x4>; 2324 <0xb8010 0x4>;
2325 reg-names = "rev", "s 2325 reg-names = "rev", "sysc";
2326 ti,sysc-mask = <(SYSC 2326 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2327 SYSC 2327 SYSC_OMAP4_SOFTRESET)>;
2328 ti,sysc-sidle = <SYSC 2328 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2329 <SYSC 2329 <SYSC_IDLE_NO>,
2330 <SYSC 2330 <SYSC_IDLE_SMART>,
2331 <SYSC 2331 <SYSC_IDLE_SMART_WKUP>;
2332 /* Domains (V, P, C): 2332 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
2333 clocks = <&l4_per_clk 2333 clocks = <&l4_per_clkctrl OMAP4_MCSPI3_CLKCTRL 0>;
2334 clock-names = "fck"; 2334 clock-names = "fck";
2335 #address-cells = <1>; 2335 #address-cells = <1>;
2336 #size-cells = <1>; 2336 #size-cells = <1>;
2337 ranges = <0x0 0xb8000 2337 ranges = <0x0 0xb8000 0x1000>;
2338 2338
2339 mcspi3: spi@0 { 2339 mcspi3: spi@0 {
2340 compatible = 2340 compatible = "ti,omap4-mcspi";
2341 reg = <0x0 0x 2341 reg = <0x0 0x200>;
2342 interrupts = 2342 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
2343 #address-cell 2343 #address-cells = <1>;
2344 #size-cells = 2344 #size-cells = <0>;
2345 ti,spi-num-cs 2345 ti,spi-num-cs = <2>;
2346 dmas = <&sdma 2346 dmas = <&sdma 15>, <&sdma 16>;
2347 dma-names = " 2347 dma-names = "tx0", "rx0";
2348 }; 2348 };
2349 }; 2349 };
2350 2350
2351 target-module@ba000 { 2351 target-module@ba000 { /* 0x480ba000, ap 71 32.0 */
2352 compatible = "ti,sysc 2352 compatible = "ti,sysc-omap4", "ti,sysc";
2353 reg = <0xba000 0x4>, 2353 reg = <0xba000 0x4>,
2354 <0xba010 0x4>; 2354 <0xba010 0x4>;
2355 reg-names = "rev", "s 2355 reg-names = "rev", "sysc";
2356 ti,sysc-mask = <(SYSC 2356 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2357 SYSC 2357 SYSC_OMAP4_SOFTRESET)>;
2358 ti,sysc-sidle = <SYSC 2358 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2359 <SYSC 2359 <SYSC_IDLE_NO>,
2360 <SYSC 2360 <SYSC_IDLE_SMART>,
2361 <SYSC 2361 <SYSC_IDLE_SMART_WKUP>;
2362 /* Domains (V, P, C): 2362 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
2363 clocks = <&l4_per_clk 2363 clocks = <&l4_per_clkctrl OMAP4_MCSPI4_CLKCTRL 0>;
2364 clock-names = "fck"; 2364 clock-names = "fck";
2365 #address-cells = <1>; 2365 #address-cells = <1>;
2366 #size-cells = <1>; 2366 #size-cells = <1>;
2367 ranges = <0x0 0xba000 2367 ranges = <0x0 0xba000 0x1000>;
2368 2368
2369 mcspi4: spi@0 { 2369 mcspi4: spi@0 {
2370 compatible = 2370 compatible = "ti,omap4-mcspi";
2371 reg = <0x0 0x 2371 reg = <0x0 0x200>;
2372 interrupts = 2372 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
2373 #address-cell 2373 #address-cells = <1>;
2374 #size-cells = 2374 #size-cells = <0>;
2375 ti,spi-num-cs 2375 ti,spi-num-cs = <1>;
2376 dmas = <&sdma 2376 dmas = <&sdma 70>, <&sdma 71>;
2377 dma-names = " 2377 dma-names = "tx0", "rx0";
2378 }; 2378 };
2379 }; 2379 };
2380 2380
2381 target-module@d1000 { 2381 target-module@d1000 { /* 0x480d1000, ap 73 44.0 */
2382 compatible = "ti,sysc 2382 compatible = "ti,sysc-omap4", "ti,sysc";
2383 reg = <0xd1000 0x4>, 2383 reg = <0xd1000 0x4>,
2384 <0xd1010 0x4>; 2384 <0xd1010 0x4>;
2385 reg-names = "rev", "s 2385 reg-names = "rev", "sysc";
2386 ti,sysc-mask = <(SYSC 2386 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2387 SYSC 2387 SYSC_OMAP4_SOFTRESET)>;
2388 ti,sysc-midle = <SYSC 2388 ti,sysc-midle = <SYSC_IDLE_FORCE>,
2389 <SYSC 2389 <SYSC_IDLE_NO>,
2390 <SYSC 2390 <SYSC_IDLE_SMART>,
2391 <SYSC 2391 <SYSC_IDLE_SMART_WKUP>;
2392 ti,sysc-sidle = <SYSC 2392 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2393 <SYSC 2393 <SYSC_IDLE_NO>,
2394 <SYSC 2394 <SYSC_IDLE_SMART>,
2395 <SYSC 2395 <SYSC_IDLE_SMART_WKUP>;
2396 /* Domains (V, P, C): 2396 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
2397 clocks = <&l4_per_clk 2397 clocks = <&l4_per_clkctrl OMAP4_MMC4_CLKCTRL 0>;
2398 clock-names = "fck"; 2398 clock-names = "fck";
2399 #address-cells = <1>; 2399 #address-cells = <1>;
2400 #size-cells = <1>; 2400 #size-cells = <1>;
2401 ranges = <0x0 0xd1000 2401 ranges = <0x0 0xd1000 0x1000>;
2402 2402
2403 mmc4: mmc@0 { 2403 mmc4: mmc@0 {
2404 compatible = 2404 compatible = "ti,omap4-hsmmc";
2405 reg = <0x0 0x 2405 reg = <0x0 0x400>;
2406 interrupts = 2406 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2407 ti,needs-spec 2407 ti,needs-special-reset;
2408 dmas = <&sdma 2408 dmas = <&sdma 57>, <&sdma 58>;
2409 dma-names = " 2409 dma-names = "tx", "rx";
2410 }; 2410 };
2411 }; 2411 };
2412 2412
2413 target-module@d5000 { 2413 target-module@d5000 { /* 0x480d5000, ap 75 4e.0 */
2414 compatible = "ti,sysc 2414 compatible = "ti,sysc-omap4", "ti,sysc";
2415 reg = <0xd5000 0x4>, 2415 reg = <0xd5000 0x4>,
2416 <0xd5010 0x4>; 2416 <0xd5010 0x4>;
2417 reg-names = "rev", "s 2417 reg-names = "rev", "sysc";
2418 ti,sysc-mask = <(SYSC 2418 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2419 SYSC 2419 SYSC_OMAP4_SOFTRESET)>;
2420 ti,sysc-midle = <SYSC 2420 ti,sysc-midle = <SYSC_IDLE_FORCE>,
2421 <SYSC 2421 <SYSC_IDLE_NO>,
2422 <SYSC 2422 <SYSC_IDLE_SMART>,
2423 <SYSC 2423 <SYSC_IDLE_SMART_WKUP>;
2424 ti,sysc-sidle = <SYSC 2424 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2425 <SYSC 2425 <SYSC_IDLE_NO>,
2426 <SYSC 2426 <SYSC_IDLE_SMART>,
2427 <SYSC 2427 <SYSC_IDLE_SMART_WKUP>;
2428 /* Domains (V, P, C): 2428 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
2429 clocks = <&l4_per_clk 2429 clocks = <&l4_per_clkctrl OMAP4_MMC5_CLKCTRL 0>;
2430 clock-names = "fck"; 2430 clock-names = "fck";
2431 #address-cells = <1>; 2431 #address-cells = <1>;
2432 #size-cells = <1>; 2432 #size-cells = <1>;
2433 ranges = <0x0 0xd5000 2433 ranges = <0x0 0xd5000 0x1000>;
2434 2434
2435 mmc5: mmc@0 { 2435 mmc5: mmc@0 {
2436 compatible = 2436 compatible = "ti,omap4-hsmmc";
2437 reg = <0x0 0x 2437 reg = <0x0 0x400>;
2438 interrupts = 2438 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
2439 ti,needs-spec 2439 ti,needs-special-reset;
2440 dmas = <&sdma 2440 dmas = <&sdma 59>, <&sdma 60>;
2441 dma-names = " 2441 dma-names = "tx", "rx";
2442 }; 2442 };
2443 }; 2443 };
2444 }; 2444 };
2445 2445
2446 segment@200000 { 2446 segment@200000 { /* 0x48200000 */
2447 compatible = "simple-pm-bus"; 2447 compatible = "simple-pm-bus";
2448 #address-cells = <1>; 2448 #address-cells = <1>;
2449 #size-cells = <1>; 2449 #size-cells = <1>;
2450 ranges = <0x00150000 0x003500 2450 ranges = <0x00150000 0x00350000 0x001000>, /* ap 77 */
2451 <0x00151000 0x003510 2451 <0x00151000 0x00351000 0x001000>; /* ap 78 */
2452 2452
2453 target-module@150000 { 2453 target-module@150000 { /* 0x48350000, ap 77 4c.0 */
2454 compatible = "ti,sysc 2454 compatible = "ti,sysc-omap2", "ti,sysc";
2455 reg = <0x150000 0x8>, 2455 reg = <0x150000 0x8>,
2456 <0x150010 0x8>, 2456 <0x150010 0x8>,
2457 <0x150090 0x8>; 2457 <0x150090 0x8>;
2458 reg-names = "rev", "s 2458 reg-names = "rev", "sysc", "syss";
2459 ti,sysc-mask = <(SYSC 2459 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
2460 SYSC 2460 SYSC_OMAP2_ENAWAKEUP |
2461 SYSC 2461 SYSC_OMAP2_SOFTRESET |
2462 SYSC 2462 SYSC_OMAP2_AUTOIDLE)>;
2463 ti,sysc-sidle = <SYSC 2463 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2464 <SYSC 2464 <SYSC_IDLE_NO>,
2465 <SYSC 2465 <SYSC_IDLE_SMART>,
2466 <SYSC 2466 <SYSC_IDLE_SMART_WKUP>;
2467 ti,syss-mask = <1>; 2467 ti,syss-mask = <1>;
2468 /* Domains (V, P, C): 2468 /* Domains (V, P, C): core, l4per_pwrdm, l4_per_clkdm */
2469 clocks = <&l4_per_clk 2469 clocks = <&l4_per_clkctrl OMAP4_I2C4_CLKCTRL 0>;
2470 clock-names = "fck"; 2470 clock-names = "fck";
2471 #address-cells = <1>; 2471 #address-cells = <1>;
2472 #size-cells = <1>; 2472 #size-cells = <1>;
2473 ranges = <0x0 0x15000 2473 ranges = <0x0 0x150000 0x1000>;
2474 2474
2475 i2c4: i2c@0 { 2475 i2c4: i2c@0 {
2476 compatible = 2476 compatible = "ti,omap4-i2c";
2477 reg = <0x0 0x 2477 reg = <0x0 0x100>;
2478 interrupts = 2478 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
2479 #address-cell 2479 #address-cells = <1>;
2480 #size-cells = 2480 #size-cells = <0>;
2481 }; 2481 };
2482 }; 2482 };
2483 }; 2483 };
2484 }; 2484 };
2485 2485
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