1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * wm8505.dtsi - Device tree file for Wonderme
4 *
5 * Copyright (C) 2012 Tony Prisk <linux@priskte
6 */
7
8 / {
9 #address-cells = <1>;
10 #size-cells = <1>;
11 compatible = "wm,wm8505";
12
13 cpus {
14 #address-cells = <0>;
15 #size-cells = <0>;
16
17 cpu {
18 device_type = "cpu";
19 compatible = "arm,arm9
20 };
21 };
22
23 memory {
24 device_type = "memory";
25 reg = <0x0 0x0>;
26 };
27
28 aliases {
29 serial0 = &uart0;
30 serial1 = &uart1;
31 serial2 = &uart2;
32 serial3 = &uart3;
33 serial4 = &uart4;
34 serial5 = &uart5;
35 };
36
37 soc {
38 #address-cells = <1>;
39 #size-cells = <1>;
40 compatible = "simple-bus";
41 ranges;
42 interrupt-parent = <&intc0>;
43
44 intc0: interrupt-controller@d8
45 compatible = "via,vt85
46 interrupt-controller;
47 reg = <0xd8140000 0x10
48 #interrupt-cells = <1>
49 };
50
51 /* Secondary IC cascaded to in
52 intc1: interrupt-controller@d8
53 compatible = "via,vt85
54 interrupt-controller;
55 #interrupt-cells = <1>
56 reg = <0xD8150000 0x10
57 interrupts = <56 57 58
58 };
59
60 pinctrl: pinctrl@d8110000 {
61 compatible = "wm,wm850
62 reg = <0xd8110000 0x10
63 interrupt-controller;
64 #interrupt-cells = <2>
65 gpio-controller;
66 #gpio-cells = <2>;
67 };
68
69 pmc@d8130000 {
70 compatible = "via,vt85
71 reg = <0xd8130000 0x10
72 clocks {
73 #address-cells
74 #size-cells =
75
76 ref24: ref24M
77 #clock
78 compat
79 clock-
80 };
81
82 ref25: ref25M
83 #clock
84 compat
85 clock-
86 };
87
88 plla: plla {
89 #clock
90 compat
91 clocks
92 reg =
93 };
94
95 pllb: pllb {
96 #clock
97 compat
98 clocks
99 reg =
100 };
101
102 pllc: pllc {
103 #clock
104 compat
105 clocks
106 reg =
107 };
108
109 plld: plld {
110 #clock
111 compat
112 clocks
113 reg =
114 };
115
116 clkarm: arm {
117 #clock
118 compat
119 clocks
120 diviso
121 };
122
123 clkahb: ahb {
124 #clock
125 compat
126 clocks
127 diviso
128 };
129
130 clkapb: apb {
131 #clock
132 compat
133 clocks
134 diviso
135 };
136
137 clkddr: ddr {
138 #clock
139 compat
140 clocks
141 diviso
142 };
143
144 clkuart0: uart
145 #clock
146 compat
147 clocks
148 enable
149 enable
150 };
151
152 clkuart1: uart
153 #clock
154 compat
155 clocks
156 enable
157 enable
158 };
159
160 clkuart2: uart
161 #clock
162 compat
163 clocks
164 enable
165 enable
166 };
167
168 clkuart3: uart
169 #clock
170 compat
171 clocks
172 enable
173 enable
174 };
175
176 clkuart4: uart
177 #clock
178 compat
179 clocks
180 enable
181 enable
182 };
183
184 clkuart5: uart
185 #clock
186 compat
187 clocks
188 enable
189 enable
190 };
191
192 clksdhc: sdhc
193 #clock
194 compat
195 clocks
196 diviso
197 diviso
198 enable
199 enable
200 };
201 };
202 };
203
204 timer@d8130100 {
205 compatible = "via,vt85
206 reg = <0xd8130100 0x28
207 interrupts = <36>;
208 };
209
210 ehci@d8007100 {
211 compatible = "via,vt85
212 reg = <0xd8007100 0x20
213 interrupts = <1>;
214 };
215
216 usb@d8007300 {
217 compatible = "platform
218 reg = <0xd8007300 0x20
219 interrupts = <0>;
220 };
221
222 fb: fb@d8050800 {
223 compatible = "wm,wm850
224 reg = <0xd8050800 0x20
225 };
226
227 ge_rops@d8050400 {
228 compatible = "wm,prizm
229 reg = <0xd8050400 0x10
230 };
231
232 uart0: serial@d8200000 {
233 compatible = "via,vt85
234 reg = <0xd8200000 0x10
235 interrupts = <32>;
236 clocks = <&clkuart0>;
237 status = "disabled";
238 };
239
240 uart1: serial@d82b0000 {
241 compatible = "via,vt85
242 reg = <0xd82b0000 0x10
243 interrupts = <33>;
244 clocks = <&clkuart1>;
245 status = "disabled";
246 };
247
248 uart2: serial@d8210000 {
249 compatible = "via,vt85
250 reg = <0xd8210000 0x10
251 interrupts = <47>;
252 clocks = <&clkuart2>;
253 status = "disabled";
254 };
255
256 uart3: serial@d82c0000 {
257 compatible = "via,vt85
258 reg = <0xd82c0000 0x10
259 interrupts = <50>;
260 clocks = <&clkuart3>;
261 status = "disabled";
262 };
263
264 uart4: serial@d8370000 {
265 compatible = "via,vt85
266 reg = <0xd8370000 0x10
267 interrupts = <31>;
268 clocks = <&clkuart4>;
269 status = "disabled";
270 };
271
272 uart5: serial@d8380000 {
273 compatible = "via,vt85
274 reg = <0xd8380000 0x10
275 interrupts = <30>;
276 clocks = <&clkuart5>;
277 status = "disabled";
278 };
279
280 rtc@d8100000 {
281 compatible = "via,vt85
282 reg = <0xd8100000 0x10
283 interrupts = <48>;
284 };
285
286 sdhc@d800a000 {
287 compatible = "wm,wm850
288 reg = <0xd800a000 0x40
289 interrupts = <20>, <21
290 clocks = <&clksdhc>;
291 bus-width = <4>;
292 };
293 };
294 };
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