1 // SPDX-License-Identifier: GPL-2.0-or-later 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* 2 /*
3 * wm8505.dtsi - Device tree file for Wonderme 3 * wm8505.dtsi - Device tree file for Wondermedia WM8505 SoC
4 * 4 *
5 * Copyright (C) 2012 Tony Prisk <linux@priskte 5 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
6 */ 6 */
7 7
8 / { 8 / {
9 #address-cells = <1>; 9 #address-cells = <1>;
10 #size-cells = <1>; 10 #size-cells = <1>;
11 compatible = "wm,wm8505"; 11 compatible = "wm,wm8505";
12 12
13 cpus { 13 cpus {
14 #address-cells = <0>; 14 #address-cells = <0>;
15 #size-cells = <0>; 15 #size-cells = <0>;
16 16
17 cpu { 17 cpu {
18 device_type = "cpu"; 18 device_type = "cpu";
19 compatible = "arm,arm9 19 compatible = "arm,arm926ej-s";
20 }; 20 };
21 }; 21 };
22 22
23 memory { 23 memory {
24 device_type = "memory"; 24 device_type = "memory";
25 reg = <0x0 0x0>; 25 reg = <0x0 0x0>;
26 }; 26 };
27 27
28 aliases { 28 aliases {
29 serial0 = &uart0; 29 serial0 = &uart0;
30 serial1 = &uart1; 30 serial1 = &uart1;
31 serial2 = &uart2; 31 serial2 = &uart2;
32 serial3 = &uart3; 32 serial3 = &uart3;
33 serial4 = &uart4; 33 serial4 = &uart4;
34 serial5 = &uart5; 34 serial5 = &uart5;
35 }; 35 };
36 36
37 soc { 37 soc {
38 #address-cells = <1>; 38 #address-cells = <1>;
39 #size-cells = <1>; 39 #size-cells = <1>;
40 compatible = "simple-bus"; 40 compatible = "simple-bus";
41 ranges; 41 ranges;
42 interrupt-parent = <&intc0>; 42 interrupt-parent = <&intc0>;
43 43
44 intc0: interrupt-controller@d8 44 intc0: interrupt-controller@d8140000 {
45 compatible = "via,vt85 45 compatible = "via,vt8500-intc";
46 interrupt-controller; 46 interrupt-controller;
47 reg = <0xd8140000 0x10 47 reg = <0xd8140000 0x10000>;
48 #interrupt-cells = <1> 48 #interrupt-cells = <1>;
49 }; 49 };
50 50
51 /* Secondary IC cascaded to in 51 /* Secondary IC cascaded to intc0 */
52 intc1: interrupt-controller@d8 52 intc1: interrupt-controller@d8150000 {
53 compatible = "via,vt85 53 compatible = "via,vt8500-intc";
54 interrupt-controller; 54 interrupt-controller;
55 #interrupt-cells = <1> 55 #interrupt-cells = <1>;
56 reg = <0xD8150000 0x10 56 reg = <0xD8150000 0x10000>;
57 interrupts = <56 57 58 57 interrupts = <56 57 58 59 60 61 62 63>;
58 }; 58 };
59 59
60 pinctrl: pinctrl@d8110000 { 60 pinctrl: pinctrl@d8110000 {
61 compatible = "wm,wm850 61 compatible = "wm,wm8505-pinctrl";
62 reg = <0xd8110000 0x10 62 reg = <0xd8110000 0x10000>;
63 interrupt-controller; 63 interrupt-controller;
64 #interrupt-cells = <2> 64 #interrupt-cells = <2>;
65 gpio-controller; 65 gpio-controller;
66 #gpio-cells = <2>; 66 #gpio-cells = <2>;
67 }; 67 };
68 68
69 pmc@d8130000 { 69 pmc@d8130000 {
70 compatible = "via,vt85 70 compatible = "via,vt8500-pmc";
71 reg = <0xd8130000 0x10 71 reg = <0xd8130000 0x1000>;
72 clocks { 72 clocks {
73 #address-cells 73 #address-cells = <1>;
74 #size-cells = 74 #size-cells = <0>;
75 75
76 ref24: ref24M 76 ref24: ref24M {
77 #clock 77 #clock-cells = <0>;
78 compat 78 compatible = "fixed-clock";
79 clock- 79 clock-frequency = <24000000>;
80 }; 80 };
81 81
82 ref25: ref25M 82 ref25: ref25M {
83 #clock 83 #clock-cells = <0>;
84 compat 84 compatible = "fixed-clock";
85 clock- 85 clock-frequency = <25000000>;
86 }; 86 };
87 87
88 plla: plla { 88 plla: plla {
89 #clock 89 #clock-cells = <0>;
90 compat 90 compatible = "via,vt8500-pll-clock";
91 clocks 91 clocks = <&ref25>;
92 reg = 92 reg = <0x200>;
93 }; 93 };
94 94
95 pllb: pllb { 95 pllb: pllb {
96 #clock 96 #clock-cells = <0>;
97 compat 97 compatible = "via,vt8500-pll-clock";
98 clocks 98 clocks = <&ref25>;
99 reg = 99 reg = <0x204>;
100 }; 100 };
101 101
102 pllc: pllc { 102 pllc: pllc {
103 #clock 103 #clock-cells = <0>;
104 compat 104 compatible = "via,vt8500-pll-clock";
105 clocks 105 clocks = <&ref25>;
106 reg = 106 reg = <0x208>;
107 }; 107 };
108 108
109 plld: plld { 109 plld: plld {
110 #clock 110 #clock-cells = <0>;
111 compat 111 compatible = "via,vt8500-pll-clock";
112 clocks 112 clocks = <&ref25>;
113 reg = 113 reg = <0x20c>;
114 }; 114 };
115 115
116 clkarm: arm { 116 clkarm: arm {
117 #clock 117 #clock-cells = <0>;
118 compat 118 compatible = "via,vt8500-device-clock";
119 clocks 119 clocks = <&plla>;
120 diviso 120 divisor-reg = <0x300>;
121 }; 121 };
122 122
123 clkahb: ahb { 123 clkahb: ahb {
124 #clock 124 #clock-cells = <0>;
125 compat 125 compatible = "via,vt8500-device-clock";
126 clocks 126 clocks = <&pllb>;
127 diviso 127 divisor-reg = <0x304>;
128 }; 128 };
129 129
130 clkapb: apb { 130 clkapb: apb {
131 #clock 131 #clock-cells = <0>;
132 compat 132 compatible = "via,vt8500-device-clock";
133 clocks 133 clocks = <&pllb>;
134 diviso 134 divisor-reg = <0x350>;
135 }; 135 };
136 136
137 clkddr: ddr { 137 clkddr: ddr {
138 #clock 138 #clock-cells = <0>;
139 compat 139 compatible = "via,vt8500-device-clock";
140 clocks 140 clocks = <&plld>;
141 diviso 141 divisor-reg = <0x310>;
142 }; 142 };
143 143
144 clkuart0: uart 144 clkuart0: uart0 {
145 #clock 145 #clock-cells = <0>;
146 compat 146 compatible = "via,vt8500-device-clock";
147 clocks 147 clocks = <&ref24>;
148 enable 148 enable-reg = <0x250>;
149 enable 149 enable-bit = <1>;
150 }; 150 };
151 151
152 clkuart1: uart 152 clkuart1: uart1 {
153 #clock 153 #clock-cells = <0>;
154 compat 154 compatible = "via,vt8500-device-clock";
155 clocks 155 clocks = <&ref24>;
156 enable 156 enable-reg = <0x250>;
157 enable 157 enable-bit = <2>;
158 }; 158 };
159 159
160 clkuart2: uart 160 clkuart2: uart2 {
161 #clock 161 #clock-cells = <0>;
162 compat 162 compatible = "via,vt8500-device-clock";
163 clocks 163 clocks = <&ref24>;
164 enable 164 enable-reg = <0x250>;
165 enable 165 enable-bit = <3>;
166 }; 166 };
167 167
168 clkuart3: uart 168 clkuart3: uart3 {
169 #clock 169 #clock-cells = <0>;
170 compat 170 compatible = "via,vt8500-device-clock";
171 clocks 171 clocks = <&ref24>;
172 enable 172 enable-reg = <0x250>;
173 enable 173 enable-bit = <4>;
174 }; 174 };
175 175
176 clkuart4: uart 176 clkuart4: uart4 {
177 #clock 177 #clock-cells = <0>;
178 compat 178 compatible = "via,vt8500-device-clock";
179 clocks 179 clocks = <&ref24>;
180 enable 180 enable-reg = <0x250>;
181 enable 181 enable-bit = <22>;
182 }; 182 };
183 183
184 clkuart5: uart 184 clkuart5: uart5 {
185 #clock 185 #clock-cells = <0>;
186 compat 186 compatible = "via,vt8500-device-clock";
187 clocks 187 clocks = <&ref24>;
188 enable 188 enable-reg = <0x250>;
189 enable 189 enable-bit = <23>;
190 }; 190 };
191 191
192 clksdhc: sdhc 192 clksdhc: sdhc {
193 #clock 193 #clock-cells = <0>;
194 compat 194 compatible = "via,vt8500-device-clock";
195 clocks 195 clocks = <&pllb>;
196 diviso 196 divisor-reg = <0x328>;
197 diviso 197 divisor-mask = <0x3f>;
198 enable 198 enable-reg = <0x254>;
199 enable 199 enable-bit = <18>;
200 }; 200 };
201 }; 201 };
202 }; 202 };
203 203
204 timer@d8130100 { 204 timer@d8130100 {
205 compatible = "via,vt85 205 compatible = "via,vt8500-timer";
206 reg = <0xd8130100 0x28 206 reg = <0xd8130100 0x28>;
207 interrupts = <36>; 207 interrupts = <36>;
208 }; 208 };
209 209
210 ehci@d8007100 { 210 ehci@d8007100 {
211 compatible = "via,vt85 211 compatible = "via,vt8500-ehci";
212 reg = <0xd8007100 0x20 212 reg = <0xd8007100 0x200>;
213 interrupts = <1>; 213 interrupts = <1>;
214 }; 214 };
215 215
216 usb@d8007300 { !! 216 uhci@d8007300 {
217 compatible = "platform 217 compatible = "platform-uhci";
218 reg = <0xd8007300 0x20 218 reg = <0xd8007300 0x200>;
219 interrupts = <0>; 219 interrupts = <0>;
220 }; 220 };
221 221
222 fb: fb@d8050800 { 222 fb: fb@d8050800 {
223 compatible = "wm,wm850 223 compatible = "wm,wm8505-fb";
224 reg = <0xd8050800 0x20 224 reg = <0xd8050800 0x200>;
225 }; 225 };
226 226
227 ge_rops@d8050400 { 227 ge_rops@d8050400 {
228 compatible = "wm,prizm 228 compatible = "wm,prizm-ge-rops";
229 reg = <0xd8050400 0x10 229 reg = <0xd8050400 0x100>;
230 }; 230 };
231 231
232 uart0: serial@d8200000 { 232 uart0: serial@d8200000 {
233 compatible = "via,vt85 233 compatible = "via,vt8500-uart";
234 reg = <0xd8200000 0x10 234 reg = <0xd8200000 0x1040>;
235 interrupts = <32>; 235 interrupts = <32>;
236 clocks = <&clkuart0>; 236 clocks = <&clkuart0>;
237 status = "disabled"; 237 status = "disabled";
238 }; 238 };
239 239
240 uart1: serial@d82b0000 { 240 uart1: serial@d82b0000 {
241 compatible = "via,vt85 241 compatible = "via,vt8500-uart";
242 reg = <0xd82b0000 0x10 242 reg = <0xd82b0000 0x1040>;
243 interrupts = <33>; 243 interrupts = <33>;
244 clocks = <&clkuart1>; 244 clocks = <&clkuart1>;
245 status = "disabled"; 245 status = "disabled";
246 }; 246 };
247 247
248 uart2: serial@d8210000 { 248 uart2: serial@d8210000 {
249 compatible = "via,vt85 249 compatible = "via,vt8500-uart";
250 reg = <0xd8210000 0x10 250 reg = <0xd8210000 0x1040>;
251 interrupts = <47>; 251 interrupts = <47>;
252 clocks = <&clkuart2>; 252 clocks = <&clkuart2>;
253 status = "disabled"; 253 status = "disabled";
254 }; 254 };
255 255
256 uart3: serial@d82c0000 { 256 uart3: serial@d82c0000 {
257 compatible = "via,vt85 257 compatible = "via,vt8500-uart";
258 reg = <0xd82c0000 0x10 258 reg = <0xd82c0000 0x1040>;
259 interrupts = <50>; 259 interrupts = <50>;
260 clocks = <&clkuart3>; 260 clocks = <&clkuart3>;
261 status = "disabled"; 261 status = "disabled";
262 }; 262 };
263 263
264 uart4: serial@d8370000 { 264 uart4: serial@d8370000 {
265 compatible = "via,vt85 265 compatible = "via,vt8500-uart";
266 reg = <0xd8370000 0x10 266 reg = <0xd8370000 0x1040>;
267 interrupts = <31>; 267 interrupts = <31>;
268 clocks = <&clkuart4>; 268 clocks = <&clkuart4>;
269 status = "disabled"; 269 status = "disabled";
270 }; 270 };
271 271
272 uart5: serial@d8380000 { 272 uart5: serial@d8380000 {
273 compatible = "via,vt85 273 compatible = "via,vt8500-uart";
274 reg = <0xd8380000 0x10 274 reg = <0xd8380000 0x1040>;
275 interrupts = <30>; 275 interrupts = <30>;
276 clocks = <&clkuart5>; 276 clocks = <&clkuart5>;
277 status = "disabled"; 277 status = "disabled";
278 }; 278 };
279 279
280 rtc@d8100000 { 280 rtc@d8100000 {
281 compatible = "via,vt85 281 compatible = "via,vt8500-rtc";
282 reg = <0xd8100000 0x10 282 reg = <0xd8100000 0x10000>;
283 interrupts = <48>; 283 interrupts = <48>;
284 }; 284 };
285 285
286 sdhc@d800a000 { 286 sdhc@d800a000 {
287 compatible = "wm,wm850 287 compatible = "wm,wm8505-sdhc";
288 reg = <0xd800a000 0x40 288 reg = <0xd800a000 0x400>;
289 interrupts = <20>, <21 289 interrupts = <20>, <21>;
290 clocks = <&clksdhc>; 290 clocks = <&clksdhc>;
291 bus-width = <4>; 291 bus-width = <4>;
292 }; 292 };
293 }; 293 };
294 }; 294 };
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