1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * wm8650.dtsi - Device tree file for Wonderme
4 *
5 * Copyright (C) 2012 Tony Prisk <linux@priskte
6 */
7
8 / {
9 #address-cells = <1>;
10 #size-cells = <1>;
11 compatible = "wm,wm8650";
12
13 cpus {
14 #address-cells = <0>;
15 #size-cells = <0>;
16
17 cpu {
18 device_type = "cpu";
19 compatible = "arm,arm9
20 };
21 };
22
23 memory {
24 device_type = "memory";
25 reg = <0x0 0x0>;
26 };
27
28 aliases {
29 serial0 = &uart0;
30 serial1 = &uart1;
31 };
32
33 soc {
34 #address-cells = <1>;
35 #size-cells = <1>;
36 compatible = "simple-bus";
37 ranges;
38 interrupt-parent = <&intc0>;
39
40 intc0: interrupt-controller@d8
41 compatible = "via,vt85
42 interrupt-controller;
43 reg = <0xd8140000 0x10
44 #interrupt-cells = <1>
45 };
46
47 /* Secondary IC cascaded to in
48 intc1: interrupt-controller@d8
49 compatible = "via,vt85
50 interrupt-controller;
51 #interrupt-cells = <1>
52 reg = <0xD8150000 0x10
53 interrupts = <56 57 58
54 };
55
56 pinctrl: pinctrl@d8110000 {
57 compatible = "wm,wm865
58 reg = <0xd8110000 0x10
59 interrupt-controller;
60 #interrupt-cells = <2>
61 gpio-controller;
62 #gpio-cells = <2>;
63 };
64
65 pmc@d8130000 {
66 compatible = "via,vt85
67 reg = <0xd8130000 0x10
68
69 clocks {
70 #address-cells
71 #size-cells =
72
73 ref25: ref25M
74 #clock
75 compat
76 clock-
77 };
78
79 ref24: ref24M
80 #clock
81 compat
82 clock-
83 };
84
85 plla: plla {
86 #clock
87 compat
88 clocks
89 reg =
90 };
91
92 pllb: pllb {
93 #clock
94 compat
95 clocks
96 reg =
97 };
98
99 pllc: pllc {
100 #clock
101 compat
102 clocks
103 reg =
104 };
105
106 plld: plld {
107 #clock
108 compat
109 clocks
110 reg =
111 };
112
113 plle: plle {
114 #clock
115 compat
116 clocks
117 reg =
118 };
119
120 clkarm: arm {
121 #clock
122 compat
123 clocks
124 diviso
125 };
126
127 clkahb: ahb {
128 #clock
129 compat
130 clocks
131 diviso
132 };
133
134 clkapb: apb {
135 #clock
136 compat
137 clocks
138 diviso
139 };
140
141 clkddr: ddr {
142 #clock
143 compat
144 clocks
145 diviso
146 };
147
148 clkuart0: uart
149 #clock
150 compat
151 clocks
152 enable
153 enable
154 };
155
156 clkuart1: uart
157 #clock
158 compat
159 clocks
160 enable
161 enable
162 };
163
164 clksdhc: sdhc
165 #clock
166 compat
167 clocks
168 diviso
169 diviso
170 enable
171 enable
172 };
173 };
174 };
175
176 timer@d8130100 {
177 compatible = "via,vt85
178 reg = <0xd8130100 0x28
179 interrupts = <36>;
180 };
181
182 ehci@d8007900 {
183 compatible = "via,vt85
184 reg = <0xd8007900 0x20
185 interrupts = <43>;
186 };
187
188 usb@d8007b00 {
189 compatible = "platform
190 reg = <0xd8007b00 0x20
191 interrupts = <43>;
192 };
193
194 sdhc@d800a000 {
195 compatible = "wm,wm850
196 reg = <0xd800a000 0x40
197 interrupts = <20>, <21
198 clocks = <&clksdhc>;
199 bus-width = <4>;
200 sdon-inverted;
201 };
202
203 fb: fb@d8050800 {
204 compatible = "wm,wm850
205 reg = <0xd8050800 0x20
206 };
207
208 ge_rops@d8050400 {
209 compatible = "wm,prizm
210 reg = <0xd8050400 0x10
211 };
212
213 uart0: serial@d8200000 {
214 compatible = "via,vt85
215 reg = <0xd8200000 0x10
216 interrupts = <32>;
217 clocks = <&clkuart0>;
218 status = "disabled";
219 };
220
221 uart1: serial@d82b0000 {
222 compatible = "via,vt85
223 reg = <0xd82b0000 0x10
224 interrupts = <33>;
225 clocks = <&clkuart1>;
226 status = "disabled";
227 };
228
229 rtc@d8100000 {
230 compatible = "via,vt85
231 reg = <0xd8100000 0x10
232 interrupts = <48>;
233 };
234
235 ethernet@d8004000 {
236 compatible = "via,vt85
237 reg = <0xd8004000 0x10
238 interrupts = <10>;
239 };
240 };
241 };
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