1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * wm8750.dtsi - Device tree file for Wonderme
4 *
5 * Copyright (C) 2012 Tony Prisk <linux@priskte
6 */
7
8 / {
9 #address-cells = <1>;
10 #size-cells = <1>;
11 compatible = "wm,wm8750";
12
13 cpus {
14 #address-cells = <0>;
15 #size-cells = <0>;
16
17 cpu {
18 device_type = "cpu";
19 compatible = "arm,arm1
20 };
21 };
22
23 memory {
24 device_type = "memory";
25 reg = <0x0 0x0>;
26 };
27
28 aliases {
29 serial0 = &uart0;
30 serial1 = &uart1;
31 serial2 = &uart2;
32 serial3 = &uart3;
33 serial4 = &uart4;
34 serial5 = &uart5;
35 i2c0 = &i2c_0;
36 i2c1 = &i2c_1;
37 };
38
39 soc {
40 #address-cells = <1>;
41 #size-cells = <1>;
42 compatible = "simple-bus";
43 ranges;
44 interrupt-parent = <&intc0>;
45
46 intc0: interrupt-controller@d8
47 compatible = "via,vt85
48 interrupt-controller;
49 reg = <0xd8140000 0x10
50 #interrupt-cells = <1>
51 };
52
53 /* Secondary IC cascaded to in
54 intc1: interrupt-controller@d8
55 compatible = "via,vt85
56 interrupt-controller;
57 #interrupt-cells = <1>
58 reg = <0xD8150000 0x10
59 interrupts = <56 57 58
60 };
61
62 pinctrl: pinctrl@d8110000 {
63 compatible = "wm,wm875
64 reg = <0xd8110000 0x10
65 interrupt-controller;
66 #interrupt-cells = <2>
67 gpio-controller;
68 #gpio-cells = <2>;
69 };
70
71 pmc@d8130000 {
72 compatible = "via,vt85
73 reg = <0xd8130000 0x10
74
75 clocks {
76 #address-cells
77 #size-cells =
78
79 ref24: ref24M
80 #clock
81 compat
82 clock-
83 };
84
85 ref25: ref25M
86 #clock
87 compat
88 clock-
89 };
90
91 plla: plla {
92 #clock
93 compat
94 clocks
95 reg =
96 };
97
98 pllb: pllb {
99 #clock
100 compat
101 clocks
102 reg =
103 };
104
105 pllc: pllc {
106 #clock
107 compat
108 clocks
109 reg =
110 };
111
112 plld: plld {
113 #clock
114 compat
115 clocks
116 reg =
117 };
118
119 plle: plle {
120 #clock
121 compat
122 clocks
123 reg =
124 };
125
126 clkarm: arm {
127 #clock
128 compat
129 clocks
130 diviso
131 };
132
133 clkahb: ahb {
134 #clock
135 compat
136 clocks
137 diviso
138 };
139
140 clkapb: apb {
141 #clock
142 compat
143 clocks
144 diviso
145 };
146
147 clkddr: ddr {
148 #clock
149 compat
150 clocks
151 diviso
152 };
153
154 clkuart0: uart
155 #clock
156 compat
157 clocks
158 enable
159 enable
160 };
161
162 clkuart1: uart
163 #clock
164 compat
165 clocks
166 enable
167 enable
168 };
169
170 clkuart2: uart
171 #clock
172 compat
173 clocks
174 enable
175 enable
176 };
177
178 clkuart3: uart
179 #clock
180 compat
181 clocks
182 enable
183 enable
184 };
185
186 clkuart4: uart
187 #clock
188 compat
189 clocks
190 enable
191 enable
192 };
193
194 clkuart5: uart
195 #clock
196 compat
197 clocks
198 enable
199 enable
200 };
201
202 clkpwm: pwm {
203 #clock
204 compat
205 clocks
206 diviso
207 enable
208 enable
209 };
210
211 clksdhc: sdhc
212 #clock
213 compat
214 clocks
215 diviso
216 diviso
217 enable
218 enable
219 };
220
221 clki2c0: i2c0c
222 #clock
223 compat
224 clocks
225 diviso
226 enable
227 enable
228 };
229
230 clki2c1: i2c1c
231 #clock
232 compat
233 clocks
234 diviso
235 enable
236 enable
237 };
238 };
239 };
240
241 pwm: pwm@d8220000 {
242 #pwm-cells = <3>;
243 compatible = "via,vt85
244 reg = <0xd8220000 0x10
245 clocks = <&clkpwm>;
246 };
247
248 timer@d8130100 {
249 compatible = "via,vt85
250 reg = <0xd8130100 0x28
251 interrupts = <36>;
252 };
253
254 ehci@d8007900 {
255 compatible = "via,vt85
256 reg = <0xd8007900 0x20
257 interrupts = <26>;
258 };
259
260 usb@d8007b00 {
261 compatible = "platform
262 reg = <0xd8007b00 0x20
263 interrupts = <26>;
264 };
265
266 usb@d8008d00 {
267 compatible = "platform
268 reg = <0xd8008d00 0x20
269 interrupts = <26>;
270 };
271
272 uart0: serial@d8200000 {
273 compatible = "via,vt85
274 reg = <0xd8200000 0x10
275 interrupts = <32>;
276 clocks = <&clkuart0>;
277 status = "disabled";
278 };
279
280 uart1: serial@d82b0000 {
281 compatible = "via,vt85
282 reg = <0xd82b0000 0x10
283 interrupts = <33>;
284 clocks = <&clkuart1>;
285 status = "disabled";
286 };
287
288 uart2: serial@d8210000 {
289 compatible = "via,vt85
290 reg = <0xd8210000 0x10
291 interrupts = <47>;
292 clocks = <&clkuart2>;
293 status = "disabled";
294 };
295
296 uart3: serial@d82c0000 {
297 compatible = "via,vt85
298 reg = <0xd82c0000 0x10
299 interrupts = <50>;
300 clocks = <&clkuart3>;
301 status = "disabled";
302 };
303
304 uart4: serial@d8370000 {
305 compatible = "via,vt85
306 reg = <0xd8370000 0x10
307 interrupts = <30>;
308 clocks = <&clkuart4>;
309 status = "disabled";
310 };
311
312 uart5: serial@d8380000 {
313 compatible = "via,vt85
314 reg = <0xd8380000 0x10
315 interrupts = <43>;
316 clocks = <&clkuart5>;
317 status = "disabled";
318 };
319
320 rtc@d8100000 {
321 compatible = "via,vt85
322 reg = <0xd8100000 0x10
323 interrupts = <48>;
324 };
325
326 sdhc@d800a000 {
327 compatible = "wm,wm850
328 reg = <0xd800a000 0x10
329 interrupts = <20 21>;
330 clocks = <&clksdhc>;
331 bus-width = <4>;
332 sdon-inverted;
333 };
334
335 i2c_0: i2c@d8280000 {
336 compatible = "wm,wm850
337 reg = <0xd8280000 0x10
338 interrupts = <19>;
339 clocks = <&clki2c0>;
340 clock-frequency = <400
341 };
342
343 i2c_1: i2c@d8320000 {
344 compatible = "wm,wm850
345 reg = <0xd8320000 0x10
346 interrupts = <18>;
347 clocks = <&clki2c1>;
348 clock-frequency = <400
349 };
350 };
351 };
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