1 // SPDX-License-Identifier: GPL-2.0-or-later 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* 2 /*
3 * wm8750.dtsi - Device tree file for Wonderme 3 * wm8750.dtsi - Device tree file for Wondermedia WM8750 SoC
4 * 4 *
5 * Copyright (C) 2012 Tony Prisk <linux@priskte 5 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
6 */ 6 */
7 7
8 / { 8 / {
9 #address-cells = <1>; 9 #address-cells = <1>;
10 #size-cells = <1>; 10 #size-cells = <1>;
11 compatible = "wm,wm8750"; 11 compatible = "wm,wm8750";
12 12
13 cpus { 13 cpus {
14 #address-cells = <0>; 14 #address-cells = <0>;
15 #size-cells = <0>; 15 #size-cells = <0>;
16 16
17 cpu { 17 cpu {
18 device_type = "cpu"; 18 device_type = "cpu";
19 compatible = "arm,arm1 19 compatible = "arm,arm1176jzf";
20 }; 20 };
21 }; 21 };
22 22
23 memory { 23 memory {
24 device_type = "memory"; 24 device_type = "memory";
25 reg = <0x0 0x0>; 25 reg = <0x0 0x0>;
26 }; 26 };
27 27
28 aliases { 28 aliases {
29 serial0 = &uart0; 29 serial0 = &uart0;
30 serial1 = &uart1; 30 serial1 = &uart1;
31 serial2 = &uart2; 31 serial2 = &uart2;
32 serial3 = &uart3; 32 serial3 = &uart3;
33 serial4 = &uart4; 33 serial4 = &uart4;
34 serial5 = &uart5; 34 serial5 = &uart5;
35 i2c0 = &i2c_0; 35 i2c0 = &i2c_0;
36 i2c1 = &i2c_1; 36 i2c1 = &i2c_1;
37 }; 37 };
38 38
39 soc { 39 soc {
40 #address-cells = <1>; 40 #address-cells = <1>;
41 #size-cells = <1>; 41 #size-cells = <1>;
42 compatible = "simple-bus"; 42 compatible = "simple-bus";
43 ranges; 43 ranges;
44 interrupt-parent = <&intc0>; 44 interrupt-parent = <&intc0>;
45 45
46 intc0: interrupt-controller@d8 46 intc0: interrupt-controller@d8140000 {
47 compatible = "via,vt85 47 compatible = "via,vt8500-intc";
48 interrupt-controller; 48 interrupt-controller;
49 reg = <0xd8140000 0x10 49 reg = <0xd8140000 0x10000>;
50 #interrupt-cells = <1> 50 #interrupt-cells = <1>;
51 }; 51 };
52 52
53 /* Secondary IC cascaded to in 53 /* Secondary IC cascaded to intc0 */
54 intc1: interrupt-controller@d8 54 intc1: interrupt-controller@d8150000 {
55 compatible = "via,vt85 55 compatible = "via,vt8500-intc";
56 interrupt-controller; 56 interrupt-controller;
57 #interrupt-cells = <1> 57 #interrupt-cells = <1>;
58 reg = <0xD8150000 0x10 58 reg = <0xD8150000 0x10000>;
59 interrupts = <56 57 58 59 interrupts = <56 57 58 59 60 61 62 63>;
60 }; 60 };
61 61
62 pinctrl: pinctrl@d8110000 { 62 pinctrl: pinctrl@d8110000 {
63 compatible = "wm,wm875 63 compatible = "wm,wm8750-pinctrl";
64 reg = <0xd8110000 0x10 64 reg = <0xd8110000 0x10000>;
65 interrupt-controller; 65 interrupt-controller;
66 #interrupt-cells = <2> 66 #interrupt-cells = <2>;
67 gpio-controller; 67 gpio-controller;
68 #gpio-cells = <2>; 68 #gpio-cells = <2>;
69 }; 69 };
70 70
71 pmc@d8130000 { 71 pmc@d8130000 {
72 compatible = "via,vt85 72 compatible = "via,vt8500-pmc";
73 reg = <0xd8130000 0x10 73 reg = <0xd8130000 0x1000>;
74 74
75 clocks { 75 clocks {
76 #address-cells 76 #address-cells = <1>;
77 #size-cells = 77 #size-cells = <0>;
78 78
79 ref24: ref24M 79 ref24: ref24M {
80 #clock 80 #clock-cells = <0>;
81 compat 81 compatible = "fixed-clock";
82 clock- 82 clock-frequency = <24000000>;
83 }; 83 };
84 84
85 ref25: ref25M 85 ref25: ref25M {
86 #clock 86 #clock-cells = <0>;
87 compat 87 compatible = "fixed-clock";
88 clock- 88 clock-frequency = <25000000>;
89 }; 89 };
90 90
91 plla: plla { 91 plla: plla {
92 #clock 92 #clock-cells = <0>;
93 compat 93 compatible = "wm,wm8750-pll-clock";
94 clocks 94 clocks = <&ref25>;
95 reg = 95 reg = <0x200>;
96 }; 96 };
97 97
98 pllb: pllb { 98 pllb: pllb {
99 #clock 99 #clock-cells = <0>;
100 compat 100 compatible = "wm,wm8750-pll-clock";
101 clocks 101 clocks = <&ref25>;
102 reg = 102 reg = <0x204>;
103 }; 103 };
104 104
105 pllc: pllc { 105 pllc: pllc {
106 #clock 106 #clock-cells = <0>;
107 compat 107 compatible = "wm,wm8750-pll-clock";
108 clocks 108 clocks = <&ref25>;
109 reg = 109 reg = <0x208>;
110 }; 110 };
111 111
112 plld: plld { 112 plld: plld {
113 #clock 113 #clock-cells = <0>;
114 compat 114 compatible = "wm,wm8750-pll-clock";
115 clocks 115 clocks = <&ref25>;
116 reg = 116 reg = <0x20C>;
117 }; 117 };
118 118
119 plle: plle { 119 plle: plle {
120 #clock 120 #clock-cells = <0>;
121 compat 121 compatible = "wm,wm8750-pll-clock";
122 clocks 122 clocks = <&ref25>;
123 reg = 123 reg = <0x210>;
124 }; 124 };
125 125
126 clkarm: arm { 126 clkarm: arm {
127 #clock 127 #clock-cells = <0>;
128 compat 128 compatible = "via,vt8500-device-clock";
129 clocks 129 clocks = <&plla>;
130 diviso 130 divisor-reg = <0x300>;
131 }; 131 };
132 132
133 clkahb: ahb { 133 clkahb: ahb {
134 #clock 134 #clock-cells = <0>;
135 compat 135 compatible = "via,vt8500-device-clock";
136 clocks 136 clocks = <&pllb>;
137 diviso 137 divisor-reg = <0x304>;
138 }; 138 };
139 139
140 clkapb: apb { 140 clkapb: apb {
141 #clock 141 #clock-cells = <0>;
142 compat 142 compatible = "via,vt8500-device-clock";
143 clocks 143 clocks = <&pllb>;
144 diviso 144 divisor-reg = <0x320>;
145 }; 145 };
146 146
147 clkddr: ddr { 147 clkddr: ddr {
148 #clock 148 #clock-cells = <0>;
149 compat 149 compatible = "via,vt8500-device-clock";
150 clocks 150 clocks = <&plld>;
151 diviso 151 divisor-reg = <0x310>;
152 }; 152 };
153 153
154 clkuart0: uart 154 clkuart0: uart0 {
155 #clock 155 #clock-cells = <0>;
156 compat 156 compatible = "via,vt8500-device-clock";
157 clocks 157 clocks = <&ref24>;
158 enable 158 enable-reg = <0x254>;
159 enable 159 enable-bit = <24>;
160 }; 160 };
161 161
162 clkuart1: uart 162 clkuart1: uart1 {
163 #clock 163 #clock-cells = <0>;
164 compat 164 compatible = "via,vt8500-device-clock";
165 clocks 165 clocks = <&ref24>;
166 enable 166 enable-reg = <0x254>;
167 enable 167 enable-bit = <25>;
168 }; 168 };
169 169
170 clkuart2: uart 170 clkuart2: uart2 {
171 #clock 171 #clock-cells = <0>;
172 compat 172 compatible = "via,vt8500-device-clock";
173 clocks 173 clocks = <&ref24>;
174 enable 174 enable-reg = <0x254>;
175 enable 175 enable-bit = <26>;
176 }; 176 };
177 177
178 clkuart3: uart 178 clkuart3: uart3 {
179 #clock 179 #clock-cells = <0>;
180 compat 180 compatible = "via,vt8500-device-clock";
181 clocks 181 clocks = <&ref24>;
182 enable 182 enable-reg = <0x254>;
183 enable 183 enable-bit = <27>;
184 }; 184 };
185 185
186 clkuart4: uart 186 clkuart4: uart4 {
187 #clock 187 #clock-cells = <0>;
188 compat 188 compatible = "via,vt8500-device-clock";
189 clocks 189 clocks = <&ref24>;
190 enable 190 enable-reg = <0x254>;
191 enable 191 enable-bit = <28>;
192 }; 192 };
193 193
194 clkuart5: uart 194 clkuart5: uart5 {
195 #clock 195 #clock-cells = <0>;
196 compat 196 compatible = "via,vt8500-device-clock";
197 clocks 197 clocks = <&ref24>;
198 enable 198 enable-reg = <0x254>;
199 enable 199 enable-bit = <29>;
200 }; 200 };
201 201
202 clkpwm: pwm { 202 clkpwm: pwm {
203 #clock 203 #clock-cells = <0>;
204 compat 204 compatible = "via,vt8500-device-clock";
205 clocks 205 clocks = <&pllb>;
206 diviso 206 divisor-reg = <0x350>;
207 enable 207 enable-reg = <0x250>;
208 enable 208 enable-bit = <17>;
209 }; 209 };
210 210
211 clksdhc: sdhc 211 clksdhc: sdhc {
212 #clock 212 #clock-cells = <0>;
213 compat 213 compatible = "via,vt8500-device-clock";
214 clocks 214 clocks = <&pllb>;
215 diviso 215 divisor-reg = <0x330>;
216 diviso 216 divisor-mask = <0x3f>;
217 enable 217 enable-reg = <0x250>;
218 enable 218 enable-bit = <0>;
219 }; 219 };
220 220
221 clki2c0: i2c0c 221 clki2c0: i2c0clk {
222 #clock 222 #clock-cells = <0>;
223 compat 223 compatible = "via,vt8500-device-clock";
224 clocks 224 clocks = <&pllb>;
225 diviso 225 divisor-reg = <0x3A0>;
226 enable 226 enable-reg = <0x250>;
227 enable 227 enable-bit = <8>;
228 }; 228 };
229 229
230 clki2c1: i2c1c 230 clki2c1: i2c1clk {
231 #clock 231 #clock-cells = <0>;
232 compat 232 compatible = "via,vt8500-device-clock";
233 clocks 233 clocks = <&pllb>;
234 diviso 234 divisor-reg = <0x3A4>;
235 enable 235 enable-reg = <0x250>;
236 enable 236 enable-bit = <9>;
237 }; 237 };
238 }; 238 };
239 }; 239 };
240 240
241 pwm: pwm@d8220000 { 241 pwm: pwm@d8220000 {
242 #pwm-cells = <3>; 242 #pwm-cells = <3>;
243 compatible = "via,vt85 243 compatible = "via,vt8500-pwm";
244 reg = <0xd8220000 0x10 244 reg = <0xd8220000 0x100>;
245 clocks = <&clkpwm>; 245 clocks = <&clkpwm>;
246 }; 246 };
247 247
248 timer@d8130100 { 248 timer@d8130100 {
249 compatible = "via,vt85 249 compatible = "via,vt8500-timer";
250 reg = <0xd8130100 0x28 250 reg = <0xd8130100 0x28>;
251 interrupts = <36>; 251 interrupts = <36>;
252 }; 252 };
253 253
254 ehci@d8007900 { 254 ehci@d8007900 {
255 compatible = "via,vt85 255 compatible = "via,vt8500-ehci";
256 reg = <0xd8007900 0x20 256 reg = <0xd8007900 0x200>;
257 interrupts = <26>; 257 interrupts = <26>;
258 }; 258 };
259 259
260 usb@d8007b00 { 260 usb@d8007b00 {
261 compatible = "platform 261 compatible = "platform-uhci";
262 reg = <0xd8007b00 0x20 262 reg = <0xd8007b00 0x200>;
263 interrupts = <26>; 263 interrupts = <26>;
264 }; 264 };
265 265
266 usb@d8008d00 { 266 usb@d8008d00 {
267 compatible = "platform 267 compatible = "platform-uhci";
268 reg = <0xd8008d00 0x20 268 reg = <0xd8008d00 0x200>;
269 interrupts = <26>; 269 interrupts = <26>;
270 }; 270 };
271 271
272 uart0: serial@d8200000 { 272 uart0: serial@d8200000 {
273 compatible = "via,vt85 273 compatible = "via,vt8500-uart";
274 reg = <0xd8200000 0x10 274 reg = <0xd8200000 0x1040>;
275 interrupts = <32>; 275 interrupts = <32>;
276 clocks = <&clkuart0>; 276 clocks = <&clkuart0>;
277 status = "disabled"; 277 status = "disabled";
278 }; 278 };
279 279
280 uart1: serial@d82b0000 { 280 uart1: serial@d82b0000 {
281 compatible = "via,vt85 281 compatible = "via,vt8500-uart";
282 reg = <0xd82b0000 0x10 282 reg = <0xd82b0000 0x1040>;
283 interrupts = <33>; 283 interrupts = <33>;
284 clocks = <&clkuart1>; 284 clocks = <&clkuart1>;
285 status = "disabled"; 285 status = "disabled";
286 }; 286 };
287 287
288 uart2: serial@d8210000 { 288 uart2: serial@d8210000 {
289 compatible = "via,vt85 289 compatible = "via,vt8500-uart";
290 reg = <0xd8210000 0x10 290 reg = <0xd8210000 0x1040>;
291 interrupts = <47>; 291 interrupts = <47>;
292 clocks = <&clkuart2>; 292 clocks = <&clkuart2>;
293 status = "disabled"; 293 status = "disabled";
294 }; 294 };
295 295
296 uart3: serial@d82c0000 { 296 uart3: serial@d82c0000 {
297 compatible = "via,vt85 297 compatible = "via,vt8500-uart";
298 reg = <0xd82c0000 0x10 298 reg = <0xd82c0000 0x1040>;
299 interrupts = <50>; 299 interrupts = <50>;
300 clocks = <&clkuart3>; 300 clocks = <&clkuart3>;
301 status = "disabled"; 301 status = "disabled";
302 }; 302 };
303 303
304 uart4: serial@d8370000 { 304 uart4: serial@d8370000 {
305 compatible = "via,vt85 305 compatible = "via,vt8500-uart";
306 reg = <0xd8370000 0x10 306 reg = <0xd8370000 0x1040>;
307 interrupts = <30>; 307 interrupts = <30>;
308 clocks = <&clkuart4>; 308 clocks = <&clkuart4>;
309 status = "disabled"; 309 status = "disabled";
310 }; 310 };
311 311
312 uart5: serial@d8380000 { 312 uart5: serial@d8380000 {
313 compatible = "via,vt85 313 compatible = "via,vt8500-uart";
314 reg = <0xd8380000 0x10 314 reg = <0xd8380000 0x1040>;
315 interrupts = <43>; 315 interrupts = <43>;
316 clocks = <&clkuart5>; 316 clocks = <&clkuart5>;
317 status = "disabled"; 317 status = "disabled";
318 }; 318 };
319 319
320 rtc@d8100000 { 320 rtc@d8100000 {
321 compatible = "via,vt85 321 compatible = "via,vt8500-rtc";
322 reg = <0xd8100000 0x10 322 reg = <0xd8100000 0x10000>;
323 interrupts = <48>; 323 interrupts = <48>;
324 }; 324 };
325 325
326 sdhc@d800a000 { 326 sdhc@d800a000 {
327 compatible = "wm,wm850 327 compatible = "wm,wm8505-sdhc";
328 reg = <0xd800a000 0x10 328 reg = <0xd800a000 0x1000>;
329 interrupts = <20 21>; 329 interrupts = <20 21>;
330 clocks = <&clksdhc>; 330 clocks = <&clksdhc>;
331 bus-width = <4>; 331 bus-width = <4>;
332 sdon-inverted; 332 sdon-inverted;
333 }; 333 };
334 334
335 i2c_0: i2c@d8280000 { 335 i2c_0: i2c@d8280000 {
336 compatible = "wm,wm850 336 compatible = "wm,wm8505-i2c";
337 reg = <0xd8280000 0x10 337 reg = <0xd8280000 0x1000>;
338 interrupts = <19>; 338 interrupts = <19>;
339 clocks = <&clki2c0>; 339 clocks = <&clki2c0>;
340 clock-frequency = <400 340 clock-frequency = <400000>;
341 }; 341 };
342 342
343 i2c_1: i2c@d8320000 { 343 i2c_1: i2c@d8320000 {
344 compatible = "wm,wm850 344 compatible = "wm,wm8505-i2c";
345 reg = <0xd8320000 0x10 345 reg = <0xd8320000 0x1000>;
346 interrupts = <18>; 346 interrupts = <18>;
347 clocks = <&clki2c1>; 347 clocks = <&clki2c1>;
348 clock-frequency = <400 348 clock-frequency = <400000>;
349 }; 349 };
350 }; 350 };
351 }; 351 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.