1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Copyright (C) 2021 Michael Walle <michael@wa 3 * Copyright (C) 2021 Michael Walle <michael@walle.cc>
4 */ 4 */
5 /dts-v1/; 5 /dts-v1/;
6 /include/ "zynq-7000.dtsi" 6 /include/ "zynq-7000.dtsi"
7 7
8 / { 8 / {
9 model = "Ebang EBAZ4205"; 9 model = "Ebang EBAZ4205";
10 compatible = "ebang,ebaz4205", "xlnx,z 10 compatible = "ebang,ebaz4205", "xlnx,zynq-7000";
11 11
12 aliases { 12 aliases {
13 ethernet0 = &gem0; 13 ethernet0 = &gem0;
14 serial0 = &uart1; 14 serial0 = &uart1;
15 }; 15 };
16 16
17 memory@0 { 17 memory@0 {
18 device_type = "memory"; 18 device_type = "memory";
19 reg = <0x0 0x10000000>; 19 reg = <0x0 0x10000000>;
20 }; 20 };
21 21
22 chosen { 22 chosen {
23 stdout-path = "serial0:115200n 23 stdout-path = "serial0:115200n8";
24 }; 24 };
25 }; 25 };
26 26
27 &clkc { 27 &clkc {
28 ps-clk-frequency = <33333333>; 28 ps-clk-frequency = <33333333>;
29 fclk-enable = <8>; 29 fclk-enable = <8>;
30 }; 30 };
31 31
32 &gem0 { 32 &gem0 {
33 status = "okay"; 33 status = "okay";
34 phy-mode = "mii"; 34 phy-mode = "mii";
35 phy-handle = <&phy>; 35 phy-handle = <&phy>;
36 36
37 /* PHY clock */ 37 /* PHY clock */
38 assigned-clocks = <&clkc 18>; 38 assigned-clocks = <&clkc 18>;
39 assigned-clock-rates = <25000000>; 39 assigned-clock-rates = <25000000>;
40 40
41 phy: ethernet-phy@0 { 41 phy: ethernet-phy@0 {
42 reg = <0>; 42 reg = <0>;
43 }; 43 };
44 }; 44 };
45 45
46 &gpio0 { 46 &gpio0 {
47 pinctrl-names = "default"; 47 pinctrl-names = "default";
48 pinctrl-0 = <&pinctrl_gpio0_default>; 48 pinctrl-0 = <&pinctrl_gpio0_default>;
49 }; 49 };
50 50
51 &nfc0 { 51 &nfc0 {
52 status = "okay"; 52 status = "okay";
53 53
54 nand@0 { 54 nand@0 {
55 reg = <0>; 55 reg = <0>;
56 }; 56 };
57 }; 57 };
58 58
59 &pinctrl0 { 59 &pinctrl0 {
60 pinctrl_gpio0_default: gpio0-default { 60 pinctrl_gpio0_default: gpio0-default {
61 mux { 61 mux {
62 groups = "gpio0_20_grp 62 groups = "gpio0_20_grp", "gpio0_32_grp";
63 function = "gpio0"; 63 function = "gpio0";
64 }; 64 };
65 65
66 conf { 66 conf {
67 groups = "gpio0_20_grp 67 groups = "gpio0_20_grp", "gpio0_32_grp";
68 io-standard = <3>; 68 io-standard = <3>;
69 slew-rate = <0>; 69 slew-rate = <0>;
70 }; 70 };
71 71
72 conf-pull-up { 72 conf-pull-up {
73 pins = "MIO20", "MIO32 73 pins = "MIO20", "MIO32";
74 bias-disable; 74 bias-disable;
75 }; 75 };
76 }; 76 };
77 77
78 pinctrl_sdhci0_default: sdhci0-default 78 pinctrl_sdhci0_default: sdhci0-default {
79 mux { 79 mux {
80 groups = "sdio0_2_grp" 80 groups = "sdio0_2_grp";
81 function = "sdio0"; 81 function = "sdio0";
82 }; 82 };
83 83
84 conf { 84 conf {
85 groups = "sdio0_2_grp" 85 groups = "sdio0_2_grp";
86 io-standard = <3>; 86 io-standard = <3>;
87 slew-rate = <0>; 87 slew-rate = <0>;
88 bias-disable; 88 bias-disable;
89 }; 89 };
90 90
91 mux-cd { 91 mux-cd {
92 groups = "gpio0_34_grp 92 groups = "gpio0_34_grp";
93 function = "sdio0_cd"; 93 function = "sdio0_cd";
94 }; 94 };
95 95
96 conf-cd { 96 conf-cd {
97 groups = "gpio0_34_grp 97 groups = "gpio0_34_grp";
98 io-standard = <3>; 98 io-standard = <3>;
99 slew-rate = <0>; 99 slew-rate = <0>;
100 bias-high-impedance; 100 bias-high-impedance;
101 bias-pull-up; 101 bias-pull-up;
102 }; 102 };
103 }; 103 };
104 104
105 pinctrl_uart1_default: uart1-default { 105 pinctrl_uart1_default: uart1-default {
106 mux { 106 mux {
107 groups = "uart1_4_grp" 107 groups = "uart1_4_grp";
108 function = "uart1"; 108 function = "uart1";
109 }; 109 };
110 110
111 conf { 111 conf {
112 groups = "uart1_4_grp" 112 groups = "uart1_4_grp";
113 io-standard = <3>; 113 io-standard = <3>;
114 slew-rate = <0>; 114 slew-rate = <0>;
115 }; 115 };
116 116
117 conf-rx { 117 conf-rx {
118 pins = "MIO25"; 118 pins = "MIO25";
119 bias-high-impedance; 119 bias-high-impedance;
120 }; 120 };
121 121
122 conf-tx { 122 conf-tx {
123 pins = "MIO24"; 123 pins = "MIO24";
124 bias-disable; 124 bias-disable;
125 }; 125 };
126 }; 126 };
127 }; 127 };
128 128
129 &smcc { 129 &smcc {
130 status = "okay"; 130 status = "okay";
131 }; 131 };
132 132
133 &sdhci0 { 133 &sdhci0 {
134 status = "okay"; 134 status = "okay";
135 disable-wp; 135 disable-wp;
136 pinctrl-names = "default"; 136 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_sdhci0_default>; 137 pinctrl-0 = <&pinctrl_sdhci0_default>;
138 }; 138 };
139 139
140 &uart1 { 140 &uart1 {
141 status = "okay"; 141 status = "okay";
142 pinctrl-names = "default"; 142 pinctrl-names = "default";
143 pinctrl-0 = <&pinctrl_uart1_default>; 143 pinctrl-0 = <&pinctrl_uart1_default>;
144 }; 144 };
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