1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Xilinx ZC770 XM012 board DTS 3 * Xilinx ZC770 XM012 board DTS
4 * 4 *
5 * Copyright (C) 2013-2018 Xilinx, Inc. 5 * Copyright (C) 2013-2018 Xilinx, Inc.
6 */ 6 */
7 /dts-v1/; 7 /dts-v1/;
8 #include "zynq-7000.dtsi" 8 #include "zynq-7000.dtsi"
9 9
10 / { 10 / {
11 model = "Xilinx ZC770 XM012 board"; 11 model = "Xilinx ZC770 XM012 board";
12 compatible = "xlnx,zynq-zc770-xm012", 12 compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000";
13 13
14 aliases { 14 aliases {
15 i2c0 = &i2c0; 15 i2c0 = &i2c0;
16 i2c1 = &i2c1; 16 i2c1 = &i2c1;
17 serial0 = &uart1; 17 serial0 = &uart1;
18 spi0 = &spi1; 18 spi0 = &spi1;
19 }; 19 };
20 20
21 chosen { 21 chosen {
22 bootargs = ""; 22 bootargs = "";
23 stdout-path = "serial0:115200n 23 stdout-path = "serial0:115200n8";
24 }; 24 };
25 25
26 memory@0 { 26 memory@0 {
27 device_type = "memory"; 27 device_type = "memory";
28 reg = <0x0 0x40000000>; 28 reg = <0x0 0x40000000>;
29 }; 29 };
30 }; 30 };
31 31
32 &can1 { 32 &can1 {
33 status = "okay"; 33 status = "okay";
34 }; 34 };
35 35
36 &i2c0 { 36 &i2c0 {
37 status = "okay"; 37 status = "okay";
38 clock-frequency = <400000>; 38 clock-frequency = <400000>;
39 39
40 eeprom0: eeprom@52 { 40 eeprom0: eeprom@52 {
41 compatible = "atmel,24c02"; 41 compatible = "atmel,24c02";
42 reg = <0x52>; 42 reg = <0x52>;
43 }; 43 };
44 }; 44 };
45 45
46 &i2c1 { 46 &i2c1 {
47 status = "okay"; 47 status = "okay";
48 clock-frequency = <400000>; 48 clock-frequency = <400000>;
49 49
50 eeprom1: eeprom@52 { 50 eeprom1: eeprom@52 {
51 compatible = "atmel,24c02"; 51 compatible = "atmel,24c02";
52 reg = <0x52>; 52 reg = <0x52>;
53 }; 53 };
54 }; 54 };
55 55
56 &spi1 { 56 &spi1 {
57 status = "okay"; 57 status = "okay";
58 num-cs = <4>; 58 num-cs = <4>;
59 is-decoded-cs = <0>; 59 is-decoded-cs = <0>;
60 }; 60 };
61 61
62 &uart1 { 62 &uart1 {
63 status = "okay"; 63 status = "okay";
64 }; 64 };
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