1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Copyright (C) 2011 - 2014 Xilinx 3 * Copyright (C) 2011 - 2014 Xilinx
4 * Copyright (C) 2012 National Instruments Co 4 * Copyright (C) 2012 National Instruments Corp.
5 */ 5 */
6 /dts-v1/; 6 /dts-v1/;
7 #include "zynq-7000.dtsi" 7 #include "zynq-7000.dtsi"
8 8
9 / { 9 / {
10 model = "Avnet ZedBoard board"; 10 model = "Avnet ZedBoard board";
11 compatible = "avnet,zynq-zed", "xlnx,z 11 compatible = "avnet,zynq-zed", "xlnx,zynq-zed", "xlnx,zynq-7000";
12 12
13 aliases { 13 aliases {
14 ethernet0 = &gem0; 14 ethernet0 = &gem0;
15 serial0 = &uart1; 15 serial0 = &uart1;
16 mmc0 = &sdhci0; 16 mmc0 = &sdhci0;
17 }; 17 };
18 18
19 memory@0 { 19 memory@0 {
20 device_type = "memory"; 20 device_type = "memory";
21 reg = <0x0 0x20000000>; 21 reg = <0x0 0x20000000>;
22 }; 22 };
23 23
24 chosen { 24 chosen {
25 bootargs = ""; 25 bootargs = "";
26 stdout-path = "serial0:115200n 26 stdout-path = "serial0:115200n8";
27 }; 27 };
28 28
29 usb_phy0: phy0 { 29 usb_phy0: phy0 {
30 compatible = "usb-nop-xceiv"; 30 compatible = "usb-nop-xceiv";
31 #phy-cells = <0>; 31 #phy-cells = <0>;
32 }; 32 };
33 }; 33 };
34 34
35 &clkc { 35 &clkc {
36 ps-clk-frequency = <33333333>; 36 ps-clk-frequency = <33333333>;
37 }; 37 };
38 38
39 &gem0 { 39 &gem0 {
40 status = "okay"; 40 status = "okay";
41 phy-mode = "rgmii-id"; 41 phy-mode = "rgmii-id";
42 phy-handle = <ðernet_phy>; 42 phy-handle = <ðernet_phy>;
43 43
44 ethernet_phy: ethernet-phy@0 { 44 ethernet_phy: ethernet-phy@0 {
45 reg = <0>; 45 reg = <0>;
46 device_type = "ethernet-phy"; 46 device_type = "ethernet-phy";
47 }; 47 };
48 }; 48 };
49 49
50 &sdhci0 { 50 &sdhci0 {
51 status = "okay"; 51 status = "okay";
52 }; 52 };
53 53
54 &uart1 { 54 &uart1 {
55 status = "okay"; 55 status = "okay";
56 }; 56 };
57 57
58 &usb0 { 58 &usb0 {
59 status = "okay"; 59 status = "okay";
60 dr_mode = "host"; 60 dr_mode = "host";
61 usb-phy = <&usb_phy0>; 61 usb-phy = <&usb_phy0>;
62 }; 62 };
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