1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2020 Yangtao Li <frank@allwinn
4 */
5
6 #include <dt-bindings/interrupt-controller/arm
7 #include <dt-bindings/clock/sun50i-a100-ccu.h>
8 #include <dt-bindings/clock/sun50i-a100-r-ccu.
9 #include <dt-bindings/reset/sun50i-a100-ccu.h>
10 #include <dt-bindings/reset/sun50i-a100-r-ccu.
11
12 / {
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
16
17 cpus {
18 #address-cells = <1>;
19 #size-cells = <0>;
20
21 cpu0: cpu@0 {
22 compatible = "arm,cort
23 device_type = "cpu";
24 reg = <0x0>;
25 enable-method = "psci"
26 };
27
28 cpu@1 {
29 compatible = "arm,cort
30 device_type = "cpu";
31 reg = <0x1>;
32 enable-method = "psci"
33 };
34
35 cpu@2 {
36 compatible = "arm,cort
37 device_type = "cpu";
38 reg = <0x2>;
39 enable-method = "psci"
40 };
41
42 cpu@3 {
43 compatible = "arm,cort
44 device_type = "cpu";
45 reg = <0x3>;
46 enable-method = "psci"
47 };
48 };
49
50 psci {
51 compatible = "arm,psci-1.0";
52 method = "smc";
53 };
54
55 dcxo24M: dcxo24M-clk {
56 compatible = "fixed-clock";
57 clock-frequency = <24000000>;
58 clock-output-names = "dcxo24M"
59 #clock-cells = <0>;
60 };
61
62 iosc: internal-osc-clk {
63 compatible = "fixed-clock";
64 clock-frequency = <16000000>;
65 clock-accuracy = <300000000>;
66 clock-output-names = "iosc";
67 #clock-cells = <0>;
68 };
69
70 osc32k: osc32k-clk {
71 compatible = "fixed-clock";
72 clock-frequency = <32768>;
73 clock-output-names = "osc32k";
74 #clock-cells = <0>;
75 };
76
77 timer {
78 compatible = "arm,armv8-timer"
79 interrupts = <GIC_PPI 13
80 (GIC_CPU_MASK_SIMPLE(4
81 <GIC_PPI 14
82 (GIC_CPU_MASK_SIMPLE(4
83 <GIC_PPI 11
84 (GIC_CPU_MASK_SIMPLE(4
85 <GIC_PPI 10
86 (GIC_CPU_MASK_SIMPLE(4
87 };
88
89 soc {
90 compatible = "simple-bus";
91 #address-cells = <1>;
92 #size-cells = <1>;
93 ranges = <0 0 0 0x3fffffff>;
94
95 ccu: clock@3001000 {
96 compatible = "allwinne
97 reg = <0x03001000 0x10
98 clocks = <&dcxo24M>, <
99 clock-names = "hosc",
100 #clock-cells = <1>;
101 #reset-cells = <1>;
102 };
103
104 dma: dma-controller@3002000 {
105 compatible = "allwinne
106 reg = <0x03002000 0x10
107 interrupts = <GIC_SPI
108 clocks = <&ccu CLK_BUS
109 clock-names = "bus", "
110 resets = <&ccu RST_BUS
111 dma-channels = <8>;
112 dma-requests = <52>;
113 #dma-cells = <1>;
114 };
115
116 gic: interrupt-controller@3021
117 compatible = "arm,gic-
118 reg = <0x03021000 0x10
119 <0x03024000 0x20
120 interrupts = <GIC_PPI
121
122 interrupt-controller;
123 #interrupt-cells = <3>
124 };
125
126 efuse@3006000 {
127 compatible = "allwinne
128 "allwinne
129 reg = <0x03006000 0x10
130 #address-cells = <1>;
131 #size-cells = <1>;
132
133 ths_calibration: calib
134 reg = <0x14 8>
135 };
136 };
137
138 pio: pinctrl@300b000 {
139 compatible = "allwinne
140 reg = <0x0300b000 0x40
141 interrupts = <GIC_SPI
142 <GIC_SPI
143 <GIC_SPI
144 <GIC_SPI
145 <GIC_SPI
146 <GIC_SPI
147 <GIC_SPI
148 clocks = <&ccu CLK_APB
149 clock-names = "apb", "
150 gpio-controller;
151 #gpio-cells = <3>;
152 interrupt-controller;
153 #interrupt-cells = <3>
154
155 uart0_pb_pins: uart0-p
156 pins = "PB9",
157 function = "ua
158 };
159 };
160
161 uart0: serial@5000000 {
162 compatible = "snps,dw-
163 reg = <0x05000000 0x40
164 interrupts = <GIC_SPI
165 reg-shift = <2>;
166 reg-io-width = <4>;
167 clocks = <&ccu CLK_BUS
168 resets = <&ccu RST_BUS
169 status = "disabled";
170 };
171
172 uart1: serial@5000400 {
173 compatible = "snps,dw-
174 reg = <0x05000400 0x40
175 interrupts = <GIC_SPI
176 reg-shift = <2>;
177 reg-io-width = <4>;
178 clocks = <&ccu CLK_BUS
179 resets = <&ccu RST_BUS
180 status = "disabled";
181 };
182
183 uart2: serial@5000800 {
184 compatible = "snps,dw-
185 reg = <0x05000800 0x40
186 interrupts = <GIC_SPI
187 reg-shift = <2>;
188 reg-io-width = <4>;
189 clocks = <&ccu CLK_BUS
190 resets = <&ccu RST_BUS
191 status = "disabled";
192 };
193
194 uart3: serial@5000c00 {
195 compatible = "snps,dw-
196 reg = <0x05000c00 0x40
197 interrupts = <GIC_SPI
198 reg-shift = <2>;
199 reg-io-width = <4>;
200 clocks = <&ccu CLK_BUS
201 resets = <&ccu RST_BUS
202 status = "disabled";
203 };
204
205 uart4: serial@5001000 {
206 compatible = "snps,dw-
207 reg = <0x05001000 0x40
208 interrupts = <GIC_SPI
209 reg-shift = <2>;
210 reg-io-width = <4>;
211 clocks = <&ccu CLK_BUS
212 resets = <&ccu RST_BUS
213 status = "disabled";
214 };
215
216 i2c0: i2c@5002000 {
217 compatible = "allwinne
218 "allwinne
219 "allwinne
220 reg = <0x05002000 0x40
221 interrupts = <GIC_SPI
222 clocks = <&ccu CLK_BUS
223 resets = <&ccu RST_BUS
224 dmas = <&dma 43>, <&dm
225 dma-names = "rx", "tx"
226 status = "disabled";
227 #address-cells = <1>;
228 #size-cells = <0>;
229 };
230
231 i2c1: i2c@5002400 {
232 compatible = "allwinne
233 "allwinne
234 "allwinne
235 reg = <0x05002400 0x40
236 interrupts = <GIC_SPI
237 clocks = <&ccu CLK_BUS
238 resets = <&ccu RST_BUS
239 dmas = <&dma 44>, <&dm
240 dma-names = "rx", "tx"
241 status = "disabled";
242 #address-cells = <1>;
243 #size-cells = <0>;
244 };
245
246 i2c2: i2c@5002800 {
247 compatible = "allwinne
248 "allwinne
249 "allwinne
250 reg = <0x05002800 0x40
251 interrupts = <GIC_SPI
252 clocks = <&ccu CLK_BUS
253 resets = <&ccu RST_BUS
254 dmas = <&dma 45>, <&dm
255 dma-names = "rx", "tx"
256 status = "disabled";
257 #address-cells = <1>;
258 #size-cells = <0>;
259 };
260
261 i2c3: i2c@5002c00 {
262 compatible = "allwinne
263 "allwinne
264 "allwinne
265 reg = <0x05002c00 0x40
266 interrupts = <GIC_SPI
267 clocks = <&ccu CLK_BUS
268 resets = <&ccu RST_BUS
269 dmas = <&dma 46>, <&dm
270 dma-names = "rx", "tx"
271 status = "disabled";
272 #address-cells = <1>;
273 #size-cells = <0>;
274 };
275
276 ths: thermal-sensor@5070400 {
277 compatible = "allwinne
278 reg = <0x05070400 0x10
279 interrupts = <GIC_SPI
280 clocks = <&ccu CLK_BUS
281 clock-names = "bus";
282 resets = <&ccu RST_BUS
283 nvmem-cells = <&ths_ca
284 nvmem-cell-names = "ca
285 #thermal-sensor-cells
286 };
287
288 r_ccu: clock@7010000 {
289 compatible = "allwinne
290 reg = <0x07010000 0x30
291 clocks = <&dcxo24M>, <
292 <&ccu CLK_PLL
293 clock-names = "hosc",
294 #clock-cells = <1>;
295 #reset-cells = <1>;
296 };
297
298 r_intc: interrupt-controller@7
299 compatible = "allwinne
300 "allwinne
301 interrupt-controller;
302 #interrupt-cells = <2>
303 reg = <0x07010320 0xc>
304 interrupts = <GIC_SPI
305 };
306
307 r_pio: pinctrl@7022000 {
308 compatible = "allwinne
309 reg = <0x07022000 0x40
310 interrupts = <GIC_SPI
311 clocks = <&r_ccu CLK_R
312 clock-names = "apb", "
313 gpio-controller;
314 #gpio-cells = <3>;
315 interrupt-controller;
316 #interrupt-cells = <3>
317
318 r_i2c0_pins: r-i2c0-pi
319 pins = "PL0",
320 function = "s_
321 };
322
323 r_i2c1_pins: r-i2c1-pi
324 pins = "PL8",
325 function = "s_
326 };
327 };
328
329 r_uart: serial@7080000 {
330 compatible = "snps,dw-
331 reg = <0x07080000 0x40
332 interrupts = <GIC_SPI
333 reg-shift = <2>;
334 reg-io-width = <4>;
335 clocks = <&r_ccu CLK_R
336 resets = <&r_ccu RST_R
337 status = "disabled";
338 };
339
340 r_i2c0: i2c@7081400 {
341 compatible = "allwinne
342 "allwinne
343 "allwinne
344 reg = <0x07081400 0x40
345 interrupts = <GIC_SPI
346 clocks = <&r_ccu CLK_R
347 resets = <&r_ccu RST_R
348 dmas = <&dma 50>, <&dm
349 dma-names = "rx", "tx"
350 pinctrl-names = "defau
351 pinctrl-0 = <&r_i2c0_p
352 status = "disabled";
353 #address-cells = <1>;
354 #size-cells = <0>;
355 };
356
357 r_i2c1: i2c@7081800 {
358 compatible = "allwinne
359 "allwinne
360 "allwinne
361 reg = <0x07081800 0x40
362 interrupts = <GIC_SPI
363 clocks = <&r_ccu CLK_R
364 resets = <&r_ccu RST_R
365 dmas = <&dma 51>, <&dm
366 dma-names = "rx", "tx"
367 pinctrl-names = "defau
368 pinctrl-0 = <&r_i2c1_p
369 status = "disabled";
370 #address-cells = <1>;
371 #size-cells = <0>;
372 };
373 };
374
375 thermal-zones {
376 cpu-thermal {
377 polling-delay-passive
378 polling-delay = <0>;
379 thermal-sensors = <&th
380 };
381
382 ddr-thermal {
383 polling-delay-passive
384 polling-delay = <0>;
385 thermal-sensors = <&th
386 };
387
388 gpu-thermal {
389 polling-delay-passive
390 polling-delay = <0>;
391 thermal-sensors = <&th
392 };
393 };
394 };
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