1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2016 ARM Ltd.
3 // based on the Allwinner H3 dtsi:
4 // Copyright (C) 2015 Jens Kuske <jenskuske@
5
6 #include <dt-bindings/clock/sun50i-a64-ccu.h>
7 #include <dt-bindings/clock/sun6i-rtc.h>
8 #include <dt-bindings/clock/sun8i-de2.h>
9 #include <dt-bindings/clock/sun8i-r-ccu.h>
10 #include <dt-bindings/interrupt-controller/arm
11 #include <dt-bindings/reset/sun50i-a64-ccu.h>
12 #include <dt-bindings/reset/sun8i-de2.h>
13 #include <dt-bindings/reset/sun8i-r-ccu.h>
14 #include <dt-bindings/thermal/thermal.h>
15
16 / {
17 interrupt-parent = <&gic>;
18 #address-cells = <1>;
19 #size-cells = <1>;
20
21 chosen {
22 #address-cells = <1>;
23 #size-cells = <1>;
24 ranges;
25
26 simplefb_lcd: framebuffer-lcd
27 compatible = "allwinne
28 "simple-f
29 allwinner,pipeline = "
30 clocks = <&ccu CLK_TCO
31 <&display_clo
32 status = "disabled";
33 };
34
35 simplefb_hdmi: framebuffer-hdm
36 compatible = "allwinne
37 "simple-f
38 allwinner,pipeline = "
39 clocks = <&display_clo
40 <&ccu CLK_TCO
41 status = "disabled";
42 };
43 };
44
45 cpus {
46 #address-cells = <1>;
47 #size-cells = <0>;
48
49 cpu0: cpu@0 {
50 compatible = "arm,cort
51 device_type = "cpu";
52 reg = <0>;
53 enable-method = "psci"
54 clocks = <&ccu CLK_CPU
55 clock-names = "cpu";
56 #cooling-cells = <2>;
57 i-cache-size = <0x8000
58 i-cache-line-size = <6
59 i-cache-sets = <256>;
60 d-cache-size = <0x8000
61 d-cache-line-size = <6
62 d-cache-sets = <128>;
63 next-level-cache = <&l
64 };
65
66 cpu1: cpu@1 {
67 compatible = "arm,cort
68 device_type = "cpu";
69 reg = <1>;
70 enable-method = "psci"
71 clocks = <&ccu CLK_CPU
72 clock-names = "cpu";
73 #cooling-cells = <2>;
74 i-cache-size = <0x8000
75 i-cache-line-size = <6
76 i-cache-sets = <256>;
77 d-cache-size = <0x8000
78 d-cache-line-size = <6
79 d-cache-sets = <128>;
80 next-level-cache = <&l
81 };
82
83 cpu2: cpu@2 {
84 compatible = "arm,cort
85 device_type = "cpu";
86 reg = <2>;
87 enable-method = "psci"
88 clocks = <&ccu CLK_CPU
89 clock-names = "cpu";
90 #cooling-cells = <2>;
91 i-cache-size = <0x8000
92 i-cache-line-size = <6
93 i-cache-sets = <256>;
94 d-cache-size = <0x8000
95 d-cache-line-size = <6
96 d-cache-sets = <128>;
97 next-level-cache = <&l
98 };
99
100 cpu3: cpu@3 {
101 compatible = "arm,cort
102 device_type = "cpu";
103 reg = <3>;
104 enable-method = "psci"
105 clocks = <&ccu CLK_CPU
106 clock-names = "cpu";
107 #cooling-cells = <2>;
108 i-cache-size = <0x8000
109 i-cache-line-size = <6
110 i-cache-sets = <256>;
111 d-cache-size = <0x8000
112 d-cache-line-size = <6
113 d-cache-sets = <128>;
114 next-level-cache = <&l
115 };
116
117 l2_cache: l2-cache {
118 compatible = "cache";
119 cache-level = <2>;
120 cache-unified;
121 cache-size = <0x80000>
122 cache-line-size = <64>
123 cache-sets = <512>;
124 };
125 };
126
127 de: display-engine {
128 compatible = "allwinner,sun50i
129 allwinner,pipelines = <&mixer0
130 <&mixer1
131 status = "disabled";
132 };
133
134 gpu_opp_table: opp-table-gpu {
135 compatible = "operating-points
136
137 opp-432000000 {
138 opp-hz = /bits/ 64 <43
139 };
140 };
141
142 osc24M: osc24M-clk {
143 #clock-cells = <0>;
144 compatible = "fixed-clock";
145 clock-frequency = <24000000>;
146 clock-output-names = "osc24M";
147 };
148
149 osc32k: osc32k-clk {
150 #clock-cells = <0>;
151 compatible = "fixed-clock";
152 clock-frequency = <32768>;
153 clock-output-names = "ext-osc3
154 };
155
156 pmu {
157 compatible = "arm,cortex-a53-p
158 interrupts = <GIC_SPI 116 IRQ_
159 <GIC_SPI 117 IRQ_
160 <GIC_SPI 118 IRQ_
161 <GIC_SPI 119 IRQ_
162 interrupt-affinity = <&cpu0>,
163 };
164
165 psci {
166 compatible = "arm,psci-0.2";
167 method = "smc";
168 };
169
170 sound: sound {
171 #address-cells = <1>;
172 #size-cells = <0>;
173 compatible = "simple-audio-car
174 simple-audio-card,name = "sun5
175 simple-audio-card,aux-devs = <
176 simple-audio-card,routing =
177 "Left DAC", "D
178 "Right DAC", "
179 "ADCL", "Left
180 "ADCR", "Right
181 status = "disabled";
182
183 simple-audio-card,dai-link@0 {
184 format = "i2s";
185 frame-master = <&link0
186 bitclock-master = <&li
187 mclk-fs = <128>;
188
189 link0_cpu: cpu {
190 sound-dai = <&
191 };
192
193 link0_codec: codec {
194 sound-dai = <&
195 };
196 };
197 };
198
199 timer {
200 compatible = "arm,armv8-timer"
201 allwinner,erratum-unknown1;
202 arm,no-tick-in-suspend;
203 interrupts = <GIC_PPI 13
204 (GIC_CPU_MASK_SIMPLE(4
205 <GIC_PPI 14
206 (GIC_CPU_MASK_SIMPLE(4
207 <GIC_PPI 11
208 (GIC_CPU_MASK_SIMPLE(4
209 <GIC_PPI 10
210 (GIC_CPU_MASK_SIMPLE(4
211 };
212
213 thermal-zones {
214 cpu_thermal: cpu0-thermal {
215 /* milliseconds */
216 polling-delay-passive
217 polling-delay = <0>;
218 thermal-sensors = <&th
219
220 cooling-maps {
221 map0 {
222 trip =
223 coolin
224
225
226
227 };
228 map1 {
229 trip =
230 coolin
231
232
233
234 };
235 };
236
237 trips {
238 cpu_alert0: cp
239 /* mil
240 temper
241 hyster
242 type =
243 };
244
245 cpu_alert1: cp
246 /* mil
247 temper
248 hyster
249 type =
250 };
251
252 cpu_crit: cpu-
253 /* mil
254 temper
255 hyster
256 type =
257 };
258 };
259 };
260
261 gpu0_thermal: gpu0-thermal {
262 /* milliseconds */
263 polling-delay-passive
264 polling-delay = <0>;
265 thermal-sensors = <&th
266
267 trips {
268 gpu0_crit: gpu
269 temper
270 hyster
271 type =
272 };
273 };
274 };
275
276 gpu1_thermal: gpu1-thermal {
277 /* milliseconds */
278 polling-delay-passive
279 polling-delay = <0>;
280 thermal-sensors = <&th
281
282 trips {
283 gpu1_crit: gpu
284 temper
285 hyster
286 type =
287 };
288 };
289 };
290 };
291
292 soc {
293 compatible = "simple-bus";
294 #address-cells = <1>;
295 #size-cells = <1>;
296 ranges;
297
298 bus@1000000 {
299 compatible = "allwinne
300 reg = <0x1000000 0x400
301 allwinner,sram = <&de2
302 #address-cells = <1>;
303 #size-cells = <1>;
304 ranges = <0 0x1000000
305
306 display_clocks: clock@
307 compatible = "
308 reg = <0x0 0x1
309 clocks = <&ccu
310 <&ccu
311 clock-names =
312
313 resets = <&ccu
314 #clock-cells =
315 #reset-cells =
316 };
317
318 rotate: rotate@20000 {
319 compatible = "
320 "
321 reg = <0x20000
322 interrupts = <
323 clocks = <&dis
324 <&dis
325 clock-names =
326
327 resets = <&dis
328 };
329
330 mixer0: mixer@100000 {
331 compatible = "
332 reg = <0x10000
333 clocks = <&dis
334 <&dis
335 clock-names =
336
337 resets = <&dis
338
339 ports {
340 #addre
341 #size-
342
343 mixer0
344
345
346
347
348
349
350
351
352
353
354
355
356
357 };
358 };
359 };
360
361 mixer1: mixer@200000 {
362 compatible = "
363 reg = <0x20000
364 clocks = <&dis
365 <&dis
366 clock-names =
367
368 resets = <&dis
369
370 ports {
371 #addre
372 #size-
373
374 mixer1
375
376
377
378
379
380
381
382
383
384
385
386
387
388 };
389 };
390 };
391 };
392
393 syscon: syscon@1c00000 {
394 compatible = "allwinne
395 reg = <0x01c00000 0x10
396 #address-cells = <1>;
397 #size-cells = <1>;
398 ranges;
399
400 sram_c: sram@18000 {
401 compatible = "
402 reg = <0x00018
403 #address-cells
404 #size-cells =
405 ranges = <0 0x
406
407 de2_sram: sram
408 compat
409 reg =
410 };
411 };
412
413 sram_c1: sram@1d00000
414 compatible = "
415 reg = <0x01d00
416 #address-cells
417 #size-cells =
418 ranges = <0 0x
419
420 ve_sram: sram-
421 compat
422
423 reg =
424 };
425 };
426 };
427
428 dma: dma-controller@1c02000 {
429 compatible = "allwinne
430 reg = <0x01c02000 0x10
431 interrupts = <GIC_SPI
432 clocks = <&ccu CLK_BUS
433 dma-channels = <8>;
434 dma-requests = <27>;
435 resets = <&ccu RST_BUS
436 #dma-cells = <1>;
437 };
438
439 tcon0: lcd-controller@1c0c000
440 compatible = "allwinne
441 "allwinne
442 reg = <0x01c0c000 0x10
443 interrupts = <GIC_SPI
444 clocks = <&ccu CLK_BUS
445 clock-names = "ahb", "
446 clock-output-names = "
447 #clock-cells = <0>;
448 resets = <&ccu RST_BUS
449 reset-names = "lcd", "
450
451 ports {
452 #address-cells
453 #size-cells =
454
455 tcon0_in: port
456 #addre
457 #size-
458 reg =
459
460 tcon0_
461
462
463 };
464
465 tcon0_
466
467
468 };
469 };
470
471 tcon0_out: por
472 #addre
473 #size-
474 reg =
475
476 tcon0_
477
478
479
480 };
481 };
482 };
483 };
484
485 tcon1: lcd-controller@1c0d000
486 compatible = "allwinne
487 "allwinne
488 reg = <0x01c0d000 0x10
489 interrupts = <GIC_SPI
490 clocks = <&ccu CLK_BUS
491 clock-names = "ahb", "
492 resets = <&ccu RST_BUS
493 reset-names = "lcd";
494
495 ports {
496 #address-cells
497 #size-cells =
498
499 tcon1_in: port
500 #addre
501 #size-
502 reg =
503
504 tcon1_
505
506
507 };
508
509 tcon1_
510
511
512 };
513 };
514
515 tcon1_out: por
516 #addre
517 #size-
518 reg =
519
520 tcon1_
521
522
523 };
524 };
525 };
526 };
527
528 video-codec@1c0e000 {
529 compatible = "allwinne
530 reg = <0x01c0e000 0x10
531 clocks = <&ccu CLK_BUS
532 <&ccu CLK_DRA
533 clock-names = "ahb", "
534 resets = <&ccu RST_BUS
535 interrupts = <GIC_SPI
536 allwinner,sram = <&ve_
537 };
538
539 mmc0: mmc@1c0f000 {
540 compatible = "allwinne
541 reg = <0x01c0f000 0x10
542 clocks = <&ccu CLK_BUS
543 clock-names = "ahb", "
544 resets = <&ccu RST_BUS
545 reset-names = "ahb";
546 interrupts = <GIC_SPI
547 max-frequency = <15000
548 status = "disabled";
549 #address-cells = <1>;
550 #size-cells = <0>;
551 };
552
553 mmc1: mmc@1c10000 {
554 compatible = "allwinne
555 reg = <0x01c10000 0x10
556 clocks = <&ccu CLK_BUS
557 clock-names = "ahb", "
558 resets = <&ccu RST_BUS
559 reset-names = "ahb";
560 interrupts = <GIC_SPI
561 max-frequency = <15000
562 status = "disabled";
563 #address-cells = <1>;
564 #size-cells = <0>;
565 };
566
567 mmc2: mmc@1c11000 {
568 compatible = "allwinne
569 reg = <0x01c11000 0x10
570 clocks = <&ccu CLK_BUS
571 clock-names = "ahb", "
572 resets = <&ccu RST_BUS
573 reset-names = "ahb";
574 interrupts = <GIC_SPI
575 max-frequency = <15000
576 status = "disabled";
577 #address-cells = <1>;
578 #size-cells = <0>;
579 };
580
581 sid: eeprom@1c14000 {
582 compatible = "allwinne
583 reg = <0x1c14000 0x400
584 #address-cells = <1>;
585 #size-cells = <1>;
586
587 ths_calibration: therm
588 reg = <0x34 0x
589 };
590 };
591
592 crypto: crypto@1c15000 {
593 compatible = "allwinne
594 reg = <0x01c15000 0x10
595 interrupts = <GIC_SPI
596 clocks = <&ccu CLK_BUS
597 clock-names = "bus", "
598 resets = <&ccu RST_BUS
599 };
600
601 msgbox: mailbox@1c17000 {
602 compatible = "allwinne
603 "allwinne
604 reg = <0x01c17000 0x10
605 clocks = <&ccu CLK_BUS
606 resets = <&ccu RST_BUS
607 interrupts = <GIC_SPI
608 #mbox-cells = <1>;
609 };
610
611 usb_otg: usb@1c19000 {
612 compatible = "allwinne
613 reg = <0x01c19000 0x04
614 clocks = <&ccu CLK_BUS
615 resets = <&ccu RST_BUS
616 interrupts = <GIC_SPI
617 interrupt-names = "mc"
618 phys = <&usbphy 0>;
619 phy-names = "usb";
620 extcon = <&usbphy 0>;
621 dr_mode = "otg";
622 status = "disabled";
623 };
624
625 usbphy: phy@1c19400 {
626 compatible = "allwinne
627 reg = <0x01c19400 0x14
628 <0x01c1a800 0x4>
629 <0x01c1b800 0x4>
630 reg-names = "phy_ctrl"
631 "pmu0",
632 "pmu1";
633 clocks = <&ccu CLK_USB
634 <&ccu CLK_USB
635 clock-names = "usb0_ph
636 "usb1_ph
637 resets = <&ccu RST_USB
638 <&ccu RST_USB
639 reset-names = "usb0_re
640 "usb1_re
641 status = "disabled";
642 #phy-cells = <1>;
643 };
644
645 ehci0: usb@1c1a000 {
646 compatible = "allwinne
647 reg = <0x01c1a000 0x10
648 interrupts = <GIC_SPI
649 clocks = <&ccu CLK_BUS
650 <&ccu CLK_BUS
651 <&ccu CLK_USB
652 resets = <&ccu RST_BUS
653 <&ccu RST_BUS
654 phys = <&usbphy 0>;
655 phy-names = "usb";
656 status = "disabled";
657 };
658
659 ohci0: usb@1c1a400 {
660 compatible = "allwinne
661 reg = <0x01c1a400 0x10
662 interrupts = <GIC_SPI
663 clocks = <&ccu CLK_BUS
664 <&ccu CLK_USB
665 resets = <&ccu RST_BUS
666 phys = <&usbphy 0>;
667 phy-names = "usb";
668 status = "disabled";
669 };
670
671 ehci1: usb@1c1b000 {
672 compatible = "allwinne
673 reg = <0x01c1b000 0x10
674 interrupts = <GIC_SPI
675 clocks = <&ccu CLK_BUS
676 <&ccu CLK_BUS
677 <&ccu CLK_USB
678 resets = <&ccu RST_BUS
679 <&ccu RST_BUS
680 phys = <&usbphy 1>;
681 phy-names = "usb";
682 status = "disabled";
683 };
684
685 ohci1: usb@1c1b400 {
686 compatible = "allwinne
687 reg = <0x01c1b400 0x10
688 interrupts = <GIC_SPI
689 clocks = <&ccu CLK_BUS
690 <&ccu CLK_USB
691 resets = <&ccu RST_BUS
692 phys = <&usbphy 1>;
693 phy-names = "usb";
694 status = "disabled";
695 };
696
697 ccu: clock@1c20000 {
698 compatible = "allwinne
699 reg = <0x01c20000 0x40
700 clocks = <&osc24M>, <&
701 clock-names = "hosc",
702 #clock-cells = <1>;
703 #reset-cells = <1>;
704 };
705
706 pio: pinctrl@1c20800 {
707 compatible = "allwinne
708 reg = <0x01c20800 0x40
709 interrupt-parent = <&r
710 interrupts = <GIC_SPI
711 <GIC_SPI
712 <GIC_SPI
713 clocks = <&ccu CLK_BUS
714 <&rtc CLK_OSC
715 clock-names = "apb", "
716 gpio-controller;
717 #gpio-cells = <3>;
718 interrupt-controller;
719 #interrupt-cells = <3>
720
721 /omit-if-no-ref/
722 aif2_pins: aif2-pins {
723 pins = "PB4",
724 function = "ai
725 };
726
727 /omit-if-no-ref/
728 aif3_pins: aif3-pins {
729 pins = "PG10",
730 function = "ai
731 };
732
733 csi_pins: csi-pins {
734 pins = "PE0",
735 "PE7",
736 function = "cs
737 };
738
739 /omit-if-no-ref/
740 csi_mclk_pin: csi-mclk
741 pins = "PE1";
742 function = "cs
743 };
744
745 i2c0_pins: i2c0-pins {
746 pins = "PH0",
747 function = "i2
748 };
749
750 i2c1_pins: i2c1-pins {
751 pins = "PH2",
752 function = "i2
753 };
754
755 i2c2_pins: i2c2-pins {
756 pins = "PE14",
757 function = "i2
758 };
759
760 /omit-if-no-ref/
761 lcd_rgb666_pins: lcd-r
762 pins = "PD0",
763 "PD5",
764 "PD10",
765 "PD14",
766 "PD18",
767 function = "lc
768 };
769
770 mmc0_pins: mmc0-pins {
771 pins = "PF0",
772 "PF4",
773 function = "mm
774 drive-strength
775 bias-pull-up;
776 };
777
778 mmc1_pins: mmc1-pins {
779 pins = "PG0",
780 "PG4",
781 function = "mm
782 drive-strength
783 bias-pull-up;
784 };
785
786 mmc2_pins: mmc2-pins {
787 pins = "PC5",
788 "PC10",
789 "PC14",
790 function = "mm
791 drive-strength
792 bias-pull-up;
793 };
794
795 mmc2_ds_pin: mmc2-ds-p
796 pins = "PC1";
797 function = "mm
798 drive-strength
799 bias-pull-up;
800 };
801
802 pwm_pin: pwm-pin {
803 pins = "PD22";
804 function = "pw
805 };
806
807 rmii_pins: rmii-pins {
808 pins = "PD10",
809 "PD18",
810 function = "em
811 drive-strength
812 };
813
814 rgmii_pins: rgmii-pins
815 pins = "PD8",
816 "PD13",
817 "PD19",
818 function = "em
819 drive-strength
820 };
821
822 spdif_tx_pin: spdif-tx
823 pins = "PH8";
824 function = "sp
825 };
826
827 spi0_pins: spi0-pins {
828 pins = "PC0",
829 function = "sp
830 };
831
832 spi1_pins: spi1-pins {
833 pins = "PD0",
834 function = "sp
835 };
836
837 uart0_pb_pins: uart0-p
838 pins = "PB8",
839 function = "ua
840 };
841
842 uart1_pins: uart1-pins
843 pins = "PG6",
844 function = "ua
845 };
846
847 uart1_rts_cts_pins: ua
848 pins = "PG8",
849 function = "ua
850 };
851
852 uart2_pins: uart2-pins
853 pins = "PB0",
854 function = "ua
855 };
856
857 uart3_pins: uart3-pins
858 pins = "PD0",
859 function = "ua
860 };
861
862 uart4_pins: uart4-pins
863 pins = "PD2",
864 function = "ua
865 };
866
867 uart4_rts_cts_pins: ua
868 pins = "PD4",
869 function = "ua
870 };
871 };
872
873 timer@1c20c00 {
874 compatible = "allwinne
875 "allwinne
876 reg = <0x01c20c00 0xa0
877 interrupts = <GIC_SPI
878 <GIC_SPI
879 clocks = <&osc24M>;
880 };
881
882 wdt0: watchdog@1c20ca0 {
883 compatible = "allwinne
884 "allwinne
885 reg = <0x01c20ca0 0x20
886 interrupts = <GIC_SPI
887 clocks = <&osc24M>;
888 };
889
890 spdif: spdif@1c21000 {
891 #sound-dai-cells = <0>
892 compatible = "allwinne
893 "allwinne
894 reg = <0x01c21000 0x40
895 interrupts = <GIC_SPI
896 clocks = <&ccu CLK_BUS
897 resets = <&ccu RST_BUS
898 clock-names = "apb", "
899 dmas = <&dma 2>;
900 dma-names = "tx";
901 pinctrl-names = "defau
902 pinctrl-0 = <&spdif_tx
903 status = "disabled";
904 };
905
906 lradc: lradc@1c21800 {
907 compatible = "allwinne
908 "allwinne
909 reg = <0x01c21800 0x40
910 interrupt-parent = <&r
911 interrupts = <GIC_SPI
912 status = "disabled";
913 };
914
915 i2s0: i2s@1c22000 {
916 #sound-dai-cells = <0>
917 compatible = "allwinne
918 "allwinne
919 reg = <0x01c22000 0x40
920 interrupts = <GIC_SPI
921 clocks = <&ccu CLK_BUS
922 clock-names = "apb", "
923 resets = <&ccu RST_BUS
924 dma-names = "rx", "tx"
925 dmas = <&dma 3>, <&dma
926 status = "disabled";
927 };
928
929 i2s1: i2s@1c22400 {
930 #sound-dai-cells = <0>
931 compatible = "allwinne
932 "allwinne
933 reg = <0x01c22400 0x40
934 interrupts = <GIC_SPI
935 clocks = <&ccu CLK_BUS
936 clock-names = "apb", "
937 resets = <&ccu RST_BUS
938 dma-names = "rx", "tx"
939 dmas = <&dma 4>, <&dma
940 status = "disabled";
941 };
942
943 i2s2: i2s@1c22800 {
944 #sound-dai-cells = <0>
945 compatible = "allwinne
946 "allwinne
947 reg = <0x01c22800 0x40
948 interrupts = <GIC_SPI
949 clocks = <&ccu CLK_BUS
950 clock-names = "apb", "
951 resets = <&ccu RST_BUS
952 dma-names = "rx", "tx"
953 dmas = <&dma 27>, <&dm
954 status = "disabled";
955 };
956
957 dai: dai@1c22c00 {
958 #sound-dai-cells = <0>
959 compatible = "allwinne
960 reg = <0x01c22c00 0x20
961 interrupts = <GIC_SPI
962 clocks = <&ccu CLK_BUS
963 clock-names = "apb", "
964 resets = <&ccu RST_BUS
965 dmas = <&dma 15>, <&dm
966 dma-names = "rx", "tx"
967 status = "disabled";
968 };
969
970 codec: codec@1c22e00 {
971 #sound-dai-cells = <1>
972 compatible = "allwinne
973 "allwinne
974 reg = <0x01c22e00 0x60
975 interrupts = <GIC_SPI
976 clocks = <&ccu CLK_BUS
977 clock-names = "bus", "
978 status = "disabled";
979 };
980
981 ths: thermal-sensor@1c25000 {
982 compatible = "allwinne
983 reg = <0x01c25000 0x10
984 clocks = <&ccu CLK_BUS
985 clock-names = "bus", "
986 interrupts = <GIC_SPI
987 resets = <&ccu RST_BUS
988 nvmem-cells = <&ths_ca
989 nvmem-cell-names = "ca
990 #thermal-sensor-cells
991 };
992
993 uart0: serial@1c28000 {
994 compatible = "snps,dw-
995 reg = <0x01c28000 0x40
996 interrupts = <GIC_SPI
997 reg-shift = <2>;
998 reg-io-width = <4>;
999 clocks = <&ccu CLK_BUS
1000 resets = <&ccu RST_BU
1001 status = "disabled";
1002 };
1003
1004 uart1: serial@1c28400 {
1005 compatible = "snps,dw
1006 reg = <0x01c28400 0x4
1007 interrupts = <GIC_SPI
1008 reg-shift = <2>;
1009 reg-io-width = <4>;
1010 clocks = <&ccu CLK_BU
1011 resets = <&ccu RST_BU
1012 status = "disabled";
1013 };
1014
1015 uart2: serial@1c28800 {
1016 compatible = "snps,dw
1017 reg = <0x01c28800 0x4
1018 interrupts = <GIC_SPI
1019 reg-shift = <2>;
1020 reg-io-width = <4>;
1021 clocks = <&ccu CLK_BU
1022 resets = <&ccu RST_BU
1023 status = "disabled";
1024 };
1025
1026 uart3: serial@1c28c00 {
1027 compatible = "snps,dw
1028 reg = <0x01c28c00 0x4
1029 interrupts = <GIC_SPI
1030 reg-shift = <2>;
1031 reg-io-width = <4>;
1032 clocks = <&ccu CLK_BU
1033 resets = <&ccu RST_BU
1034 status = "disabled";
1035 };
1036
1037 uart4: serial@1c29000 {
1038 compatible = "snps,dw
1039 reg = <0x01c29000 0x4
1040 interrupts = <GIC_SPI
1041 reg-shift = <2>;
1042 reg-io-width = <4>;
1043 clocks = <&ccu CLK_BU
1044 resets = <&ccu RST_BU
1045 status = "disabled";
1046 };
1047
1048 i2c0: i2c@1c2ac00 {
1049 compatible = "allwinn
1050 reg = <0x01c2ac00 0x4
1051 interrupts = <GIC_SPI
1052 clocks = <&ccu CLK_BU
1053 resets = <&ccu RST_BU
1054 pinctrl-names = "defa
1055 pinctrl-0 = <&i2c0_pi
1056 status = "disabled";
1057 #address-cells = <1>;
1058 #size-cells = <0>;
1059 };
1060
1061 i2c1: i2c@1c2b000 {
1062 compatible = "allwinn
1063 reg = <0x01c2b000 0x4
1064 interrupts = <GIC_SPI
1065 clocks = <&ccu CLK_BU
1066 resets = <&ccu RST_BU
1067 pinctrl-names = "defa
1068 pinctrl-0 = <&i2c1_pi
1069 status = "disabled";
1070 #address-cells = <1>;
1071 #size-cells = <0>;
1072 };
1073
1074 i2c2: i2c@1c2b400 {
1075 compatible = "allwinn
1076 reg = <0x01c2b400 0x4
1077 interrupts = <GIC_SPI
1078 clocks = <&ccu CLK_BU
1079 resets = <&ccu RST_BU
1080 pinctrl-names = "defa
1081 pinctrl-0 = <&i2c2_pi
1082 status = "disabled";
1083 #address-cells = <1>;
1084 #size-cells = <0>;
1085 };
1086
1087 spi0: spi@1c68000 {
1088 compatible = "allwinn
1089 reg = <0x01c68000 0x1
1090 interrupts = <GIC_SPI
1091 clocks = <&ccu CLK_BU
1092 clock-names = "ahb",
1093 dmas = <&dma 23>, <&d
1094 dma-names = "rx", "tx
1095 pinctrl-names = "defa
1096 pinctrl-0 = <&spi0_pi
1097 resets = <&ccu RST_BU
1098 status = "disabled";
1099 num-cs = <1>;
1100 #address-cells = <1>;
1101 #size-cells = <0>;
1102 };
1103
1104 spi1: spi@1c69000 {
1105 compatible = "allwinn
1106 reg = <0x01c69000 0x1
1107 interrupts = <GIC_SPI
1108 clocks = <&ccu CLK_BU
1109 clock-names = "ahb",
1110 dmas = <&dma 24>, <&d
1111 dma-names = "rx", "tx
1112 pinctrl-names = "defa
1113 pinctrl-0 = <&spi1_pi
1114 resets = <&ccu RST_BU
1115 status = "disabled";
1116 num-cs = <1>;
1117 #address-cells = <1>;
1118 #size-cells = <0>;
1119 };
1120
1121 emac: ethernet@1c30000 {
1122 compatible = "allwinn
1123 syscon = <&syscon>;
1124 reg = <0x01c30000 0x1
1125 interrupts = <GIC_SPI
1126 interrupt-names = "ma
1127 resets = <&ccu RST_BU
1128 reset-names = "stmmac
1129 clocks = <&ccu CLK_BU
1130 clock-names = "stmmac
1131 status = "disabled";
1132
1133 mdio: mdio {
1134 compatible =
1135 #address-cell
1136 #size-cells =
1137 };
1138 };
1139
1140 mali: gpu@1c40000 {
1141 compatible = "allwinn
1142 reg = <0x01c40000 0x1
1143 interrupts = <GIC_SPI
1144 <GIC_SPI
1145 <GIC_SPI
1146 <GIC_SPI
1147 <GIC_SPI
1148 <GIC_SPI
1149 <GIC_SPI
1150 interrupt-names = "gp
1151 "gp
1152 "pp
1153 "pp
1154 "pp
1155 "pp
1156 "pm
1157 clocks = <&ccu CLK_BU
1158 clock-names = "bus",
1159 resets = <&ccu RST_BU
1160 operating-points-v2 =
1161 };
1162
1163 gic: interrupt-controller@1c8
1164 compatible = "arm,gic
1165 reg = <0x01c81000 0x1
1166 <0x01c82000 0x2
1167 <0x01c84000 0x2
1168 <0x01c86000 0x2
1169 interrupts = <GIC_PPI
1170 interrupt-controller;
1171 #interrupt-cells = <3
1172 };
1173
1174 pwm: pwm@1c21400 {
1175 compatible = "allwinn
1176 "allwinn
1177 reg = <0x01c21400 0x4
1178 clocks = <&osc24M>;
1179 pinctrl-names = "defa
1180 pinctrl-0 = <&pwm_pin
1181 #pwm-cells = <3>;
1182 status = "disabled";
1183 };
1184
1185 mbus: dram-controller@1c62000
1186 compatible = "allwinn
1187 reg = <0x01c62000 0x1
1188 <0x01c63000 0x1
1189 reg-names = "mbus", "
1190 clocks = <&ccu CLK_MB
1191 <&ccu CLK_DR
1192 <&ccu CLK_BU
1193 clock-names = "mbus",
1194 interrupts = <GIC_SPI
1195 #address-cells = <1>;
1196 #size-cells = <1>;
1197 dma-ranges = <0x00000
1198 #interconnect-cells =
1199 };
1200
1201 csi: csi@1cb0000 {
1202 compatible = "allwinn
1203 reg = <0x01cb0000 0x1
1204 interrupts = <GIC_SPI
1205 clocks = <&ccu CLK_BU
1206 <&ccu CLK_CS
1207 <&ccu CLK_DR
1208 clock-names = "bus",
1209 resets = <&ccu RST_BU
1210 pinctrl-names = "defa
1211 pinctrl-0 = <&csi_pin
1212 status = "disabled";
1213 };
1214
1215 dsi: dsi@1ca0000 {
1216 compatible = "allwinn
1217 reg = <0x01ca0000 0x1
1218 interrupts = <GIC_SPI
1219 clocks = <&ccu CLK_BU
1220 resets = <&ccu RST_BU
1221 phys = <&dphy>;
1222 phy-names = "dphy";
1223 status = "disabled";
1224 #address-cells = <1>;
1225 #size-cells = <0>;
1226
1227 port {
1228 dsi_in_tcon0:
1229 remot
1230 };
1231 };
1232 };
1233
1234 dphy: d-phy@1ca1000 {
1235 compatible = "allwinn
1236 "allwinn
1237 reg = <0x01ca1000 0x1
1238 interrupts = <GIC_SPI
1239 clocks = <&ccu CLK_BU
1240 <&ccu CLK_DS
1241 clock-names = "bus",
1242 resets = <&ccu RST_BU
1243 status = "disabled";
1244 #phy-cells = <0>;
1245 };
1246
1247 deinterlace: deinterlace@1e00
1248 compatible = "allwinn
1249 "allwinn
1250 reg = <0x01e00000 0x2
1251 clocks = <&ccu CLK_BU
1252 <&ccu CLK_DE
1253 <&ccu CLK_DR
1254 clock-names = "bus",
1255 resets = <&ccu RST_BU
1256 interrupts = <GIC_SPI
1257 interconnects = <&mbu
1258 interconnect-names =
1259 };
1260
1261 hdmi: hdmi@1ee0000 {
1262 compatible = "allwinn
1263 "allwinn
1264 reg = <0x01ee0000 0x1
1265 reg-io-width = <1>;
1266 interrupts = <GIC_SPI
1267 clocks = <&ccu CLK_BU
1268 <&ccu CLK_HD
1269 clock-names = "iahb",
1270 resets = <&ccu RST_BU
1271 reset-names = "ctrl";
1272 phys = <&hdmi_phy>;
1273 phy-names = "phy";
1274 status = "disabled";
1275
1276 ports {
1277 #address-cell
1278 #size-cells =
1279
1280 hdmi_in: port
1281 reg =
1282
1283 hdmi_
1284
1285 };
1286 };
1287
1288 hdmi_out: por
1289 reg =
1290 };
1291 };
1292 };
1293
1294 hdmi_phy: hdmi-phy@1ef0000 {
1295 compatible = "allwinn
1296 reg = <0x01ef0000 0x1
1297 clocks = <&ccu CLK_BU
1298 <&ccu CLK_PL
1299 clock-names = "bus",
1300 resets = <&ccu RST_BU
1301 reset-names = "phy";
1302 #phy-cells = <0>;
1303 };
1304
1305 rtc: rtc@1f00000 {
1306 compatible = "allwinn
1307 "allwinn
1308 reg = <0x01f00000 0x4
1309 interrupt-parent = <&
1310 interrupts = <GIC_SPI
1311 <GIC_SPI
1312 clock-output-names =
1313 clocks = <&osc32k>;
1314 #clock-cells = <1>;
1315 };
1316
1317 r_intc: interrupt-controller@
1318 compatible = "allwinn
1319 "allwinn
1320 interrupt-controller;
1321 #interrupt-cells = <3
1322 reg = <0x01f00c00 0x4
1323 interrupts = <GIC_SPI
1324 };
1325
1326 r_ccu: clock@1f01400 {
1327 compatible = "allwinn
1328 reg = <0x01f01400 0x1
1329 clocks = <&osc24M>, <
1330 <&ccu CLK_PL
1331 clock-names = "hosc",
1332 #clock-cells = <1>;
1333 #reset-cells = <1>;
1334 };
1335
1336 codec_analog: codec-analog@1f
1337 compatible = "allwinn
1338 reg = <0x01f015c0 0x4
1339 status = "disabled";
1340 };
1341
1342 r_i2c: i2c@1f02400 {
1343 compatible = "allwinn
1344 "allwinn
1345 reg = <0x01f02400 0x4
1346 interrupts = <GIC_SPI
1347 clocks = <&r_ccu CLK_
1348 resets = <&r_ccu RST_
1349 status = "disabled";
1350 #address-cells = <1>;
1351 #size-cells = <0>;
1352 };
1353
1354 r_ir: ir@1f02000 {
1355 compatible = "allwinn
1356 "allwinn
1357 reg = <0x01f02000 0x4
1358 clocks = <&r_ccu CLK_
1359 clock-names = "apb",
1360 resets = <&r_ccu RST_
1361 interrupts = <GIC_SPI
1362 pinctrl-names = "defa
1363 pinctrl-0 = <&r_ir_rx
1364 status = "disabled";
1365 };
1366
1367 r_pwm: pwm@1f03800 {
1368 compatible = "allwinn
1369 "allwinn
1370 reg = <0x01f03800 0x4
1371 clocks = <&osc24M>;
1372 pinctrl-names = "defa
1373 pinctrl-0 = <&r_pwm_p
1374 #pwm-cells = <3>;
1375 status = "disabled";
1376 };
1377
1378 r_pio: pinctrl@1f02c00 {
1379 compatible = "allwinn
1380 reg = <0x01f02c00 0x4
1381 interrupt-parent = <&
1382 interrupts = <GIC_SPI
1383 clocks = <&r_ccu CLK_
1384 clock-names = "apb",
1385 gpio-controller;
1386 #gpio-cells = <3>;
1387 interrupt-controller;
1388 #interrupt-cells = <3
1389
1390 r_i2c_pl89_pins: r-i2
1391 pins = "PL8",
1392 function = "s
1393 };
1394
1395 r_ir_rx_pin: r-ir-rx-
1396 pins = "PL11"
1397 function = "s
1398 };
1399
1400 r_pwm_pin: r-pwm-pin
1401 pins = "PL10"
1402 function = "s
1403 };
1404
1405 r_rsb_pins: r-rsb-pin
1406 pins = "PL0",
1407 function = "s
1408 };
1409 };
1410
1411 r_rsb: rsb@1f03400 {
1412 compatible = "allwinn
1413 reg = <0x01f03400 0x4
1414 interrupts = <GIC_SPI
1415 clocks = <&r_ccu 6>;
1416 clock-frequency = <30
1417 resets = <&r_ccu 2>;
1418 pinctrl-names = "defa
1419 pinctrl-0 = <&r_rsb_p
1420 status = "disabled";
1421 #address-cells = <1>;
1422 #size-cells = <0>;
1423 };
1424 };
1425 };
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