1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) !! 1 /*
2 // Copyright (C) 2016 ARM Ltd. !! 2 * Copyright (C) 2016 ARM Ltd.
3 // based on the Allwinner H3 dtsi: !! 3 * based on the Allwinner H3 dtsi:
4 // Copyright (C) 2015 Jens Kuske <jenskuske@ !! 4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
>> 5 *
>> 6 * This file is dual-licensed: you can use it either under the terms
>> 7 * of the GPL or the X11 license, at your option. Note that this dual
>> 8 * licensing only applies to this file, and not this project as a
>> 9 * whole.
>> 10 *
>> 11 * a) This file is free software; you can redistribute it and/or
>> 12 * modify it under the terms of the GNU General Public License as
>> 13 * published by the Free Software Foundation; either version 2 of the
>> 14 * License, or (at your option) any later version.
>> 15 *
>> 16 * This file is distributed in the hope that it will be useful,
>> 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 19 * GNU General Public License for more details.
>> 20 *
>> 21 * Or, alternatively,
>> 22 *
>> 23 * b) Permission is hereby granted, free of charge, to any person
>> 24 * obtaining a copy of this software and associated documentation
>> 25 * files (the "Software"), to deal in the Software without
>> 26 * restriction, including without limitation the rights to use,
>> 27 * copy, modify, merge, publish, distribute, sublicense, and/or
>> 28 * sell copies of the Software, and to permit persons to whom the
>> 29 * Software is furnished to do so, subject to the following
>> 30 * conditions:
>> 31 *
>> 32 * The above copyright notice and this permission notice shall be
>> 33 * included in all copies or substantial portions of the Software.
>> 34 *
>> 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> 42 * OTHER DEALINGS IN THE SOFTWARE.
>> 43 */
5 44
6 #include <dt-bindings/clock/sun50i-a64-ccu.h> 45 #include <dt-bindings/clock/sun50i-a64-ccu.h>
7 #include <dt-bindings/clock/sun6i-rtc.h> <<
8 #include <dt-bindings/clock/sun8i-de2.h> 46 #include <dt-bindings/clock/sun8i-de2.h>
9 #include <dt-bindings/clock/sun8i-r-ccu.h> 47 #include <dt-bindings/clock/sun8i-r-ccu.h>
10 #include <dt-bindings/interrupt-controller/arm 48 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/sun50i-a64-ccu.h> 49 #include <dt-bindings/reset/sun50i-a64-ccu.h>
12 #include <dt-bindings/reset/sun8i-de2.h> 50 #include <dt-bindings/reset/sun8i-de2.h>
13 #include <dt-bindings/reset/sun8i-r-ccu.h> 51 #include <dt-bindings/reset/sun8i-r-ccu.h>
14 #include <dt-bindings/thermal/thermal.h> <<
15 52
16 / { 53 / {
17 interrupt-parent = <&gic>; 54 interrupt-parent = <&gic>;
18 #address-cells = <1>; 55 #address-cells = <1>;
19 #size-cells = <1>; 56 #size-cells = <1>;
20 57
21 chosen { 58 chosen {
22 #address-cells = <1>; 59 #address-cells = <1>;
23 #size-cells = <1>; 60 #size-cells = <1>;
24 ranges; 61 ranges;
25 62
26 simplefb_lcd: framebuffer-lcd 63 simplefb_lcd: framebuffer-lcd {
27 compatible = "allwinne 64 compatible = "allwinner,simple-framebuffer",
28 "simple-f 65 "simple-framebuffer";
29 allwinner,pipeline = " 66 allwinner,pipeline = "mixer0-lcd0";
30 clocks = <&ccu CLK_TCO 67 clocks = <&ccu CLK_TCON0>,
31 <&display_clo 68 <&display_clocks CLK_MIXER0>;
32 status = "disabled"; 69 status = "disabled";
33 }; 70 };
34 71
35 simplefb_hdmi: framebuffer-hdm 72 simplefb_hdmi: framebuffer-hdmi {
36 compatible = "allwinne 73 compatible = "allwinner,simple-framebuffer",
37 "simple-f 74 "simple-framebuffer";
38 allwinner,pipeline = " 75 allwinner,pipeline = "mixer1-lcd1-hdmi";
39 clocks = <&display_clo 76 clocks = <&display_clocks CLK_MIXER1>,
40 <&ccu CLK_TCO 77 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
41 status = "disabled"; 78 status = "disabled";
42 }; 79 };
43 }; 80 };
44 81
45 cpus { 82 cpus {
46 #address-cells = <1>; 83 #address-cells = <1>;
47 #size-cells = <0>; 84 #size-cells = <0>;
48 85
49 cpu0: cpu@0 { 86 cpu0: cpu@0 {
50 compatible = "arm,cort !! 87 compatible = "arm,cortex-a53", "arm,armv8";
51 device_type = "cpu"; 88 device_type = "cpu";
52 reg = <0>; 89 reg = <0>;
53 enable-method = "psci" 90 enable-method = "psci";
54 clocks = <&ccu CLK_CPU <<
55 clock-names = "cpu"; <<
56 #cooling-cells = <2>; <<
57 i-cache-size = <0x8000 <<
58 i-cache-line-size = <6 <<
59 i-cache-sets = <256>; <<
60 d-cache-size = <0x8000 <<
61 d-cache-line-size = <6 <<
62 d-cache-sets = <128>; <<
63 next-level-cache = <&l <<
64 }; 91 };
65 92
66 cpu1: cpu@1 { 93 cpu1: cpu@1 {
67 compatible = "arm,cort !! 94 compatible = "arm,cortex-a53", "arm,armv8";
68 device_type = "cpu"; 95 device_type = "cpu";
69 reg = <1>; 96 reg = <1>;
70 enable-method = "psci" 97 enable-method = "psci";
71 clocks = <&ccu CLK_CPU <<
72 clock-names = "cpu"; <<
73 #cooling-cells = <2>; <<
74 i-cache-size = <0x8000 <<
75 i-cache-line-size = <6 <<
76 i-cache-sets = <256>; <<
77 d-cache-size = <0x8000 <<
78 d-cache-line-size = <6 <<
79 d-cache-sets = <128>; <<
80 next-level-cache = <&l <<
81 }; 98 };
82 99
83 cpu2: cpu@2 { 100 cpu2: cpu@2 {
84 compatible = "arm,cort !! 101 compatible = "arm,cortex-a53", "arm,armv8";
85 device_type = "cpu"; 102 device_type = "cpu";
86 reg = <2>; 103 reg = <2>;
87 enable-method = "psci" 104 enable-method = "psci";
88 clocks = <&ccu CLK_CPU <<
89 clock-names = "cpu"; <<
90 #cooling-cells = <2>; <<
91 i-cache-size = <0x8000 <<
92 i-cache-line-size = <6 <<
93 i-cache-sets = <256>; <<
94 d-cache-size = <0x8000 <<
95 d-cache-line-size = <6 <<
96 d-cache-sets = <128>; <<
97 next-level-cache = <&l <<
98 }; 105 };
99 106
100 cpu3: cpu@3 { 107 cpu3: cpu@3 {
101 compatible = "arm,cort !! 108 compatible = "arm,cortex-a53", "arm,armv8";
102 device_type = "cpu"; 109 device_type = "cpu";
103 reg = <3>; 110 reg = <3>;
104 enable-method = "psci" 111 enable-method = "psci";
105 clocks = <&ccu CLK_CPU <<
106 clock-names = "cpu"; <<
107 #cooling-cells = <2>; <<
108 i-cache-size = <0x8000 <<
109 i-cache-line-size = <6 <<
110 i-cache-sets = <256>; <<
111 d-cache-size = <0x8000 <<
112 d-cache-line-size = <6 <<
113 d-cache-sets = <128>; <<
114 next-level-cache = <&l <<
115 }; <<
116 <<
117 l2_cache: l2-cache { <<
118 compatible = "cache"; <<
119 cache-level = <2>; <<
120 cache-unified; <<
121 cache-size = <0x80000> <<
122 cache-line-size = <64> <<
123 cache-sets = <512>; <<
124 }; 112 };
125 }; 113 };
126 114
127 de: display-engine { !! 115 osc24M: osc24M_clk {
128 compatible = "allwinner,sun50i <<
129 allwinner,pipelines = <&mixer0 <<
130 <&mixer1 <<
131 status = "disabled"; <<
132 }; <<
133 <<
134 gpu_opp_table: opp-table-gpu { <<
135 compatible = "operating-points <<
136 <<
137 opp-432000000 { <<
138 opp-hz = /bits/ 64 <43 <<
139 }; <<
140 }; <<
141 <<
142 osc24M: osc24M-clk { <<
143 #clock-cells = <0>; 116 #clock-cells = <0>;
144 compatible = "fixed-clock"; 117 compatible = "fixed-clock";
145 clock-frequency = <24000000>; 118 clock-frequency = <24000000>;
146 clock-output-names = "osc24M"; 119 clock-output-names = "osc24M";
147 }; 120 };
148 121
149 osc32k: osc32k-clk { !! 122 osc32k: osc32k_clk {
150 #clock-cells = <0>; 123 #clock-cells = <0>;
151 compatible = "fixed-clock"; 124 compatible = "fixed-clock";
152 clock-frequency = <32768>; 125 clock-frequency = <32768>;
153 clock-output-names = "ext-osc3 !! 126 clock-output-names = "osc32k";
154 }; 127 };
155 128
156 pmu { !! 129 iosc: internal-osc-clk {
157 compatible = "arm,cortex-a53-p !! 130 #clock-cells = <0>;
158 interrupts = <GIC_SPI 116 IRQ_ !! 131 compatible = "fixed-clock";
159 <GIC_SPI 117 IRQ_ !! 132 clock-frequency = <16000000>;
160 <GIC_SPI 118 IRQ_ !! 133 clock-accuracy = <300000000>;
161 <GIC_SPI 119 IRQ_ !! 134 clock-output-names = "iosc";
162 interrupt-affinity = <&cpu0>, <<
163 }; 135 };
164 136
165 psci { 137 psci {
166 compatible = "arm,psci-0.2"; 138 compatible = "arm,psci-0.2";
167 method = "smc"; 139 method = "smc";
168 }; 140 };
169 141
170 sound: sound { !! 142 sound_spdif {
171 #address-cells = <1>; <<
172 #size-cells = <0>; <<
173 compatible = "simple-audio-car 143 compatible = "simple-audio-card";
174 simple-audio-card,name = "sun5 !! 144 simple-audio-card,name = "On-board SPDIF";
175 simple-audio-card,aux-devs = < <<
176 simple-audio-card,routing = <<
177 "Left DAC", "D <<
178 "Right DAC", " <<
179 "ADCL", "Left <<
180 "ADCR", "Right <<
181 status = "disabled"; <<
182 <<
183 simple-audio-card,dai-link@0 { <<
184 format = "i2s"; <<
185 frame-master = <&link0 <<
186 bitclock-master = <&li <<
187 mclk-fs = <128>; <<
188 145
189 link0_cpu: cpu { !! 146 simple-audio-card,cpu {
190 sound-dai = <& !! 147 sound-dai = <&spdif>;
191 }; !! 148 };
192 149
193 link0_codec: codec { !! 150 simple-audio-card,codec {
194 sound-dai = <& !! 151 sound-dai = <&spdif_out>;
195 }; <<
196 }; 152 };
197 }; 153 };
198 154
>> 155 spdif_out: spdif-out {
>> 156 #sound-dai-cells = <0>;
>> 157 compatible = "linux,spdif-dit";
>> 158 };
>> 159
199 timer { 160 timer {
200 compatible = "arm,armv8-timer" 161 compatible = "arm,armv8-timer";
201 allwinner,erratum-unknown1; <<
202 arm,no-tick-in-suspend; <<
203 interrupts = <GIC_PPI 13 162 interrupts = <GIC_PPI 13
204 (GIC_CPU_MASK_SIMPLE(4 163 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
205 <GIC_PPI 14 164 <GIC_PPI 14
206 (GIC_CPU_MASK_SIMPLE(4 165 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
207 <GIC_PPI 11 166 <GIC_PPI 11
208 (GIC_CPU_MASK_SIMPLE(4 167 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
209 <GIC_PPI 10 168 <GIC_PPI 10
210 (GIC_CPU_MASK_SIMPLE(4 169 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
211 }; 170 };
212 171
213 thermal-zones { <<
214 cpu_thermal: cpu0-thermal { <<
215 /* milliseconds */ <<
216 polling-delay-passive <<
217 polling-delay = <0>; <<
218 thermal-sensors = <&th <<
219 <<
220 cooling-maps { <<
221 map0 { <<
222 trip = <<
223 coolin <<
224 <<
225 <<
226 <<
227 }; <<
228 map1 { <<
229 trip = <<
230 coolin <<
231 <<
232 <<
233 <<
234 }; <<
235 }; <<
236 <<
237 trips { <<
238 cpu_alert0: cp <<
239 /* mil <<
240 temper <<
241 hyster <<
242 type = <<
243 }; <<
244 <<
245 cpu_alert1: cp <<
246 /* mil <<
247 temper <<
248 hyster <<
249 type = <<
250 }; <<
251 <<
252 cpu_crit: cpu- <<
253 /* mil <<
254 temper <<
255 hyster <<
256 type = <<
257 }; <<
258 }; <<
259 }; <<
260 <<
261 gpu0_thermal: gpu0-thermal { <<
262 /* milliseconds */ <<
263 polling-delay-passive <<
264 polling-delay = <0>; <<
265 thermal-sensors = <&th <<
266 <<
267 trips { <<
268 gpu0_crit: gpu <<
269 temper <<
270 hyster <<
271 type = <<
272 }; <<
273 }; <<
274 }; <<
275 <<
276 gpu1_thermal: gpu1-thermal { <<
277 /* milliseconds */ <<
278 polling-delay-passive <<
279 polling-delay = <0>; <<
280 thermal-sensors = <&th <<
281 <<
282 trips { <<
283 gpu1_crit: gpu <<
284 temper <<
285 hyster <<
286 type = <<
287 }; <<
288 }; <<
289 }; <<
290 }; <<
291 <<
292 soc { 172 soc {
293 compatible = "simple-bus"; 173 compatible = "simple-bus";
294 #address-cells = <1>; 174 #address-cells = <1>;
295 #size-cells = <1>; 175 #size-cells = <1>;
296 ranges; 176 ranges;
297 177
298 bus@1000000 { !! 178 de2@1000000 {
299 compatible = "allwinne 179 compatible = "allwinner,sun50i-a64-de2";
300 reg = <0x1000000 0x400 180 reg = <0x1000000 0x400000>;
301 allwinner,sram = <&de2 181 allwinner,sram = <&de2_sram 1>;
302 #address-cells = <1>; 182 #address-cells = <1>;
303 #size-cells = <1>; 183 #size-cells = <1>;
304 ranges = <0 0x1000000 184 ranges = <0 0x1000000 0x400000>;
305 185
306 display_clocks: clock@ 186 display_clocks: clock@0 {
307 compatible = " 187 compatible = "allwinner,sun50i-a64-de2-clk";
308 reg = <0x0 0x1 !! 188 reg = <0x0 0x100000>;
309 clocks = <&ccu !! 189 clocks = <&ccu CLK_DE>,
310 <&ccu !! 190 <&ccu CLK_BUS_DE>;
311 clock-names = !! 191 clock-names = "mod",
312 !! 192 "bus";
313 resets = <&ccu 193 resets = <&ccu RST_BUS_DE>;
314 #clock-cells = 194 #clock-cells = <1>;
315 #reset-cells = 195 #reset-cells = <1>;
316 }; 196 };
317 <<
318 rotate: rotate@20000 { <<
319 compatible = " <<
320 " <<
321 reg = <0x20000 <<
322 interrupts = < <<
323 clocks = <&dis <<
324 <&dis <<
325 clock-names = <<
326 <<
327 resets = <&dis <<
328 }; <<
329 <<
330 mixer0: mixer@100000 { <<
331 compatible = " <<
332 reg = <0x10000 <<
333 clocks = <&dis <<
334 <&dis <<
335 clock-names = <<
336 <<
337 resets = <&dis <<
338 <<
339 ports { <<
340 #addre <<
341 #size- <<
342 <<
343 mixer0 <<
344 <<
345 <<
346 <<
347 <<
348 <<
349 <<
350 <<
351 <<
352 <<
353 <<
354 <<
355 <<
356 <<
357 }; <<
358 }; <<
359 }; <<
360 <<
361 mixer1: mixer@200000 { <<
362 compatible = " <<
363 reg = <0x20000 <<
364 clocks = <&dis <<
365 <&dis <<
366 clock-names = <<
367 <<
368 resets = <&dis <<
369 <<
370 ports { <<
371 #addre <<
372 #size- <<
373 <<
374 mixer1 <<
375 <<
376 <<
377 <<
378 <<
379 <<
380 <<
381 <<
382 <<
383 <<
384 <<
385 <<
386 <<
387 <<
388 }; <<
389 }; <<
390 }; <<
391 }; 197 };
392 198
393 syscon: syscon@1c00000 { 199 syscon: syscon@1c00000 {
394 compatible = "allwinne 200 compatible = "allwinner,sun50i-a64-system-control";
395 reg = <0x01c00000 0x10 201 reg = <0x01c00000 0x1000>;
396 #address-cells = <1>; 202 #address-cells = <1>;
397 #size-cells = <1>; 203 #size-cells = <1>;
398 ranges; 204 ranges;
399 205
400 sram_c: sram@18000 { 206 sram_c: sram@18000 {
401 compatible = " 207 compatible = "mmio-sram";
402 reg = <0x00018 208 reg = <0x00018000 0x28000>;
403 #address-cells 209 #address-cells = <1>;
404 #size-cells = 210 #size-cells = <1>;
405 ranges = <0 0x 211 ranges = <0 0x00018000 0x28000>;
406 212
407 de2_sram: sram 213 de2_sram: sram-section@0 {
408 compat 214 compatible = "allwinner,sun50i-a64-sram-c";
409 reg = 215 reg = <0x0000 0x28000>;
410 }; 216 };
411 }; 217 };
412 <<
413 sram_c1: sram@1d00000 <<
414 compatible = " <<
415 reg = <0x01d00 <<
416 #address-cells <<
417 #size-cells = <<
418 ranges = <0 0x <<
419 <<
420 ve_sram: sram- <<
421 compat <<
422 <<
423 reg = <<
424 }; <<
425 }; <<
426 }; 218 };
427 219
428 dma: dma-controller@1c02000 { 220 dma: dma-controller@1c02000 {
429 compatible = "allwinne 221 compatible = "allwinner,sun50i-a64-dma";
430 reg = <0x01c02000 0x10 222 reg = <0x01c02000 0x1000>;
431 interrupts = <GIC_SPI 223 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&ccu CLK_BUS 224 clocks = <&ccu CLK_BUS_DMA>;
433 dma-channels = <8>; 225 dma-channels = <8>;
434 dma-requests = <27>; 226 dma-requests = <27>;
435 resets = <&ccu RST_BUS 227 resets = <&ccu RST_BUS_DMA>;
436 #dma-cells = <1>; 228 #dma-cells = <1>;
437 }; 229 };
438 230
439 tcon0: lcd-controller@1c0c000 <<
440 compatible = "allwinne <<
441 "allwinne <<
442 reg = <0x01c0c000 0x10 <<
443 interrupts = <GIC_SPI <<
444 clocks = <&ccu CLK_BUS <<
445 clock-names = "ahb", " <<
446 clock-output-names = " <<
447 #clock-cells = <0>; <<
448 resets = <&ccu RST_BUS <<
449 reset-names = "lcd", " <<
450 <<
451 ports { <<
452 #address-cells <<
453 #size-cells = <<
454 <<
455 tcon0_in: port <<
456 #addre <<
457 #size- <<
458 reg = <<
459 <<
460 tcon0_ <<
461 <<
462 <<
463 }; <<
464 <<
465 tcon0_ <<
466 <<
467 <<
468 }; <<
469 }; <<
470 <<
471 tcon0_out: por <<
472 #addre <<
473 #size- <<
474 reg = <<
475 <<
476 tcon0_ <<
477 <<
478 <<
479 <<
480 }; <<
481 }; <<
482 }; <<
483 }; <<
484 <<
485 tcon1: lcd-controller@1c0d000 <<
486 compatible = "allwinne <<
487 "allwinne <<
488 reg = <0x01c0d000 0x10 <<
489 interrupts = <GIC_SPI <<
490 clocks = <&ccu CLK_BUS <<
491 clock-names = "ahb", " <<
492 resets = <&ccu RST_BUS <<
493 reset-names = "lcd"; <<
494 <<
495 ports { <<
496 #address-cells <<
497 #size-cells = <<
498 <<
499 tcon1_in: port <<
500 #addre <<
501 #size- <<
502 reg = <<
503 <<
504 tcon1_ <<
505 <<
506 <<
507 }; <<
508 <<
509 tcon1_ <<
510 <<
511 <<
512 }; <<
513 }; <<
514 <<
515 tcon1_out: por <<
516 #addre <<
517 #size- <<
518 reg = <<
519 <<
520 tcon1_ <<
521 <<
522 <<
523 }; <<
524 }; <<
525 }; <<
526 }; <<
527 <<
528 video-codec@1c0e000 { <<
529 compatible = "allwinne <<
530 reg = <0x01c0e000 0x10 <<
531 clocks = <&ccu CLK_BUS <<
532 <&ccu CLK_DRA <<
533 clock-names = "ahb", " <<
534 resets = <&ccu RST_BUS <<
535 interrupts = <GIC_SPI <<
536 allwinner,sram = <&ve_ <<
537 }; <<
538 <<
539 mmc0: mmc@1c0f000 { 231 mmc0: mmc@1c0f000 {
540 compatible = "allwinne 232 compatible = "allwinner,sun50i-a64-mmc";
541 reg = <0x01c0f000 0x10 233 reg = <0x01c0f000 0x1000>;
542 clocks = <&ccu CLK_BUS 234 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
543 clock-names = "ahb", " 235 clock-names = "ahb", "mmc";
544 resets = <&ccu RST_BUS 236 resets = <&ccu RST_BUS_MMC0>;
545 reset-names = "ahb"; 237 reset-names = "ahb";
546 interrupts = <GIC_SPI 238 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
547 max-frequency = <15000 239 max-frequency = <150000000>;
548 status = "disabled"; 240 status = "disabled";
549 #address-cells = <1>; 241 #address-cells = <1>;
550 #size-cells = <0>; 242 #size-cells = <0>;
551 }; 243 };
552 244
553 mmc1: mmc@1c10000 { 245 mmc1: mmc@1c10000 {
554 compatible = "allwinne 246 compatible = "allwinner,sun50i-a64-mmc";
555 reg = <0x01c10000 0x10 247 reg = <0x01c10000 0x1000>;
556 clocks = <&ccu CLK_BUS 248 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
557 clock-names = "ahb", " 249 clock-names = "ahb", "mmc";
558 resets = <&ccu RST_BUS 250 resets = <&ccu RST_BUS_MMC1>;
559 reset-names = "ahb"; 251 reset-names = "ahb";
560 interrupts = <GIC_SPI 252 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
561 max-frequency = <15000 253 max-frequency = <150000000>;
562 status = "disabled"; 254 status = "disabled";
563 #address-cells = <1>; 255 #address-cells = <1>;
564 #size-cells = <0>; 256 #size-cells = <0>;
565 }; 257 };
566 258
567 mmc2: mmc@1c11000 { 259 mmc2: mmc@1c11000 {
568 compatible = "allwinne 260 compatible = "allwinner,sun50i-a64-emmc";
569 reg = <0x01c11000 0x10 261 reg = <0x01c11000 0x1000>;
570 clocks = <&ccu CLK_BUS 262 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
571 clock-names = "ahb", " 263 clock-names = "ahb", "mmc";
572 resets = <&ccu RST_BUS 264 resets = <&ccu RST_BUS_MMC2>;
573 reset-names = "ahb"; 265 reset-names = "ahb";
574 interrupts = <GIC_SPI 266 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
575 max-frequency = <15000 267 max-frequency = <150000000>;
576 status = "disabled"; 268 status = "disabled";
577 #address-cells = <1>; 269 #address-cells = <1>;
578 #size-cells = <0>; 270 #size-cells = <0>;
579 }; 271 };
580 272
581 sid: eeprom@1c14000 { <<
582 compatible = "allwinne <<
583 reg = <0x1c14000 0x400 <<
584 #address-cells = <1>; <<
585 #size-cells = <1>; <<
586 <<
587 ths_calibration: therm <<
588 reg = <0x34 0x <<
589 }; <<
590 }; <<
591 <<
592 crypto: crypto@1c15000 { <<
593 compatible = "allwinne <<
594 reg = <0x01c15000 0x10 <<
595 interrupts = <GIC_SPI <<
596 clocks = <&ccu CLK_BUS <<
597 clock-names = "bus", " <<
598 resets = <&ccu RST_BUS <<
599 }; <<
600 <<
601 msgbox: mailbox@1c17000 { <<
602 compatible = "allwinne <<
603 "allwinne <<
604 reg = <0x01c17000 0x10 <<
605 clocks = <&ccu CLK_BUS <<
606 resets = <&ccu RST_BUS <<
607 interrupts = <GIC_SPI <<
608 #mbox-cells = <1>; <<
609 }; <<
610 <<
611 usb_otg: usb@1c19000 { 273 usb_otg: usb@1c19000 {
612 compatible = "allwinne 274 compatible = "allwinner,sun8i-a33-musb";
613 reg = <0x01c19000 0x04 275 reg = <0x01c19000 0x0400>;
614 clocks = <&ccu CLK_BUS 276 clocks = <&ccu CLK_BUS_OTG>;
615 resets = <&ccu RST_BUS 277 resets = <&ccu RST_BUS_OTG>;
616 interrupts = <GIC_SPI 278 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
617 interrupt-names = "mc" 279 interrupt-names = "mc";
618 phys = <&usbphy 0>; 280 phys = <&usbphy 0>;
619 phy-names = "usb"; 281 phy-names = "usb";
620 extcon = <&usbphy 0>; 282 extcon = <&usbphy 0>;
621 dr_mode = "otg"; <<
622 status = "disabled"; 283 status = "disabled";
623 }; 284 };
624 285
625 usbphy: phy@1c19400 { 286 usbphy: phy@1c19400 {
626 compatible = "allwinne 287 compatible = "allwinner,sun50i-a64-usb-phy";
627 reg = <0x01c19400 0x14 288 reg = <0x01c19400 0x14>,
628 <0x01c1a800 0x4> 289 <0x01c1a800 0x4>,
629 <0x01c1b800 0x4> 290 <0x01c1b800 0x4>;
630 reg-names = "phy_ctrl" 291 reg-names = "phy_ctrl",
631 "pmu0", 292 "pmu0",
632 "pmu1"; 293 "pmu1";
633 clocks = <&ccu CLK_USB 294 clocks = <&ccu CLK_USB_PHY0>,
634 <&ccu CLK_USB 295 <&ccu CLK_USB_PHY1>;
635 clock-names = "usb0_ph 296 clock-names = "usb0_phy",
636 "usb1_ph 297 "usb1_phy";
637 resets = <&ccu RST_USB 298 resets = <&ccu RST_USB_PHY0>,
638 <&ccu RST_USB 299 <&ccu RST_USB_PHY1>;
639 reset-names = "usb0_re 300 reset-names = "usb0_reset",
640 "usb1_re 301 "usb1_reset";
641 status = "disabled"; 302 status = "disabled";
642 #phy-cells = <1>; 303 #phy-cells = <1>;
643 }; 304 };
644 305
645 ehci0: usb@1c1a000 { 306 ehci0: usb@1c1a000 {
646 compatible = "allwinne 307 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
647 reg = <0x01c1a000 0x10 308 reg = <0x01c1a000 0x100>;
648 interrupts = <GIC_SPI 309 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
649 clocks = <&ccu CLK_BUS 310 clocks = <&ccu CLK_BUS_OHCI0>,
650 <&ccu CLK_BUS 311 <&ccu CLK_BUS_EHCI0>,
651 <&ccu CLK_USB 312 <&ccu CLK_USB_OHCI0>;
652 resets = <&ccu RST_BUS 313 resets = <&ccu RST_BUS_OHCI0>,
653 <&ccu RST_BUS 314 <&ccu RST_BUS_EHCI0>;
654 phys = <&usbphy 0>; 315 phys = <&usbphy 0>;
655 phy-names = "usb"; 316 phy-names = "usb";
656 status = "disabled"; 317 status = "disabled";
657 }; 318 };
658 319
659 ohci0: usb@1c1a400 { 320 ohci0: usb@1c1a400 {
660 compatible = "allwinne 321 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
661 reg = <0x01c1a400 0x10 322 reg = <0x01c1a400 0x100>;
662 interrupts = <GIC_SPI 323 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
663 clocks = <&ccu CLK_BUS 324 clocks = <&ccu CLK_BUS_OHCI0>,
664 <&ccu CLK_USB 325 <&ccu CLK_USB_OHCI0>;
665 resets = <&ccu RST_BUS 326 resets = <&ccu RST_BUS_OHCI0>;
666 phys = <&usbphy 0>; 327 phys = <&usbphy 0>;
667 phy-names = "usb"; 328 phy-names = "usb";
668 status = "disabled"; 329 status = "disabled";
669 }; 330 };
670 331
671 ehci1: usb@1c1b000 { 332 ehci1: usb@1c1b000 {
672 compatible = "allwinne 333 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
673 reg = <0x01c1b000 0x10 334 reg = <0x01c1b000 0x100>;
674 interrupts = <GIC_SPI 335 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
675 clocks = <&ccu CLK_BUS 336 clocks = <&ccu CLK_BUS_OHCI1>,
676 <&ccu CLK_BUS 337 <&ccu CLK_BUS_EHCI1>,
677 <&ccu CLK_USB 338 <&ccu CLK_USB_OHCI1>;
678 resets = <&ccu RST_BUS 339 resets = <&ccu RST_BUS_OHCI1>,
679 <&ccu RST_BUS 340 <&ccu RST_BUS_EHCI1>;
680 phys = <&usbphy 1>; 341 phys = <&usbphy 1>;
681 phy-names = "usb"; 342 phy-names = "usb";
682 status = "disabled"; 343 status = "disabled";
683 }; 344 };
684 345
685 ohci1: usb@1c1b400 { 346 ohci1: usb@1c1b400 {
686 compatible = "allwinne 347 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
687 reg = <0x01c1b400 0x10 348 reg = <0x01c1b400 0x100>;
688 interrupts = <GIC_SPI 349 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
689 clocks = <&ccu CLK_BUS 350 clocks = <&ccu CLK_BUS_OHCI1>,
690 <&ccu CLK_USB 351 <&ccu CLK_USB_OHCI1>;
691 resets = <&ccu RST_BUS 352 resets = <&ccu RST_BUS_OHCI1>;
692 phys = <&usbphy 1>; 353 phys = <&usbphy 1>;
693 phy-names = "usb"; 354 phy-names = "usb";
694 status = "disabled"; 355 status = "disabled";
695 }; 356 };
696 357
697 ccu: clock@1c20000 { 358 ccu: clock@1c20000 {
698 compatible = "allwinne 359 compatible = "allwinner,sun50i-a64-ccu";
699 reg = <0x01c20000 0x40 360 reg = <0x01c20000 0x400>;
700 clocks = <&osc24M>, <& !! 361 clocks = <&osc24M>, <&osc32k>;
701 clock-names = "hosc", 362 clock-names = "hosc", "losc";
702 #clock-cells = <1>; 363 #clock-cells = <1>;
703 #reset-cells = <1>; 364 #reset-cells = <1>;
704 }; 365 };
705 366
706 pio: pinctrl@1c20800 { 367 pio: pinctrl@1c20800 {
707 compatible = "allwinne 368 compatible = "allwinner,sun50i-a64-pinctrl";
708 reg = <0x01c20800 0x40 369 reg = <0x01c20800 0x400>;
709 interrupt-parent = <&r <<
710 interrupts = <GIC_SPI 370 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
711 <GIC_SPI 371 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
712 <GIC_SPI 372 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&ccu CLK_BUS !! 373 clocks = <&ccu 58>, <&osc24M>, <&rtc 0>;
714 <&rtc CLK_OSC <<
715 clock-names = "apb", " 374 clock-names = "apb", "hosc", "losc";
716 gpio-controller; 375 gpio-controller;
717 #gpio-cells = <3>; 376 #gpio-cells = <3>;
718 interrupt-controller; 377 interrupt-controller;
719 #interrupt-cells = <3> 378 #interrupt-cells = <3>;
720 379
721 /omit-if-no-ref/ !! 380 i2c0_pins: i2c0_pins {
722 aif2_pins: aif2-pins { <<
723 pins = "PB4", <<
724 function = "ai <<
725 }; <<
726 <<
727 /omit-if-no-ref/ <<
728 aif3_pins: aif3-pins { <<
729 pins = "PG10", <<
730 function = "ai <<
731 }; <<
732 <<
733 csi_pins: csi-pins { <<
734 pins = "PE0", <<
735 "PE7", <<
736 function = "cs <<
737 }; <<
738 <<
739 /omit-if-no-ref/ <<
740 csi_mclk_pin: csi-mclk <<
741 pins = "PE1"; <<
742 function = "cs <<
743 }; <<
744 <<
745 i2c0_pins: i2c0-pins { <<
746 pins = "PH0", 381 pins = "PH0", "PH1";
747 function = "i2 382 function = "i2c0";
748 }; 383 };
749 384
750 i2c1_pins: i2c1-pins { !! 385 i2c1_pins: i2c1_pins {
751 pins = "PH2", 386 pins = "PH2", "PH3";
752 function = "i2 387 function = "i2c1";
753 }; 388 };
754 389
755 i2c2_pins: i2c2-pins { <<
756 pins = "PE14", <<
757 function = "i2 <<
758 }; <<
759 <<
760 /omit-if-no-ref/ <<
761 lcd_rgb666_pins: lcd-r <<
762 pins = "PD0", <<
763 "PD5", <<
764 "PD10", <<
765 "PD14", <<
766 "PD18", <<
767 function = "lc <<
768 }; <<
769 <<
770 mmc0_pins: mmc0-pins { 390 mmc0_pins: mmc0-pins {
771 pins = "PF0", 391 pins = "PF0", "PF1", "PF2", "PF3",
772 "PF4", 392 "PF4", "PF5";
773 function = "mm 393 function = "mmc0";
774 drive-strength 394 drive-strength = <30>;
775 bias-pull-up; 395 bias-pull-up;
776 }; 396 };
777 397
778 mmc1_pins: mmc1-pins { 398 mmc1_pins: mmc1-pins {
779 pins = "PG0", 399 pins = "PG0", "PG1", "PG2", "PG3",
780 "PG4", 400 "PG4", "PG5";
781 function = "mm 401 function = "mmc1";
782 drive-strength 402 drive-strength = <30>;
783 bias-pull-up; 403 bias-pull-up;
784 }; 404 };
785 405
786 mmc2_pins: mmc2-pins { 406 mmc2_pins: mmc2-pins {
787 pins = "PC5", !! 407 pins = "PC1", "PC5", "PC6", "PC8", "PC9",
788 "PC10", 408 "PC10","PC11", "PC12", "PC13",
789 "PC14", 409 "PC14", "PC15", "PC16";
790 function = "mm 410 function = "mmc2";
791 drive-strength 411 drive-strength = <30>;
792 bias-pull-up; 412 bias-pull-up;
793 }; 413 };
794 414
795 mmc2_ds_pin: mmc2-ds-p !! 415 pwm_pin: pwm_pin {
796 pins = "PC1"; <<
797 function = "mm <<
798 drive-strength <<
799 bias-pull-up; <<
800 }; <<
801 <<
802 pwm_pin: pwm-pin { <<
803 pins = "PD22"; 416 pins = "PD22";
804 function = "pw 417 function = "pwm";
805 }; 418 };
806 419
807 rmii_pins: rmii-pins { !! 420 rmii_pins: rmii_pins {
808 pins = "PD10", 421 pins = "PD10", "PD11", "PD13", "PD14", "PD17",
809 "PD18", 422 "PD18", "PD19", "PD20", "PD22", "PD23";
810 function = "em 423 function = "emac";
811 drive-strength 424 drive-strength = <40>;
812 }; 425 };
813 426
814 rgmii_pins: rgmii-pins !! 427 rgmii_pins: rgmii_pins {
815 pins = "PD8", 428 pins = "PD8", "PD9", "PD10", "PD11", "PD12",
816 "PD13", 429 "PD13", "PD15", "PD16", "PD17", "PD18",
817 "PD19", 430 "PD19", "PD20", "PD21", "PD22", "PD23";
818 function = "em 431 function = "emac";
819 drive-strength 432 drive-strength = <40>;
820 }; 433 };
821 434
822 spdif_tx_pin: spdif-tx !! 435 spdif_tx_pin: spdif {
823 pins = "PH8"; 436 pins = "PH8";
824 function = "sp 437 function = "spdif";
825 }; 438 };
826 439
827 spi0_pins: spi0-pins { !! 440 spi0_pins: spi0 {
828 pins = "PC0", 441 pins = "PC0", "PC1", "PC2", "PC3";
829 function = "sp 442 function = "spi0";
830 }; 443 };
831 444
832 spi1_pins: spi1-pins { !! 445 spi1_pins: spi1 {
833 pins = "PD0", 446 pins = "PD0", "PD1", "PD2", "PD3";
834 function = "sp 447 function = "spi1";
835 }; 448 };
836 449
837 uart0_pb_pins: uart0-p !! 450 uart0_pins_a: uart0 {
838 pins = "PB8", 451 pins = "PB8", "PB9";
839 function = "ua 452 function = "uart0";
840 }; 453 };
841 454
842 uart1_pins: uart1-pins !! 455 uart1_pins: uart1_pins {
843 pins = "PG6", 456 pins = "PG6", "PG7";
844 function = "ua 457 function = "uart1";
845 }; 458 };
846 459
847 uart1_rts_cts_pins: ua !! 460 uart1_rts_cts_pins: uart1_rts_cts_pins {
848 pins = "PG8", 461 pins = "PG8", "PG9";
849 function = "ua 462 function = "uart1";
850 }; 463 };
851 464
852 uart2_pins: uart2-pins 465 uart2_pins: uart2-pins {
853 pins = "PB0", 466 pins = "PB0", "PB1";
854 function = "ua 467 function = "uart2";
855 }; 468 };
856 469
857 uart3_pins: uart3-pins 470 uart3_pins: uart3-pins {
858 pins = "PD0", 471 pins = "PD0", "PD1";
859 function = "ua 472 function = "uart3";
860 }; 473 };
861 474
862 uart4_pins: uart4-pins 475 uart4_pins: uart4-pins {
863 pins = "PD2", 476 pins = "PD2", "PD3";
864 function = "ua 477 function = "uart4";
865 }; 478 };
866 479
867 uart4_rts_cts_pins: ua 480 uart4_rts_cts_pins: uart4-rts-cts-pins {
868 pins = "PD4", 481 pins = "PD4", "PD5";
869 function = "ua 482 function = "uart4";
870 }; 483 };
871 }; 484 };
872 485
873 timer@1c20c00 { <<
874 compatible = "allwinne <<
875 "allwinne <<
876 reg = <0x01c20c00 0xa0 <<
877 interrupts = <GIC_SPI <<
878 <GIC_SPI <<
879 clocks = <&osc24M>; <<
880 }; <<
881 <<
882 wdt0: watchdog@1c20ca0 { <<
883 compatible = "allwinne <<
884 "allwinne <<
885 reg = <0x01c20ca0 0x20 <<
886 interrupts = <GIC_SPI <<
887 clocks = <&osc24M>; <<
888 }; <<
889 <<
890 spdif: spdif@1c21000 { 486 spdif: spdif@1c21000 {
891 #sound-dai-cells = <0> 487 #sound-dai-cells = <0>;
892 compatible = "allwinne 488 compatible = "allwinner,sun50i-a64-spdif",
893 "allwinne 489 "allwinner,sun8i-h3-spdif";
894 reg = <0x01c21000 0x40 490 reg = <0x01c21000 0x400>;
895 interrupts = <GIC_SPI 491 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
896 clocks = <&ccu CLK_BUS 492 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
897 resets = <&ccu RST_BUS 493 resets = <&ccu RST_BUS_SPDIF>;
898 clock-names = "apb", " 494 clock-names = "apb", "spdif";
899 dmas = <&dma 2>; 495 dmas = <&dma 2>;
900 dma-names = "tx"; 496 dma-names = "tx";
901 pinctrl-names = "defau 497 pinctrl-names = "default";
902 pinctrl-0 = <&spdif_tx 498 pinctrl-0 = <&spdif_tx_pin>;
903 status = "disabled"; 499 status = "disabled";
904 }; 500 };
905 501
906 lradc: lradc@1c21800 { <<
907 compatible = "allwinne <<
908 "allwinne <<
909 reg = <0x01c21800 0x40 <<
910 interrupt-parent = <&r <<
911 interrupts = <GIC_SPI <<
912 status = "disabled"; <<
913 }; <<
914 <<
915 i2s0: i2s@1c22000 { 502 i2s0: i2s@1c22000 {
916 #sound-dai-cells = <0> 503 #sound-dai-cells = <0>;
917 compatible = "allwinne 504 compatible = "allwinner,sun50i-a64-i2s",
918 "allwinne 505 "allwinner,sun8i-h3-i2s";
919 reg = <0x01c22000 0x40 506 reg = <0x01c22000 0x400>;
920 interrupts = <GIC_SPI 507 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
921 clocks = <&ccu CLK_BUS 508 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
922 clock-names = "apb", " 509 clock-names = "apb", "mod";
923 resets = <&ccu RST_BUS 510 resets = <&ccu RST_BUS_I2S0>;
924 dma-names = "rx", "tx" 511 dma-names = "rx", "tx";
925 dmas = <&dma 3>, <&dma 512 dmas = <&dma 3>, <&dma 3>;
926 status = "disabled"; 513 status = "disabled";
927 }; 514 };
928 515
929 i2s1: i2s@1c22400 { 516 i2s1: i2s@1c22400 {
930 #sound-dai-cells = <0> 517 #sound-dai-cells = <0>;
931 compatible = "allwinne 518 compatible = "allwinner,sun50i-a64-i2s",
932 "allwinne 519 "allwinner,sun8i-h3-i2s";
933 reg = <0x01c22400 0x40 520 reg = <0x01c22400 0x400>;
934 interrupts = <GIC_SPI 521 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
935 clocks = <&ccu CLK_BUS 522 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
936 clock-names = "apb", " 523 clock-names = "apb", "mod";
937 resets = <&ccu RST_BUS 524 resets = <&ccu RST_BUS_I2S1>;
938 dma-names = "rx", "tx" 525 dma-names = "rx", "tx";
939 dmas = <&dma 4>, <&dma 526 dmas = <&dma 4>, <&dma 4>;
940 status = "disabled"; 527 status = "disabled";
941 }; 528 };
942 529
943 i2s2: i2s@1c22800 { <<
944 #sound-dai-cells = <0> <<
945 compatible = "allwinne <<
946 "allwinne <<
947 reg = <0x01c22800 0x40 <<
948 interrupts = <GIC_SPI <<
949 clocks = <&ccu CLK_BUS <<
950 clock-names = "apb", " <<
951 resets = <&ccu RST_BUS <<
952 dma-names = "rx", "tx" <<
953 dmas = <&dma 27>, <&dm <<
954 status = "disabled"; <<
955 }; <<
956 <<
957 dai: dai@1c22c00 { <<
958 #sound-dai-cells = <0> <<
959 compatible = "allwinne <<
960 reg = <0x01c22c00 0x20 <<
961 interrupts = <GIC_SPI <<
962 clocks = <&ccu CLK_BUS <<
963 clock-names = "apb", " <<
964 resets = <&ccu RST_BUS <<
965 dmas = <&dma 15>, <&dm <<
966 dma-names = "rx", "tx" <<
967 status = "disabled"; <<
968 }; <<
969 <<
970 codec: codec@1c22e00 { <<
971 #sound-dai-cells = <1> <<
972 compatible = "allwinne <<
973 "allwinne <<
974 reg = <0x01c22e00 0x60 <<
975 interrupts = <GIC_SPI <<
976 clocks = <&ccu CLK_BUS <<
977 clock-names = "bus", " <<
978 status = "disabled"; <<
979 }; <<
980 <<
981 ths: thermal-sensor@1c25000 { <<
982 compatible = "allwinne <<
983 reg = <0x01c25000 0x10 <<
984 clocks = <&ccu CLK_BUS <<
985 clock-names = "bus", " <<
986 interrupts = <GIC_SPI <<
987 resets = <&ccu RST_BUS <<
988 nvmem-cells = <&ths_ca <<
989 nvmem-cell-names = "ca <<
990 #thermal-sensor-cells <<
991 }; <<
992 <<
993 uart0: serial@1c28000 { 530 uart0: serial@1c28000 {
994 compatible = "snps,dw- 531 compatible = "snps,dw-apb-uart";
995 reg = <0x01c28000 0x40 532 reg = <0x01c28000 0x400>;
996 interrupts = <GIC_SPI 533 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
997 reg-shift = <2>; 534 reg-shift = <2>;
998 reg-io-width = <4>; 535 reg-io-width = <4>;
999 clocks = <&ccu CLK_BUS 536 clocks = <&ccu CLK_BUS_UART0>;
1000 resets = <&ccu RST_BU 537 resets = <&ccu RST_BUS_UART0>;
1001 status = "disabled"; 538 status = "disabled";
1002 }; 539 };
1003 540
1004 uart1: serial@1c28400 { 541 uart1: serial@1c28400 {
1005 compatible = "snps,dw 542 compatible = "snps,dw-apb-uart";
1006 reg = <0x01c28400 0x4 543 reg = <0x01c28400 0x400>;
1007 interrupts = <GIC_SPI 544 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1008 reg-shift = <2>; 545 reg-shift = <2>;
1009 reg-io-width = <4>; 546 reg-io-width = <4>;
1010 clocks = <&ccu CLK_BU 547 clocks = <&ccu CLK_BUS_UART1>;
1011 resets = <&ccu RST_BU 548 resets = <&ccu RST_BUS_UART1>;
1012 status = "disabled"; 549 status = "disabled";
1013 }; 550 };
1014 551
1015 uart2: serial@1c28800 { 552 uart2: serial@1c28800 {
1016 compatible = "snps,dw 553 compatible = "snps,dw-apb-uart";
1017 reg = <0x01c28800 0x4 554 reg = <0x01c28800 0x400>;
1018 interrupts = <GIC_SPI 555 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1019 reg-shift = <2>; 556 reg-shift = <2>;
1020 reg-io-width = <4>; 557 reg-io-width = <4>;
1021 clocks = <&ccu CLK_BU 558 clocks = <&ccu CLK_BUS_UART2>;
1022 resets = <&ccu RST_BU 559 resets = <&ccu RST_BUS_UART2>;
1023 status = "disabled"; 560 status = "disabled";
1024 }; 561 };
1025 562
1026 uart3: serial@1c28c00 { 563 uart3: serial@1c28c00 {
1027 compatible = "snps,dw 564 compatible = "snps,dw-apb-uart";
1028 reg = <0x01c28c00 0x4 565 reg = <0x01c28c00 0x400>;
1029 interrupts = <GIC_SPI 566 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1030 reg-shift = <2>; 567 reg-shift = <2>;
1031 reg-io-width = <4>; 568 reg-io-width = <4>;
1032 clocks = <&ccu CLK_BU 569 clocks = <&ccu CLK_BUS_UART3>;
1033 resets = <&ccu RST_BU 570 resets = <&ccu RST_BUS_UART3>;
1034 status = "disabled"; 571 status = "disabled";
1035 }; 572 };
1036 573
1037 uart4: serial@1c29000 { 574 uart4: serial@1c29000 {
1038 compatible = "snps,dw 575 compatible = "snps,dw-apb-uart";
1039 reg = <0x01c29000 0x4 576 reg = <0x01c29000 0x400>;
1040 interrupts = <GIC_SPI 577 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1041 reg-shift = <2>; 578 reg-shift = <2>;
1042 reg-io-width = <4>; 579 reg-io-width = <4>;
1043 clocks = <&ccu CLK_BU 580 clocks = <&ccu CLK_BUS_UART4>;
1044 resets = <&ccu RST_BU 581 resets = <&ccu RST_BUS_UART4>;
1045 status = "disabled"; 582 status = "disabled";
1046 }; 583 };
1047 584
1048 i2c0: i2c@1c2ac00 { 585 i2c0: i2c@1c2ac00 {
1049 compatible = "allwinn 586 compatible = "allwinner,sun6i-a31-i2c";
1050 reg = <0x01c2ac00 0x4 587 reg = <0x01c2ac00 0x400>;
1051 interrupts = <GIC_SPI 588 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1052 clocks = <&ccu CLK_BU 589 clocks = <&ccu CLK_BUS_I2C0>;
1053 resets = <&ccu RST_BU 590 resets = <&ccu RST_BUS_I2C0>;
1054 pinctrl-names = "defa <<
1055 pinctrl-0 = <&i2c0_pi <<
1056 status = "disabled"; 591 status = "disabled";
1057 #address-cells = <1>; 592 #address-cells = <1>;
1058 #size-cells = <0>; 593 #size-cells = <0>;
1059 }; 594 };
1060 595
1061 i2c1: i2c@1c2b000 { 596 i2c1: i2c@1c2b000 {
1062 compatible = "allwinn 597 compatible = "allwinner,sun6i-a31-i2c";
1063 reg = <0x01c2b000 0x4 598 reg = <0x01c2b000 0x400>;
1064 interrupts = <GIC_SPI 599 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1065 clocks = <&ccu CLK_BU 600 clocks = <&ccu CLK_BUS_I2C1>;
1066 resets = <&ccu RST_BU 601 resets = <&ccu RST_BUS_I2C1>;
1067 pinctrl-names = "defa <<
1068 pinctrl-0 = <&i2c1_pi <<
1069 status = "disabled"; 602 status = "disabled";
1070 #address-cells = <1>; 603 #address-cells = <1>;
1071 #size-cells = <0>; 604 #size-cells = <0>;
1072 }; 605 };
1073 606
1074 i2c2: i2c@1c2b400 { 607 i2c2: i2c@1c2b400 {
1075 compatible = "allwinn 608 compatible = "allwinner,sun6i-a31-i2c";
1076 reg = <0x01c2b400 0x4 609 reg = <0x01c2b400 0x400>;
1077 interrupts = <GIC_SPI 610 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1078 clocks = <&ccu CLK_BU 611 clocks = <&ccu CLK_BUS_I2C2>;
1079 resets = <&ccu RST_BU 612 resets = <&ccu RST_BUS_I2C2>;
1080 pinctrl-names = "defa <<
1081 pinctrl-0 = <&i2c2_pi <<
1082 status = "disabled"; 613 status = "disabled";
1083 #address-cells = <1>; 614 #address-cells = <1>;
1084 #size-cells = <0>; 615 #size-cells = <0>;
1085 }; 616 };
1086 617
>> 618
1087 spi0: spi@1c68000 { 619 spi0: spi@1c68000 {
1088 compatible = "allwinn 620 compatible = "allwinner,sun8i-h3-spi";
1089 reg = <0x01c68000 0x1 621 reg = <0x01c68000 0x1000>;
1090 interrupts = <GIC_SPI 622 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1091 clocks = <&ccu CLK_BU 623 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
1092 clock-names = "ahb", 624 clock-names = "ahb", "mod";
1093 dmas = <&dma 23>, <&d 625 dmas = <&dma 23>, <&dma 23>;
1094 dma-names = "rx", "tx 626 dma-names = "rx", "tx";
1095 pinctrl-names = "defa 627 pinctrl-names = "default";
1096 pinctrl-0 = <&spi0_pi 628 pinctrl-0 = <&spi0_pins>;
1097 resets = <&ccu RST_BU 629 resets = <&ccu RST_BUS_SPI0>;
1098 status = "disabled"; 630 status = "disabled";
1099 num-cs = <1>; 631 num-cs = <1>;
1100 #address-cells = <1>; 632 #address-cells = <1>;
1101 #size-cells = <0>; 633 #size-cells = <0>;
1102 }; 634 };
1103 635
1104 spi1: spi@1c69000 { 636 spi1: spi@1c69000 {
1105 compatible = "allwinn 637 compatible = "allwinner,sun8i-h3-spi";
1106 reg = <0x01c69000 0x1 638 reg = <0x01c69000 0x1000>;
1107 interrupts = <GIC_SPI 639 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1108 clocks = <&ccu CLK_BU 640 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
1109 clock-names = "ahb", 641 clock-names = "ahb", "mod";
1110 dmas = <&dma 24>, <&d 642 dmas = <&dma 24>, <&dma 24>;
1111 dma-names = "rx", "tx 643 dma-names = "rx", "tx";
1112 pinctrl-names = "defa 644 pinctrl-names = "default";
1113 pinctrl-0 = <&spi1_pi 645 pinctrl-0 = <&spi1_pins>;
1114 resets = <&ccu RST_BU 646 resets = <&ccu RST_BUS_SPI1>;
1115 status = "disabled"; 647 status = "disabled";
1116 num-cs = <1>; 648 num-cs = <1>;
1117 #address-cells = <1>; 649 #address-cells = <1>;
1118 #size-cells = <0>; 650 #size-cells = <0>;
1119 }; 651 };
1120 652
1121 emac: ethernet@1c30000 { 653 emac: ethernet@1c30000 {
1122 compatible = "allwinn 654 compatible = "allwinner,sun50i-a64-emac";
1123 syscon = <&syscon>; 655 syscon = <&syscon>;
1124 reg = <0x01c30000 0x1 656 reg = <0x01c30000 0x10000>;
1125 interrupts = <GIC_SPI 657 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1126 interrupt-names = "ma 658 interrupt-names = "macirq";
1127 resets = <&ccu RST_BU 659 resets = <&ccu RST_BUS_EMAC>;
1128 reset-names = "stmmac 660 reset-names = "stmmaceth";
1129 clocks = <&ccu CLK_BU 661 clocks = <&ccu CLK_BUS_EMAC>;
1130 clock-names = "stmmac 662 clock-names = "stmmaceth";
1131 status = "disabled"; 663 status = "disabled";
1132 664
1133 mdio: mdio { 665 mdio: mdio {
1134 compatible = 666 compatible = "snps,dwmac-mdio";
1135 #address-cell 667 #address-cells = <1>;
1136 #size-cells = 668 #size-cells = <0>;
1137 }; 669 };
1138 }; 670 };
1139 671
1140 mali: gpu@1c40000 { <<
1141 compatible = "allwinn <<
1142 reg = <0x01c40000 0x1 <<
1143 interrupts = <GIC_SPI <<
1144 <GIC_SPI <<
1145 <GIC_SPI <<
1146 <GIC_SPI <<
1147 <GIC_SPI <<
1148 <GIC_SPI <<
1149 <GIC_SPI <<
1150 interrupt-names = "gp <<
1151 "gp <<
1152 "pp <<
1153 "pp <<
1154 "pp <<
1155 "pp <<
1156 "pm <<
1157 clocks = <&ccu CLK_BU <<
1158 clock-names = "bus", <<
1159 resets = <&ccu RST_BU <<
1160 operating-points-v2 = <<
1161 }; <<
1162 <<
1163 gic: interrupt-controller@1c8 672 gic: interrupt-controller@1c81000 {
1164 compatible = "arm,gic 673 compatible = "arm,gic-400";
1165 reg = <0x01c81000 0x1 674 reg = <0x01c81000 0x1000>,
1166 <0x01c82000 0x2 675 <0x01c82000 0x2000>,
1167 <0x01c84000 0x2 676 <0x01c84000 0x2000>,
1168 <0x01c86000 0x2 677 <0x01c86000 0x2000>;
1169 interrupts = <GIC_PPI 678 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1170 interrupt-controller; 679 interrupt-controller;
1171 #interrupt-cells = <3 680 #interrupt-cells = <3>;
1172 }; 681 };
1173 682
1174 pwm: pwm@1c21400 { 683 pwm: pwm@1c21400 {
1175 compatible = "allwinn 684 compatible = "allwinner,sun50i-a64-pwm",
1176 "allwinn 685 "allwinner,sun5i-a13-pwm";
1177 reg = <0x01c21400 0x4 686 reg = <0x01c21400 0x400>;
1178 clocks = <&osc24M>; 687 clocks = <&osc24M>;
1179 pinctrl-names = "defa 688 pinctrl-names = "default";
1180 pinctrl-0 = <&pwm_pin 689 pinctrl-0 = <&pwm_pin>;
1181 #pwm-cells = <3>; 690 #pwm-cells = <3>;
1182 status = "disabled"; 691 status = "disabled";
1183 }; 692 };
1184 693
1185 mbus: dram-controller@1c62000 <<
1186 compatible = "allwinn <<
1187 reg = <0x01c62000 0x1 <<
1188 <0x01c63000 0x1 <<
1189 reg-names = "mbus", " <<
1190 clocks = <&ccu CLK_MB <<
1191 <&ccu CLK_DR <<
1192 <&ccu CLK_BU <<
1193 clock-names = "mbus", <<
1194 interrupts = <GIC_SPI <<
1195 #address-cells = <1>; <<
1196 #size-cells = <1>; <<
1197 dma-ranges = <0x00000 <<
1198 #interconnect-cells = <<
1199 }; <<
1200 <<
1201 csi: csi@1cb0000 { <<
1202 compatible = "allwinn <<
1203 reg = <0x01cb0000 0x1 <<
1204 interrupts = <GIC_SPI <<
1205 clocks = <&ccu CLK_BU <<
1206 <&ccu CLK_CS <<
1207 <&ccu CLK_DR <<
1208 clock-names = "bus", <<
1209 resets = <&ccu RST_BU <<
1210 pinctrl-names = "defa <<
1211 pinctrl-0 = <&csi_pin <<
1212 status = "disabled"; <<
1213 }; <<
1214 <<
1215 dsi: dsi@1ca0000 { <<
1216 compatible = "allwinn <<
1217 reg = <0x01ca0000 0x1 <<
1218 interrupts = <GIC_SPI <<
1219 clocks = <&ccu CLK_BU <<
1220 resets = <&ccu RST_BU <<
1221 phys = <&dphy>; <<
1222 phy-names = "dphy"; <<
1223 status = "disabled"; <<
1224 #address-cells = <1>; <<
1225 #size-cells = <0>; <<
1226 <<
1227 port { <<
1228 dsi_in_tcon0: <<
1229 remot <<
1230 }; <<
1231 }; <<
1232 }; <<
1233 <<
1234 dphy: d-phy@1ca1000 { <<
1235 compatible = "allwinn <<
1236 "allwinn <<
1237 reg = <0x01ca1000 0x1 <<
1238 interrupts = <GIC_SPI <<
1239 clocks = <&ccu CLK_BU <<
1240 <&ccu CLK_DS <<
1241 clock-names = "bus", <<
1242 resets = <&ccu RST_BU <<
1243 status = "disabled"; <<
1244 #phy-cells = <0>; <<
1245 }; <<
1246 <<
1247 deinterlace: deinterlace@1e00 <<
1248 compatible = "allwinn <<
1249 "allwinn <<
1250 reg = <0x01e00000 0x2 <<
1251 clocks = <&ccu CLK_BU <<
1252 <&ccu CLK_DE <<
1253 <&ccu CLK_DR <<
1254 clock-names = "bus", <<
1255 resets = <&ccu RST_BU <<
1256 interrupts = <GIC_SPI <<
1257 interconnects = <&mbu <<
1258 interconnect-names = <<
1259 }; <<
1260 <<
1261 hdmi: hdmi@1ee0000 { <<
1262 compatible = "allwinn <<
1263 "allwinn <<
1264 reg = <0x01ee0000 0x1 <<
1265 reg-io-width = <1>; <<
1266 interrupts = <GIC_SPI <<
1267 clocks = <&ccu CLK_BU <<
1268 <&ccu CLK_HD <<
1269 clock-names = "iahb", <<
1270 resets = <&ccu RST_BU <<
1271 reset-names = "ctrl"; <<
1272 phys = <&hdmi_phy>; <<
1273 phy-names = "phy"; <<
1274 status = "disabled"; <<
1275 <<
1276 ports { <<
1277 #address-cell <<
1278 #size-cells = <<
1279 <<
1280 hdmi_in: port <<
1281 reg = <<
1282 <<
1283 hdmi_ <<
1284 <<
1285 }; <<
1286 }; <<
1287 <<
1288 hdmi_out: por <<
1289 reg = <<
1290 }; <<
1291 }; <<
1292 }; <<
1293 <<
1294 hdmi_phy: hdmi-phy@1ef0000 { <<
1295 compatible = "allwinn <<
1296 reg = <0x01ef0000 0x1 <<
1297 clocks = <&ccu CLK_BU <<
1298 <&ccu CLK_PL <<
1299 clock-names = "bus", <<
1300 resets = <&ccu RST_BU <<
1301 reset-names = "phy"; <<
1302 #phy-cells = <0>; <<
1303 }; <<
1304 <<
1305 rtc: rtc@1f00000 { 694 rtc: rtc@1f00000 {
1306 compatible = "allwinn !! 695 compatible = "allwinner,sun6i-a31-rtc";
1307 "allwinn !! 696 reg = <0x01f00000 0x54>;
1308 reg = <0x01f00000 0x4 <<
1309 interrupt-parent = <& <<
1310 interrupts = <GIC_SPI 697 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1311 <GIC_SPI 698 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1312 clock-output-names = !! 699 clock-output-names = "rtc-osc32k", "rtc-osc32k-out";
1313 clocks = <&osc32k>; 700 clocks = <&osc32k>;
1314 #clock-cells = <1>; 701 #clock-cells = <1>;
1315 }; 702 };
1316 703
1317 r_intc: interrupt-controller@ 704 r_intc: interrupt-controller@1f00c00 {
1318 compatible = "allwinn 705 compatible = "allwinner,sun50i-a64-r-intc",
1319 "allwinn 706 "allwinner,sun6i-a31-r-intc";
1320 interrupt-controller; 707 interrupt-controller;
1321 #interrupt-cells = <3 !! 708 #interrupt-cells = <2>;
1322 reg = <0x01f00c00 0x4 709 reg = <0x01f00c00 0x400>;
1323 interrupts = <GIC_SPI 710 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1324 }; 711 };
1325 712
1326 r_ccu: clock@1f01400 { 713 r_ccu: clock@1f01400 {
1327 compatible = "allwinn 714 compatible = "allwinner,sun50i-a64-r-ccu";
1328 reg = <0x01f01400 0x1 715 reg = <0x01f01400 0x100>;
1329 clocks = <&osc24M>, < !! 716 clocks = <&osc24M>, <&osc32k>, <&iosc>,
1330 <&ccu CLK_PL !! 717 <&ccu 11>;
1331 clock-names = "hosc", 718 clock-names = "hosc", "losc", "iosc", "pll-periph";
1332 #clock-cells = <1>; 719 #clock-cells = <1>;
1333 #reset-cells = <1>; 720 #reset-cells = <1>;
1334 }; 721 };
1335 722
1336 codec_analog: codec-analog@1f <<
1337 compatible = "allwinn <<
1338 reg = <0x01f015c0 0x4 <<
1339 status = "disabled"; <<
1340 }; <<
1341 <<
1342 r_i2c: i2c@1f02400 { 723 r_i2c: i2c@1f02400 {
1343 compatible = "allwinn 724 compatible = "allwinner,sun50i-a64-i2c",
1344 "allwinn 725 "allwinner,sun6i-a31-i2c";
1345 reg = <0x01f02400 0x4 726 reg = <0x01f02400 0x400>;
1346 interrupts = <GIC_SPI 727 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1347 clocks = <&r_ccu CLK_ 728 clocks = <&r_ccu CLK_APB0_I2C>;
1348 resets = <&r_ccu RST_ 729 resets = <&r_ccu RST_APB0_I2C>;
1349 status = "disabled"; 730 status = "disabled";
1350 #address-cells = <1>; 731 #address-cells = <1>;
1351 #size-cells = <0>; 732 #size-cells = <0>;
1352 }; 733 };
1353 734
1354 r_ir: ir@1f02000 { <<
1355 compatible = "allwinn <<
1356 "allwinn <<
1357 reg = <0x01f02000 0x4 <<
1358 clocks = <&r_ccu CLK_ <<
1359 clock-names = "apb", <<
1360 resets = <&r_ccu RST_ <<
1361 interrupts = <GIC_SPI <<
1362 pinctrl-names = "defa <<
1363 pinctrl-0 = <&r_ir_rx <<
1364 status = "disabled"; <<
1365 }; <<
1366 <<
1367 r_pwm: pwm@1f03800 { 735 r_pwm: pwm@1f03800 {
1368 compatible = "allwinn 736 compatible = "allwinner,sun50i-a64-pwm",
1369 "allwinn 737 "allwinner,sun5i-a13-pwm";
1370 reg = <0x01f03800 0x4 738 reg = <0x01f03800 0x400>;
1371 clocks = <&osc24M>; 739 clocks = <&osc24M>;
1372 pinctrl-names = "defa 740 pinctrl-names = "default";
1373 pinctrl-0 = <&r_pwm_p 741 pinctrl-0 = <&r_pwm_pin>;
1374 #pwm-cells = <3>; 742 #pwm-cells = <3>;
1375 status = "disabled"; 743 status = "disabled";
1376 }; 744 };
1377 745
1378 r_pio: pinctrl@1f02c00 { 746 r_pio: pinctrl@1f02c00 {
1379 compatible = "allwinn 747 compatible = "allwinner,sun50i-a64-r-pinctrl";
1380 reg = <0x01f02c00 0x4 748 reg = <0x01f02c00 0x400>;
1381 interrupt-parent = <& <<
1382 interrupts = <GIC_SPI 749 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1383 clocks = <&r_ccu CLK_ 750 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
1384 clock-names = "apb", 751 clock-names = "apb", "hosc", "losc";
1385 gpio-controller; 752 gpio-controller;
1386 #gpio-cells = <3>; 753 #gpio-cells = <3>;
1387 interrupt-controller; 754 interrupt-controller;
1388 #interrupt-cells = <3 755 #interrupt-cells = <3>;
1389 756
1390 r_i2c_pl89_pins: r-i2 !! 757 r_i2c_pins_a: i2c-a {
1391 pins = "PL8", 758 pins = "PL8", "PL9";
1392 function = "s 759 function = "s_i2c";
1393 }; 760 };
1394 761
1395 r_ir_rx_pin: r-ir-rx- !! 762 r_pwm_pin: pwm {
1396 pins = "PL11" <<
1397 function = "s <<
1398 }; <<
1399 <<
1400 r_pwm_pin: r-pwm-pin <<
1401 pins = "PL10" 763 pins = "PL10";
1402 function = "s 764 function = "s_pwm";
1403 }; 765 };
1404 766
1405 r_rsb_pins: r-rsb-pin !! 767 r_rsb_pins: rsb {
1406 pins = "PL0", 768 pins = "PL0", "PL1";
1407 function = "s 769 function = "s_rsb";
1408 }; 770 };
1409 }; 771 };
1410 772
1411 r_rsb: rsb@1f03400 { 773 r_rsb: rsb@1f03400 {
1412 compatible = "allwinn 774 compatible = "allwinner,sun8i-a23-rsb";
1413 reg = <0x01f03400 0x4 775 reg = <0x01f03400 0x400>;
1414 interrupts = <GIC_SPI 776 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1415 clocks = <&r_ccu 6>; 777 clocks = <&r_ccu 6>;
1416 clock-frequency = <30 778 clock-frequency = <3000000>;
1417 resets = <&r_ccu 2>; 779 resets = <&r_ccu 2>;
1418 pinctrl-names = "defa 780 pinctrl-names = "default";
1419 pinctrl-0 = <&r_rsb_p 781 pinctrl-0 = <&r_rsb_pins>;
1420 status = "disabled"; 782 status = "disabled";
1421 #address-cells = <1>; 783 #address-cells = <1>;
1422 #size-cells = <0>; 784 #size-cells = <0>;
>> 785 };
>> 786
>> 787 wdt0: watchdog@1c20ca0 {
>> 788 compatible = "allwinner,sun50i-a64-wdt",
>> 789 "allwinner,sun6i-a31-wdt";
>> 790 reg = <0x01c20ca0 0x20>;
>> 791 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1423 }; 792 };
1424 }; 793 };
1425 }; 794 };
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