1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2016 ARM Ltd. 2 // Copyright (C) 2016 ARM Ltd.
3 // based on the Allwinner H3 dtsi: 3 // based on the Allwinner H3 dtsi:
4 // Copyright (C) 2015 Jens Kuske <jenskuske@ 4 // Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
5 5
6 #include <dt-bindings/clock/sun50i-a64-ccu.h> 6 #include <dt-bindings/clock/sun50i-a64-ccu.h>
7 #include <dt-bindings/clock/sun6i-rtc.h> <<
8 #include <dt-bindings/clock/sun8i-de2.h> 7 #include <dt-bindings/clock/sun8i-de2.h>
9 #include <dt-bindings/clock/sun8i-r-ccu.h> 8 #include <dt-bindings/clock/sun8i-r-ccu.h>
10 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/sun50i-a64-ccu.h> 10 #include <dt-bindings/reset/sun50i-a64-ccu.h>
12 #include <dt-bindings/reset/sun8i-de2.h> 11 #include <dt-bindings/reset/sun8i-de2.h>
13 #include <dt-bindings/reset/sun8i-r-ccu.h> 12 #include <dt-bindings/reset/sun8i-r-ccu.h>
14 #include <dt-bindings/thermal/thermal.h> 13 #include <dt-bindings/thermal/thermal.h>
15 14
16 / { 15 / {
17 interrupt-parent = <&gic>; 16 interrupt-parent = <&gic>;
18 #address-cells = <1>; 17 #address-cells = <1>;
19 #size-cells = <1>; 18 #size-cells = <1>;
20 19
21 chosen { 20 chosen {
22 #address-cells = <1>; 21 #address-cells = <1>;
23 #size-cells = <1>; 22 #size-cells = <1>;
24 ranges; 23 ranges;
25 24
26 simplefb_lcd: framebuffer-lcd 25 simplefb_lcd: framebuffer-lcd {
27 compatible = "allwinne 26 compatible = "allwinner,simple-framebuffer",
28 "simple-f 27 "simple-framebuffer";
29 allwinner,pipeline = " 28 allwinner,pipeline = "mixer0-lcd0";
30 clocks = <&ccu CLK_TCO 29 clocks = <&ccu CLK_TCON0>,
31 <&display_clo 30 <&display_clocks CLK_MIXER0>;
32 status = "disabled"; 31 status = "disabled";
33 }; 32 };
34 33
35 simplefb_hdmi: framebuffer-hdm 34 simplefb_hdmi: framebuffer-hdmi {
36 compatible = "allwinne 35 compatible = "allwinner,simple-framebuffer",
37 "simple-f 36 "simple-framebuffer";
38 allwinner,pipeline = " 37 allwinner,pipeline = "mixer1-lcd1-hdmi";
39 clocks = <&display_clo 38 clocks = <&display_clocks CLK_MIXER1>,
40 <&ccu CLK_TCO 39 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
41 status = "disabled"; 40 status = "disabled";
42 }; 41 };
43 }; 42 };
44 43
45 cpus { 44 cpus {
46 #address-cells = <1>; 45 #address-cells = <1>;
47 #size-cells = <0>; 46 #size-cells = <0>;
48 47
49 cpu0: cpu@0 { 48 cpu0: cpu@0 {
50 compatible = "arm,cort 49 compatible = "arm,cortex-a53";
51 device_type = "cpu"; 50 device_type = "cpu";
52 reg = <0>; 51 reg = <0>;
53 enable-method = "psci" 52 enable-method = "psci";
>> 53 next-level-cache = <&L2>;
54 clocks = <&ccu CLK_CPU 54 clocks = <&ccu CLK_CPUX>;
55 clock-names = "cpu"; 55 clock-names = "cpu";
56 #cooling-cells = <2>; 56 #cooling-cells = <2>;
57 i-cache-size = <0x8000 <<
58 i-cache-line-size = <6 <<
59 i-cache-sets = <256>; <<
60 d-cache-size = <0x8000 <<
61 d-cache-line-size = <6 <<
62 d-cache-sets = <128>; <<
63 next-level-cache = <&l <<
64 }; 57 };
65 58
66 cpu1: cpu@1 { 59 cpu1: cpu@1 {
67 compatible = "arm,cort 60 compatible = "arm,cortex-a53";
68 device_type = "cpu"; 61 device_type = "cpu";
69 reg = <1>; 62 reg = <1>;
70 enable-method = "psci" 63 enable-method = "psci";
>> 64 next-level-cache = <&L2>;
71 clocks = <&ccu CLK_CPU 65 clocks = <&ccu CLK_CPUX>;
72 clock-names = "cpu"; 66 clock-names = "cpu";
73 #cooling-cells = <2>; 67 #cooling-cells = <2>;
74 i-cache-size = <0x8000 <<
75 i-cache-line-size = <6 <<
76 i-cache-sets = <256>; <<
77 d-cache-size = <0x8000 <<
78 d-cache-line-size = <6 <<
79 d-cache-sets = <128>; <<
80 next-level-cache = <&l <<
81 }; 68 };
82 69
83 cpu2: cpu@2 { 70 cpu2: cpu@2 {
84 compatible = "arm,cort 71 compatible = "arm,cortex-a53";
85 device_type = "cpu"; 72 device_type = "cpu";
86 reg = <2>; 73 reg = <2>;
87 enable-method = "psci" 74 enable-method = "psci";
>> 75 next-level-cache = <&L2>;
88 clocks = <&ccu CLK_CPU 76 clocks = <&ccu CLK_CPUX>;
89 clock-names = "cpu"; 77 clock-names = "cpu";
90 #cooling-cells = <2>; 78 #cooling-cells = <2>;
91 i-cache-size = <0x8000 <<
92 i-cache-line-size = <6 <<
93 i-cache-sets = <256>; <<
94 d-cache-size = <0x8000 <<
95 d-cache-line-size = <6 <<
96 d-cache-sets = <128>; <<
97 next-level-cache = <&l <<
98 }; 79 };
99 80
100 cpu3: cpu@3 { 81 cpu3: cpu@3 {
101 compatible = "arm,cort 82 compatible = "arm,cortex-a53";
102 device_type = "cpu"; 83 device_type = "cpu";
103 reg = <3>; 84 reg = <3>;
104 enable-method = "psci" 85 enable-method = "psci";
>> 86 next-level-cache = <&L2>;
105 clocks = <&ccu CLK_CPU 87 clocks = <&ccu CLK_CPUX>;
106 clock-names = "cpu"; 88 clock-names = "cpu";
107 #cooling-cells = <2>; 89 #cooling-cells = <2>;
108 i-cache-size = <0x8000 <<
109 i-cache-line-size = <6 <<
110 i-cache-sets = <256>; <<
111 d-cache-size = <0x8000 <<
112 d-cache-line-size = <6 <<
113 d-cache-sets = <128>; <<
114 next-level-cache = <&l <<
115 }; 90 };
116 91
117 l2_cache: l2-cache { !! 92 L2: l2-cache {
118 compatible = "cache"; 93 compatible = "cache";
119 cache-level = <2>; 94 cache-level = <2>;
120 cache-unified; <<
121 cache-size = <0x80000> <<
122 cache-line-size = <64> <<
123 cache-sets = <512>; <<
124 }; 95 };
125 }; 96 };
126 97
127 de: display-engine { 98 de: display-engine {
128 compatible = "allwinner,sun50i 99 compatible = "allwinner,sun50i-a64-display-engine";
129 allwinner,pipelines = <&mixer0 100 allwinner,pipelines = <&mixer0>,
130 <&mixer1 101 <&mixer1>;
131 status = "disabled"; 102 status = "disabled";
132 }; 103 };
133 104
134 gpu_opp_table: opp-table-gpu { !! 105 osc24M: osc24M_clk {
135 compatible = "operating-points <<
136 <<
137 opp-432000000 { <<
138 opp-hz = /bits/ 64 <43 <<
139 }; <<
140 }; <<
141 <<
142 osc24M: osc24M-clk { <<
143 #clock-cells = <0>; 106 #clock-cells = <0>;
144 compatible = "fixed-clock"; 107 compatible = "fixed-clock";
145 clock-frequency = <24000000>; 108 clock-frequency = <24000000>;
146 clock-output-names = "osc24M"; 109 clock-output-names = "osc24M";
147 }; 110 };
148 111
149 osc32k: osc32k-clk { !! 112 osc32k: osc32k_clk {
150 #clock-cells = <0>; 113 #clock-cells = <0>;
151 compatible = "fixed-clock"; 114 compatible = "fixed-clock";
152 clock-frequency = <32768>; 115 clock-frequency = <32768>;
153 clock-output-names = "ext-osc3 116 clock-output-names = "ext-osc32k";
154 }; 117 };
155 118
156 pmu { 119 pmu {
157 compatible = "arm,cortex-a53-p 120 compatible = "arm,cortex-a53-pmu";
158 interrupts = <GIC_SPI 116 IRQ_ 121 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 117 IRQ_ 122 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 118 IRQ_ 123 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 119 IRQ_ 124 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
162 interrupt-affinity = <&cpu0>, 125 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
163 }; 126 };
164 127
165 psci { 128 psci {
166 compatible = "arm,psci-0.2"; 129 compatible = "arm,psci-0.2";
167 method = "smc"; 130 method = "smc";
168 }; 131 };
169 132
170 sound: sound { 133 sound: sound {
171 #address-cells = <1>; 134 #address-cells = <1>;
172 #size-cells = <0>; 135 #size-cells = <0>;
173 compatible = "simple-audio-car 136 compatible = "simple-audio-card";
174 simple-audio-card,name = "sun5 137 simple-audio-card,name = "sun50i-a64-audio";
175 simple-audio-card,aux-devs = < 138 simple-audio-card,aux-devs = <&codec_analog>;
176 simple-audio-card,routing = 139 simple-audio-card,routing =
177 "Left DAC", "D 140 "Left DAC", "DACL",
178 "Right DAC", " 141 "Right DAC", "DACR",
179 "ADCL", "Left 142 "ADCL", "Left ADC",
180 "ADCR", "Right 143 "ADCR", "Right ADC";
181 status = "disabled"; 144 status = "disabled";
182 145
183 simple-audio-card,dai-link@0 { 146 simple-audio-card,dai-link@0 {
184 format = "i2s"; 147 format = "i2s";
185 frame-master = <&link0 148 frame-master = <&link0_cpu>;
186 bitclock-master = <&li 149 bitclock-master = <&link0_cpu>;
187 mclk-fs = <128>; 150 mclk-fs = <128>;
188 151
189 link0_cpu: cpu { 152 link0_cpu: cpu {
190 sound-dai = <& 153 sound-dai = <&dai>;
191 }; 154 };
192 155
193 link0_codec: codec { 156 link0_codec: codec {
194 sound-dai = <& 157 sound-dai = <&codec 0>;
195 }; 158 };
196 }; 159 };
197 }; 160 };
198 161
199 timer { 162 timer {
200 compatible = "arm,armv8-timer" 163 compatible = "arm,armv8-timer";
201 allwinner,erratum-unknown1; 164 allwinner,erratum-unknown1;
202 arm,no-tick-in-suspend; 165 arm,no-tick-in-suspend;
203 interrupts = <GIC_PPI 13 166 interrupts = <GIC_PPI 13
204 (GIC_CPU_MASK_SIMPLE(4 167 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
205 <GIC_PPI 14 168 <GIC_PPI 14
206 (GIC_CPU_MASK_SIMPLE(4 169 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
207 <GIC_PPI 11 170 <GIC_PPI 11
208 (GIC_CPU_MASK_SIMPLE(4 171 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
209 <GIC_PPI 10 172 <GIC_PPI 10
210 (GIC_CPU_MASK_SIMPLE(4 173 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
211 }; 174 };
212 175
213 thermal-zones { 176 thermal-zones {
214 cpu_thermal: cpu0-thermal { 177 cpu_thermal: cpu0-thermal {
215 /* milliseconds */ 178 /* milliseconds */
216 polling-delay-passive 179 polling-delay-passive = <0>;
217 polling-delay = <0>; 180 polling-delay = <0>;
218 thermal-sensors = <&th 181 thermal-sensors = <&ths 0>;
219 182
220 cooling-maps { 183 cooling-maps {
221 map0 { 184 map0 {
222 trip = 185 trip = <&cpu_alert0>;
223 coolin 186 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
224 187 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
225 188 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
226 189 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
227 }; 190 };
228 map1 { 191 map1 {
229 trip = 192 trip = <&cpu_alert1>;
230 coolin 193 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
231 194 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
232 195 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
233 196 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
234 }; 197 };
235 }; 198 };
236 199
237 trips { 200 trips {
238 cpu_alert0: cp !! 201 cpu_alert0: cpu_alert0 {
239 /* mil 202 /* milliCelsius */
240 temper 203 temperature = <75000>;
241 hyster 204 hysteresis = <2000>;
242 type = 205 type = "passive";
243 }; 206 };
244 207
245 cpu_alert1: cp !! 208 cpu_alert1: cpu_alert1 {
246 /* mil 209 /* milliCelsius */
247 temper 210 temperature = <90000>;
248 hyster 211 hysteresis = <2000>;
249 type = 212 type = "hot";
250 }; 213 };
251 214
252 cpu_crit: cpu- !! 215 cpu_crit: cpu_crit {
253 /* mil 216 /* milliCelsius */
254 temper 217 temperature = <110000>;
255 hyster 218 hysteresis = <2000>;
256 type = 219 type = "critical";
257 }; 220 };
258 }; 221 };
259 }; 222 };
260 223
261 gpu0_thermal: gpu0-thermal { 224 gpu0_thermal: gpu0-thermal {
262 /* milliseconds */ 225 /* milliseconds */
263 polling-delay-passive 226 polling-delay-passive = <0>;
264 polling-delay = <0>; 227 polling-delay = <0>;
265 thermal-sensors = <&th 228 thermal-sensors = <&ths 1>;
266 <<
267 trips { <<
268 gpu0_crit: gpu <<
269 temper <<
270 hyster <<
271 type = <<
272 }; <<
273 }; <<
274 }; 229 };
275 230
276 gpu1_thermal: gpu1-thermal { 231 gpu1_thermal: gpu1-thermal {
277 /* milliseconds */ 232 /* milliseconds */
278 polling-delay-passive 233 polling-delay-passive = <0>;
279 polling-delay = <0>; 234 polling-delay = <0>;
280 thermal-sensors = <&th 235 thermal-sensors = <&ths 2>;
281 <<
282 trips { <<
283 gpu1_crit: gpu <<
284 temper <<
285 hyster <<
286 type = <<
287 }; <<
288 }; <<
289 }; 236 };
290 }; 237 };
291 238
292 soc { 239 soc {
293 compatible = "simple-bus"; 240 compatible = "simple-bus";
294 #address-cells = <1>; 241 #address-cells = <1>;
295 #size-cells = <1>; 242 #size-cells = <1>;
296 ranges; 243 ranges;
297 244
298 bus@1000000 { 245 bus@1000000 {
299 compatible = "allwinne 246 compatible = "allwinner,sun50i-a64-de2";
300 reg = <0x1000000 0x400 247 reg = <0x1000000 0x400000>;
301 allwinner,sram = <&de2 248 allwinner,sram = <&de2_sram 1>;
302 #address-cells = <1>; 249 #address-cells = <1>;
303 #size-cells = <1>; 250 #size-cells = <1>;
304 ranges = <0 0x1000000 251 ranges = <0 0x1000000 0x400000>;
305 252
306 display_clocks: clock@ 253 display_clocks: clock@0 {
307 compatible = " 254 compatible = "allwinner,sun50i-a64-de2-clk";
308 reg = <0x0 0x1 255 reg = <0x0 0x10000>;
309 clocks = <&ccu 256 clocks = <&ccu CLK_BUS_DE>,
310 <&ccu 257 <&ccu CLK_DE>;
311 clock-names = 258 clock-names = "bus",
312 259 "mod";
313 resets = <&ccu 260 resets = <&ccu RST_BUS_DE>;
314 #clock-cells = 261 #clock-cells = <1>;
315 #reset-cells = 262 #reset-cells = <1>;
316 }; 263 };
317 264
318 rotate: rotate@20000 { 265 rotate: rotate@20000 {
319 compatible = " 266 compatible = "allwinner,sun50i-a64-de2-rotate",
320 " 267 "allwinner,sun8i-a83t-de2-rotate";
321 reg = <0x20000 268 reg = <0x20000 0x10000>;
322 interrupts = < 269 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&dis 270 clocks = <&display_clocks CLK_BUS_ROT>,
324 <&dis 271 <&display_clocks CLK_ROT>;
325 clock-names = 272 clock-names = "bus",
326 273 "mod";
327 resets = <&dis 274 resets = <&display_clocks RST_ROT>;
328 }; 275 };
329 276
330 mixer0: mixer@100000 { 277 mixer0: mixer@100000 {
331 compatible = " 278 compatible = "allwinner,sun50i-a64-de2-mixer-0";
332 reg = <0x10000 279 reg = <0x100000 0x100000>;
333 clocks = <&dis 280 clocks = <&display_clocks CLK_BUS_MIXER0>,
334 <&dis 281 <&display_clocks CLK_MIXER0>;
335 clock-names = 282 clock-names = "bus",
336 283 "mod";
337 resets = <&dis 284 resets = <&display_clocks RST_MIXER0>;
338 285
339 ports { 286 ports {
340 #addre 287 #address-cells = <1>;
341 #size- 288 #size-cells = <0>;
342 289
343 mixer0 290 mixer0_out: port@1 {
344 291 #address-cells = <1>;
345 292 #size-cells = <0>;
346 293 reg = <1>;
347 294
348 295 mixer0_out_tcon0: endpoint@0 {
349 296 reg = <0>;
350 297 remote-endpoint = <&tcon0_in_mixer0>;
351 298 };
352 299
353 300 mixer0_out_tcon1: endpoint@1 {
354 301 reg = <1>;
355 302 remote-endpoint = <&tcon1_in_mixer0>;
356 303 };
357 }; 304 };
358 }; 305 };
359 }; 306 };
360 307
361 mixer1: mixer@200000 { 308 mixer1: mixer@200000 {
362 compatible = " 309 compatible = "allwinner,sun50i-a64-de2-mixer-1";
363 reg = <0x20000 310 reg = <0x200000 0x100000>;
364 clocks = <&dis 311 clocks = <&display_clocks CLK_BUS_MIXER1>,
365 <&dis 312 <&display_clocks CLK_MIXER1>;
366 clock-names = 313 clock-names = "bus",
367 314 "mod";
368 resets = <&dis 315 resets = <&display_clocks RST_MIXER1>;
369 316
370 ports { 317 ports {
371 #addre 318 #address-cells = <1>;
372 #size- 319 #size-cells = <0>;
373 320
374 mixer1 321 mixer1_out: port@1 {
375 322 #address-cells = <1>;
376 323 #size-cells = <0>;
377 324 reg = <1>;
378 325
379 326 mixer1_out_tcon0: endpoint@0 {
380 327 reg = <0>;
381 328 remote-endpoint = <&tcon0_in_mixer1>;
382 329 };
383 330
384 331 mixer1_out_tcon1: endpoint@1 {
385 332 reg = <1>;
386 333 remote-endpoint = <&tcon1_in_mixer1>;
387 334 };
388 }; 335 };
389 }; 336 };
390 }; 337 };
391 }; 338 };
392 339
393 syscon: syscon@1c00000 { 340 syscon: syscon@1c00000 {
394 compatible = "allwinne 341 compatible = "allwinner,sun50i-a64-system-control";
395 reg = <0x01c00000 0x10 342 reg = <0x01c00000 0x1000>;
396 #address-cells = <1>; 343 #address-cells = <1>;
397 #size-cells = <1>; 344 #size-cells = <1>;
398 ranges; 345 ranges;
399 346
400 sram_c: sram@18000 { 347 sram_c: sram@18000 {
401 compatible = " 348 compatible = "mmio-sram";
402 reg = <0x00018 349 reg = <0x00018000 0x28000>;
403 #address-cells 350 #address-cells = <1>;
404 #size-cells = 351 #size-cells = <1>;
405 ranges = <0 0x 352 ranges = <0 0x00018000 0x28000>;
406 353
407 de2_sram: sram 354 de2_sram: sram-section@0 {
408 compat 355 compatible = "allwinner,sun50i-a64-sram-c";
409 reg = 356 reg = <0x0000 0x28000>;
410 }; 357 };
411 }; 358 };
412 359
413 sram_c1: sram@1d00000 360 sram_c1: sram@1d00000 {
414 compatible = " 361 compatible = "mmio-sram";
415 reg = <0x01d00 362 reg = <0x01d00000 0x40000>;
416 #address-cells 363 #address-cells = <1>;
417 #size-cells = 364 #size-cells = <1>;
418 ranges = <0 0x 365 ranges = <0 0x01d00000 0x40000>;
419 366
420 ve_sram: sram- 367 ve_sram: sram-section@0 {
421 compat 368 compatible = "allwinner,sun50i-a64-sram-c1",
422 369 "allwinner,sun4i-a10-sram-c1";
423 reg = 370 reg = <0x000000 0x40000>;
424 }; 371 };
425 }; 372 };
426 }; 373 };
427 374
428 dma: dma-controller@1c02000 { 375 dma: dma-controller@1c02000 {
429 compatible = "allwinne 376 compatible = "allwinner,sun50i-a64-dma";
430 reg = <0x01c02000 0x10 377 reg = <0x01c02000 0x1000>;
431 interrupts = <GIC_SPI 378 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&ccu CLK_BUS 379 clocks = <&ccu CLK_BUS_DMA>;
433 dma-channels = <8>; 380 dma-channels = <8>;
434 dma-requests = <27>; 381 dma-requests = <27>;
435 resets = <&ccu RST_BUS 382 resets = <&ccu RST_BUS_DMA>;
436 #dma-cells = <1>; 383 #dma-cells = <1>;
437 }; 384 };
438 385
439 tcon0: lcd-controller@1c0c000 386 tcon0: lcd-controller@1c0c000 {
440 compatible = "allwinne 387 compatible = "allwinner,sun50i-a64-tcon-lcd",
441 "allwinne 388 "allwinner,sun8i-a83t-tcon-lcd";
442 reg = <0x01c0c000 0x10 389 reg = <0x01c0c000 0x1000>;
443 interrupts = <GIC_SPI 390 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
444 clocks = <&ccu CLK_BUS 391 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
445 clock-names = "ahb", " 392 clock-names = "ahb", "tcon-ch0";
446 clock-output-names = " !! 393 clock-output-names = "tcon-pixel-clock";
447 #clock-cells = <0>; 394 #clock-cells = <0>;
448 resets = <&ccu RST_BUS 395 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
449 reset-names = "lcd", " 396 reset-names = "lcd", "lvds";
450 397
451 ports { 398 ports {
452 #address-cells 399 #address-cells = <1>;
453 #size-cells = 400 #size-cells = <0>;
454 401
455 tcon0_in: port 402 tcon0_in: port@0 {
456 #addre 403 #address-cells = <1>;
457 #size- 404 #size-cells = <0>;
458 reg = 405 reg = <0>;
459 406
460 tcon0_ 407 tcon0_in_mixer0: endpoint@0 {
461 408 reg = <0>;
462 409 remote-endpoint = <&mixer0_out_tcon0>;
463 }; 410 };
464 411
465 tcon0_ 412 tcon0_in_mixer1: endpoint@1 {
466 413 reg = <1>;
467 414 remote-endpoint = <&mixer1_out_tcon0>;
468 }; 415 };
469 }; 416 };
470 417
471 tcon0_out: por 418 tcon0_out: port@1 {
472 #addre 419 #address-cells = <1>;
473 #size- 420 #size-cells = <0>;
474 reg = 421 reg = <1>;
475 422
476 tcon0_ 423 tcon0_out_dsi: endpoint@1 {
477 424 reg = <1>;
478 425 remote-endpoint = <&dsi_in_tcon0>;
479 426 allwinner,tcon-channel = <1>;
480 }; 427 };
481 }; 428 };
482 }; 429 };
483 }; 430 };
484 431
485 tcon1: lcd-controller@1c0d000 432 tcon1: lcd-controller@1c0d000 {
486 compatible = "allwinne 433 compatible = "allwinner,sun50i-a64-tcon-tv",
487 "allwinne 434 "allwinner,sun8i-a83t-tcon-tv";
488 reg = <0x01c0d000 0x10 435 reg = <0x01c0d000 0x1000>;
489 interrupts = <GIC_SPI 436 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&ccu CLK_BUS 437 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
491 clock-names = "ahb", " 438 clock-names = "ahb", "tcon-ch1";
492 resets = <&ccu RST_BUS 439 resets = <&ccu RST_BUS_TCON1>;
493 reset-names = "lcd"; 440 reset-names = "lcd";
494 441
495 ports { 442 ports {
496 #address-cells 443 #address-cells = <1>;
497 #size-cells = 444 #size-cells = <0>;
498 445
499 tcon1_in: port 446 tcon1_in: port@0 {
500 #addre 447 #address-cells = <1>;
501 #size- 448 #size-cells = <0>;
502 reg = 449 reg = <0>;
503 450
504 tcon1_ 451 tcon1_in_mixer0: endpoint@0 {
505 452 reg = <0>;
506 453 remote-endpoint = <&mixer0_out_tcon1>;
507 }; 454 };
508 455
509 tcon1_ 456 tcon1_in_mixer1: endpoint@1 {
510 457 reg = <1>;
511 458 remote-endpoint = <&mixer1_out_tcon1>;
512 }; 459 };
513 }; 460 };
514 461
515 tcon1_out: por 462 tcon1_out: port@1 {
516 #addre 463 #address-cells = <1>;
517 #size- 464 #size-cells = <0>;
518 reg = 465 reg = <1>;
519 466
520 tcon1_ 467 tcon1_out_hdmi: endpoint@1 {
521 468 reg = <1>;
522 469 remote-endpoint = <&hdmi_in_tcon1>;
523 }; 470 };
524 }; 471 };
525 }; 472 };
526 }; 473 };
527 474
528 video-codec@1c0e000 { 475 video-codec@1c0e000 {
529 compatible = "allwinne 476 compatible = "allwinner,sun50i-a64-video-engine";
530 reg = <0x01c0e000 0x10 477 reg = <0x01c0e000 0x1000>;
531 clocks = <&ccu CLK_BUS 478 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
532 <&ccu CLK_DRA 479 <&ccu CLK_DRAM_VE>;
533 clock-names = "ahb", " 480 clock-names = "ahb", "mod", "ram";
534 resets = <&ccu RST_BUS 481 resets = <&ccu RST_BUS_VE>;
535 interrupts = <GIC_SPI 482 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
536 allwinner,sram = <&ve_ 483 allwinner,sram = <&ve_sram 1>;
537 }; 484 };
538 485
539 mmc0: mmc@1c0f000 { 486 mmc0: mmc@1c0f000 {
540 compatible = "allwinne 487 compatible = "allwinner,sun50i-a64-mmc";
541 reg = <0x01c0f000 0x10 488 reg = <0x01c0f000 0x1000>;
542 clocks = <&ccu CLK_BUS 489 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
543 clock-names = "ahb", " 490 clock-names = "ahb", "mmc";
544 resets = <&ccu RST_BUS 491 resets = <&ccu RST_BUS_MMC0>;
545 reset-names = "ahb"; 492 reset-names = "ahb";
546 interrupts = <GIC_SPI 493 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
547 max-frequency = <15000 494 max-frequency = <150000000>;
548 status = "disabled"; 495 status = "disabled";
549 #address-cells = <1>; 496 #address-cells = <1>;
550 #size-cells = <0>; 497 #size-cells = <0>;
551 }; 498 };
552 499
553 mmc1: mmc@1c10000 { 500 mmc1: mmc@1c10000 {
554 compatible = "allwinne 501 compatible = "allwinner,sun50i-a64-mmc";
555 reg = <0x01c10000 0x10 502 reg = <0x01c10000 0x1000>;
556 clocks = <&ccu CLK_BUS 503 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
557 clock-names = "ahb", " 504 clock-names = "ahb", "mmc";
558 resets = <&ccu RST_BUS 505 resets = <&ccu RST_BUS_MMC1>;
559 reset-names = "ahb"; 506 reset-names = "ahb";
560 interrupts = <GIC_SPI 507 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
561 max-frequency = <15000 508 max-frequency = <150000000>;
562 status = "disabled"; 509 status = "disabled";
563 #address-cells = <1>; 510 #address-cells = <1>;
564 #size-cells = <0>; 511 #size-cells = <0>;
565 }; 512 };
566 513
567 mmc2: mmc@1c11000 { 514 mmc2: mmc@1c11000 {
568 compatible = "allwinne 515 compatible = "allwinner,sun50i-a64-emmc";
569 reg = <0x01c11000 0x10 516 reg = <0x01c11000 0x1000>;
570 clocks = <&ccu CLK_BUS 517 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
571 clock-names = "ahb", " 518 clock-names = "ahb", "mmc";
572 resets = <&ccu RST_BUS 519 resets = <&ccu RST_BUS_MMC2>;
573 reset-names = "ahb"; 520 reset-names = "ahb";
574 interrupts = <GIC_SPI 521 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
575 max-frequency = <15000 522 max-frequency = <150000000>;
576 status = "disabled"; 523 status = "disabled";
577 #address-cells = <1>; 524 #address-cells = <1>;
578 #size-cells = <0>; 525 #size-cells = <0>;
579 }; 526 };
580 527
581 sid: eeprom@1c14000 { 528 sid: eeprom@1c14000 {
582 compatible = "allwinne 529 compatible = "allwinner,sun50i-a64-sid";
583 reg = <0x1c14000 0x400 530 reg = <0x1c14000 0x400>;
584 #address-cells = <1>; 531 #address-cells = <1>;
585 #size-cells = <1>; 532 #size-cells = <1>;
586 533
587 ths_calibration: therm 534 ths_calibration: thermal-sensor-calibration@34 {
588 reg = <0x34 0x 535 reg = <0x34 0x8>;
589 }; 536 };
590 }; 537 };
591 538
592 crypto: crypto@1c15000 { 539 crypto: crypto@1c15000 {
593 compatible = "allwinne 540 compatible = "allwinner,sun50i-a64-crypto";
594 reg = <0x01c15000 0x10 541 reg = <0x01c15000 0x1000>;
595 interrupts = <GIC_SPI 542 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
596 clocks = <&ccu CLK_BUS 543 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
597 clock-names = "bus", " 544 clock-names = "bus", "mod";
598 resets = <&ccu RST_BUS 545 resets = <&ccu RST_BUS_CE>;
599 }; 546 };
600 547
601 msgbox: mailbox@1c17000 { 548 msgbox: mailbox@1c17000 {
602 compatible = "allwinne 549 compatible = "allwinner,sun50i-a64-msgbox",
603 "allwinne 550 "allwinner,sun6i-a31-msgbox";
604 reg = <0x01c17000 0x10 551 reg = <0x01c17000 0x1000>;
605 clocks = <&ccu CLK_BUS 552 clocks = <&ccu CLK_BUS_MSGBOX>;
606 resets = <&ccu RST_BUS 553 resets = <&ccu RST_BUS_MSGBOX>;
607 interrupts = <GIC_SPI 554 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
608 #mbox-cells = <1>; 555 #mbox-cells = <1>;
609 }; 556 };
610 557
611 usb_otg: usb@1c19000 { 558 usb_otg: usb@1c19000 {
612 compatible = "allwinne 559 compatible = "allwinner,sun8i-a33-musb";
613 reg = <0x01c19000 0x04 560 reg = <0x01c19000 0x0400>;
614 clocks = <&ccu CLK_BUS 561 clocks = <&ccu CLK_BUS_OTG>;
615 resets = <&ccu RST_BUS 562 resets = <&ccu RST_BUS_OTG>;
616 interrupts = <GIC_SPI 563 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
617 interrupt-names = "mc" 564 interrupt-names = "mc";
618 phys = <&usbphy 0>; 565 phys = <&usbphy 0>;
619 phy-names = "usb"; 566 phy-names = "usb";
620 extcon = <&usbphy 0>; 567 extcon = <&usbphy 0>;
621 dr_mode = "otg"; 568 dr_mode = "otg";
622 status = "disabled"; 569 status = "disabled";
623 }; 570 };
624 571
625 usbphy: phy@1c19400 { 572 usbphy: phy@1c19400 {
626 compatible = "allwinne 573 compatible = "allwinner,sun50i-a64-usb-phy";
627 reg = <0x01c19400 0x14 574 reg = <0x01c19400 0x14>,
628 <0x01c1a800 0x4> 575 <0x01c1a800 0x4>,
629 <0x01c1b800 0x4> 576 <0x01c1b800 0x4>;
630 reg-names = "phy_ctrl" 577 reg-names = "phy_ctrl",
631 "pmu0", 578 "pmu0",
632 "pmu1"; 579 "pmu1";
633 clocks = <&ccu CLK_USB 580 clocks = <&ccu CLK_USB_PHY0>,
634 <&ccu CLK_USB 581 <&ccu CLK_USB_PHY1>;
635 clock-names = "usb0_ph 582 clock-names = "usb0_phy",
636 "usb1_ph 583 "usb1_phy";
637 resets = <&ccu RST_USB 584 resets = <&ccu RST_USB_PHY0>,
638 <&ccu RST_USB 585 <&ccu RST_USB_PHY1>;
639 reset-names = "usb0_re 586 reset-names = "usb0_reset",
640 "usb1_re 587 "usb1_reset";
641 status = "disabled"; 588 status = "disabled";
642 #phy-cells = <1>; 589 #phy-cells = <1>;
643 }; 590 };
644 591
645 ehci0: usb@1c1a000 { 592 ehci0: usb@1c1a000 {
646 compatible = "allwinne 593 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
647 reg = <0x01c1a000 0x10 594 reg = <0x01c1a000 0x100>;
648 interrupts = <GIC_SPI 595 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
649 clocks = <&ccu CLK_BUS 596 clocks = <&ccu CLK_BUS_OHCI0>,
650 <&ccu CLK_BUS 597 <&ccu CLK_BUS_EHCI0>,
651 <&ccu CLK_USB 598 <&ccu CLK_USB_OHCI0>;
652 resets = <&ccu RST_BUS 599 resets = <&ccu RST_BUS_OHCI0>,
653 <&ccu RST_BUS 600 <&ccu RST_BUS_EHCI0>;
654 phys = <&usbphy 0>; 601 phys = <&usbphy 0>;
655 phy-names = "usb"; 602 phy-names = "usb";
656 status = "disabled"; 603 status = "disabled";
657 }; 604 };
658 605
659 ohci0: usb@1c1a400 { 606 ohci0: usb@1c1a400 {
660 compatible = "allwinne 607 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
661 reg = <0x01c1a400 0x10 608 reg = <0x01c1a400 0x100>;
662 interrupts = <GIC_SPI 609 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
663 clocks = <&ccu CLK_BUS 610 clocks = <&ccu CLK_BUS_OHCI0>,
664 <&ccu CLK_USB 611 <&ccu CLK_USB_OHCI0>;
665 resets = <&ccu RST_BUS 612 resets = <&ccu RST_BUS_OHCI0>;
666 phys = <&usbphy 0>; 613 phys = <&usbphy 0>;
667 phy-names = "usb"; 614 phy-names = "usb";
668 status = "disabled"; 615 status = "disabled";
669 }; 616 };
670 617
671 ehci1: usb@1c1b000 { 618 ehci1: usb@1c1b000 {
672 compatible = "allwinne 619 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
673 reg = <0x01c1b000 0x10 620 reg = <0x01c1b000 0x100>;
674 interrupts = <GIC_SPI 621 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
675 clocks = <&ccu CLK_BUS 622 clocks = <&ccu CLK_BUS_OHCI1>,
676 <&ccu CLK_BUS 623 <&ccu CLK_BUS_EHCI1>,
677 <&ccu CLK_USB 624 <&ccu CLK_USB_OHCI1>;
678 resets = <&ccu RST_BUS 625 resets = <&ccu RST_BUS_OHCI1>,
679 <&ccu RST_BUS 626 <&ccu RST_BUS_EHCI1>;
680 phys = <&usbphy 1>; 627 phys = <&usbphy 1>;
681 phy-names = "usb"; 628 phy-names = "usb";
682 status = "disabled"; 629 status = "disabled";
683 }; 630 };
684 631
685 ohci1: usb@1c1b400 { 632 ohci1: usb@1c1b400 {
686 compatible = "allwinne 633 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
687 reg = <0x01c1b400 0x10 634 reg = <0x01c1b400 0x100>;
688 interrupts = <GIC_SPI 635 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
689 clocks = <&ccu CLK_BUS 636 clocks = <&ccu CLK_BUS_OHCI1>,
690 <&ccu CLK_USB 637 <&ccu CLK_USB_OHCI1>;
691 resets = <&ccu RST_BUS 638 resets = <&ccu RST_BUS_OHCI1>;
692 phys = <&usbphy 1>; 639 phys = <&usbphy 1>;
693 phy-names = "usb"; 640 phy-names = "usb";
694 status = "disabled"; 641 status = "disabled";
695 }; 642 };
696 643
697 ccu: clock@1c20000 { 644 ccu: clock@1c20000 {
698 compatible = "allwinne 645 compatible = "allwinner,sun50i-a64-ccu";
699 reg = <0x01c20000 0x40 646 reg = <0x01c20000 0x400>;
700 clocks = <&osc24M>, <& !! 647 clocks = <&osc24M>, <&rtc 0>;
701 clock-names = "hosc", 648 clock-names = "hosc", "losc";
702 #clock-cells = <1>; 649 #clock-cells = <1>;
703 #reset-cells = <1>; 650 #reset-cells = <1>;
704 }; 651 };
705 652
706 pio: pinctrl@1c20800 { 653 pio: pinctrl@1c20800 {
707 compatible = "allwinne 654 compatible = "allwinner,sun50i-a64-pinctrl";
708 reg = <0x01c20800 0x40 655 reg = <0x01c20800 0x400>;
709 interrupt-parent = <&r 656 interrupt-parent = <&r_intc>;
710 interrupts = <GIC_SPI 657 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
711 <GIC_SPI 658 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
712 <GIC_SPI 659 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&ccu CLK_BUS !! 660 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
714 <&rtc CLK_OSC <<
715 clock-names = "apb", " 661 clock-names = "apb", "hosc", "losc";
716 gpio-controller; 662 gpio-controller;
717 #gpio-cells = <3>; 663 #gpio-cells = <3>;
718 interrupt-controller; 664 interrupt-controller;
719 #interrupt-cells = <3> 665 #interrupt-cells = <3>;
720 666
721 /omit-if-no-ref/ 667 /omit-if-no-ref/
722 aif2_pins: aif2-pins { 668 aif2_pins: aif2-pins {
723 pins = "PB4", 669 pins = "PB4", "PB5", "PB6", "PB7";
724 function = "ai 670 function = "aif2";
725 }; 671 };
726 672
727 /omit-if-no-ref/ 673 /omit-if-no-ref/
728 aif3_pins: aif3-pins { 674 aif3_pins: aif3-pins {
729 pins = "PG10", 675 pins = "PG10", "PG11", "PG12", "PG13";
730 function = "ai 676 function = "aif3";
731 }; 677 };
732 678
733 csi_pins: csi-pins { 679 csi_pins: csi-pins {
734 pins = "PE0", 680 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
735 "PE7", 681 "PE7", "PE8", "PE9", "PE10", "PE11";
736 function = "cs 682 function = "csi";
737 }; 683 };
738 684
739 /omit-if-no-ref/ 685 /omit-if-no-ref/
740 csi_mclk_pin: csi-mclk 686 csi_mclk_pin: csi-mclk-pin {
741 pins = "PE1"; 687 pins = "PE1";
742 function = "cs 688 function = "csi";
743 }; 689 };
744 690
745 i2c0_pins: i2c0-pins { 691 i2c0_pins: i2c0-pins {
746 pins = "PH0", 692 pins = "PH0", "PH1";
747 function = "i2 693 function = "i2c0";
748 }; 694 };
749 695
750 i2c1_pins: i2c1-pins { 696 i2c1_pins: i2c1-pins {
751 pins = "PH2", 697 pins = "PH2", "PH3";
752 function = "i2 698 function = "i2c1";
753 }; 699 };
754 700
755 i2c2_pins: i2c2-pins { 701 i2c2_pins: i2c2-pins {
756 pins = "PE14", 702 pins = "PE14", "PE15";
757 function = "i2 703 function = "i2c2";
758 }; 704 };
759 705
760 /omit-if-no-ref/ 706 /omit-if-no-ref/
761 lcd_rgb666_pins: lcd-r 707 lcd_rgb666_pins: lcd-rgb666-pins {
762 pins = "PD0", 708 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
763 "PD5", 709 "PD5", "PD6", "PD7", "PD8", "PD9",
764 "PD10", 710 "PD10", "PD11", "PD12", "PD13",
765 "PD14", 711 "PD14", "PD15", "PD16", "PD17",
766 "PD18", 712 "PD18", "PD19", "PD20", "PD21";
767 function = "lc 713 function = "lcd0";
768 }; 714 };
769 715
770 mmc0_pins: mmc0-pins { 716 mmc0_pins: mmc0-pins {
771 pins = "PF0", 717 pins = "PF0", "PF1", "PF2", "PF3",
772 "PF4", 718 "PF4", "PF5";
773 function = "mm 719 function = "mmc0";
774 drive-strength 720 drive-strength = <30>;
775 bias-pull-up; 721 bias-pull-up;
776 }; 722 };
777 723
778 mmc1_pins: mmc1-pins { 724 mmc1_pins: mmc1-pins {
779 pins = "PG0", 725 pins = "PG0", "PG1", "PG2", "PG3",
780 "PG4", 726 "PG4", "PG5";
781 function = "mm 727 function = "mmc1";
782 drive-strength 728 drive-strength = <30>;
783 bias-pull-up; 729 bias-pull-up;
784 }; 730 };
785 731
786 mmc2_pins: mmc2-pins { 732 mmc2_pins: mmc2-pins {
787 pins = "PC5", 733 pins = "PC5", "PC6", "PC8", "PC9",
788 "PC10", 734 "PC10","PC11", "PC12", "PC13",
789 "PC14", 735 "PC14", "PC15", "PC16";
790 function = "mm 736 function = "mmc2";
791 drive-strength 737 drive-strength = <30>;
792 bias-pull-up; 738 bias-pull-up;
793 }; 739 };
794 740
795 mmc2_ds_pin: mmc2-ds-p 741 mmc2_ds_pin: mmc2-ds-pin {
796 pins = "PC1"; 742 pins = "PC1";
797 function = "mm 743 function = "mmc2";
798 drive-strength 744 drive-strength = <30>;
799 bias-pull-up; 745 bias-pull-up;
800 }; 746 };
801 747
802 pwm_pin: pwm-pin { 748 pwm_pin: pwm-pin {
803 pins = "PD22"; 749 pins = "PD22";
804 function = "pw 750 function = "pwm";
805 }; 751 };
806 752
807 rmii_pins: rmii-pins { 753 rmii_pins: rmii-pins {
808 pins = "PD10", 754 pins = "PD10", "PD11", "PD13", "PD14", "PD17",
809 "PD18", 755 "PD18", "PD19", "PD20", "PD22", "PD23";
810 function = "em 756 function = "emac";
811 drive-strength 757 drive-strength = <40>;
812 }; 758 };
813 759
814 rgmii_pins: rgmii-pins 760 rgmii_pins: rgmii-pins {
815 pins = "PD8", 761 pins = "PD8", "PD9", "PD10", "PD11", "PD12",
816 "PD13", 762 "PD13", "PD15", "PD16", "PD17", "PD18",
817 "PD19", 763 "PD19", "PD20", "PD21", "PD22", "PD23";
818 function = "em 764 function = "emac";
819 drive-strength 765 drive-strength = <40>;
820 }; 766 };
821 767
822 spdif_tx_pin: spdif-tx 768 spdif_tx_pin: spdif-tx-pin {
823 pins = "PH8"; 769 pins = "PH8";
824 function = "sp 770 function = "spdif";
825 }; 771 };
826 772
827 spi0_pins: spi0-pins { 773 spi0_pins: spi0-pins {
828 pins = "PC0", 774 pins = "PC0", "PC1", "PC2", "PC3";
829 function = "sp 775 function = "spi0";
830 }; 776 };
831 777
832 spi1_pins: spi1-pins { 778 spi1_pins: spi1-pins {
833 pins = "PD0", 779 pins = "PD0", "PD1", "PD2", "PD3";
834 function = "sp 780 function = "spi1";
835 }; 781 };
836 782
837 uart0_pb_pins: uart0-p 783 uart0_pb_pins: uart0-pb-pins {
838 pins = "PB8", 784 pins = "PB8", "PB9";
839 function = "ua 785 function = "uart0";
840 }; 786 };
841 787
842 uart1_pins: uart1-pins 788 uart1_pins: uart1-pins {
843 pins = "PG6", 789 pins = "PG6", "PG7";
844 function = "ua 790 function = "uart1";
845 }; 791 };
846 792
847 uart1_rts_cts_pins: ua 793 uart1_rts_cts_pins: uart1-rts-cts-pins {
848 pins = "PG8", 794 pins = "PG8", "PG9";
849 function = "ua 795 function = "uart1";
850 }; 796 };
851 797
852 uart2_pins: uart2-pins 798 uart2_pins: uart2-pins {
853 pins = "PB0", 799 pins = "PB0", "PB1";
854 function = "ua 800 function = "uart2";
855 }; 801 };
856 802
857 uart3_pins: uart3-pins 803 uart3_pins: uart3-pins {
858 pins = "PD0", 804 pins = "PD0", "PD1";
859 function = "ua 805 function = "uart3";
860 }; 806 };
861 807
862 uart4_pins: uart4-pins 808 uart4_pins: uart4-pins {
863 pins = "PD2", 809 pins = "PD2", "PD3";
864 function = "ua 810 function = "uart4";
865 }; 811 };
866 812
867 uart4_rts_cts_pins: ua 813 uart4_rts_cts_pins: uart4-rts-cts-pins {
868 pins = "PD4", 814 pins = "PD4", "PD5";
869 function = "ua 815 function = "uart4";
870 }; 816 };
871 }; 817 };
872 818
873 timer@1c20c00 { 819 timer@1c20c00 {
874 compatible = "allwinne 820 compatible = "allwinner,sun50i-a64-timer",
875 "allwinne 821 "allwinner,sun8i-a23-timer";
876 reg = <0x01c20c00 0xa0 822 reg = <0x01c20c00 0xa0>;
877 interrupts = <GIC_SPI 823 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
878 <GIC_SPI 824 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
879 clocks = <&osc24M>; 825 clocks = <&osc24M>;
880 }; 826 };
881 827
882 wdt0: watchdog@1c20ca0 { 828 wdt0: watchdog@1c20ca0 {
883 compatible = "allwinne 829 compatible = "allwinner,sun50i-a64-wdt",
884 "allwinne 830 "allwinner,sun6i-a31-wdt";
885 reg = <0x01c20ca0 0x20 831 reg = <0x01c20ca0 0x20>;
886 interrupts = <GIC_SPI 832 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
887 clocks = <&osc24M>; 833 clocks = <&osc24M>;
888 }; 834 };
889 835
890 spdif: spdif@1c21000 { 836 spdif: spdif@1c21000 {
891 #sound-dai-cells = <0> 837 #sound-dai-cells = <0>;
892 compatible = "allwinne 838 compatible = "allwinner,sun50i-a64-spdif",
893 "allwinne 839 "allwinner,sun8i-h3-spdif";
894 reg = <0x01c21000 0x40 840 reg = <0x01c21000 0x400>;
895 interrupts = <GIC_SPI 841 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
896 clocks = <&ccu CLK_BUS 842 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
897 resets = <&ccu RST_BUS 843 resets = <&ccu RST_BUS_SPDIF>;
898 clock-names = "apb", " 844 clock-names = "apb", "spdif";
899 dmas = <&dma 2>; 845 dmas = <&dma 2>;
900 dma-names = "tx"; 846 dma-names = "tx";
901 pinctrl-names = "defau 847 pinctrl-names = "default";
902 pinctrl-0 = <&spdif_tx 848 pinctrl-0 = <&spdif_tx_pin>;
903 status = "disabled"; 849 status = "disabled";
904 }; 850 };
905 851
906 lradc: lradc@1c21800 { 852 lradc: lradc@1c21800 {
907 compatible = "allwinne 853 compatible = "allwinner,sun50i-a64-lradc",
908 "allwinne 854 "allwinner,sun8i-a83t-r-lradc";
909 reg = <0x01c21800 0x40 855 reg = <0x01c21800 0x400>;
910 interrupt-parent = <&r 856 interrupt-parent = <&r_intc>;
911 interrupts = <GIC_SPI 857 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
912 status = "disabled"; 858 status = "disabled";
913 }; 859 };
914 860
915 i2s0: i2s@1c22000 { 861 i2s0: i2s@1c22000 {
916 #sound-dai-cells = <0> 862 #sound-dai-cells = <0>;
917 compatible = "allwinne 863 compatible = "allwinner,sun50i-a64-i2s",
918 "allwinne 864 "allwinner,sun8i-h3-i2s";
919 reg = <0x01c22000 0x40 865 reg = <0x01c22000 0x400>;
920 interrupts = <GIC_SPI 866 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
921 clocks = <&ccu CLK_BUS 867 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
922 clock-names = "apb", " 868 clock-names = "apb", "mod";
923 resets = <&ccu RST_BUS 869 resets = <&ccu RST_BUS_I2S0>;
924 dma-names = "rx", "tx" 870 dma-names = "rx", "tx";
925 dmas = <&dma 3>, <&dma 871 dmas = <&dma 3>, <&dma 3>;
926 status = "disabled"; 872 status = "disabled";
927 }; 873 };
928 874
929 i2s1: i2s@1c22400 { 875 i2s1: i2s@1c22400 {
930 #sound-dai-cells = <0> 876 #sound-dai-cells = <0>;
931 compatible = "allwinne 877 compatible = "allwinner,sun50i-a64-i2s",
932 "allwinne 878 "allwinner,sun8i-h3-i2s";
933 reg = <0x01c22400 0x40 879 reg = <0x01c22400 0x400>;
934 interrupts = <GIC_SPI 880 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
935 clocks = <&ccu CLK_BUS 881 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
936 clock-names = "apb", " 882 clock-names = "apb", "mod";
937 resets = <&ccu RST_BUS 883 resets = <&ccu RST_BUS_I2S1>;
938 dma-names = "rx", "tx" 884 dma-names = "rx", "tx";
939 dmas = <&dma 4>, <&dma 885 dmas = <&dma 4>, <&dma 4>;
940 status = "disabled"; 886 status = "disabled";
941 }; 887 };
942 888
943 i2s2: i2s@1c22800 { 889 i2s2: i2s@1c22800 {
944 #sound-dai-cells = <0> 890 #sound-dai-cells = <0>;
945 compatible = "allwinne 891 compatible = "allwinner,sun50i-a64-i2s",
946 "allwinne 892 "allwinner,sun8i-h3-i2s";
947 reg = <0x01c22800 0x40 893 reg = <0x01c22800 0x400>;
948 interrupts = <GIC_SPI 894 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
949 clocks = <&ccu CLK_BUS 895 clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
950 clock-names = "apb", " 896 clock-names = "apb", "mod";
951 resets = <&ccu RST_BUS 897 resets = <&ccu RST_BUS_I2S2>;
952 dma-names = "rx", "tx" 898 dma-names = "rx", "tx";
953 dmas = <&dma 27>, <&dm 899 dmas = <&dma 27>, <&dma 27>;
954 status = "disabled"; 900 status = "disabled";
955 }; 901 };
956 902
957 dai: dai@1c22c00 { 903 dai: dai@1c22c00 {
958 #sound-dai-cells = <0> 904 #sound-dai-cells = <0>;
959 compatible = "allwinne 905 compatible = "allwinner,sun50i-a64-codec-i2s";
960 reg = <0x01c22c00 0x20 906 reg = <0x01c22c00 0x200>;
961 interrupts = <GIC_SPI 907 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
962 clocks = <&ccu CLK_BUS 908 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
963 clock-names = "apb", " 909 clock-names = "apb", "mod";
964 resets = <&ccu RST_BUS 910 resets = <&ccu RST_BUS_CODEC>;
965 dmas = <&dma 15>, <&dm 911 dmas = <&dma 15>, <&dma 15>;
966 dma-names = "rx", "tx" 912 dma-names = "rx", "tx";
967 status = "disabled"; 913 status = "disabled";
968 }; 914 };
969 915
970 codec: codec@1c22e00 { 916 codec: codec@1c22e00 {
971 #sound-dai-cells = <1> 917 #sound-dai-cells = <1>;
972 compatible = "allwinne 918 compatible = "allwinner,sun50i-a64-codec",
973 "allwinne 919 "allwinner,sun8i-a33-codec";
974 reg = <0x01c22e00 0x60 920 reg = <0x01c22e00 0x600>;
975 interrupts = <GIC_SPI 921 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
976 clocks = <&ccu CLK_BUS 922 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
977 clock-names = "bus", " 923 clock-names = "bus", "mod";
978 status = "disabled"; 924 status = "disabled";
979 }; 925 };
980 926
981 ths: thermal-sensor@1c25000 { 927 ths: thermal-sensor@1c25000 {
982 compatible = "allwinne 928 compatible = "allwinner,sun50i-a64-ths";
983 reg = <0x01c25000 0x10 929 reg = <0x01c25000 0x100>;
984 clocks = <&ccu CLK_BUS 930 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
985 clock-names = "bus", " 931 clock-names = "bus", "mod";
986 interrupts = <GIC_SPI 932 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
987 resets = <&ccu RST_BUS 933 resets = <&ccu RST_BUS_THS>;
988 nvmem-cells = <&ths_ca 934 nvmem-cells = <&ths_calibration>;
989 nvmem-cell-names = "ca 935 nvmem-cell-names = "calibration";
990 #thermal-sensor-cells 936 #thermal-sensor-cells = <1>;
991 }; 937 };
992 938
993 uart0: serial@1c28000 { 939 uart0: serial@1c28000 {
994 compatible = "snps,dw- 940 compatible = "snps,dw-apb-uart";
995 reg = <0x01c28000 0x40 941 reg = <0x01c28000 0x400>;
996 interrupts = <GIC_SPI 942 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
997 reg-shift = <2>; 943 reg-shift = <2>;
998 reg-io-width = <4>; 944 reg-io-width = <4>;
999 clocks = <&ccu CLK_BUS 945 clocks = <&ccu CLK_BUS_UART0>;
1000 resets = <&ccu RST_BU 946 resets = <&ccu RST_BUS_UART0>;
1001 status = "disabled"; 947 status = "disabled";
1002 }; 948 };
1003 949
1004 uart1: serial@1c28400 { 950 uart1: serial@1c28400 {
1005 compatible = "snps,dw 951 compatible = "snps,dw-apb-uart";
1006 reg = <0x01c28400 0x4 952 reg = <0x01c28400 0x400>;
1007 interrupts = <GIC_SPI 953 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1008 reg-shift = <2>; 954 reg-shift = <2>;
1009 reg-io-width = <4>; 955 reg-io-width = <4>;
1010 clocks = <&ccu CLK_BU 956 clocks = <&ccu CLK_BUS_UART1>;
1011 resets = <&ccu RST_BU 957 resets = <&ccu RST_BUS_UART1>;
1012 status = "disabled"; 958 status = "disabled";
1013 }; 959 };
1014 960
1015 uart2: serial@1c28800 { 961 uart2: serial@1c28800 {
1016 compatible = "snps,dw 962 compatible = "snps,dw-apb-uart";
1017 reg = <0x01c28800 0x4 963 reg = <0x01c28800 0x400>;
1018 interrupts = <GIC_SPI 964 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1019 reg-shift = <2>; 965 reg-shift = <2>;
1020 reg-io-width = <4>; 966 reg-io-width = <4>;
1021 clocks = <&ccu CLK_BU 967 clocks = <&ccu CLK_BUS_UART2>;
1022 resets = <&ccu RST_BU 968 resets = <&ccu RST_BUS_UART2>;
1023 status = "disabled"; 969 status = "disabled";
1024 }; 970 };
1025 971
1026 uart3: serial@1c28c00 { 972 uart3: serial@1c28c00 {
1027 compatible = "snps,dw 973 compatible = "snps,dw-apb-uart";
1028 reg = <0x01c28c00 0x4 974 reg = <0x01c28c00 0x400>;
1029 interrupts = <GIC_SPI 975 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1030 reg-shift = <2>; 976 reg-shift = <2>;
1031 reg-io-width = <4>; 977 reg-io-width = <4>;
1032 clocks = <&ccu CLK_BU 978 clocks = <&ccu CLK_BUS_UART3>;
1033 resets = <&ccu RST_BU 979 resets = <&ccu RST_BUS_UART3>;
1034 status = "disabled"; 980 status = "disabled";
1035 }; 981 };
1036 982
1037 uart4: serial@1c29000 { 983 uart4: serial@1c29000 {
1038 compatible = "snps,dw 984 compatible = "snps,dw-apb-uart";
1039 reg = <0x01c29000 0x4 985 reg = <0x01c29000 0x400>;
1040 interrupts = <GIC_SPI 986 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1041 reg-shift = <2>; 987 reg-shift = <2>;
1042 reg-io-width = <4>; 988 reg-io-width = <4>;
1043 clocks = <&ccu CLK_BU 989 clocks = <&ccu CLK_BUS_UART4>;
1044 resets = <&ccu RST_BU 990 resets = <&ccu RST_BUS_UART4>;
1045 status = "disabled"; 991 status = "disabled";
1046 }; 992 };
1047 993
1048 i2c0: i2c@1c2ac00 { 994 i2c0: i2c@1c2ac00 {
1049 compatible = "allwinn 995 compatible = "allwinner,sun6i-a31-i2c";
1050 reg = <0x01c2ac00 0x4 996 reg = <0x01c2ac00 0x400>;
1051 interrupts = <GIC_SPI 997 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1052 clocks = <&ccu CLK_BU 998 clocks = <&ccu CLK_BUS_I2C0>;
1053 resets = <&ccu RST_BU 999 resets = <&ccu RST_BUS_I2C0>;
1054 pinctrl-names = "defa 1000 pinctrl-names = "default";
1055 pinctrl-0 = <&i2c0_pi 1001 pinctrl-0 = <&i2c0_pins>;
1056 status = "disabled"; 1002 status = "disabled";
1057 #address-cells = <1>; 1003 #address-cells = <1>;
1058 #size-cells = <0>; 1004 #size-cells = <0>;
1059 }; 1005 };
1060 1006
1061 i2c1: i2c@1c2b000 { 1007 i2c1: i2c@1c2b000 {
1062 compatible = "allwinn 1008 compatible = "allwinner,sun6i-a31-i2c";
1063 reg = <0x01c2b000 0x4 1009 reg = <0x01c2b000 0x400>;
1064 interrupts = <GIC_SPI 1010 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1065 clocks = <&ccu CLK_BU 1011 clocks = <&ccu CLK_BUS_I2C1>;
1066 resets = <&ccu RST_BU 1012 resets = <&ccu RST_BUS_I2C1>;
1067 pinctrl-names = "defa 1013 pinctrl-names = "default";
1068 pinctrl-0 = <&i2c1_pi 1014 pinctrl-0 = <&i2c1_pins>;
1069 status = "disabled"; 1015 status = "disabled";
1070 #address-cells = <1>; 1016 #address-cells = <1>;
1071 #size-cells = <0>; 1017 #size-cells = <0>;
1072 }; 1018 };
1073 1019
1074 i2c2: i2c@1c2b400 { 1020 i2c2: i2c@1c2b400 {
1075 compatible = "allwinn 1021 compatible = "allwinner,sun6i-a31-i2c";
1076 reg = <0x01c2b400 0x4 1022 reg = <0x01c2b400 0x400>;
1077 interrupts = <GIC_SPI 1023 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1078 clocks = <&ccu CLK_BU 1024 clocks = <&ccu CLK_BUS_I2C2>;
1079 resets = <&ccu RST_BU 1025 resets = <&ccu RST_BUS_I2C2>;
1080 pinctrl-names = "defa 1026 pinctrl-names = "default";
1081 pinctrl-0 = <&i2c2_pi 1027 pinctrl-0 = <&i2c2_pins>;
1082 status = "disabled"; 1028 status = "disabled";
1083 #address-cells = <1>; 1029 #address-cells = <1>;
1084 #size-cells = <0>; 1030 #size-cells = <0>;
1085 }; 1031 };
1086 1032
1087 spi0: spi@1c68000 { 1033 spi0: spi@1c68000 {
1088 compatible = "allwinn 1034 compatible = "allwinner,sun8i-h3-spi";
1089 reg = <0x01c68000 0x1 1035 reg = <0x01c68000 0x1000>;
1090 interrupts = <GIC_SPI 1036 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1091 clocks = <&ccu CLK_BU 1037 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
1092 clock-names = "ahb", 1038 clock-names = "ahb", "mod";
1093 dmas = <&dma 23>, <&d 1039 dmas = <&dma 23>, <&dma 23>;
1094 dma-names = "rx", "tx 1040 dma-names = "rx", "tx";
1095 pinctrl-names = "defa 1041 pinctrl-names = "default";
1096 pinctrl-0 = <&spi0_pi 1042 pinctrl-0 = <&spi0_pins>;
1097 resets = <&ccu RST_BU 1043 resets = <&ccu RST_BUS_SPI0>;
1098 status = "disabled"; 1044 status = "disabled";
1099 num-cs = <1>; 1045 num-cs = <1>;
1100 #address-cells = <1>; 1046 #address-cells = <1>;
1101 #size-cells = <0>; 1047 #size-cells = <0>;
1102 }; 1048 };
1103 1049
1104 spi1: spi@1c69000 { 1050 spi1: spi@1c69000 {
1105 compatible = "allwinn 1051 compatible = "allwinner,sun8i-h3-spi";
1106 reg = <0x01c69000 0x1 1052 reg = <0x01c69000 0x1000>;
1107 interrupts = <GIC_SPI 1053 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1108 clocks = <&ccu CLK_BU 1054 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
1109 clock-names = "ahb", 1055 clock-names = "ahb", "mod";
1110 dmas = <&dma 24>, <&d 1056 dmas = <&dma 24>, <&dma 24>;
1111 dma-names = "rx", "tx 1057 dma-names = "rx", "tx";
1112 pinctrl-names = "defa 1058 pinctrl-names = "default";
1113 pinctrl-0 = <&spi1_pi 1059 pinctrl-0 = <&spi1_pins>;
1114 resets = <&ccu RST_BU 1060 resets = <&ccu RST_BUS_SPI1>;
1115 status = "disabled"; 1061 status = "disabled";
1116 num-cs = <1>; 1062 num-cs = <1>;
1117 #address-cells = <1>; 1063 #address-cells = <1>;
1118 #size-cells = <0>; 1064 #size-cells = <0>;
1119 }; 1065 };
1120 1066
1121 emac: ethernet@1c30000 { 1067 emac: ethernet@1c30000 {
1122 compatible = "allwinn 1068 compatible = "allwinner,sun50i-a64-emac";
1123 syscon = <&syscon>; 1069 syscon = <&syscon>;
1124 reg = <0x01c30000 0x1 1070 reg = <0x01c30000 0x10000>;
1125 interrupts = <GIC_SPI 1071 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1126 interrupt-names = "ma 1072 interrupt-names = "macirq";
1127 resets = <&ccu RST_BU 1073 resets = <&ccu RST_BUS_EMAC>;
1128 reset-names = "stmmac 1074 reset-names = "stmmaceth";
1129 clocks = <&ccu CLK_BU 1075 clocks = <&ccu CLK_BUS_EMAC>;
1130 clock-names = "stmmac 1076 clock-names = "stmmaceth";
1131 status = "disabled"; 1077 status = "disabled";
1132 1078
1133 mdio: mdio { 1079 mdio: mdio {
1134 compatible = 1080 compatible = "snps,dwmac-mdio";
1135 #address-cell 1081 #address-cells = <1>;
1136 #size-cells = 1082 #size-cells = <0>;
1137 }; 1083 };
1138 }; 1084 };
1139 1085
1140 mali: gpu@1c40000 { 1086 mali: gpu@1c40000 {
1141 compatible = "allwinn 1087 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400";
1142 reg = <0x01c40000 0x1 1088 reg = <0x01c40000 0x10000>;
1143 interrupts = <GIC_SPI 1089 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1144 <GIC_SPI 1090 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1145 <GIC_SPI 1091 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1146 <GIC_SPI 1092 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1147 <GIC_SPI 1093 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1148 <GIC_SPI 1094 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1149 <GIC_SPI 1095 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1150 interrupt-names = "gp 1096 interrupt-names = "gp",
1151 "gp 1097 "gpmmu",
1152 "pp 1098 "pp0",
1153 "pp 1099 "ppmmu0",
1154 "pp 1100 "pp1",
1155 "pp 1101 "ppmmu1",
1156 "pm 1102 "pmu";
1157 clocks = <&ccu CLK_BU 1103 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
1158 clock-names = "bus", 1104 clock-names = "bus", "core";
1159 resets = <&ccu RST_BU 1105 resets = <&ccu RST_BUS_GPU>;
1160 operating-points-v2 = <<
1161 }; 1106 };
1162 1107
1163 gic: interrupt-controller@1c8 1108 gic: interrupt-controller@1c81000 {
1164 compatible = "arm,gic 1109 compatible = "arm,gic-400";
1165 reg = <0x01c81000 0x1 1110 reg = <0x01c81000 0x1000>,
1166 <0x01c82000 0x2 1111 <0x01c82000 0x2000>,
1167 <0x01c84000 0x2 1112 <0x01c84000 0x2000>,
1168 <0x01c86000 0x2 1113 <0x01c86000 0x2000>;
1169 interrupts = <GIC_PPI 1114 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1170 interrupt-controller; 1115 interrupt-controller;
1171 #interrupt-cells = <3 1116 #interrupt-cells = <3>;
1172 }; 1117 };
1173 1118
1174 pwm: pwm@1c21400 { 1119 pwm: pwm@1c21400 {
1175 compatible = "allwinn 1120 compatible = "allwinner,sun50i-a64-pwm",
1176 "allwinn 1121 "allwinner,sun5i-a13-pwm";
1177 reg = <0x01c21400 0x4 1122 reg = <0x01c21400 0x400>;
1178 clocks = <&osc24M>; 1123 clocks = <&osc24M>;
1179 pinctrl-names = "defa 1124 pinctrl-names = "default";
1180 pinctrl-0 = <&pwm_pin 1125 pinctrl-0 = <&pwm_pin>;
1181 #pwm-cells = <3>; 1126 #pwm-cells = <3>;
1182 status = "disabled"; 1127 status = "disabled";
1183 }; 1128 };
1184 1129
1185 mbus: dram-controller@1c62000 1130 mbus: dram-controller@1c62000 {
1186 compatible = "allwinn 1131 compatible = "allwinner,sun50i-a64-mbus";
1187 reg = <0x01c62000 0x1 !! 1132 reg = <0x01c62000 0x1000>;
1188 <0x01c63000 0x1 !! 1133 clocks = <&ccu 112>;
1189 reg-names = "mbus", " <<
1190 clocks = <&ccu CLK_MB <<
1191 <&ccu CLK_DR <<
1192 <&ccu CLK_BU <<
1193 clock-names = "mbus", <<
1194 interrupts = <GIC_SPI <<
1195 #address-cells = <1>; 1134 #address-cells = <1>;
1196 #size-cells = <1>; 1135 #size-cells = <1>;
1197 dma-ranges = <0x00000 1136 dma-ranges = <0x00000000 0x40000000 0xc0000000>;
1198 #interconnect-cells = 1137 #interconnect-cells = <1>;
1199 }; 1138 };
1200 1139
1201 csi: csi@1cb0000 { 1140 csi: csi@1cb0000 {
1202 compatible = "allwinn 1141 compatible = "allwinner,sun50i-a64-csi";
1203 reg = <0x01cb0000 0x1 1142 reg = <0x01cb0000 0x1000>;
1204 interrupts = <GIC_SPI 1143 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1205 clocks = <&ccu CLK_BU 1144 clocks = <&ccu CLK_BUS_CSI>,
1206 <&ccu CLK_CS 1145 <&ccu CLK_CSI_SCLK>,
1207 <&ccu CLK_DR 1146 <&ccu CLK_DRAM_CSI>;
1208 clock-names = "bus", 1147 clock-names = "bus", "mod", "ram";
1209 resets = <&ccu RST_BU 1148 resets = <&ccu RST_BUS_CSI>;
1210 pinctrl-names = "defa 1149 pinctrl-names = "default";
1211 pinctrl-0 = <&csi_pin 1150 pinctrl-0 = <&csi_pins>;
1212 status = "disabled"; 1151 status = "disabled";
1213 }; 1152 };
1214 1153
1215 dsi: dsi@1ca0000 { 1154 dsi: dsi@1ca0000 {
1216 compatible = "allwinn 1155 compatible = "allwinner,sun50i-a64-mipi-dsi";
1217 reg = <0x01ca0000 0x1 1156 reg = <0x01ca0000 0x1000>;
1218 interrupts = <GIC_SPI 1157 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1219 clocks = <&ccu CLK_BU 1158 clocks = <&ccu CLK_BUS_MIPI_DSI>;
1220 resets = <&ccu RST_BU 1159 resets = <&ccu RST_BUS_MIPI_DSI>;
1221 phys = <&dphy>; 1160 phys = <&dphy>;
1222 phy-names = "dphy"; 1161 phy-names = "dphy";
1223 status = "disabled"; 1162 status = "disabled";
1224 #address-cells = <1>; 1163 #address-cells = <1>;
1225 #size-cells = <0>; 1164 #size-cells = <0>;
1226 1165
1227 port { 1166 port {
1228 dsi_in_tcon0: 1167 dsi_in_tcon0: endpoint {
1229 remot 1168 remote-endpoint = <&tcon0_out_dsi>;
1230 }; 1169 };
1231 }; 1170 };
1232 }; 1171 };
1233 1172
1234 dphy: d-phy@1ca1000 { 1173 dphy: d-phy@1ca1000 {
1235 compatible = "allwinn 1174 compatible = "allwinner,sun50i-a64-mipi-dphy",
1236 "allwinn 1175 "allwinner,sun6i-a31-mipi-dphy";
1237 reg = <0x01ca1000 0x1 1176 reg = <0x01ca1000 0x1000>;
1238 interrupts = <GIC_SPI <<
1239 clocks = <&ccu CLK_BU 1177 clocks = <&ccu CLK_BUS_MIPI_DSI>,
1240 <&ccu CLK_DS 1178 <&ccu CLK_DSI_DPHY>;
1241 clock-names = "bus", 1179 clock-names = "bus", "mod";
1242 resets = <&ccu RST_BU 1180 resets = <&ccu RST_BUS_MIPI_DSI>;
1243 status = "disabled"; 1181 status = "disabled";
1244 #phy-cells = <0>; 1182 #phy-cells = <0>;
1245 }; 1183 };
1246 1184
1247 deinterlace: deinterlace@1e00 1185 deinterlace: deinterlace@1e00000 {
1248 compatible = "allwinn 1186 compatible = "allwinner,sun50i-a64-deinterlace",
1249 "allwinn 1187 "allwinner,sun8i-h3-deinterlace";
1250 reg = <0x01e00000 0x2 1188 reg = <0x01e00000 0x20000>;
1251 clocks = <&ccu CLK_BU 1189 clocks = <&ccu CLK_BUS_DEINTERLACE>,
1252 <&ccu CLK_DE 1190 <&ccu CLK_DEINTERLACE>,
1253 <&ccu CLK_DR 1191 <&ccu CLK_DRAM_DEINTERLACE>;
1254 clock-names = "bus", 1192 clock-names = "bus", "mod", "ram";
1255 resets = <&ccu RST_BU 1193 resets = <&ccu RST_BUS_DEINTERLACE>;
1256 interrupts = <GIC_SPI 1194 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1257 interconnects = <&mbu 1195 interconnects = <&mbus 9>;
1258 interconnect-names = 1196 interconnect-names = "dma-mem";
1259 }; 1197 };
1260 1198
1261 hdmi: hdmi@1ee0000 { 1199 hdmi: hdmi@1ee0000 {
1262 compatible = "allwinn 1200 compatible = "allwinner,sun50i-a64-dw-hdmi",
1263 "allwinn 1201 "allwinner,sun8i-a83t-dw-hdmi";
1264 reg = <0x01ee0000 0x1 1202 reg = <0x01ee0000 0x10000>;
1265 reg-io-width = <1>; 1203 reg-io-width = <1>;
1266 interrupts = <GIC_SPI 1204 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1267 clocks = <&ccu CLK_BU 1205 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1268 <&ccu CLK_HD !! 1206 <&ccu CLK_HDMI>;
1269 clock-names = "iahb", !! 1207 clock-names = "iahb", "isfr", "tmds";
1270 resets = <&ccu RST_BU 1208 resets = <&ccu RST_BUS_HDMI1>;
1271 reset-names = "ctrl"; 1209 reset-names = "ctrl";
1272 phys = <&hdmi_phy>; 1210 phys = <&hdmi_phy>;
1273 phy-names = "phy"; 1211 phy-names = "phy";
1274 status = "disabled"; 1212 status = "disabled";
1275 1213
1276 ports { 1214 ports {
1277 #address-cell 1215 #address-cells = <1>;
1278 #size-cells = 1216 #size-cells = <0>;
1279 1217
1280 hdmi_in: port 1218 hdmi_in: port@0 {
1281 reg = 1219 reg = <0>;
1282 1220
1283 hdmi_ 1221 hdmi_in_tcon1: endpoint {
1284 1222 remote-endpoint = <&tcon1_out_hdmi>;
1285 }; 1223 };
1286 }; 1224 };
1287 1225
1288 hdmi_out: por 1226 hdmi_out: port@1 {
1289 reg = 1227 reg = <1>;
1290 }; 1228 };
1291 }; 1229 };
1292 }; 1230 };
1293 1231
1294 hdmi_phy: hdmi-phy@1ef0000 { 1232 hdmi_phy: hdmi-phy@1ef0000 {
1295 compatible = "allwinn 1233 compatible = "allwinner,sun50i-a64-hdmi-phy";
1296 reg = <0x01ef0000 0x1 1234 reg = <0x01ef0000 0x10000>;
1297 clocks = <&ccu CLK_BU 1235 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1298 <&ccu CLK_PL 1236 <&ccu CLK_PLL_VIDEO0>;
1299 clock-names = "bus", 1237 clock-names = "bus", "mod", "pll-0";
1300 resets = <&ccu RST_BU 1238 resets = <&ccu RST_BUS_HDMI0>;
1301 reset-names = "phy"; 1239 reset-names = "phy";
1302 #phy-cells = <0>; 1240 #phy-cells = <0>;
1303 }; 1241 };
1304 1242
1305 rtc: rtc@1f00000 { 1243 rtc: rtc@1f00000 {
1306 compatible = "allwinn 1244 compatible = "allwinner,sun50i-a64-rtc",
1307 "allwinn 1245 "allwinner,sun8i-h3-rtc";
1308 reg = <0x01f00000 0x4 1246 reg = <0x01f00000 0x400>;
1309 interrupt-parent = <& 1247 interrupt-parent = <&r_intc>;
1310 interrupts = <GIC_SPI 1248 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1311 <GIC_SPI 1249 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1312 clock-output-names = 1250 clock-output-names = "osc32k", "osc32k-out", "iosc";
1313 clocks = <&osc32k>; 1251 clocks = <&osc32k>;
1314 #clock-cells = <1>; 1252 #clock-cells = <1>;
1315 }; 1253 };
1316 1254
1317 r_intc: interrupt-controller@ 1255 r_intc: interrupt-controller@1f00c00 {
1318 compatible = "allwinn 1256 compatible = "allwinner,sun50i-a64-r-intc",
1319 "allwinn 1257 "allwinner,sun6i-a31-r-intc";
1320 interrupt-controller; 1258 interrupt-controller;
1321 #interrupt-cells = <3 1259 #interrupt-cells = <3>;
1322 reg = <0x01f00c00 0x4 1260 reg = <0x01f00c00 0x400>;
1323 interrupts = <GIC_SPI 1261 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1324 }; 1262 };
1325 1263
1326 r_ccu: clock@1f01400 { 1264 r_ccu: clock@1f01400 {
1327 compatible = "allwinn 1265 compatible = "allwinner,sun50i-a64-r-ccu";
1328 reg = <0x01f01400 0x1 1266 reg = <0x01f01400 0x100>;
1329 clocks = <&osc24M>, < !! 1267 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
1330 <&ccu CLK_PL 1268 <&ccu CLK_PLL_PERIPH0>;
1331 clock-names = "hosc", 1269 clock-names = "hosc", "losc", "iosc", "pll-periph";
1332 #clock-cells = <1>; 1270 #clock-cells = <1>;
1333 #reset-cells = <1>; 1271 #reset-cells = <1>;
1334 }; 1272 };
1335 1273
1336 codec_analog: codec-analog@1f 1274 codec_analog: codec-analog@1f015c0 {
1337 compatible = "allwinn 1275 compatible = "allwinner,sun50i-a64-codec-analog";
1338 reg = <0x01f015c0 0x4 1276 reg = <0x01f015c0 0x4>;
1339 status = "disabled"; 1277 status = "disabled";
1340 }; 1278 };
1341 1279
1342 r_i2c: i2c@1f02400 { 1280 r_i2c: i2c@1f02400 {
1343 compatible = "allwinn 1281 compatible = "allwinner,sun50i-a64-i2c",
1344 "allwinn 1282 "allwinner,sun6i-a31-i2c";
1345 reg = <0x01f02400 0x4 1283 reg = <0x01f02400 0x400>;
1346 interrupts = <GIC_SPI 1284 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1347 clocks = <&r_ccu CLK_ 1285 clocks = <&r_ccu CLK_APB0_I2C>;
1348 resets = <&r_ccu RST_ 1286 resets = <&r_ccu RST_APB0_I2C>;
1349 status = "disabled"; 1287 status = "disabled";
1350 #address-cells = <1>; 1288 #address-cells = <1>;
1351 #size-cells = <0>; 1289 #size-cells = <0>;
1352 }; 1290 };
1353 1291
1354 r_ir: ir@1f02000 { 1292 r_ir: ir@1f02000 {
1355 compatible = "allwinn 1293 compatible = "allwinner,sun50i-a64-ir",
1356 "allwinn 1294 "allwinner,sun6i-a31-ir";
1357 reg = <0x01f02000 0x4 1295 reg = <0x01f02000 0x400>;
1358 clocks = <&r_ccu CLK_ 1296 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
1359 clock-names = "apb", 1297 clock-names = "apb", "ir";
1360 resets = <&r_ccu RST_ 1298 resets = <&r_ccu RST_APB0_IR>;
1361 interrupts = <GIC_SPI 1299 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1362 pinctrl-names = "defa 1300 pinctrl-names = "default";
1363 pinctrl-0 = <&r_ir_rx 1301 pinctrl-0 = <&r_ir_rx_pin>;
1364 status = "disabled"; 1302 status = "disabled";
1365 }; 1303 };
1366 1304
1367 r_pwm: pwm@1f03800 { 1305 r_pwm: pwm@1f03800 {
1368 compatible = "allwinn 1306 compatible = "allwinner,sun50i-a64-pwm",
1369 "allwinn 1307 "allwinner,sun5i-a13-pwm";
1370 reg = <0x01f03800 0x4 1308 reg = <0x01f03800 0x400>;
1371 clocks = <&osc24M>; 1309 clocks = <&osc24M>;
1372 pinctrl-names = "defa 1310 pinctrl-names = "default";
1373 pinctrl-0 = <&r_pwm_p 1311 pinctrl-0 = <&r_pwm_pin>;
1374 #pwm-cells = <3>; 1312 #pwm-cells = <3>;
1375 status = "disabled"; 1313 status = "disabled";
1376 }; 1314 };
1377 1315
1378 r_pio: pinctrl@1f02c00 { 1316 r_pio: pinctrl@1f02c00 {
1379 compatible = "allwinn 1317 compatible = "allwinner,sun50i-a64-r-pinctrl";
1380 reg = <0x01f02c00 0x4 1318 reg = <0x01f02c00 0x400>;
1381 interrupt-parent = <& 1319 interrupt-parent = <&r_intc>;
1382 interrupts = <GIC_SPI 1320 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1383 clocks = <&r_ccu CLK_ 1321 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
1384 clock-names = "apb", 1322 clock-names = "apb", "hosc", "losc";
1385 gpio-controller; 1323 gpio-controller;
1386 #gpio-cells = <3>; 1324 #gpio-cells = <3>;
1387 interrupt-controller; 1325 interrupt-controller;
1388 #interrupt-cells = <3 1326 #interrupt-cells = <3>;
1389 1327
1390 r_i2c_pl89_pins: r-i2 1328 r_i2c_pl89_pins: r-i2c-pl89-pins {
1391 pins = "PL8", 1329 pins = "PL8", "PL9";
1392 function = "s 1330 function = "s_i2c";
1393 }; 1331 };
1394 1332
1395 r_ir_rx_pin: r-ir-rx- 1333 r_ir_rx_pin: r-ir-rx-pin {
1396 pins = "PL11" 1334 pins = "PL11";
1397 function = "s 1335 function = "s_cir_rx";
1398 }; 1336 };
1399 1337
1400 r_pwm_pin: r-pwm-pin 1338 r_pwm_pin: r-pwm-pin {
1401 pins = "PL10" 1339 pins = "PL10";
1402 function = "s 1340 function = "s_pwm";
1403 }; 1341 };
1404 1342
1405 r_rsb_pins: r-rsb-pin 1343 r_rsb_pins: r-rsb-pins {
1406 pins = "PL0", 1344 pins = "PL0", "PL1";
1407 function = "s 1345 function = "s_rsb";
1408 }; 1346 };
1409 }; 1347 };
1410 1348
1411 r_rsb: rsb@1f03400 { 1349 r_rsb: rsb@1f03400 {
1412 compatible = "allwinn 1350 compatible = "allwinner,sun8i-a23-rsb";
1413 reg = <0x01f03400 0x4 1351 reg = <0x01f03400 0x400>;
1414 interrupts = <GIC_SPI 1352 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1415 clocks = <&r_ccu 6>; 1353 clocks = <&r_ccu 6>;
1416 clock-frequency = <30 1354 clock-frequency = <3000000>;
1417 resets = <&r_ccu 2>; 1355 resets = <&r_ccu 2>;
1418 pinctrl-names = "defa 1356 pinctrl-names = "default";
1419 pinctrl-0 = <&r_rsb_p 1357 pinctrl-0 = <&r_rsb_pins>;
1420 status = "disabled"; 1358 status = "disabled";
1421 #address-cells = <1>; 1359 #address-cells = <1>;
1422 #size-cells = <0>; 1360 #size-cells = <0>;
1423 }; 1361 };
1424 }; 1362 };
1425 }; 1363 };
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