1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2016 ARM Ltd. 2 // Copyright (C) 2016 ARM Ltd.
3 // based on the Allwinner H3 dtsi: 3 // based on the Allwinner H3 dtsi:
4 // Copyright (C) 2015 Jens Kuske <jenskuske@ 4 // Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
5 5
6 #include <dt-bindings/clock/sun50i-a64-ccu.h> 6 #include <dt-bindings/clock/sun50i-a64-ccu.h>
7 #include <dt-bindings/clock/sun6i-rtc.h> <<
8 #include <dt-bindings/clock/sun8i-de2.h> 7 #include <dt-bindings/clock/sun8i-de2.h>
9 #include <dt-bindings/clock/sun8i-r-ccu.h> 8 #include <dt-bindings/clock/sun8i-r-ccu.h>
10 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/sun50i-a64-ccu.h> 10 #include <dt-bindings/reset/sun50i-a64-ccu.h>
12 #include <dt-bindings/reset/sun8i-de2.h> 11 #include <dt-bindings/reset/sun8i-de2.h>
13 #include <dt-bindings/reset/sun8i-r-ccu.h> 12 #include <dt-bindings/reset/sun8i-r-ccu.h>
14 #include <dt-bindings/thermal/thermal.h> 13 #include <dt-bindings/thermal/thermal.h>
15 14
16 / { 15 / {
17 interrupt-parent = <&gic>; 16 interrupt-parent = <&gic>;
18 #address-cells = <1>; 17 #address-cells = <1>;
19 #size-cells = <1>; 18 #size-cells = <1>;
20 19
21 chosen { 20 chosen {
22 #address-cells = <1>; 21 #address-cells = <1>;
23 #size-cells = <1>; 22 #size-cells = <1>;
24 ranges; 23 ranges;
25 24
26 simplefb_lcd: framebuffer-lcd 25 simplefb_lcd: framebuffer-lcd {
27 compatible = "allwinne 26 compatible = "allwinner,simple-framebuffer",
28 "simple-f 27 "simple-framebuffer";
29 allwinner,pipeline = " 28 allwinner,pipeline = "mixer0-lcd0";
30 clocks = <&ccu CLK_TCO 29 clocks = <&ccu CLK_TCON0>,
31 <&display_clo 30 <&display_clocks CLK_MIXER0>;
32 status = "disabled"; 31 status = "disabled";
33 }; 32 };
34 33
35 simplefb_hdmi: framebuffer-hdm 34 simplefb_hdmi: framebuffer-hdmi {
36 compatible = "allwinne 35 compatible = "allwinner,simple-framebuffer",
37 "simple-f 36 "simple-framebuffer";
38 allwinner,pipeline = " 37 allwinner,pipeline = "mixer1-lcd1-hdmi";
39 clocks = <&display_clo 38 clocks = <&display_clocks CLK_MIXER1>,
40 <&ccu CLK_TCO 39 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
41 status = "disabled"; 40 status = "disabled";
42 }; 41 };
43 }; 42 };
44 43
45 cpus { 44 cpus {
46 #address-cells = <1>; 45 #address-cells = <1>;
47 #size-cells = <0>; 46 #size-cells = <0>;
48 47
49 cpu0: cpu@0 { 48 cpu0: cpu@0 {
50 compatible = "arm,cort 49 compatible = "arm,cortex-a53";
51 device_type = "cpu"; 50 device_type = "cpu";
52 reg = <0>; 51 reg = <0>;
53 enable-method = "psci" 52 enable-method = "psci";
>> 53 next-level-cache = <&L2>;
54 clocks = <&ccu CLK_CPU 54 clocks = <&ccu CLK_CPUX>;
55 clock-names = "cpu"; 55 clock-names = "cpu";
56 #cooling-cells = <2>; 56 #cooling-cells = <2>;
57 i-cache-size = <0x8000 <<
58 i-cache-line-size = <6 <<
59 i-cache-sets = <256>; <<
60 d-cache-size = <0x8000 <<
61 d-cache-line-size = <6 <<
62 d-cache-sets = <128>; <<
63 next-level-cache = <&l <<
64 }; 57 };
65 58
66 cpu1: cpu@1 { 59 cpu1: cpu@1 {
67 compatible = "arm,cort 60 compatible = "arm,cortex-a53";
68 device_type = "cpu"; 61 device_type = "cpu";
69 reg = <1>; 62 reg = <1>;
70 enable-method = "psci" 63 enable-method = "psci";
>> 64 next-level-cache = <&L2>;
71 clocks = <&ccu CLK_CPU 65 clocks = <&ccu CLK_CPUX>;
72 clock-names = "cpu"; 66 clock-names = "cpu";
73 #cooling-cells = <2>; 67 #cooling-cells = <2>;
74 i-cache-size = <0x8000 <<
75 i-cache-line-size = <6 <<
76 i-cache-sets = <256>; <<
77 d-cache-size = <0x8000 <<
78 d-cache-line-size = <6 <<
79 d-cache-sets = <128>; <<
80 next-level-cache = <&l <<
81 }; 68 };
82 69
83 cpu2: cpu@2 { 70 cpu2: cpu@2 {
84 compatible = "arm,cort 71 compatible = "arm,cortex-a53";
85 device_type = "cpu"; 72 device_type = "cpu";
86 reg = <2>; 73 reg = <2>;
87 enable-method = "psci" 74 enable-method = "psci";
>> 75 next-level-cache = <&L2>;
88 clocks = <&ccu CLK_CPU 76 clocks = <&ccu CLK_CPUX>;
89 clock-names = "cpu"; 77 clock-names = "cpu";
90 #cooling-cells = <2>; 78 #cooling-cells = <2>;
91 i-cache-size = <0x8000 <<
92 i-cache-line-size = <6 <<
93 i-cache-sets = <256>; <<
94 d-cache-size = <0x8000 <<
95 d-cache-line-size = <6 <<
96 d-cache-sets = <128>; <<
97 next-level-cache = <&l <<
98 }; 79 };
99 80
100 cpu3: cpu@3 { 81 cpu3: cpu@3 {
101 compatible = "arm,cort 82 compatible = "arm,cortex-a53";
102 device_type = "cpu"; 83 device_type = "cpu";
103 reg = <3>; 84 reg = <3>;
104 enable-method = "psci" 85 enable-method = "psci";
>> 86 next-level-cache = <&L2>;
105 clocks = <&ccu CLK_CPU 87 clocks = <&ccu CLK_CPUX>;
106 clock-names = "cpu"; 88 clock-names = "cpu";
107 #cooling-cells = <2>; 89 #cooling-cells = <2>;
108 i-cache-size = <0x8000 <<
109 i-cache-line-size = <6 <<
110 i-cache-sets = <256>; <<
111 d-cache-size = <0x8000 <<
112 d-cache-line-size = <6 <<
113 d-cache-sets = <128>; <<
114 next-level-cache = <&l <<
115 }; 90 };
116 91
117 l2_cache: l2-cache { !! 92 L2: l2-cache {
118 compatible = "cache"; 93 compatible = "cache";
119 cache-level = <2>; 94 cache-level = <2>;
120 cache-unified; <<
121 cache-size = <0x80000> <<
122 cache-line-size = <64> <<
123 cache-sets = <512>; <<
124 }; 95 };
125 }; 96 };
126 97
127 de: display-engine { 98 de: display-engine {
128 compatible = "allwinner,sun50i 99 compatible = "allwinner,sun50i-a64-display-engine";
129 allwinner,pipelines = <&mixer0 100 allwinner,pipelines = <&mixer0>,
130 <&mixer1 101 <&mixer1>;
131 status = "disabled"; 102 status = "disabled";
132 }; 103 };
133 104
134 gpu_opp_table: opp-table-gpu { 105 gpu_opp_table: opp-table-gpu {
135 compatible = "operating-points 106 compatible = "operating-points-v2";
136 107
>> 108 opp-120000000 {
>> 109 opp-hz = /bits/ 64 <120000000>;
>> 110 };
>> 111
>> 112 opp-312000000 {
>> 113 opp-hz = /bits/ 64 <312000000>;
>> 114 };
>> 115
137 opp-432000000 { 116 opp-432000000 {
138 opp-hz = /bits/ 64 <43 117 opp-hz = /bits/ 64 <432000000>;
139 }; 118 };
140 }; 119 };
141 120
142 osc24M: osc24M-clk { !! 121 osc24M: osc24M_clk {
143 #clock-cells = <0>; 122 #clock-cells = <0>;
144 compatible = "fixed-clock"; 123 compatible = "fixed-clock";
145 clock-frequency = <24000000>; 124 clock-frequency = <24000000>;
146 clock-output-names = "osc24M"; 125 clock-output-names = "osc24M";
147 }; 126 };
148 127
149 osc32k: osc32k-clk { !! 128 osc32k: osc32k_clk {
150 #clock-cells = <0>; 129 #clock-cells = <0>;
151 compatible = "fixed-clock"; 130 compatible = "fixed-clock";
152 clock-frequency = <32768>; 131 clock-frequency = <32768>;
153 clock-output-names = "ext-osc3 132 clock-output-names = "ext-osc32k";
154 }; 133 };
155 134
156 pmu { 135 pmu {
157 compatible = "arm,cortex-a53-p 136 compatible = "arm,cortex-a53-pmu";
158 interrupts = <GIC_SPI 116 IRQ_ 137 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 117 IRQ_ 138 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 118 IRQ_ 139 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 119 IRQ_ 140 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
162 interrupt-affinity = <&cpu0>, 141 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
163 }; 142 };
164 143
165 psci { 144 psci {
166 compatible = "arm,psci-0.2"; 145 compatible = "arm,psci-0.2";
167 method = "smc"; 146 method = "smc";
168 }; 147 };
169 148
170 sound: sound { 149 sound: sound {
171 #address-cells = <1>; 150 #address-cells = <1>;
172 #size-cells = <0>; 151 #size-cells = <0>;
173 compatible = "simple-audio-car 152 compatible = "simple-audio-card";
174 simple-audio-card,name = "sun5 153 simple-audio-card,name = "sun50i-a64-audio";
175 simple-audio-card,aux-devs = < 154 simple-audio-card,aux-devs = <&codec_analog>;
176 simple-audio-card,routing = 155 simple-audio-card,routing =
177 "Left DAC", "D 156 "Left DAC", "DACL",
178 "Right DAC", " 157 "Right DAC", "DACR",
179 "ADCL", "Left 158 "ADCL", "Left ADC",
180 "ADCR", "Right 159 "ADCR", "Right ADC";
181 status = "disabled"; 160 status = "disabled";
182 161
183 simple-audio-card,dai-link@0 { 162 simple-audio-card,dai-link@0 {
184 format = "i2s"; 163 format = "i2s";
185 frame-master = <&link0 164 frame-master = <&link0_cpu>;
186 bitclock-master = <&li 165 bitclock-master = <&link0_cpu>;
187 mclk-fs = <128>; 166 mclk-fs = <128>;
188 167
189 link0_cpu: cpu { 168 link0_cpu: cpu {
190 sound-dai = <& 169 sound-dai = <&dai>;
191 }; 170 };
192 171
193 link0_codec: codec { 172 link0_codec: codec {
194 sound-dai = <& 173 sound-dai = <&codec 0>;
195 }; 174 };
196 }; 175 };
197 }; 176 };
198 177
199 timer { 178 timer {
200 compatible = "arm,armv8-timer" 179 compatible = "arm,armv8-timer";
201 allwinner,erratum-unknown1; 180 allwinner,erratum-unknown1;
202 arm,no-tick-in-suspend; 181 arm,no-tick-in-suspend;
203 interrupts = <GIC_PPI 13 182 interrupts = <GIC_PPI 13
204 (GIC_CPU_MASK_SIMPLE(4 183 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
205 <GIC_PPI 14 184 <GIC_PPI 14
206 (GIC_CPU_MASK_SIMPLE(4 185 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
207 <GIC_PPI 11 186 <GIC_PPI 11
208 (GIC_CPU_MASK_SIMPLE(4 187 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
209 <GIC_PPI 10 188 <GIC_PPI 10
210 (GIC_CPU_MASK_SIMPLE(4 189 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
211 }; 190 };
212 191
213 thermal-zones { 192 thermal-zones {
214 cpu_thermal: cpu0-thermal { 193 cpu_thermal: cpu0-thermal {
215 /* milliseconds */ 194 /* milliseconds */
216 polling-delay-passive 195 polling-delay-passive = <0>;
217 polling-delay = <0>; 196 polling-delay = <0>;
218 thermal-sensors = <&th 197 thermal-sensors = <&ths 0>;
219 198
220 cooling-maps { 199 cooling-maps {
221 map0 { 200 map0 {
222 trip = 201 trip = <&cpu_alert0>;
223 coolin 202 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
224 203 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
225 204 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
226 205 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
227 }; 206 };
228 map1 { 207 map1 {
229 trip = 208 trip = <&cpu_alert1>;
230 coolin 209 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
231 210 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
232 211 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
233 212 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
234 }; 213 };
235 }; 214 };
236 215
237 trips { 216 trips {
238 cpu_alert0: cp !! 217 cpu_alert0: cpu_alert0 {
239 /* mil 218 /* milliCelsius */
240 temper 219 temperature = <75000>;
241 hyster 220 hysteresis = <2000>;
242 type = 221 type = "passive";
243 }; 222 };
244 223
245 cpu_alert1: cp !! 224 cpu_alert1: cpu_alert1 {
246 /* mil 225 /* milliCelsius */
247 temper 226 temperature = <90000>;
248 hyster 227 hysteresis = <2000>;
249 type = 228 type = "hot";
250 }; 229 };
251 230
252 cpu_crit: cpu- !! 231 cpu_crit: cpu_crit {
253 /* mil 232 /* milliCelsius */
254 temper 233 temperature = <110000>;
255 hyster 234 hysteresis = <2000>;
256 type = 235 type = "critical";
257 }; 236 };
258 }; 237 };
259 }; 238 };
260 239
261 gpu0_thermal: gpu0-thermal { 240 gpu0_thermal: gpu0-thermal {
262 /* milliseconds */ 241 /* milliseconds */
263 polling-delay-passive 242 polling-delay-passive = <0>;
264 polling-delay = <0>; 243 polling-delay = <0>;
265 thermal-sensors = <&th 244 thermal-sensors = <&ths 1>;
266 <<
267 trips { <<
268 gpu0_crit: gpu <<
269 temper <<
270 hyster <<
271 type = <<
272 }; <<
273 }; <<
274 }; 245 };
275 246
276 gpu1_thermal: gpu1-thermal { 247 gpu1_thermal: gpu1-thermal {
277 /* milliseconds */ 248 /* milliseconds */
278 polling-delay-passive 249 polling-delay-passive = <0>;
279 polling-delay = <0>; 250 polling-delay = <0>;
280 thermal-sensors = <&th 251 thermal-sensors = <&ths 2>;
281 <<
282 trips { <<
283 gpu1_crit: gpu <<
284 temper <<
285 hyster <<
286 type = <<
287 }; <<
288 }; <<
289 }; 252 };
290 }; 253 };
291 254
292 soc { 255 soc {
293 compatible = "simple-bus"; 256 compatible = "simple-bus";
294 #address-cells = <1>; 257 #address-cells = <1>;
295 #size-cells = <1>; 258 #size-cells = <1>;
296 ranges; 259 ranges;
297 260
298 bus@1000000 { 261 bus@1000000 {
299 compatible = "allwinne 262 compatible = "allwinner,sun50i-a64-de2";
300 reg = <0x1000000 0x400 263 reg = <0x1000000 0x400000>;
301 allwinner,sram = <&de2 264 allwinner,sram = <&de2_sram 1>;
302 #address-cells = <1>; 265 #address-cells = <1>;
303 #size-cells = <1>; 266 #size-cells = <1>;
304 ranges = <0 0x1000000 267 ranges = <0 0x1000000 0x400000>;
305 268
306 display_clocks: clock@ 269 display_clocks: clock@0 {
307 compatible = " 270 compatible = "allwinner,sun50i-a64-de2-clk";
308 reg = <0x0 0x1 271 reg = <0x0 0x10000>;
309 clocks = <&ccu 272 clocks = <&ccu CLK_BUS_DE>,
310 <&ccu 273 <&ccu CLK_DE>;
311 clock-names = 274 clock-names = "bus",
312 275 "mod";
313 resets = <&ccu 276 resets = <&ccu RST_BUS_DE>;
314 #clock-cells = 277 #clock-cells = <1>;
315 #reset-cells = 278 #reset-cells = <1>;
316 }; 279 };
317 280
318 rotate: rotate@20000 { 281 rotate: rotate@20000 {
319 compatible = " 282 compatible = "allwinner,sun50i-a64-de2-rotate",
320 " 283 "allwinner,sun8i-a83t-de2-rotate";
321 reg = <0x20000 284 reg = <0x20000 0x10000>;
322 interrupts = < 285 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&dis 286 clocks = <&display_clocks CLK_BUS_ROT>,
324 <&dis 287 <&display_clocks CLK_ROT>;
325 clock-names = 288 clock-names = "bus",
326 289 "mod";
327 resets = <&dis 290 resets = <&display_clocks RST_ROT>;
328 }; 291 };
329 292
330 mixer0: mixer@100000 { 293 mixer0: mixer@100000 {
331 compatible = " 294 compatible = "allwinner,sun50i-a64-de2-mixer-0";
332 reg = <0x10000 295 reg = <0x100000 0x100000>;
333 clocks = <&dis 296 clocks = <&display_clocks CLK_BUS_MIXER0>,
334 <&dis 297 <&display_clocks CLK_MIXER0>;
335 clock-names = 298 clock-names = "bus",
336 299 "mod";
337 resets = <&dis 300 resets = <&display_clocks RST_MIXER0>;
338 301
339 ports { 302 ports {
340 #addre 303 #address-cells = <1>;
341 #size- 304 #size-cells = <0>;
342 305
343 mixer0 306 mixer0_out: port@1 {
344 307 #address-cells = <1>;
345 308 #size-cells = <0>;
346 309 reg = <1>;
347 310
348 311 mixer0_out_tcon0: endpoint@0 {
349 312 reg = <0>;
350 313 remote-endpoint = <&tcon0_in_mixer0>;
351 314 };
352 315
353 316 mixer0_out_tcon1: endpoint@1 {
354 317 reg = <1>;
355 318 remote-endpoint = <&tcon1_in_mixer0>;
356 319 };
357 }; 320 };
358 }; 321 };
359 }; 322 };
360 323
361 mixer1: mixer@200000 { 324 mixer1: mixer@200000 {
362 compatible = " 325 compatible = "allwinner,sun50i-a64-de2-mixer-1";
363 reg = <0x20000 326 reg = <0x200000 0x100000>;
364 clocks = <&dis 327 clocks = <&display_clocks CLK_BUS_MIXER1>,
365 <&dis 328 <&display_clocks CLK_MIXER1>;
366 clock-names = 329 clock-names = "bus",
367 330 "mod";
368 resets = <&dis 331 resets = <&display_clocks RST_MIXER1>;
369 332
370 ports { 333 ports {
371 #addre 334 #address-cells = <1>;
372 #size- 335 #size-cells = <0>;
373 336
374 mixer1 337 mixer1_out: port@1 {
375 338 #address-cells = <1>;
376 339 #size-cells = <0>;
377 340 reg = <1>;
378 341
379 342 mixer1_out_tcon0: endpoint@0 {
380 343 reg = <0>;
381 344 remote-endpoint = <&tcon0_in_mixer1>;
382 345 };
383 346
384 347 mixer1_out_tcon1: endpoint@1 {
385 348 reg = <1>;
386 349 remote-endpoint = <&tcon1_in_mixer1>;
387 350 };
388 }; 351 };
389 }; 352 };
390 }; 353 };
391 }; 354 };
392 355
393 syscon: syscon@1c00000 { 356 syscon: syscon@1c00000 {
394 compatible = "allwinne 357 compatible = "allwinner,sun50i-a64-system-control";
395 reg = <0x01c00000 0x10 358 reg = <0x01c00000 0x1000>;
396 #address-cells = <1>; 359 #address-cells = <1>;
397 #size-cells = <1>; 360 #size-cells = <1>;
398 ranges; 361 ranges;
399 362
400 sram_c: sram@18000 { 363 sram_c: sram@18000 {
401 compatible = " 364 compatible = "mmio-sram";
402 reg = <0x00018 365 reg = <0x00018000 0x28000>;
403 #address-cells 366 #address-cells = <1>;
404 #size-cells = 367 #size-cells = <1>;
405 ranges = <0 0x 368 ranges = <0 0x00018000 0x28000>;
406 369
407 de2_sram: sram 370 de2_sram: sram-section@0 {
408 compat 371 compatible = "allwinner,sun50i-a64-sram-c";
409 reg = 372 reg = <0x0000 0x28000>;
410 }; 373 };
411 }; 374 };
412 375
413 sram_c1: sram@1d00000 376 sram_c1: sram@1d00000 {
414 compatible = " 377 compatible = "mmio-sram";
415 reg = <0x01d00 378 reg = <0x01d00000 0x40000>;
416 #address-cells 379 #address-cells = <1>;
417 #size-cells = 380 #size-cells = <1>;
418 ranges = <0 0x 381 ranges = <0 0x01d00000 0x40000>;
419 382
420 ve_sram: sram- 383 ve_sram: sram-section@0 {
421 compat 384 compatible = "allwinner,sun50i-a64-sram-c1",
422 385 "allwinner,sun4i-a10-sram-c1";
423 reg = 386 reg = <0x000000 0x40000>;
424 }; 387 };
425 }; 388 };
426 }; 389 };
427 390
428 dma: dma-controller@1c02000 { 391 dma: dma-controller@1c02000 {
429 compatible = "allwinne 392 compatible = "allwinner,sun50i-a64-dma";
430 reg = <0x01c02000 0x10 393 reg = <0x01c02000 0x1000>;
431 interrupts = <GIC_SPI 394 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&ccu CLK_BUS 395 clocks = <&ccu CLK_BUS_DMA>;
433 dma-channels = <8>; 396 dma-channels = <8>;
434 dma-requests = <27>; 397 dma-requests = <27>;
435 resets = <&ccu RST_BUS 398 resets = <&ccu RST_BUS_DMA>;
436 #dma-cells = <1>; 399 #dma-cells = <1>;
437 }; 400 };
438 401
439 tcon0: lcd-controller@1c0c000 402 tcon0: lcd-controller@1c0c000 {
440 compatible = "allwinne 403 compatible = "allwinner,sun50i-a64-tcon-lcd",
441 "allwinne 404 "allwinner,sun8i-a83t-tcon-lcd";
442 reg = <0x01c0c000 0x10 405 reg = <0x01c0c000 0x1000>;
443 interrupts = <GIC_SPI 406 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
444 clocks = <&ccu CLK_BUS 407 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
445 clock-names = "ahb", " 408 clock-names = "ahb", "tcon-ch0";
446 clock-output-names = " !! 409 clock-output-names = "tcon-pixel-clock";
447 #clock-cells = <0>; 410 #clock-cells = <0>;
448 resets = <&ccu RST_BUS 411 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
449 reset-names = "lcd", " 412 reset-names = "lcd", "lvds";
450 413
451 ports { 414 ports {
452 #address-cells 415 #address-cells = <1>;
453 #size-cells = 416 #size-cells = <0>;
454 417
455 tcon0_in: port 418 tcon0_in: port@0 {
456 #addre 419 #address-cells = <1>;
457 #size- 420 #size-cells = <0>;
458 reg = 421 reg = <0>;
459 422
460 tcon0_ 423 tcon0_in_mixer0: endpoint@0 {
461 424 reg = <0>;
462 425 remote-endpoint = <&mixer0_out_tcon0>;
463 }; 426 };
464 427
465 tcon0_ 428 tcon0_in_mixer1: endpoint@1 {
466 429 reg = <1>;
467 430 remote-endpoint = <&mixer1_out_tcon0>;
468 }; 431 };
469 }; 432 };
470 433
471 tcon0_out: por 434 tcon0_out: port@1 {
472 #addre 435 #address-cells = <1>;
473 #size- 436 #size-cells = <0>;
474 reg = 437 reg = <1>;
475 438
476 tcon0_ 439 tcon0_out_dsi: endpoint@1 {
477 440 reg = <1>;
478 441 remote-endpoint = <&dsi_in_tcon0>;
479 442 allwinner,tcon-channel = <1>;
480 }; 443 };
481 }; 444 };
482 }; 445 };
483 }; 446 };
484 447
485 tcon1: lcd-controller@1c0d000 448 tcon1: lcd-controller@1c0d000 {
486 compatible = "allwinne 449 compatible = "allwinner,sun50i-a64-tcon-tv",
487 "allwinne 450 "allwinner,sun8i-a83t-tcon-tv";
488 reg = <0x01c0d000 0x10 451 reg = <0x01c0d000 0x1000>;
489 interrupts = <GIC_SPI 452 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&ccu CLK_BUS 453 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
491 clock-names = "ahb", " 454 clock-names = "ahb", "tcon-ch1";
492 resets = <&ccu RST_BUS 455 resets = <&ccu RST_BUS_TCON1>;
493 reset-names = "lcd"; 456 reset-names = "lcd";
494 457
495 ports { 458 ports {
496 #address-cells 459 #address-cells = <1>;
497 #size-cells = 460 #size-cells = <0>;
498 461
499 tcon1_in: port 462 tcon1_in: port@0 {
500 #addre 463 #address-cells = <1>;
501 #size- 464 #size-cells = <0>;
502 reg = 465 reg = <0>;
503 466
504 tcon1_ 467 tcon1_in_mixer0: endpoint@0 {
505 468 reg = <0>;
506 469 remote-endpoint = <&mixer0_out_tcon1>;
507 }; 470 };
508 471
509 tcon1_ 472 tcon1_in_mixer1: endpoint@1 {
510 473 reg = <1>;
511 474 remote-endpoint = <&mixer1_out_tcon1>;
512 }; 475 };
513 }; 476 };
514 477
515 tcon1_out: por 478 tcon1_out: port@1 {
516 #addre 479 #address-cells = <1>;
517 #size- 480 #size-cells = <0>;
518 reg = 481 reg = <1>;
519 482
520 tcon1_ 483 tcon1_out_hdmi: endpoint@1 {
521 484 reg = <1>;
522 485 remote-endpoint = <&hdmi_in_tcon1>;
523 }; 486 };
524 }; 487 };
525 }; 488 };
526 }; 489 };
527 490
528 video-codec@1c0e000 { 491 video-codec@1c0e000 {
529 compatible = "allwinne 492 compatible = "allwinner,sun50i-a64-video-engine";
530 reg = <0x01c0e000 0x10 493 reg = <0x01c0e000 0x1000>;
531 clocks = <&ccu CLK_BUS 494 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
532 <&ccu CLK_DRA 495 <&ccu CLK_DRAM_VE>;
533 clock-names = "ahb", " 496 clock-names = "ahb", "mod", "ram";
534 resets = <&ccu RST_BUS 497 resets = <&ccu RST_BUS_VE>;
535 interrupts = <GIC_SPI 498 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
536 allwinner,sram = <&ve_ 499 allwinner,sram = <&ve_sram 1>;
537 }; 500 };
538 501
539 mmc0: mmc@1c0f000 { 502 mmc0: mmc@1c0f000 {
540 compatible = "allwinne 503 compatible = "allwinner,sun50i-a64-mmc";
541 reg = <0x01c0f000 0x10 504 reg = <0x01c0f000 0x1000>;
542 clocks = <&ccu CLK_BUS 505 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
543 clock-names = "ahb", " 506 clock-names = "ahb", "mmc";
544 resets = <&ccu RST_BUS 507 resets = <&ccu RST_BUS_MMC0>;
545 reset-names = "ahb"; 508 reset-names = "ahb";
546 interrupts = <GIC_SPI 509 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
547 max-frequency = <15000 510 max-frequency = <150000000>;
548 status = "disabled"; 511 status = "disabled";
549 #address-cells = <1>; 512 #address-cells = <1>;
550 #size-cells = <0>; 513 #size-cells = <0>;
551 }; 514 };
552 515
553 mmc1: mmc@1c10000 { 516 mmc1: mmc@1c10000 {
554 compatible = "allwinne 517 compatible = "allwinner,sun50i-a64-mmc";
555 reg = <0x01c10000 0x10 518 reg = <0x01c10000 0x1000>;
556 clocks = <&ccu CLK_BUS 519 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
557 clock-names = "ahb", " 520 clock-names = "ahb", "mmc";
558 resets = <&ccu RST_BUS 521 resets = <&ccu RST_BUS_MMC1>;
559 reset-names = "ahb"; 522 reset-names = "ahb";
560 interrupts = <GIC_SPI 523 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
561 max-frequency = <15000 524 max-frequency = <150000000>;
562 status = "disabled"; 525 status = "disabled";
563 #address-cells = <1>; 526 #address-cells = <1>;
564 #size-cells = <0>; 527 #size-cells = <0>;
565 }; 528 };
566 529
567 mmc2: mmc@1c11000 { 530 mmc2: mmc@1c11000 {
568 compatible = "allwinne 531 compatible = "allwinner,sun50i-a64-emmc";
569 reg = <0x01c11000 0x10 532 reg = <0x01c11000 0x1000>;
570 clocks = <&ccu CLK_BUS 533 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
571 clock-names = "ahb", " 534 clock-names = "ahb", "mmc";
572 resets = <&ccu RST_BUS 535 resets = <&ccu RST_BUS_MMC2>;
573 reset-names = "ahb"; 536 reset-names = "ahb";
574 interrupts = <GIC_SPI 537 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
575 max-frequency = <15000 538 max-frequency = <150000000>;
576 status = "disabled"; 539 status = "disabled";
577 #address-cells = <1>; 540 #address-cells = <1>;
578 #size-cells = <0>; 541 #size-cells = <0>;
579 }; 542 };
580 543
581 sid: eeprom@1c14000 { 544 sid: eeprom@1c14000 {
582 compatible = "allwinne 545 compatible = "allwinner,sun50i-a64-sid";
583 reg = <0x1c14000 0x400 546 reg = <0x1c14000 0x400>;
584 #address-cells = <1>; 547 #address-cells = <1>;
585 #size-cells = <1>; 548 #size-cells = <1>;
586 549
587 ths_calibration: therm 550 ths_calibration: thermal-sensor-calibration@34 {
588 reg = <0x34 0x 551 reg = <0x34 0x8>;
589 }; 552 };
590 }; 553 };
591 554
592 crypto: crypto@1c15000 { 555 crypto: crypto@1c15000 {
593 compatible = "allwinne 556 compatible = "allwinner,sun50i-a64-crypto";
594 reg = <0x01c15000 0x10 557 reg = <0x01c15000 0x1000>;
595 interrupts = <GIC_SPI 558 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
596 clocks = <&ccu CLK_BUS 559 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
597 clock-names = "bus", " 560 clock-names = "bus", "mod";
598 resets = <&ccu RST_BUS 561 resets = <&ccu RST_BUS_CE>;
599 }; 562 };
600 563
601 msgbox: mailbox@1c17000 { 564 msgbox: mailbox@1c17000 {
602 compatible = "allwinne 565 compatible = "allwinner,sun50i-a64-msgbox",
603 "allwinne 566 "allwinner,sun6i-a31-msgbox";
604 reg = <0x01c17000 0x10 567 reg = <0x01c17000 0x1000>;
605 clocks = <&ccu CLK_BUS 568 clocks = <&ccu CLK_BUS_MSGBOX>;
606 resets = <&ccu RST_BUS 569 resets = <&ccu RST_BUS_MSGBOX>;
607 interrupts = <GIC_SPI 570 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
608 #mbox-cells = <1>; 571 #mbox-cells = <1>;
609 }; 572 };
610 573
611 usb_otg: usb@1c19000 { 574 usb_otg: usb@1c19000 {
612 compatible = "allwinne 575 compatible = "allwinner,sun8i-a33-musb";
613 reg = <0x01c19000 0x04 576 reg = <0x01c19000 0x0400>;
614 clocks = <&ccu CLK_BUS 577 clocks = <&ccu CLK_BUS_OTG>;
615 resets = <&ccu RST_BUS 578 resets = <&ccu RST_BUS_OTG>;
616 interrupts = <GIC_SPI 579 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
617 interrupt-names = "mc" 580 interrupt-names = "mc";
618 phys = <&usbphy 0>; 581 phys = <&usbphy 0>;
619 phy-names = "usb"; 582 phy-names = "usb";
620 extcon = <&usbphy 0>; 583 extcon = <&usbphy 0>;
621 dr_mode = "otg"; 584 dr_mode = "otg";
622 status = "disabled"; 585 status = "disabled";
623 }; 586 };
624 587
625 usbphy: phy@1c19400 { 588 usbphy: phy@1c19400 {
626 compatible = "allwinne 589 compatible = "allwinner,sun50i-a64-usb-phy";
627 reg = <0x01c19400 0x14 590 reg = <0x01c19400 0x14>,
628 <0x01c1a800 0x4> 591 <0x01c1a800 0x4>,
629 <0x01c1b800 0x4> 592 <0x01c1b800 0x4>;
630 reg-names = "phy_ctrl" 593 reg-names = "phy_ctrl",
631 "pmu0", 594 "pmu0",
632 "pmu1"; 595 "pmu1";
633 clocks = <&ccu CLK_USB 596 clocks = <&ccu CLK_USB_PHY0>,
634 <&ccu CLK_USB 597 <&ccu CLK_USB_PHY1>;
635 clock-names = "usb0_ph 598 clock-names = "usb0_phy",
636 "usb1_ph 599 "usb1_phy";
637 resets = <&ccu RST_USB 600 resets = <&ccu RST_USB_PHY0>,
638 <&ccu RST_USB 601 <&ccu RST_USB_PHY1>;
639 reset-names = "usb0_re 602 reset-names = "usb0_reset",
640 "usb1_re 603 "usb1_reset";
641 status = "disabled"; 604 status = "disabled";
642 #phy-cells = <1>; 605 #phy-cells = <1>;
643 }; 606 };
644 607
645 ehci0: usb@1c1a000 { 608 ehci0: usb@1c1a000 {
646 compatible = "allwinne 609 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
647 reg = <0x01c1a000 0x10 610 reg = <0x01c1a000 0x100>;
648 interrupts = <GIC_SPI 611 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
649 clocks = <&ccu CLK_BUS 612 clocks = <&ccu CLK_BUS_OHCI0>,
650 <&ccu CLK_BUS 613 <&ccu CLK_BUS_EHCI0>,
651 <&ccu CLK_USB 614 <&ccu CLK_USB_OHCI0>;
652 resets = <&ccu RST_BUS 615 resets = <&ccu RST_BUS_OHCI0>,
653 <&ccu RST_BUS 616 <&ccu RST_BUS_EHCI0>;
654 phys = <&usbphy 0>; 617 phys = <&usbphy 0>;
655 phy-names = "usb"; 618 phy-names = "usb";
656 status = "disabled"; 619 status = "disabled";
657 }; 620 };
658 621
659 ohci0: usb@1c1a400 { 622 ohci0: usb@1c1a400 {
660 compatible = "allwinne 623 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
661 reg = <0x01c1a400 0x10 624 reg = <0x01c1a400 0x100>;
662 interrupts = <GIC_SPI 625 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
663 clocks = <&ccu CLK_BUS 626 clocks = <&ccu CLK_BUS_OHCI0>,
664 <&ccu CLK_USB 627 <&ccu CLK_USB_OHCI0>;
665 resets = <&ccu RST_BUS 628 resets = <&ccu RST_BUS_OHCI0>;
666 phys = <&usbphy 0>; 629 phys = <&usbphy 0>;
667 phy-names = "usb"; 630 phy-names = "usb";
668 status = "disabled"; 631 status = "disabled";
669 }; 632 };
670 633
671 ehci1: usb@1c1b000 { 634 ehci1: usb@1c1b000 {
672 compatible = "allwinne 635 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
673 reg = <0x01c1b000 0x10 636 reg = <0x01c1b000 0x100>;
674 interrupts = <GIC_SPI 637 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
675 clocks = <&ccu CLK_BUS 638 clocks = <&ccu CLK_BUS_OHCI1>,
676 <&ccu CLK_BUS 639 <&ccu CLK_BUS_EHCI1>,
677 <&ccu CLK_USB 640 <&ccu CLK_USB_OHCI1>;
678 resets = <&ccu RST_BUS 641 resets = <&ccu RST_BUS_OHCI1>,
679 <&ccu RST_BUS 642 <&ccu RST_BUS_EHCI1>;
680 phys = <&usbphy 1>; 643 phys = <&usbphy 1>;
681 phy-names = "usb"; 644 phy-names = "usb";
682 status = "disabled"; 645 status = "disabled";
683 }; 646 };
684 647
685 ohci1: usb@1c1b400 { 648 ohci1: usb@1c1b400 {
686 compatible = "allwinne 649 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
687 reg = <0x01c1b400 0x10 650 reg = <0x01c1b400 0x100>;
688 interrupts = <GIC_SPI 651 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
689 clocks = <&ccu CLK_BUS 652 clocks = <&ccu CLK_BUS_OHCI1>,
690 <&ccu CLK_USB 653 <&ccu CLK_USB_OHCI1>;
691 resets = <&ccu RST_BUS 654 resets = <&ccu RST_BUS_OHCI1>;
692 phys = <&usbphy 1>; 655 phys = <&usbphy 1>;
693 phy-names = "usb"; 656 phy-names = "usb";
694 status = "disabled"; 657 status = "disabled";
695 }; 658 };
696 659
697 ccu: clock@1c20000 { 660 ccu: clock@1c20000 {
698 compatible = "allwinne 661 compatible = "allwinner,sun50i-a64-ccu";
699 reg = <0x01c20000 0x40 662 reg = <0x01c20000 0x400>;
700 clocks = <&osc24M>, <& !! 663 clocks = <&osc24M>, <&rtc 0>;
701 clock-names = "hosc", 664 clock-names = "hosc", "losc";
702 #clock-cells = <1>; 665 #clock-cells = <1>;
703 #reset-cells = <1>; 666 #reset-cells = <1>;
704 }; 667 };
705 668
706 pio: pinctrl@1c20800 { 669 pio: pinctrl@1c20800 {
707 compatible = "allwinne 670 compatible = "allwinner,sun50i-a64-pinctrl";
708 reg = <0x01c20800 0x40 671 reg = <0x01c20800 0x400>;
709 interrupt-parent = <&r 672 interrupt-parent = <&r_intc>;
710 interrupts = <GIC_SPI 673 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
711 <GIC_SPI 674 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
712 <GIC_SPI 675 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&ccu CLK_BUS !! 676 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
714 <&rtc CLK_OSC <<
715 clock-names = "apb", " 677 clock-names = "apb", "hosc", "losc";
716 gpio-controller; 678 gpio-controller;
717 #gpio-cells = <3>; 679 #gpio-cells = <3>;
718 interrupt-controller; 680 interrupt-controller;
719 #interrupt-cells = <3> 681 #interrupt-cells = <3>;
720 682
721 /omit-if-no-ref/ 683 /omit-if-no-ref/
722 aif2_pins: aif2-pins { 684 aif2_pins: aif2-pins {
723 pins = "PB4", 685 pins = "PB4", "PB5", "PB6", "PB7";
724 function = "ai 686 function = "aif2";
725 }; 687 };
726 688
727 /omit-if-no-ref/ 689 /omit-if-no-ref/
728 aif3_pins: aif3-pins { 690 aif3_pins: aif3-pins {
729 pins = "PG10", 691 pins = "PG10", "PG11", "PG12", "PG13";
730 function = "ai 692 function = "aif3";
731 }; 693 };
732 694
733 csi_pins: csi-pins { 695 csi_pins: csi-pins {
734 pins = "PE0", 696 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
735 "PE7", 697 "PE7", "PE8", "PE9", "PE10", "PE11";
736 function = "cs 698 function = "csi";
737 }; 699 };
738 700
739 /omit-if-no-ref/ 701 /omit-if-no-ref/
740 csi_mclk_pin: csi-mclk 702 csi_mclk_pin: csi-mclk-pin {
741 pins = "PE1"; 703 pins = "PE1";
742 function = "cs 704 function = "csi";
743 }; 705 };
744 706
745 i2c0_pins: i2c0-pins { 707 i2c0_pins: i2c0-pins {
746 pins = "PH0", 708 pins = "PH0", "PH1";
747 function = "i2 709 function = "i2c0";
748 }; 710 };
749 711
750 i2c1_pins: i2c1-pins { 712 i2c1_pins: i2c1-pins {
751 pins = "PH2", 713 pins = "PH2", "PH3";
752 function = "i2 714 function = "i2c1";
753 }; 715 };
754 716
755 i2c2_pins: i2c2-pins { 717 i2c2_pins: i2c2-pins {
756 pins = "PE14", 718 pins = "PE14", "PE15";
757 function = "i2 719 function = "i2c2";
758 }; 720 };
759 721
760 /omit-if-no-ref/ 722 /omit-if-no-ref/
761 lcd_rgb666_pins: lcd-r 723 lcd_rgb666_pins: lcd-rgb666-pins {
762 pins = "PD0", 724 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
763 "PD5", 725 "PD5", "PD6", "PD7", "PD8", "PD9",
764 "PD10", 726 "PD10", "PD11", "PD12", "PD13",
765 "PD14", 727 "PD14", "PD15", "PD16", "PD17",
766 "PD18", 728 "PD18", "PD19", "PD20", "PD21";
767 function = "lc 729 function = "lcd0";
768 }; 730 };
769 731
770 mmc0_pins: mmc0-pins { 732 mmc0_pins: mmc0-pins {
771 pins = "PF0", 733 pins = "PF0", "PF1", "PF2", "PF3",
772 "PF4", 734 "PF4", "PF5";
773 function = "mm 735 function = "mmc0";
774 drive-strength 736 drive-strength = <30>;
775 bias-pull-up; 737 bias-pull-up;
776 }; 738 };
777 739
778 mmc1_pins: mmc1-pins { 740 mmc1_pins: mmc1-pins {
779 pins = "PG0", 741 pins = "PG0", "PG1", "PG2", "PG3",
780 "PG4", 742 "PG4", "PG5";
781 function = "mm 743 function = "mmc1";
782 drive-strength 744 drive-strength = <30>;
783 bias-pull-up; 745 bias-pull-up;
784 }; 746 };
785 747
786 mmc2_pins: mmc2-pins { 748 mmc2_pins: mmc2-pins {
787 pins = "PC5", 749 pins = "PC5", "PC6", "PC8", "PC9",
788 "PC10", 750 "PC10","PC11", "PC12", "PC13",
789 "PC14", 751 "PC14", "PC15", "PC16";
790 function = "mm 752 function = "mmc2";
791 drive-strength 753 drive-strength = <30>;
792 bias-pull-up; 754 bias-pull-up;
793 }; 755 };
794 756
795 mmc2_ds_pin: mmc2-ds-p 757 mmc2_ds_pin: mmc2-ds-pin {
796 pins = "PC1"; 758 pins = "PC1";
797 function = "mm 759 function = "mmc2";
798 drive-strength 760 drive-strength = <30>;
799 bias-pull-up; 761 bias-pull-up;
800 }; 762 };
801 763
802 pwm_pin: pwm-pin { 764 pwm_pin: pwm-pin {
803 pins = "PD22"; 765 pins = "PD22";
804 function = "pw 766 function = "pwm";
805 }; 767 };
806 768
807 rmii_pins: rmii-pins { 769 rmii_pins: rmii-pins {
808 pins = "PD10", 770 pins = "PD10", "PD11", "PD13", "PD14", "PD17",
809 "PD18", 771 "PD18", "PD19", "PD20", "PD22", "PD23";
810 function = "em 772 function = "emac";
811 drive-strength 773 drive-strength = <40>;
812 }; 774 };
813 775
814 rgmii_pins: rgmii-pins 776 rgmii_pins: rgmii-pins {
815 pins = "PD8", 777 pins = "PD8", "PD9", "PD10", "PD11", "PD12",
816 "PD13", 778 "PD13", "PD15", "PD16", "PD17", "PD18",
817 "PD19", 779 "PD19", "PD20", "PD21", "PD22", "PD23";
818 function = "em 780 function = "emac";
819 drive-strength 781 drive-strength = <40>;
820 }; 782 };
821 783
822 spdif_tx_pin: spdif-tx 784 spdif_tx_pin: spdif-tx-pin {
823 pins = "PH8"; 785 pins = "PH8";
824 function = "sp 786 function = "spdif";
825 }; 787 };
826 788
827 spi0_pins: spi0-pins { 789 spi0_pins: spi0-pins {
828 pins = "PC0", 790 pins = "PC0", "PC1", "PC2", "PC3";
829 function = "sp 791 function = "spi0";
830 }; 792 };
831 793
832 spi1_pins: spi1-pins { 794 spi1_pins: spi1-pins {
833 pins = "PD0", 795 pins = "PD0", "PD1", "PD2", "PD3";
834 function = "sp 796 function = "spi1";
835 }; 797 };
836 798
837 uart0_pb_pins: uart0-p 799 uart0_pb_pins: uart0-pb-pins {
838 pins = "PB8", 800 pins = "PB8", "PB9";
839 function = "ua 801 function = "uart0";
840 }; 802 };
841 803
842 uart1_pins: uart1-pins 804 uart1_pins: uart1-pins {
843 pins = "PG6", 805 pins = "PG6", "PG7";
844 function = "ua 806 function = "uart1";
845 }; 807 };
846 808
847 uart1_rts_cts_pins: ua 809 uart1_rts_cts_pins: uart1-rts-cts-pins {
848 pins = "PG8", 810 pins = "PG8", "PG9";
849 function = "ua 811 function = "uart1";
850 }; 812 };
851 813
852 uart2_pins: uart2-pins 814 uart2_pins: uart2-pins {
853 pins = "PB0", 815 pins = "PB0", "PB1";
854 function = "ua 816 function = "uart2";
855 }; 817 };
856 818
857 uart3_pins: uart3-pins 819 uart3_pins: uart3-pins {
858 pins = "PD0", 820 pins = "PD0", "PD1";
859 function = "ua 821 function = "uart3";
860 }; 822 };
861 823
862 uart4_pins: uart4-pins 824 uart4_pins: uart4-pins {
863 pins = "PD2", 825 pins = "PD2", "PD3";
864 function = "ua 826 function = "uart4";
865 }; 827 };
866 828
867 uart4_rts_cts_pins: ua 829 uart4_rts_cts_pins: uart4-rts-cts-pins {
868 pins = "PD4", 830 pins = "PD4", "PD5";
869 function = "ua 831 function = "uart4";
870 }; 832 };
871 }; 833 };
872 834
873 timer@1c20c00 { 835 timer@1c20c00 {
874 compatible = "allwinne 836 compatible = "allwinner,sun50i-a64-timer",
875 "allwinne 837 "allwinner,sun8i-a23-timer";
876 reg = <0x01c20c00 0xa0 838 reg = <0x01c20c00 0xa0>;
877 interrupts = <GIC_SPI 839 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
878 <GIC_SPI 840 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
879 clocks = <&osc24M>; 841 clocks = <&osc24M>;
880 }; 842 };
881 843
882 wdt0: watchdog@1c20ca0 { 844 wdt0: watchdog@1c20ca0 {
883 compatible = "allwinne 845 compatible = "allwinner,sun50i-a64-wdt",
884 "allwinne 846 "allwinner,sun6i-a31-wdt";
885 reg = <0x01c20ca0 0x20 847 reg = <0x01c20ca0 0x20>;
886 interrupts = <GIC_SPI 848 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
887 clocks = <&osc24M>; 849 clocks = <&osc24M>;
888 }; 850 };
889 851
890 spdif: spdif@1c21000 { 852 spdif: spdif@1c21000 {
891 #sound-dai-cells = <0> 853 #sound-dai-cells = <0>;
892 compatible = "allwinne 854 compatible = "allwinner,sun50i-a64-spdif",
893 "allwinne 855 "allwinner,sun8i-h3-spdif";
894 reg = <0x01c21000 0x40 856 reg = <0x01c21000 0x400>;
895 interrupts = <GIC_SPI 857 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
896 clocks = <&ccu CLK_BUS 858 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
897 resets = <&ccu RST_BUS 859 resets = <&ccu RST_BUS_SPDIF>;
898 clock-names = "apb", " 860 clock-names = "apb", "spdif";
899 dmas = <&dma 2>; 861 dmas = <&dma 2>;
900 dma-names = "tx"; 862 dma-names = "tx";
901 pinctrl-names = "defau 863 pinctrl-names = "default";
902 pinctrl-0 = <&spdif_tx 864 pinctrl-0 = <&spdif_tx_pin>;
903 status = "disabled"; 865 status = "disabled";
904 }; 866 };
905 867
906 lradc: lradc@1c21800 { 868 lradc: lradc@1c21800 {
907 compatible = "allwinne 869 compatible = "allwinner,sun50i-a64-lradc",
908 "allwinne 870 "allwinner,sun8i-a83t-r-lradc";
909 reg = <0x01c21800 0x40 871 reg = <0x01c21800 0x400>;
910 interrupt-parent = <&r 872 interrupt-parent = <&r_intc>;
911 interrupts = <GIC_SPI 873 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
912 status = "disabled"; 874 status = "disabled";
913 }; 875 };
914 876
915 i2s0: i2s@1c22000 { 877 i2s0: i2s@1c22000 {
916 #sound-dai-cells = <0> 878 #sound-dai-cells = <0>;
917 compatible = "allwinne 879 compatible = "allwinner,sun50i-a64-i2s",
918 "allwinne 880 "allwinner,sun8i-h3-i2s";
919 reg = <0x01c22000 0x40 881 reg = <0x01c22000 0x400>;
920 interrupts = <GIC_SPI 882 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
921 clocks = <&ccu CLK_BUS 883 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
922 clock-names = "apb", " 884 clock-names = "apb", "mod";
923 resets = <&ccu RST_BUS 885 resets = <&ccu RST_BUS_I2S0>;
924 dma-names = "rx", "tx" 886 dma-names = "rx", "tx";
925 dmas = <&dma 3>, <&dma 887 dmas = <&dma 3>, <&dma 3>;
926 status = "disabled"; 888 status = "disabled";
927 }; 889 };
928 890
929 i2s1: i2s@1c22400 { 891 i2s1: i2s@1c22400 {
930 #sound-dai-cells = <0> 892 #sound-dai-cells = <0>;
931 compatible = "allwinne 893 compatible = "allwinner,sun50i-a64-i2s",
932 "allwinne 894 "allwinner,sun8i-h3-i2s";
933 reg = <0x01c22400 0x40 895 reg = <0x01c22400 0x400>;
934 interrupts = <GIC_SPI 896 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
935 clocks = <&ccu CLK_BUS 897 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
936 clock-names = "apb", " 898 clock-names = "apb", "mod";
937 resets = <&ccu RST_BUS 899 resets = <&ccu RST_BUS_I2S1>;
938 dma-names = "rx", "tx" 900 dma-names = "rx", "tx";
939 dmas = <&dma 4>, <&dma 901 dmas = <&dma 4>, <&dma 4>;
940 status = "disabled"; 902 status = "disabled";
941 }; 903 };
942 904
943 i2s2: i2s@1c22800 { 905 i2s2: i2s@1c22800 {
944 #sound-dai-cells = <0> 906 #sound-dai-cells = <0>;
945 compatible = "allwinne 907 compatible = "allwinner,sun50i-a64-i2s",
946 "allwinne 908 "allwinner,sun8i-h3-i2s";
947 reg = <0x01c22800 0x40 909 reg = <0x01c22800 0x400>;
948 interrupts = <GIC_SPI 910 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
949 clocks = <&ccu CLK_BUS 911 clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
950 clock-names = "apb", " 912 clock-names = "apb", "mod";
951 resets = <&ccu RST_BUS 913 resets = <&ccu RST_BUS_I2S2>;
952 dma-names = "rx", "tx" 914 dma-names = "rx", "tx";
953 dmas = <&dma 27>, <&dm 915 dmas = <&dma 27>, <&dma 27>;
954 status = "disabled"; 916 status = "disabled";
955 }; 917 };
956 918
957 dai: dai@1c22c00 { 919 dai: dai@1c22c00 {
958 #sound-dai-cells = <0> 920 #sound-dai-cells = <0>;
959 compatible = "allwinne 921 compatible = "allwinner,sun50i-a64-codec-i2s";
960 reg = <0x01c22c00 0x20 922 reg = <0x01c22c00 0x200>;
961 interrupts = <GIC_SPI 923 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
962 clocks = <&ccu CLK_BUS 924 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
963 clock-names = "apb", " 925 clock-names = "apb", "mod";
964 resets = <&ccu RST_BUS 926 resets = <&ccu RST_BUS_CODEC>;
965 dmas = <&dma 15>, <&dm 927 dmas = <&dma 15>, <&dma 15>;
966 dma-names = "rx", "tx" 928 dma-names = "rx", "tx";
967 status = "disabled"; 929 status = "disabled";
968 }; 930 };
969 931
970 codec: codec@1c22e00 { 932 codec: codec@1c22e00 {
971 #sound-dai-cells = <1> 933 #sound-dai-cells = <1>;
972 compatible = "allwinne 934 compatible = "allwinner,sun50i-a64-codec",
973 "allwinne 935 "allwinner,sun8i-a33-codec";
974 reg = <0x01c22e00 0x60 936 reg = <0x01c22e00 0x600>;
975 interrupts = <GIC_SPI 937 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
976 clocks = <&ccu CLK_BUS 938 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
977 clock-names = "bus", " 939 clock-names = "bus", "mod";
978 status = "disabled"; 940 status = "disabled";
979 }; 941 };
980 942
981 ths: thermal-sensor@1c25000 { 943 ths: thermal-sensor@1c25000 {
982 compatible = "allwinne 944 compatible = "allwinner,sun50i-a64-ths";
983 reg = <0x01c25000 0x10 945 reg = <0x01c25000 0x100>;
984 clocks = <&ccu CLK_BUS 946 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
985 clock-names = "bus", " 947 clock-names = "bus", "mod";
986 interrupts = <GIC_SPI 948 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
987 resets = <&ccu RST_BUS 949 resets = <&ccu RST_BUS_THS>;
988 nvmem-cells = <&ths_ca 950 nvmem-cells = <&ths_calibration>;
989 nvmem-cell-names = "ca 951 nvmem-cell-names = "calibration";
990 #thermal-sensor-cells 952 #thermal-sensor-cells = <1>;
991 }; 953 };
992 954
993 uart0: serial@1c28000 { 955 uart0: serial@1c28000 {
994 compatible = "snps,dw- 956 compatible = "snps,dw-apb-uart";
995 reg = <0x01c28000 0x40 957 reg = <0x01c28000 0x400>;
996 interrupts = <GIC_SPI 958 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
997 reg-shift = <2>; 959 reg-shift = <2>;
998 reg-io-width = <4>; 960 reg-io-width = <4>;
999 clocks = <&ccu CLK_BUS 961 clocks = <&ccu CLK_BUS_UART0>;
1000 resets = <&ccu RST_BU 962 resets = <&ccu RST_BUS_UART0>;
1001 status = "disabled"; 963 status = "disabled";
1002 }; 964 };
1003 965
1004 uart1: serial@1c28400 { 966 uart1: serial@1c28400 {
1005 compatible = "snps,dw 967 compatible = "snps,dw-apb-uart";
1006 reg = <0x01c28400 0x4 968 reg = <0x01c28400 0x400>;
1007 interrupts = <GIC_SPI 969 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1008 reg-shift = <2>; 970 reg-shift = <2>;
1009 reg-io-width = <4>; 971 reg-io-width = <4>;
1010 clocks = <&ccu CLK_BU 972 clocks = <&ccu CLK_BUS_UART1>;
1011 resets = <&ccu RST_BU 973 resets = <&ccu RST_BUS_UART1>;
1012 status = "disabled"; 974 status = "disabled";
1013 }; 975 };
1014 976
1015 uart2: serial@1c28800 { 977 uart2: serial@1c28800 {
1016 compatible = "snps,dw 978 compatible = "snps,dw-apb-uart";
1017 reg = <0x01c28800 0x4 979 reg = <0x01c28800 0x400>;
1018 interrupts = <GIC_SPI 980 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1019 reg-shift = <2>; 981 reg-shift = <2>;
1020 reg-io-width = <4>; 982 reg-io-width = <4>;
1021 clocks = <&ccu CLK_BU 983 clocks = <&ccu CLK_BUS_UART2>;
1022 resets = <&ccu RST_BU 984 resets = <&ccu RST_BUS_UART2>;
1023 status = "disabled"; 985 status = "disabled";
1024 }; 986 };
1025 987
1026 uart3: serial@1c28c00 { 988 uart3: serial@1c28c00 {
1027 compatible = "snps,dw 989 compatible = "snps,dw-apb-uart";
1028 reg = <0x01c28c00 0x4 990 reg = <0x01c28c00 0x400>;
1029 interrupts = <GIC_SPI 991 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1030 reg-shift = <2>; 992 reg-shift = <2>;
1031 reg-io-width = <4>; 993 reg-io-width = <4>;
1032 clocks = <&ccu CLK_BU 994 clocks = <&ccu CLK_BUS_UART3>;
1033 resets = <&ccu RST_BU 995 resets = <&ccu RST_BUS_UART3>;
1034 status = "disabled"; 996 status = "disabled";
1035 }; 997 };
1036 998
1037 uart4: serial@1c29000 { 999 uart4: serial@1c29000 {
1038 compatible = "snps,dw 1000 compatible = "snps,dw-apb-uart";
1039 reg = <0x01c29000 0x4 1001 reg = <0x01c29000 0x400>;
1040 interrupts = <GIC_SPI 1002 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1041 reg-shift = <2>; 1003 reg-shift = <2>;
1042 reg-io-width = <4>; 1004 reg-io-width = <4>;
1043 clocks = <&ccu CLK_BU 1005 clocks = <&ccu CLK_BUS_UART4>;
1044 resets = <&ccu RST_BU 1006 resets = <&ccu RST_BUS_UART4>;
1045 status = "disabled"; 1007 status = "disabled";
1046 }; 1008 };
1047 1009
1048 i2c0: i2c@1c2ac00 { 1010 i2c0: i2c@1c2ac00 {
1049 compatible = "allwinn 1011 compatible = "allwinner,sun6i-a31-i2c";
1050 reg = <0x01c2ac00 0x4 1012 reg = <0x01c2ac00 0x400>;
1051 interrupts = <GIC_SPI 1013 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1052 clocks = <&ccu CLK_BU 1014 clocks = <&ccu CLK_BUS_I2C0>;
1053 resets = <&ccu RST_BU 1015 resets = <&ccu RST_BUS_I2C0>;
1054 pinctrl-names = "defa 1016 pinctrl-names = "default";
1055 pinctrl-0 = <&i2c0_pi 1017 pinctrl-0 = <&i2c0_pins>;
1056 status = "disabled"; 1018 status = "disabled";
1057 #address-cells = <1>; 1019 #address-cells = <1>;
1058 #size-cells = <0>; 1020 #size-cells = <0>;
1059 }; 1021 };
1060 1022
1061 i2c1: i2c@1c2b000 { 1023 i2c1: i2c@1c2b000 {
1062 compatible = "allwinn 1024 compatible = "allwinner,sun6i-a31-i2c";
1063 reg = <0x01c2b000 0x4 1025 reg = <0x01c2b000 0x400>;
1064 interrupts = <GIC_SPI 1026 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1065 clocks = <&ccu CLK_BU 1027 clocks = <&ccu CLK_BUS_I2C1>;
1066 resets = <&ccu RST_BU 1028 resets = <&ccu RST_BUS_I2C1>;
1067 pinctrl-names = "defa 1029 pinctrl-names = "default";
1068 pinctrl-0 = <&i2c1_pi 1030 pinctrl-0 = <&i2c1_pins>;
1069 status = "disabled"; 1031 status = "disabled";
1070 #address-cells = <1>; 1032 #address-cells = <1>;
1071 #size-cells = <0>; 1033 #size-cells = <0>;
1072 }; 1034 };
1073 1035
1074 i2c2: i2c@1c2b400 { 1036 i2c2: i2c@1c2b400 {
1075 compatible = "allwinn 1037 compatible = "allwinner,sun6i-a31-i2c";
1076 reg = <0x01c2b400 0x4 1038 reg = <0x01c2b400 0x400>;
1077 interrupts = <GIC_SPI 1039 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1078 clocks = <&ccu CLK_BU 1040 clocks = <&ccu CLK_BUS_I2C2>;
1079 resets = <&ccu RST_BU 1041 resets = <&ccu RST_BUS_I2C2>;
1080 pinctrl-names = "defa 1042 pinctrl-names = "default";
1081 pinctrl-0 = <&i2c2_pi 1043 pinctrl-0 = <&i2c2_pins>;
1082 status = "disabled"; 1044 status = "disabled";
1083 #address-cells = <1>; 1045 #address-cells = <1>;
1084 #size-cells = <0>; 1046 #size-cells = <0>;
1085 }; 1047 };
1086 1048
1087 spi0: spi@1c68000 { 1049 spi0: spi@1c68000 {
1088 compatible = "allwinn 1050 compatible = "allwinner,sun8i-h3-spi";
1089 reg = <0x01c68000 0x1 1051 reg = <0x01c68000 0x1000>;
1090 interrupts = <GIC_SPI 1052 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1091 clocks = <&ccu CLK_BU 1053 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
1092 clock-names = "ahb", 1054 clock-names = "ahb", "mod";
1093 dmas = <&dma 23>, <&d 1055 dmas = <&dma 23>, <&dma 23>;
1094 dma-names = "rx", "tx 1056 dma-names = "rx", "tx";
1095 pinctrl-names = "defa 1057 pinctrl-names = "default";
1096 pinctrl-0 = <&spi0_pi 1058 pinctrl-0 = <&spi0_pins>;
1097 resets = <&ccu RST_BU 1059 resets = <&ccu RST_BUS_SPI0>;
1098 status = "disabled"; 1060 status = "disabled";
1099 num-cs = <1>; 1061 num-cs = <1>;
1100 #address-cells = <1>; 1062 #address-cells = <1>;
1101 #size-cells = <0>; 1063 #size-cells = <0>;
1102 }; 1064 };
1103 1065
1104 spi1: spi@1c69000 { 1066 spi1: spi@1c69000 {
1105 compatible = "allwinn 1067 compatible = "allwinner,sun8i-h3-spi";
1106 reg = <0x01c69000 0x1 1068 reg = <0x01c69000 0x1000>;
1107 interrupts = <GIC_SPI 1069 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1108 clocks = <&ccu CLK_BU 1070 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
1109 clock-names = "ahb", 1071 clock-names = "ahb", "mod";
1110 dmas = <&dma 24>, <&d 1072 dmas = <&dma 24>, <&dma 24>;
1111 dma-names = "rx", "tx 1073 dma-names = "rx", "tx";
1112 pinctrl-names = "defa 1074 pinctrl-names = "default";
1113 pinctrl-0 = <&spi1_pi 1075 pinctrl-0 = <&spi1_pins>;
1114 resets = <&ccu RST_BU 1076 resets = <&ccu RST_BUS_SPI1>;
1115 status = "disabled"; 1077 status = "disabled";
1116 num-cs = <1>; 1078 num-cs = <1>;
1117 #address-cells = <1>; 1079 #address-cells = <1>;
1118 #size-cells = <0>; 1080 #size-cells = <0>;
1119 }; 1081 };
1120 1082
1121 emac: ethernet@1c30000 { 1083 emac: ethernet@1c30000 {
1122 compatible = "allwinn 1084 compatible = "allwinner,sun50i-a64-emac";
1123 syscon = <&syscon>; 1085 syscon = <&syscon>;
1124 reg = <0x01c30000 0x1 1086 reg = <0x01c30000 0x10000>;
1125 interrupts = <GIC_SPI 1087 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1126 interrupt-names = "ma 1088 interrupt-names = "macirq";
1127 resets = <&ccu RST_BU 1089 resets = <&ccu RST_BUS_EMAC>;
1128 reset-names = "stmmac 1090 reset-names = "stmmaceth";
1129 clocks = <&ccu CLK_BU 1091 clocks = <&ccu CLK_BUS_EMAC>;
1130 clock-names = "stmmac 1092 clock-names = "stmmaceth";
1131 status = "disabled"; 1093 status = "disabled";
1132 1094
1133 mdio: mdio { 1095 mdio: mdio {
1134 compatible = 1096 compatible = "snps,dwmac-mdio";
1135 #address-cell 1097 #address-cells = <1>;
1136 #size-cells = 1098 #size-cells = <0>;
1137 }; 1099 };
1138 }; 1100 };
1139 1101
1140 mali: gpu@1c40000 { 1102 mali: gpu@1c40000 {
1141 compatible = "allwinn 1103 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400";
1142 reg = <0x01c40000 0x1 1104 reg = <0x01c40000 0x10000>;
1143 interrupts = <GIC_SPI 1105 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1144 <GIC_SPI 1106 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1145 <GIC_SPI 1107 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1146 <GIC_SPI 1108 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1147 <GIC_SPI 1109 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1148 <GIC_SPI 1110 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1149 <GIC_SPI 1111 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1150 interrupt-names = "gp 1112 interrupt-names = "gp",
1151 "gp 1113 "gpmmu",
1152 "pp 1114 "pp0",
1153 "pp 1115 "ppmmu0",
1154 "pp 1116 "pp1",
1155 "pp 1117 "ppmmu1",
1156 "pm 1118 "pmu";
1157 clocks = <&ccu CLK_BU 1119 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
1158 clock-names = "bus", 1120 clock-names = "bus", "core";
1159 resets = <&ccu RST_BU 1121 resets = <&ccu RST_BUS_GPU>;
1160 operating-points-v2 = 1122 operating-points-v2 = <&gpu_opp_table>;
1161 }; 1123 };
1162 1124
1163 gic: interrupt-controller@1c8 1125 gic: interrupt-controller@1c81000 {
1164 compatible = "arm,gic 1126 compatible = "arm,gic-400";
1165 reg = <0x01c81000 0x1 1127 reg = <0x01c81000 0x1000>,
1166 <0x01c82000 0x2 1128 <0x01c82000 0x2000>,
1167 <0x01c84000 0x2 1129 <0x01c84000 0x2000>,
1168 <0x01c86000 0x2 1130 <0x01c86000 0x2000>;
1169 interrupts = <GIC_PPI 1131 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1170 interrupt-controller; 1132 interrupt-controller;
1171 #interrupt-cells = <3 1133 #interrupt-cells = <3>;
1172 }; 1134 };
1173 1135
1174 pwm: pwm@1c21400 { 1136 pwm: pwm@1c21400 {
1175 compatible = "allwinn 1137 compatible = "allwinner,sun50i-a64-pwm",
1176 "allwinn 1138 "allwinner,sun5i-a13-pwm";
1177 reg = <0x01c21400 0x4 1139 reg = <0x01c21400 0x400>;
1178 clocks = <&osc24M>; 1140 clocks = <&osc24M>;
1179 pinctrl-names = "defa 1141 pinctrl-names = "default";
1180 pinctrl-0 = <&pwm_pin 1142 pinctrl-0 = <&pwm_pin>;
1181 #pwm-cells = <3>; 1143 #pwm-cells = <3>;
1182 status = "disabled"; 1144 status = "disabled";
1183 }; 1145 };
1184 1146
1185 mbus: dram-controller@1c62000 1147 mbus: dram-controller@1c62000 {
1186 compatible = "allwinn 1148 compatible = "allwinner,sun50i-a64-mbus";
1187 reg = <0x01c62000 0x1 !! 1149 reg = <0x01c62000 0x1000>;
1188 <0x01c63000 0x1 !! 1150 clocks = <&ccu 112>;
1189 reg-names = "mbus", " <<
1190 clocks = <&ccu CLK_MB <<
1191 <&ccu CLK_DR <<
1192 <&ccu CLK_BU <<
1193 clock-names = "mbus", <<
1194 interrupts = <GIC_SPI <<
1195 #address-cells = <1>; 1151 #address-cells = <1>;
1196 #size-cells = <1>; 1152 #size-cells = <1>;
1197 dma-ranges = <0x00000 1153 dma-ranges = <0x00000000 0x40000000 0xc0000000>;
1198 #interconnect-cells = 1154 #interconnect-cells = <1>;
1199 }; 1155 };
1200 1156
1201 csi: csi@1cb0000 { 1157 csi: csi@1cb0000 {
1202 compatible = "allwinn 1158 compatible = "allwinner,sun50i-a64-csi";
1203 reg = <0x01cb0000 0x1 1159 reg = <0x01cb0000 0x1000>;
1204 interrupts = <GIC_SPI 1160 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1205 clocks = <&ccu CLK_BU 1161 clocks = <&ccu CLK_BUS_CSI>,
1206 <&ccu CLK_CS 1162 <&ccu CLK_CSI_SCLK>,
1207 <&ccu CLK_DR 1163 <&ccu CLK_DRAM_CSI>;
1208 clock-names = "bus", 1164 clock-names = "bus", "mod", "ram";
1209 resets = <&ccu RST_BU 1165 resets = <&ccu RST_BUS_CSI>;
1210 pinctrl-names = "defa 1166 pinctrl-names = "default";
1211 pinctrl-0 = <&csi_pin 1167 pinctrl-0 = <&csi_pins>;
1212 status = "disabled"; 1168 status = "disabled";
1213 }; 1169 };
1214 1170
1215 dsi: dsi@1ca0000 { 1171 dsi: dsi@1ca0000 {
1216 compatible = "allwinn 1172 compatible = "allwinner,sun50i-a64-mipi-dsi";
1217 reg = <0x01ca0000 0x1 1173 reg = <0x01ca0000 0x1000>;
1218 interrupts = <GIC_SPI 1174 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1219 clocks = <&ccu CLK_BU 1175 clocks = <&ccu CLK_BUS_MIPI_DSI>;
1220 resets = <&ccu RST_BU 1176 resets = <&ccu RST_BUS_MIPI_DSI>;
1221 phys = <&dphy>; 1177 phys = <&dphy>;
1222 phy-names = "dphy"; 1178 phy-names = "dphy";
1223 status = "disabled"; 1179 status = "disabled";
1224 #address-cells = <1>; 1180 #address-cells = <1>;
1225 #size-cells = <0>; 1181 #size-cells = <0>;
1226 1182
1227 port { 1183 port {
1228 dsi_in_tcon0: 1184 dsi_in_tcon0: endpoint {
1229 remot 1185 remote-endpoint = <&tcon0_out_dsi>;
1230 }; 1186 };
1231 }; 1187 };
1232 }; 1188 };
1233 1189
1234 dphy: d-phy@1ca1000 { 1190 dphy: d-phy@1ca1000 {
1235 compatible = "allwinn 1191 compatible = "allwinner,sun50i-a64-mipi-dphy",
1236 "allwinn 1192 "allwinner,sun6i-a31-mipi-dphy";
1237 reg = <0x01ca1000 0x1 1193 reg = <0x01ca1000 0x1000>;
1238 interrupts = <GIC_SPI <<
1239 clocks = <&ccu CLK_BU 1194 clocks = <&ccu CLK_BUS_MIPI_DSI>,
1240 <&ccu CLK_DS 1195 <&ccu CLK_DSI_DPHY>;
1241 clock-names = "bus", 1196 clock-names = "bus", "mod";
1242 resets = <&ccu RST_BU 1197 resets = <&ccu RST_BUS_MIPI_DSI>;
1243 status = "disabled"; 1198 status = "disabled";
1244 #phy-cells = <0>; 1199 #phy-cells = <0>;
1245 }; 1200 };
1246 1201
1247 deinterlace: deinterlace@1e00 1202 deinterlace: deinterlace@1e00000 {
1248 compatible = "allwinn 1203 compatible = "allwinner,sun50i-a64-deinterlace",
1249 "allwinn 1204 "allwinner,sun8i-h3-deinterlace";
1250 reg = <0x01e00000 0x2 1205 reg = <0x01e00000 0x20000>;
1251 clocks = <&ccu CLK_BU 1206 clocks = <&ccu CLK_BUS_DEINTERLACE>,
1252 <&ccu CLK_DE 1207 <&ccu CLK_DEINTERLACE>,
1253 <&ccu CLK_DR 1208 <&ccu CLK_DRAM_DEINTERLACE>;
1254 clock-names = "bus", 1209 clock-names = "bus", "mod", "ram";
1255 resets = <&ccu RST_BU 1210 resets = <&ccu RST_BUS_DEINTERLACE>;
1256 interrupts = <GIC_SPI 1211 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1257 interconnects = <&mbu 1212 interconnects = <&mbus 9>;
1258 interconnect-names = 1213 interconnect-names = "dma-mem";
1259 }; 1214 };
1260 1215
1261 hdmi: hdmi@1ee0000 { 1216 hdmi: hdmi@1ee0000 {
1262 compatible = "allwinn 1217 compatible = "allwinner,sun50i-a64-dw-hdmi",
1263 "allwinn 1218 "allwinner,sun8i-a83t-dw-hdmi";
1264 reg = <0x01ee0000 0x1 1219 reg = <0x01ee0000 0x10000>;
1265 reg-io-width = <1>; 1220 reg-io-width = <1>;
1266 interrupts = <GIC_SPI 1221 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1267 clocks = <&ccu CLK_BU 1222 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1268 <&ccu CLK_HD !! 1223 <&ccu CLK_HDMI>;
1269 clock-names = "iahb", !! 1224 clock-names = "iahb", "isfr", "tmds";
1270 resets = <&ccu RST_BU 1225 resets = <&ccu RST_BUS_HDMI1>;
1271 reset-names = "ctrl"; 1226 reset-names = "ctrl";
1272 phys = <&hdmi_phy>; 1227 phys = <&hdmi_phy>;
1273 phy-names = "phy"; 1228 phy-names = "phy";
1274 status = "disabled"; 1229 status = "disabled";
1275 1230
1276 ports { 1231 ports {
1277 #address-cell 1232 #address-cells = <1>;
1278 #size-cells = 1233 #size-cells = <0>;
1279 1234
1280 hdmi_in: port 1235 hdmi_in: port@0 {
1281 reg = 1236 reg = <0>;
1282 1237
1283 hdmi_ 1238 hdmi_in_tcon1: endpoint {
1284 1239 remote-endpoint = <&tcon1_out_hdmi>;
1285 }; 1240 };
1286 }; 1241 };
1287 1242
1288 hdmi_out: por 1243 hdmi_out: port@1 {
1289 reg = 1244 reg = <1>;
1290 }; 1245 };
1291 }; 1246 };
1292 }; 1247 };
1293 1248
1294 hdmi_phy: hdmi-phy@1ef0000 { 1249 hdmi_phy: hdmi-phy@1ef0000 {
1295 compatible = "allwinn 1250 compatible = "allwinner,sun50i-a64-hdmi-phy";
1296 reg = <0x01ef0000 0x1 1251 reg = <0x01ef0000 0x10000>;
1297 clocks = <&ccu CLK_BU 1252 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1298 <&ccu CLK_PL 1253 <&ccu CLK_PLL_VIDEO0>;
1299 clock-names = "bus", 1254 clock-names = "bus", "mod", "pll-0";
1300 resets = <&ccu RST_BU 1255 resets = <&ccu RST_BUS_HDMI0>;
1301 reset-names = "phy"; 1256 reset-names = "phy";
1302 #phy-cells = <0>; 1257 #phy-cells = <0>;
1303 }; 1258 };
1304 1259
1305 rtc: rtc@1f00000 { 1260 rtc: rtc@1f00000 {
1306 compatible = "allwinn 1261 compatible = "allwinner,sun50i-a64-rtc",
1307 "allwinn 1262 "allwinner,sun8i-h3-rtc";
1308 reg = <0x01f00000 0x4 1263 reg = <0x01f00000 0x400>;
1309 interrupt-parent = <& 1264 interrupt-parent = <&r_intc>;
1310 interrupts = <GIC_SPI 1265 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1311 <GIC_SPI 1266 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1312 clock-output-names = 1267 clock-output-names = "osc32k", "osc32k-out", "iosc";
1313 clocks = <&osc32k>; 1268 clocks = <&osc32k>;
1314 #clock-cells = <1>; 1269 #clock-cells = <1>;
1315 }; 1270 };
1316 1271
1317 r_intc: interrupt-controller@ 1272 r_intc: interrupt-controller@1f00c00 {
1318 compatible = "allwinn 1273 compatible = "allwinner,sun50i-a64-r-intc",
1319 "allwinn 1274 "allwinner,sun6i-a31-r-intc";
1320 interrupt-controller; 1275 interrupt-controller;
1321 #interrupt-cells = <3 1276 #interrupt-cells = <3>;
1322 reg = <0x01f00c00 0x4 1277 reg = <0x01f00c00 0x400>;
1323 interrupts = <GIC_SPI 1278 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1324 }; 1279 };
1325 1280
1326 r_ccu: clock@1f01400 { 1281 r_ccu: clock@1f01400 {
1327 compatible = "allwinn 1282 compatible = "allwinner,sun50i-a64-r-ccu";
1328 reg = <0x01f01400 0x1 1283 reg = <0x01f01400 0x100>;
1329 clocks = <&osc24M>, < !! 1284 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
1330 <&ccu CLK_PL 1285 <&ccu CLK_PLL_PERIPH0>;
1331 clock-names = "hosc", 1286 clock-names = "hosc", "losc", "iosc", "pll-periph";
1332 #clock-cells = <1>; 1287 #clock-cells = <1>;
1333 #reset-cells = <1>; 1288 #reset-cells = <1>;
1334 }; 1289 };
1335 1290
1336 codec_analog: codec-analog@1f 1291 codec_analog: codec-analog@1f015c0 {
1337 compatible = "allwinn 1292 compatible = "allwinner,sun50i-a64-codec-analog";
1338 reg = <0x01f015c0 0x4 1293 reg = <0x01f015c0 0x4>;
1339 status = "disabled"; 1294 status = "disabled";
1340 }; 1295 };
1341 1296
1342 r_i2c: i2c@1f02400 { 1297 r_i2c: i2c@1f02400 {
1343 compatible = "allwinn 1298 compatible = "allwinner,sun50i-a64-i2c",
1344 "allwinn 1299 "allwinner,sun6i-a31-i2c";
1345 reg = <0x01f02400 0x4 1300 reg = <0x01f02400 0x400>;
1346 interrupts = <GIC_SPI 1301 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1347 clocks = <&r_ccu CLK_ 1302 clocks = <&r_ccu CLK_APB0_I2C>;
1348 resets = <&r_ccu RST_ 1303 resets = <&r_ccu RST_APB0_I2C>;
1349 status = "disabled"; 1304 status = "disabled";
1350 #address-cells = <1>; 1305 #address-cells = <1>;
1351 #size-cells = <0>; 1306 #size-cells = <0>;
1352 }; 1307 };
1353 1308
1354 r_ir: ir@1f02000 { 1309 r_ir: ir@1f02000 {
1355 compatible = "allwinn 1310 compatible = "allwinner,sun50i-a64-ir",
1356 "allwinn 1311 "allwinner,sun6i-a31-ir";
1357 reg = <0x01f02000 0x4 1312 reg = <0x01f02000 0x400>;
1358 clocks = <&r_ccu CLK_ 1313 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
1359 clock-names = "apb", 1314 clock-names = "apb", "ir";
1360 resets = <&r_ccu RST_ 1315 resets = <&r_ccu RST_APB0_IR>;
1361 interrupts = <GIC_SPI 1316 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1362 pinctrl-names = "defa 1317 pinctrl-names = "default";
1363 pinctrl-0 = <&r_ir_rx 1318 pinctrl-0 = <&r_ir_rx_pin>;
1364 status = "disabled"; 1319 status = "disabled";
1365 }; 1320 };
1366 1321
1367 r_pwm: pwm@1f03800 { 1322 r_pwm: pwm@1f03800 {
1368 compatible = "allwinn 1323 compatible = "allwinner,sun50i-a64-pwm",
1369 "allwinn 1324 "allwinner,sun5i-a13-pwm";
1370 reg = <0x01f03800 0x4 1325 reg = <0x01f03800 0x400>;
1371 clocks = <&osc24M>; 1326 clocks = <&osc24M>;
1372 pinctrl-names = "defa 1327 pinctrl-names = "default";
1373 pinctrl-0 = <&r_pwm_p 1328 pinctrl-0 = <&r_pwm_pin>;
1374 #pwm-cells = <3>; 1329 #pwm-cells = <3>;
1375 status = "disabled"; 1330 status = "disabled";
1376 }; 1331 };
1377 1332
1378 r_pio: pinctrl@1f02c00 { 1333 r_pio: pinctrl@1f02c00 {
1379 compatible = "allwinn 1334 compatible = "allwinner,sun50i-a64-r-pinctrl";
1380 reg = <0x01f02c00 0x4 1335 reg = <0x01f02c00 0x400>;
1381 interrupt-parent = <& 1336 interrupt-parent = <&r_intc>;
1382 interrupts = <GIC_SPI 1337 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1383 clocks = <&r_ccu CLK_ 1338 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
1384 clock-names = "apb", 1339 clock-names = "apb", "hosc", "losc";
1385 gpio-controller; 1340 gpio-controller;
1386 #gpio-cells = <3>; 1341 #gpio-cells = <3>;
1387 interrupt-controller; 1342 interrupt-controller;
1388 #interrupt-cells = <3 1343 #interrupt-cells = <3>;
1389 1344
1390 r_i2c_pl89_pins: r-i2 1345 r_i2c_pl89_pins: r-i2c-pl89-pins {
1391 pins = "PL8", 1346 pins = "PL8", "PL9";
1392 function = "s 1347 function = "s_i2c";
1393 }; 1348 };
1394 1349
1395 r_ir_rx_pin: r-ir-rx- 1350 r_ir_rx_pin: r-ir-rx-pin {
1396 pins = "PL11" 1351 pins = "PL11";
1397 function = "s 1352 function = "s_cir_rx";
1398 }; 1353 };
1399 1354
1400 r_pwm_pin: r-pwm-pin 1355 r_pwm_pin: r-pwm-pin {
1401 pins = "PL10" 1356 pins = "PL10";
1402 function = "s 1357 function = "s_pwm";
1403 }; 1358 };
1404 1359
1405 r_rsb_pins: r-rsb-pin 1360 r_rsb_pins: r-rsb-pins {
1406 pins = "PL0", 1361 pins = "PL0", "PL1";
1407 function = "s 1362 function = "s_rsb";
1408 }; 1363 };
1409 }; 1364 };
1410 1365
1411 r_rsb: rsb@1f03400 { 1366 r_rsb: rsb@1f03400 {
1412 compatible = "allwinn 1367 compatible = "allwinner,sun8i-a23-rsb";
1413 reg = <0x01f03400 0x4 1368 reg = <0x01f03400 0x400>;
1414 interrupts = <GIC_SPI 1369 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1415 clocks = <&r_ccu 6>; 1370 clocks = <&r_ccu 6>;
1416 clock-frequency = <30 1371 clock-frequency = <3000000>;
1417 resets = <&r_ccu 2>; 1372 resets = <&r_ccu 2>;
1418 pinctrl-names = "defa 1373 pinctrl-names = "default";
1419 pinctrl-0 = <&r_rsb_p 1374 pinctrl-0 = <&r_rsb_pins>;
1420 status = "disabled"; 1375 status = "disabled";
1421 #address-cells = <1>; 1376 #address-cells = <1>;
1422 #size-cells = <0>; 1377 #size-cells = <0>;
1423 }; 1378 };
1424 }; 1379 };
1425 }; 1380 };
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