1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) !! 1 /*
2 // Copyright (C) 2016 ARM Ltd. !! 2 * Copyright (C) 2016 ARM Ltd.
3 // based on the Allwinner H3 dtsi: !! 3 * based on the Allwinner H3 dtsi:
4 // Copyright (C) 2015 Jens Kuske <jenskuske@ !! 4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
>> 5 *
>> 6 * This file is dual-licensed: you can use it either under the terms
>> 7 * of the GPL or the X11 license, at your option. Note that this dual
>> 8 * licensing only applies to this file, and not this project as a
>> 9 * whole.
>> 10 *
>> 11 * a) This file is free software; you can redistribute it and/or
>> 12 * modify it under the terms of the GNU General Public License as
>> 13 * published by the Free Software Foundation; either version 2 of the
>> 14 * License, or (at your option) any later version.
>> 15 *
>> 16 * This file is distributed in the hope that it will be useful,
>> 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 19 * GNU General Public License for more details.
>> 20 *
>> 21 * Or, alternatively,
>> 22 *
>> 23 * b) Permission is hereby granted, free of charge, to any person
>> 24 * obtaining a copy of this software and associated documentation
>> 25 * files (the "Software"), to deal in the Software without
>> 26 * restriction, including without limitation the rights to use,
>> 27 * copy, modify, merge, publish, distribute, sublicense, and/or
>> 28 * sell copies of the Software, and to permit persons to whom the
>> 29 * Software is furnished to do so, subject to the following
>> 30 * conditions:
>> 31 *
>> 32 * The above copyright notice and this permission notice shall be
>> 33 * included in all copies or substantial portions of the Software.
>> 34 *
>> 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> 42 * OTHER DEALINGS IN THE SOFTWARE.
>> 43 */
5 44
6 #include <dt-bindings/clock/sun50i-a64-ccu.h> 45 #include <dt-bindings/clock/sun50i-a64-ccu.h>
7 #include <dt-bindings/clock/sun6i-rtc.h> <<
8 #include <dt-bindings/clock/sun8i-de2.h> 46 #include <dt-bindings/clock/sun8i-de2.h>
9 #include <dt-bindings/clock/sun8i-r-ccu.h> 47 #include <dt-bindings/clock/sun8i-r-ccu.h>
10 #include <dt-bindings/interrupt-controller/arm 48 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/sun50i-a64-ccu.h> 49 #include <dt-bindings/reset/sun50i-a64-ccu.h>
12 #include <dt-bindings/reset/sun8i-de2.h> 50 #include <dt-bindings/reset/sun8i-de2.h>
13 #include <dt-bindings/reset/sun8i-r-ccu.h> 51 #include <dt-bindings/reset/sun8i-r-ccu.h>
14 #include <dt-bindings/thermal/thermal.h> <<
15 52
16 / { 53 / {
17 interrupt-parent = <&gic>; 54 interrupt-parent = <&gic>;
18 #address-cells = <1>; 55 #address-cells = <1>;
19 #size-cells = <1>; 56 #size-cells = <1>;
20 57
21 chosen { 58 chosen {
22 #address-cells = <1>; 59 #address-cells = <1>;
23 #size-cells = <1>; 60 #size-cells = <1>;
24 ranges; 61 ranges;
25 62
26 simplefb_lcd: framebuffer-lcd 63 simplefb_lcd: framebuffer-lcd {
27 compatible = "allwinne 64 compatible = "allwinner,simple-framebuffer",
28 "simple-f 65 "simple-framebuffer";
29 allwinner,pipeline = " 66 allwinner,pipeline = "mixer0-lcd0";
30 clocks = <&ccu CLK_TCO 67 clocks = <&ccu CLK_TCON0>,
31 <&display_clo 68 <&display_clocks CLK_MIXER0>;
32 status = "disabled"; 69 status = "disabled";
33 }; 70 };
34 71
35 simplefb_hdmi: framebuffer-hdm 72 simplefb_hdmi: framebuffer-hdmi {
36 compatible = "allwinne 73 compatible = "allwinner,simple-framebuffer",
37 "simple-f 74 "simple-framebuffer";
38 allwinner,pipeline = " 75 allwinner,pipeline = "mixer1-lcd1-hdmi";
39 clocks = <&display_clo 76 clocks = <&display_clocks CLK_MIXER1>,
40 <&ccu CLK_TCO 77 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
41 status = "disabled"; 78 status = "disabled";
42 }; 79 };
43 }; 80 };
44 81
45 cpus { 82 cpus {
46 #address-cells = <1>; 83 #address-cells = <1>;
47 #size-cells = <0>; 84 #size-cells = <0>;
48 85
49 cpu0: cpu@0 { 86 cpu0: cpu@0 {
50 compatible = "arm,cort 87 compatible = "arm,cortex-a53";
51 device_type = "cpu"; 88 device_type = "cpu";
52 reg = <0>; 89 reg = <0>;
53 enable-method = "psci" 90 enable-method = "psci";
54 clocks = <&ccu CLK_CPU !! 91 next-level-cache = <&L2>;
55 clock-names = "cpu"; <<
56 #cooling-cells = <2>; <<
57 i-cache-size = <0x8000 <<
58 i-cache-line-size = <6 <<
59 i-cache-sets = <256>; <<
60 d-cache-size = <0x8000 <<
61 d-cache-line-size = <6 <<
62 d-cache-sets = <128>; <<
63 next-level-cache = <&l <<
64 }; 92 };
65 93
66 cpu1: cpu@1 { 94 cpu1: cpu@1 {
67 compatible = "arm,cort 95 compatible = "arm,cortex-a53";
68 device_type = "cpu"; 96 device_type = "cpu";
69 reg = <1>; 97 reg = <1>;
70 enable-method = "psci" 98 enable-method = "psci";
71 clocks = <&ccu CLK_CPU !! 99 next-level-cache = <&L2>;
72 clock-names = "cpu"; <<
73 #cooling-cells = <2>; <<
74 i-cache-size = <0x8000 <<
75 i-cache-line-size = <6 <<
76 i-cache-sets = <256>; <<
77 d-cache-size = <0x8000 <<
78 d-cache-line-size = <6 <<
79 d-cache-sets = <128>; <<
80 next-level-cache = <&l <<
81 }; 100 };
82 101
83 cpu2: cpu@2 { 102 cpu2: cpu@2 {
84 compatible = "arm,cort 103 compatible = "arm,cortex-a53";
85 device_type = "cpu"; 104 device_type = "cpu";
86 reg = <2>; 105 reg = <2>;
87 enable-method = "psci" 106 enable-method = "psci";
88 clocks = <&ccu CLK_CPU !! 107 next-level-cache = <&L2>;
89 clock-names = "cpu"; <<
90 #cooling-cells = <2>; <<
91 i-cache-size = <0x8000 <<
92 i-cache-line-size = <6 <<
93 i-cache-sets = <256>; <<
94 d-cache-size = <0x8000 <<
95 d-cache-line-size = <6 <<
96 d-cache-sets = <128>; <<
97 next-level-cache = <&l <<
98 }; 108 };
99 109
100 cpu3: cpu@3 { 110 cpu3: cpu@3 {
101 compatible = "arm,cort 111 compatible = "arm,cortex-a53";
102 device_type = "cpu"; 112 device_type = "cpu";
103 reg = <3>; 113 reg = <3>;
104 enable-method = "psci" 114 enable-method = "psci";
105 clocks = <&ccu CLK_CPU !! 115 next-level-cache = <&L2>;
106 clock-names = "cpu"; <<
107 #cooling-cells = <2>; <<
108 i-cache-size = <0x8000 <<
109 i-cache-line-size = <6 <<
110 i-cache-sets = <256>; <<
111 d-cache-size = <0x8000 <<
112 d-cache-line-size = <6 <<
113 d-cache-sets = <128>; <<
114 next-level-cache = <&l <<
115 }; 116 };
116 117
117 l2_cache: l2-cache { !! 118 L2: l2-cache {
118 compatible = "cache"; 119 compatible = "cache";
119 cache-level = <2>; 120 cache-level = <2>;
120 cache-unified; <<
121 cache-size = <0x80000> <<
122 cache-line-size = <64> <<
123 cache-sets = <512>; <<
124 }; 121 };
125 }; 122 };
126 123
127 de: display-engine { 124 de: display-engine {
128 compatible = "allwinner,sun50i 125 compatible = "allwinner,sun50i-a64-display-engine";
129 allwinner,pipelines = <&mixer0 126 allwinner,pipelines = <&mixer0>,
130 <&mixer1 127 <&mixer1>;
131 status = "disabled"; 128 status = "disabled";
132 }; 129 };
133 130
134 gpu_opp_table: opp-table-gpu { !! 131 osc24M: osc24M_clk {
135 compatible = "operating-points <<
136 <<
137 opp-432000000 { <<
138 opp-hz = /bits/ 64 <43 <<
139 }; <<
140 }; <<
141 <<
142 osc24M: osc24M-clk { <<
143 #clock-cells = <0>; 132 #clock-cells = <0>;
144 compatible = "fixed-clock"; 133 compatible = "fixed-clock";
145 clock-frequency = <24000000>; 134 clock-frequency = <24000000>;
146 clock-output-names = "osc24M"; 135 clock-output-names = "osc24M";
147 }; 136 };
148 137
149 osc32k: osc32k-clk { !! 138 osc32k: osc32k_clk {
150 #clock-cells = <0>; 139 #clock-cells = <0>;
151 compatible = "fixed-clock"; 140 compatible = "fixed-clock";
152 clock-frequency = <32768>; 141 clock-frequency = <32768>;
153 clock-output-names = "ext-osc3 142 clock-output-names = "ext-osc32k";
154 }; 143 };
155 144
156 pmu { 145 pmu {
157 compatible = "arm,cortex-a53-p 146 compatible = "arm,cortex-a53-pmu";
158 interrupts = <GIC_SPI 116 IRQ_ 147 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 117 IRQ_ 148 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 118 IRQ_ 149 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 119 IRQ_ 150 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
162 interrupt-affinity = <&cpu0>, 151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
163 }; 152 };
164 153
165 psci { 154 psci {
166 compatible = "arm,psci-0.2"; 155 compatible = "arm,psci-0.2";
167 method = "smc"; 156 method = "smc";
168 }; 157 };
169 158
170 sound: sound { 159 sound: sound {
171 #address-cells = <1>; <<
172 #size-cells = <0>; <<
173 compatible = "simple-audio-car 160 compatible = "simple-audio-card";
174 simple-audio-card,name = "sun5 161 simple-audio-card,name = "sun50i-a64-audio";
>> 162 simple-audio-card,format = "i2s";
>> 163 simple-audio-card,frame-master = <&cpudai>;
>> 164 simple-audio-card,bitclock-master = <&cpudai>;
>> 165 simple-audio-card,mclk-fs = <128>;
175 simple-audio-card,aux-devs = < 166 simple-audio-card,aux-devs = <&codec_analog>;
176 simple-audio-card,routing = 167 simple-audio-card,routing =
177 "Left DAC", "D !! 168 "Left DAC", "AIF1 Slot 0 Left",
178 "Right DAC", " !! 169 "Right DAC", "AIF1 Slot 0 Right",
179 "ADCL", "Left !! 170 "AIF1 Slot 0 Left ADC", "Left ADC",
180 "ADCR", "Right !! 171 "AIF1 Slot 0 Right ADC", "Right ADC";
181 status = "disabled"; 172 status = "disabled";
182 173
183 simple-audio-card,dai-link@0 { !! 174 cpudai: simple-audio-card,cpu {
184 format = "i2s"; !! 175 sound-dai = <&dai>;
185 frame-master = <&link0 !! 176 };
186 bitclock-master = <&li <<
187 mclk-fs = <128>; <<
188 177
189 link0_cpu: cpu { !! 178 link_codec: simple-audio-card,codec {
190 sound-dai = <& !! 179 sound-dai = <&codec>;
191 }; !! 180 };
>> 181 };
192 182
193 link0_codec: codec { !! 183 sound_spdif {
194 sound-dai = <& !! 184 compatible = "simple-audio-card";
195 }; !! 185 simple-audio-card,name = "On-board SPDIF";
>> 186
>> 187 simple-audio-card,cpu {
>> 188 sound-dai = <&spdif>;
>> 189 };
>> 190
>> 191 simple-audio-card,codec {
>> 192 sound-dai = <&spdif_out>;
196 }; 193 };
197 }; 194 };
198 195
>> 196 spdif_out: spdif-out {
>> 197 #sound-dai-cells = <0>;
>> 198 compatible = "linux,spdif-dit";
>> 199 };
>> 200
199 timer { 201 timer {
200 compatible = "arm,armv8-timer" 202 compatible = "arm,armv8-timer";
201 allwinner,erratum-unknown1; 203 allwinner,erratum-unknown1;
202 arm,no-tick-in-suspend; <<
203 interrupts = <GIC_PPI 13 204 interrupts = <GIC_PPI 13
204 (GIC_CPU_MASK_SIMPLE(4 205 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
205 <GIC_PPI 14 206 <GIC_PPI 14
206 (GIC_CPU_MASK_SIMPLE(4 207 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
207 <GIC_PPI 11 208 <GIC_PPI 11
208 (GIC_CPU_MASK_SIMPLE(4 209 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
209 <GIC_PPI 10 210 <GIC_PPI 10
210 (GIC_CPU_MASK_SIMPLE(4 211 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
211 }; 212 };
212 213
213 thermal-zones { <<
214 cpu_thermal: cpu0-thermal { <<
215 /* milliseconds */ <<
216 polling-delay-passive <<
217 polling-delay = <0>; <<
218 thermal-sensors = <&th <<
219 <<
220 cooling-maps { <<
221 map0 { <<
222 trip = <<
223 coolin <<
224 <<
225 <<
226 <<
227 }; <<
228 map1 { <<
229 trip = <<
230 coolin <<
231 <<
232 <<
233 <<
234 }; <<
235 }; <<
236 <<
237 trips { <<
238 cpu_alert0: cp <<
239 /* mil <<
240 temper <<
241 hyster <<
242 type = <<
243 }; <<
244 <<
245 cpu_alert1: cp <<
246 /* mil <<
247 temper <<
248 hyster <<
249 type = <<
250 }; <<
251 <<
252 cpu_crit: cpu- <<
253 /* mil <<
254 temper <<
255 hyster <<
256 type = <<
257 }; <<
258 }; <<
259 }; <<
260 <<
261 gpu0_thermal: gpu0-thermal { <<
262 /* milliseconds */ <<
263 polling-delay-passive <<
264 polling-delay = <0>; <<
265 thermal-sensors = <&th <<
266 <<
267 trips { <<
268 gpu0_crit: gpu <<
269 temper <<
270 hyster <<
271 type = <<
272 }; <<
273 }; <<
274 }; <<
275 <<
276 gpu1_thermal: gpu1-thermal { <<
277 /* milliseconds */ <<
278 polling-delay-passive <<
279 polling-delay = <0>; <<
280 thermal-sensors = <&th <<
281 <<
282 trips { <<
283 gpu1_crit: gpu <<
284 temper <<
285 hyster <<
286 type = <<
287 }; <<
288 }; <<
289 }; <<
290 }; <<
291 <<
292 soc { 214 soc {
293 compatible = "simple-bus"; 215 compatible = "simple-bus";
294 #address-cells = <1>; 216 #address-cells = <1>;
295 #size-cells = <1>; 217 #size-cells = <1>;
296 ranges; 218 ranges;
297 219
298 bus@1000000 { 220 bus@1000000 {
299 compatible = "allwinne 221 compatible = "allwinner,sun50i-a64-de2";
300 reg = <0x1000000 0x400 222 reg = <0x1000000 0x400000>;
301 allwinner,sram = <&de2 223 allwinner,sram = <&de2_sram 1>;
302 #address-cells = <1>; 224 #address-cells = <1>;
303 #size-cells = <1>; 225 #size-cells = <1>;
304 ranges = <0 0x1000000 226 ranges = <0 0x1000000 0x400000>;
305 227
306 display_clocks: clock@ 228 display_clocks: clock@0 {
307 compatible = " 229 compatible = "allwinner,sun50i-a64-de2-clk";
308 reg = <0x0 0x1 230 reg = <0x0 0x10000>;
309 clocks = <&ccu 231 clocks = <&ccu CLK_BUS_DE>,
310 <&ccu 232 <&ccu CLK_DE>;
311 clock-names = 233 clock-names = "bus",
312 234 "mod";
313 resets = <&ccu 235 resets = <&ccu RST_BUS_DE>;
314 #clock-cells = 236 #clock-cells = <1>;
315 #reset-cells = 237 #reset-cells = <1>;
316 }; 238 };
317 239
318 rotate: rotate@20000 { <<
319 compatible = " <<
320 " <<
321 reg = <0x20000 <<
322 interrupts = < <<
323 clocks = <&dis <<
324 <&dis <<
325 clock-names = <<
326 <<
327 resets = <&dis <<
328 }; <<
329 <<
330 mixer0: mixer@100000 { 240 mixer0: mixer@100000 {
331 compatible = " 241 compatible = "allwinner,sun50i-a64-de2-mixer-0";
332 reg = <0x10000 242 reg = <0x100000 0x100000>;
333 clocks = <&dis 243 clocks = <&display_clocks CLK_BUS_MIXER0>,
334 <&dis 244 <&display_clocks CLK_MIXER0>;
335 clock-names = 245 clock-names = "bus",
336 246 "mod";
337 resets = <&dis 247 resets = <&display_clocks RST_MIXER0>;
338 248
339 ports { 249 ports {
340 #addre 250 #address-cells = <1>;
341 #size- 251 #size-cells = <0>;
342 252
343 mixer0 253 mixer0_out: port@1 {
344 254 #address-cells = <1>;
345 255 #size-cells = <0>;
346 256 reg = <1>;
347 257
348 258 mixer0_out_tcon0: endpoint@0 {
349 259 reg = <0>;
350 260 remote-endpoint = <&tcon0_in_mixer0>;
351 261 };
352 262
353 263 mixer0_out_tcon1: endpoint@1 {
354 264 reg = <1>;
355 265 remote-endpoint = <&tcon1_in_mixer0>;
356 266 };
357 }; 267 };
358 }; 268 };
359 }; 269 };
360 270
361 mixer1: mixer@200000 { 271 mixer1: mixer@200000 {
362 compatible = " 272 compatible = "allwinner,sun50i-a64-de2-mixer-1";
363 reg = <0x20000 273 reg = <0x200000 0x100000>;
364 clocks = <&dis 274 clocks = <&display_clocks CLK_BUS_MIXER1>,
365 <&dis 275 <&display_clocks CLK_MIXER1>;
366 clock-names = 276 clock-names = "bus",
367 277 "mod";
368 resets = <&dis 278 resets = <&display_clocks RST_MIXER1>;
369 279
370 ports { 280 ports {
371 #addre 281 #address-cells = <1>;
372 #size- 282 #size-cells = <0>;
373 283
374 mixer1 284 mixer1_out: port@1 {
375 285 #address-cells = <1>;
376 286 #size-cells = <0>;
377 287 reg = <1>;
378 288
379 289 mixer1_out_tcon0: endpoint@0 {
380 290 reg = <0>;
381 291 remote-endpoint = <&tcon0_in_mixer1>;
382 292 };
383 293
384 294 mixer1_out_tcon1: endpoint@1 {
385 295 reg = <1>;
386 296 remote-endpoint = <&tcon1_in_mixer1>;
387 297 };
388 }; 298 };
389 }; 299 };
390 }; 300 };
391 }; 301 };
392 302
393 syscon: syscon@1c00000 { 303 syscon: syscon@1c00000 {
394 compatible = "allwinne 304 compatible = "allwinner,sun50i-a64-system-control";
395 reg = <0x01c00000 0x10 305 reg = <0x01c00000 0x1000>;
396 #address-cells = <1>; 306 #address-cells = <1>;
397 #size-cells = <1>; 307 #size-cells = <1>;
398 ranges; 308 ranges;
399 309
400 sram_c: sram@18000 { 310 sram_c: sram@18000 {
401 compatible = " 311 compatible = "mmio-sram";
402 reg = <0x00018 312 reg = <0x00018000 0x28000>;
403 #address-cells 313 #address-cells = <1>;
404 #size-cells = 314 #size-cells = <1>;
405 ranges = <0 0x 315 ranges = <0 0x00018000 0x28000>;
406 316
407 de2_sram: sram 317 de2_sram: sram-section@0 {
408 compat 318 compatible = "allwinner,sun50i-a64-sram-c";
409 reg = 319 reg = <0x0000 0x28000>;
410 }; 320 };
411 }; 321 };
412 322
413 sram_c1: sram@1d00000 323 sram_c1: sram@1d00000 {
414 compatible = " 324 compatible = "mmio-sram";
415 reg = <0x01d00 325 reg = <0x01d00000 0x40000>;
416 #address-cells 326 #address-cells = <1>;
417 #size-cells = 327 #size-cells = <1>;
418 ranges = <0 0x 328 ranges = <0 0x01d00000 0x40000>;
419 329
420 ve_sram: sram- 330 ve_sram: sram-section@0 {
421 compat 331 compatible = "allwinner,sun50i-a64-sram-c1",
422 332 "allwinner,sun4i-a10-sram-c1";
423 reg = 333 reg = <0x000000 0x40000>;
424 }; 334 };
425 }; 335 };
426 }; 336 };
427 337
428 dma: dma-controller@1c02000 { 338 dma: dma-controller@1c02000 {
429 compatible = "allwinne 339 compatible = "allwinner,sun50i-a64-dma";
430 reg = <0x01c02000 0x10 340 reg = <0x01c02000 0x1000>;
431 interrupts = <GIC_SPI 341 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&ccu CLK_BUS 342 clocks = <&ccu CLK_BUS_DMA>;
433 dma-channels = <8>; 343 dma-channels = <8>;
434 dma-requests = <27>; 344 dma-requests = <27>;
435 resets = <&ccu RST_BUS 345 resets = <&ccu RST_BUS_DMA>;
436 #dma-cells = <1>; 346 #dma-cells = <1>;
437 }; 347 };
438 348
439 tcon0: lcd-controller@1c0c000 349 tcon0: lcd-controller@1c0c000 {
440 compatible = "allwinne 350 compatible = "allwinner,sun50i-a64-tcon-lcd",
441 "allwinne 351 "allwinner,sun8i-a83t-tcon-lcd";
442 reg = <0x01c0c000 0x10 352 reg = <0x01c0c000 0x1000>;
443 interrupts = <GIC_SPI 353 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
444 clocks = <&ccu CLK_BUS 354 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
445 clock-names = "ahb", " 355 clock-names = "ahb", "tcon-ch0";
446 clock-output-names = " !! 356 clock-output-names = "tcon-pixel-clock";
447 #clock-cells = <0>; 357 #clock-cells = <0>;
448 resets = <&ccu RST_BUS 358 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
449 reset-names = "lcd", " 359 reset-names = "lcd", "lvds";
450 360
451 ports { 361 ports {
452 #address-cells 362 #address-cells = <1>;
453 #size-cells = 363 #size-cells = <0>;
454 364
455 tcon0_in: port 365 tcon0_in: port@0 {
456 #addre 366 #address-cells = <1>;
457 #size- 367 #size-cells = <0>;
458 reg = 368 reg = <0>;
459 369
460 tcon0_ 370 tcon0_in_mixer0: endpoint@0 {
461 371 reg = <0>;
462 372 remote-endpoint = <&mixer0_out_tcon0>;
463 }; 373 };
464 374
465 tcon0_ 375 tcon0_in_mixer1: endpoint@1 {
466 376 reg = <1>;
467 377 remote-endpoint = <&mixer1_out_tcon0>;
468 }; 378 };
469 }; 379 };
470 380
471 tcon0_out: por 381 tcon0_out: port@1 {
472 #addre 382 #address-cells = <1>;
473 #size- 383 #size-cells = <0>;
474 reg = 384 reg = <1>;
475 <<
476 tcon0_ <<
477 <<
478 <<
479 <<
480 }; <<
481 }; 385 };
482 }; 386 };
483 }; 387 };
484 388
485 tcon1: lcd-controller@1c0d000 389 tcon1: lcd-controller@1c0d000 {
486 compatible = "allwinne 390 compatible = "allwinner,sun50i-a64-tcon-tv",
487 "allwinne 391 "allwinner,sun8i-a83t-tcon-tv";
488 reg = <0x01c0d000 0x10 392 reg = <0x01c0d000 0x1000>;
489 interrupts = <GIC_SPI 393 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&ccu CLK_BUS 394 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
491 clock-names = "ahb", " 395 clock-names = "ahb", "tcon-ch1";
492 resets = <&ccu RST_BUS 396 resets = <&ccu RST_BUS_TCON1>;
493 reset-names = "lcd"; 397 reset-names = "lcd";
494 398
495 ports { 399 ports {
496 #address-cells 400 #address-cells = <1>;
497 #size-cells = 401 #size-cells = <0>;
498 402
499 tcon1_in: port 403 tcon1_in: port@0 {
500 #addre 404 #address-cells = <1>;
501 #size- 405 #size-cells = <0>;
502 reg = 406 reg = <0>;
503 407
504 tcon1_ 408 tcon1_in_mixer0: endpoint@0 {
505 409 reg = <0>;
506 410 remote-endpoint = <&mixer0_out_tcon1>;
507 }; 411 };
508 412
509 tcon1_ 413 tcon1_in_mixer1: endpoint@1 {
510 414 reg = <1>;
511 415 remote-endpoint = <&mixer1_out_tcon1>;
512 }; 416 };
513 }; 417 };
514 418
515 tcon1_out: por 419 tcon1_out: port@1 {
516 #addre 420 #address-cells = <1>;
517 #size- 421 #size-cells = <0>;
518 reg = 422 reg = <1>;
519 423
520 tcon1_ 424 tcon1_out_hdmi: endpoint@1 {
521 425 reg = <1>;
522 426 remote-endpoint = <&hdmi_in_tcon1>;
523 }; 427 };
524 }; 428 };
525 }; 429 };
526 }; 430 };
527 431
528 video-codec@1c0e000 { 432 video-codec@1c0e000 {
529 compatible = "allwinne 433 compatible = "allwinner,sun50i-a64-video-engine";
530 reg = <0x01c0e000 0x10 434 reg = <0x01c0e000 0x1000>;
531 clocks = <&ccu CLK_BUS 435 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
532 <&ccu CLK_DRA 436 <&ccu CLK_DRAM_VE>;
533 clock-names = "ahb", " 437 clock-names = "ahb", "mod", "ram";
534 resets = <&ccu RST_BUS 438 resets = <&ccu RST_BUS_VE>;
535 interrupts = <GIC_SPI 439 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
536 allwinner,sram = <&ve_ 440 allwinner,sram = <&ve_sram 1>;
537 }; 441 };
538 442
539 mmc0: mmc@1c0f000 { 443 mmc0: mmc@1c0f000 {
540 compatible = "allwinne 444 compatible = "allwinner,sun50i-a64-mmc";
541 reg = <0x01c0f000 0x10 445 reg = <0x01c0f000 0x1000>;
542 clocks = <&ccu CLK_BUS 446 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
543 clock-names = "ahb", " 447 clock-names = "ahb", "mmc";
544 resets = <&ccu RST_BUS 448 resets = <&ccu RST_BUS_MMC0>;
545 reset-names = "ahb"; 449 reset-names = "ahb";
546 interrupts = <GIC_SPI 450 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
547 max-frequency = <15000 451 max-frequency = <150000000>;
548 status = "disabled"; 452 status = "disabled";
549 #address-cells = <1>; 453 #address-cells = <1>;
550 #size-cells = <0>; 454 #size-cells = <0>;
551 }; 455 };
552 456
553 mmc1: mmc@1c10000 { 457 mmc1: mmc@1c10000 {
554 compatible = "allwinne 458 compatible = "allwinner,sun50i-a64-mmc";
555 reg = <0x01c10000 0x10 459 reg = <0x01c10000 0x1000>;
556 clocks = <&ccu CLK_BUS 460 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
557 clock-names = "ahb", " 461 clock-names = "ahb", "mmc";
558 resets = <&ccu RST_BUS 462 resets = <&ccu RST_BUS_MMC1>;
559 reset-names = "ahb"; 463 reset-names = "ahb";
560 interrupts = <GIC_SPI 464 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
561 max-frequency = <15000 465 max-frequency = <150000000>;
562 status = "disabled"; 466 status = "disabled";
563 #address-cells = <1>; 467 #address-cells = <1>;
564 #size-cells = <0>; 468 #size-cells = <0>;
565 }; 469 };
566 470
567 mmc2: mmc@1c11000 { 471 mmc2: mmc@1c11000 {
568 compatible = "allwinne 472 compatible = "allwinner,sun50i-a64-emmc";
569 reg = <0x01c11000 0x10 473 reg = <0x01c11000 0x1000>;
570 clocks = <&ccu CLK_BUS 474 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
571 clock-names = "ahb", " 475 clock-names = "ahb", "mmc";
572 resets = <&ccu RST_BUS 476 resets = <&ccu RST_BUS_MMC2>;
573 reset-names = "ahb"; 477 reset-names = "ahb";
574 interrupts = <GIC_SPI 478 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
575 max-frequency = <15000 479 max-frequency = <150000000>;
576 status = "disabled"; 480 status = "disabled";
577 #address-cells = <1>; 481 #address-cells = <1>;
578 #size-cells = <0>; 482 #size-cells = <0>;
579 }; 483 };
580 484
581 sid: eeprom@1c14000 { 485 sid: eeprom@1c14000 {
582 compatible = "allwinne 486 compatible = "allwinner,sun50i-a64-sid";
583 reg = <0x1c14000 0x400 487 reg = <0x1c14000 0x400>;
584 #address-cells = <1>; <<
585 #size-cells = <1>; <<
586 <<
587 ths_calibration: therm <<
588 reg = <0x34 0x <<
589 }; <<
590 }; <<
591 <<
592 crypto: crypto@1c15000 { <<
593 compatible = "allwinne <<
594 reg = <0x01c15000 0x10 <<
595 interrupts = <GIC_SPI <<
596 clocks = <&ccu CLK_BUS <<
597 clock-names = "bus", " <<
598 resets = <&ccu RST_BUS <<
599 }; <<
600 <<
601 msgbox: mailbox@1c17000 { <<
602 compatible = "allwinne <<
603 "allwinne <<
604 reg = <0x01c17000 0x10 <<
605 clocks = <&ccu CLK_BUS <<
606 resets = <&ccu RST_BUS <<
607 interrupts = <GIC_SPI <<
608 #mbox-cells = <1>; <<
609 }; 488 };
610 489
611 usb_otg: usb@1c19000 { 490 usb_otg: usb@1c19000 {
612 compatible = "allwinne 491 compatible = "allwinner,sun8i-a33-musb";
613 reg = <0x01c19000 0x04 492 reg = <0x01c19000 0x0400>;
614 clocks = <&ccu CLK_BUS 493 clocks = <&ccu CLK_BUS_OTG>;
615 resets = <&ccu RST_BUS 494 resets = <&ccu RST_BUS_OTG>;
616 interrupts = <GIC_SPI 495 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
617 interrupt-names = "mc" 496 interrupt-names = "mc";
618 phys = <&usbphy 0>; 497 phys = <&usbphy 0>;
619 phy-names = "usb"; 498 phy-names = "usb";
620 extcon = <&usbphy 0>; 499 extcon = <&usbphy 0>;
621 dr_mode = "otg"; 500 dr_mode = "otg";
622 status = "disabled"; 501 status = "disabled";
623 }; 502 };
624 503
625 usbphy: phy@1c19400 { 504 usbphy: phy@1c19400 {
626 compatible = "allwinne 505 compatible = "allwinner,sun50i-a64-usb-phy";
627 reg = <0x01c19400 0x14 506 reg = <0x01c19400 0x14>,
628 <0x01c1a800 0x4> 507 <0x01c1a800 0x4>,
629 <0x01c1b800 0x4> 508 <0x01c1b800 0x4>;
630 reg-names = "phy_ctrl" 509 reg-names = "phy_ctrl",
631 "pmu0", 510 "pmu0",
632 "pmu1"; 511 "pmu1";
633 clocks = <&ccu CLK_USB 512 clocks = <&ccu CLK_USB_PHY0>,
634 <&ccu CLK_USB 513 <&ccu CLK_USB_PHY1>;
635 clock-names = "usb0_ph 514 clock-names = "usb0_phy",
636 "usb1_ph 515 "usb1_phy";
637 resets = <&ccu RST_USB 516 resets = <&ccu RST_USB_PHY0>,
638 <&ccu RST_USB 517 <&ccu RST_USB_PHY1>;
639 reset-names = "usb0_re 518 reset-names = "usb0_reset",
640 "usb1_re 519 "usb1_reset";
641 status = "disabled"; 520 status = "disabled";
642 #phy-cells = <1>; 521 #phy-cells = <1>;
643 }; 522 };
644 523
645 ehci0: usb@1c1a000 { 524 ehci0: usb@1c1a000 {
646 compatible = "allwinne 525 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
647 reg = <0x01c1a000 0x10 526 reg = <0x01c1a000 0x100>;
648 interrupts = <GIC_SPI 527 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
649 clocks = <&ccu CLK_BUS 528 clocks = <&ccu CLK_BUS_OHCI0>,
650 <&ccu CLK_BUS 529 <&ccu CLK_BUS_EHCI0>,
651 <&ccu CLK_USB 530 <&ccu CLK_USB_OHCI0>;
652 resets = <&ccu RST_BUS 531 resets = <&ccu RST_BUS_OHCI0>,
653 <&ccu RST_BUS 532 <&ccu RST_BUS_EHCI0>;
654 phys = <&usbphy 0>; 533 phys = <&usbphy 0>;
655 phy-names = "usb"; 534 phy-names = "usb";
656 status = "disabled"; 535 status = "disabled";
657 }; 536 };
658 537
659 ohci0: usb@1c1a400 { 538 ohci0: usb@1c1a400 {
660 compatible = "allwinne 539 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
661 reg = <0x01c1a400 0x10 540 reg = <0x01c1a400 0x100>;
662 interrupts = <GIC_SPI 541 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
663 clocks = <&ccu CLK_BUS 542 clocks = <&ccu CLK_BUS_OHCI0>,
664 <&ccu CLK_USB 543 <&ccu CLK_USB_OHCI0>;
665 resets = <&ccu RST_BUS 544 resets = <&ccu RST_BUS_OHCI0>;
666 phys = <&usbphy 0>; 545 phys = <&usbphy 0>;
667 phy-names = "usb"; 546 phy-names = "usb";
668 status = "disabled"; 547 status = "disabled";
669 }; 548 };
670 549
671 ehci1: usb@1c1b000 { 550 ehci1: usb@1c1b000 {
672 compatible = "allwinne 551 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
673 reg = <0x01c1b000 0x10 552 reg = <0x01c1b000 0x100>;
674 interrupts = <GIC_SPI 553 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
675 clocks = <&ccu CLK_BUS 554 clocks = <&ccu CLK_BUS_OHCI1>,
676 <&ccu CLK_BUS 555 <&ccu CLK_BUS_EHCI1>,
677 <&ccu CLK_USB 556 <&ccu CLK_USB_OHCI1>;
678 resets = <&ccu RST_BUS 557 resets = <&ccu RST_BUS_OHCI1>,
679 <&ccu RST_BUS 558 <&ccu RST_BUS_EHCI1>;
680 phys = <&usbphy 1>; 559 phys = <&usbphy 1>;
681 phy-names = "usb"; 560 phy-names = "usb";
682 status = "disabled"; 561 status = "disabled";
683 }; 562 };
684 563
685 ohci1: usb@1c1b400 { 564 ohci1: usb@1c1b400 {
686 compatible = "allwinne 565 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
687 reg = <0x01c1b400 0x10 566 reg = <0x01c1b400 0x100>;
688 interrupts = <GIC_SPI 567 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
689 clocks = <&ccu CLK_BUS 568 clocks = <&ccu CLK_BUS_OHCI1>,
690 <&ccu CLK_USB 569 <&ccu CLK_USB_OHCI1>;
691 resets = <&ccu RST_BUS 570 resets = <&ccu RST_BUS_OHCI1>;
692 phys = <&usbphy 1>; 571 phys = <&usbphy 1>;
693 phy-names = "usb"; 572 phy-names = "usb";
694 status = "disabled"; 573 status = "disabled";
695 }; 574 };
696 575
697 ccu: clock@1c20000 { 576 ccu: clock@1c20000 {
698 compatible = "allwinne 577 compatible = "allwinner,sun50i-a64-ccu";
699 reg = <0x01c20000 0x40 578 reg = <0x01c20000 0x400>;
700 clocks = <&osc24M>, <& !! 579 clocks = <&osc24M>, <&rtc 0>;
701 clock-names = "hosc", 580 clock-names = "hosc", "losc";
702 #clock-cells = <1>; 581 #clock-cells = <1>;
703 #reset-cells = <1>; 582 #reset-cells = <1>;
704 }; 583 };
705 584
706 pio: pinctrl@1c20800 { 585 pio: pinctrl@1c20800 {
707 compatible = "allwinne 586 compatible = "allwinner,sun50i-a64-pinctrl";
708 reg = <0x01c20800 0x40 587 reg = <0x01c20800 0x400>;
709 interrupt-parent = <&r <<
710 interrupts = <GIC_SPI 588 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
711 <GIC_SPI 589 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
712 <GIC_SPI 590 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&ccu CLK_BUS !! 591 clocks = <&ccu 58>, <&osc24M>, <&rtc 0>;
714 <&rtc CLK_OSC <<
715 clock-names = "apb", " 592 clock-names = "apb", "hosc", "losc";
716 gpio-controller; 593 gpio-controller;
717 #gpio-cells = <3>; 594 #gpio-cells = <3>;
718 interrupt-controller; 595 interrupt-controller;
719 #interrupt-cells = <3> 596 #interrupt-cells = <3>;
720 597
721 /omit-if-no-ref/ <<
722 aif2_pins: aif2-pins { <<
723 pins = "PB4", <<
724 function = "ai <<
725 }; <<
726 <<
727 /omit-if-no-ref/ <<
728 aif3_pins: aif3-pins { <<
729 pins = "PG10", <<
730 function = "ai <<
731 }; <<
732 <<
733 csi_pins: csi-pins { 598 csi_pins: csi-pins {
734 pins = "PE0", 599 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
735 "PE7", 600 "PE7", "PE8", "PE9", "PE10", "PE11";
736 function = "cs 601 function = "csi";
737 }; 602 };
738 603
739 /omit-if-no-ref/ 604 /omit-if-no-ref/
740 csi_mclk_pin: csi-mclk 605 csi_mclk_pin: csi-mclk-pin {
741 pins = "PE1"; 606 pins = "PE1";
742 function = "cs 607 function = "csi";
743 }; 608 };
744 609
745 i2c0_pins: i2c0-pins { 610 i2c0_pins: i2c0-pins {
746 pins = "PH0", 611 pins = "PH0", "PH1";
747 function = "i2 612 function = "i2c0";
748 }; 613 };
749 614
750 i2c1_pins: i2c1-pins { 615 i2c1_pins: i2c1-pins {
751 pins = "PH2", 616 pins = "PH2", "PH3";
752 function = "i2 617 function = "i2c1";
753 }; 618 };
754 619
755 i2c2_pins: i2c2-pins { <<
756 pins = "PE14", <<
757 function = "i2 <<
758 }; <<
759 <<
760 /omit-if-no-ref/ 620 /omit-if-no-ref/
761 lcd_rgb666_pins: lcd-r 621 lcd_rgb666_pins: lcd-rgb666-pins {
762 pins = "PD0", 622 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
763 "PD5", 623 "PD5", "PD6", "PD7", "PD8", "PD9",
764 "PD10", 624 "PD10", "PD11", "PD12", "PD13",
765 "PD14", 625 "PD14", "PD15", "PD16", "PD17",
766 "PD18", 626 "PD18", "PD19", "PD20", "PD21";
767 function = "lc 627 function = "lcd0";
768 }; 628 };
769 629
770 mmc0_pins: mmc0-pins { 630 mmc0_pins: mmc0-pins {
771 pins = "PF0", 631 pins = "PF0", "PF1", "PF2", "PF3",
772 "PF4", 632 "PF4", "PF5";
773 function = "mm 633 function = "mmc0";
774 drive-strength 634 drive-strength = <30>;
775 bias-pull-up; 635 bias-pull-up;
776 }; 636 };
777 637
778 mmc1_pins: mmc1-pins { 638 mmc1_pins: mmc1-pins {
779 pins = "PG0", 639 pins = "PG0", "PG1", "PG2", "PG3",
780 "PG4", 640 "PG4", "PG5";
781 function = "mm 641 function = "mmc1";
782 drive-strength 642 drive-strength = <30>;
783 bias-pull-up; 643 bias-pull-up;
784 }; 644 };
785 645
786 mmc2_pins: mmc2-pins { 646 mmc2_pins: mmc2-pins {
787 pins = "PC5", 647 pins = "PC5", "PC6", "PC8", "PC9",
788 "PC10", 648 "PC10","PC11", "PC12", "PC13",
789 "PC14", 649 "PC14", "PC15", "PC16";
790 function = "mm 650 function = "mmc2";
791 drive-strength 651 drive-strength = <30>;
792 bias-pull-up; 652 bias-pull-up;
793 }; 653 };
794 654
795 mmc2_ds_pin: mmc2-ds-p 655 mmc2_ds_pin: mmc2-ds-pin {
796 pins = "PC1"; 656 pins = "PC1";
797 function = "mm 657 function = "mmc2";
798 drive-strength 658 drive-strength = <30>;
799 bias-pull-up; 659 bias-pull-up;
800 }; 660 };
801 661
802 pwm_pin: pwm-pin { 662 pwm_pin: pwm-pin {
803 pins = "PD22"; 663 pins = "PD22";
804 function = "pw 664 function = "pwm";
805 }; 665 };
806 666
807 rmii_pins: rmii-pins { 667 rmii_pins: rmii-pins {
808 pins = "PD10", 668 pins = "PD10", "PD11", "PD13", "PD14", "PD17",
809 "PD18", 669 "PD18", "PD19", "PD20", "PD22", "PD23";
810 function = "em 670 function = "emac";
811 drive-strength 671 drive-strength = <40>;
812 }; 672 };
813 673
814 rgmii_pins: rgmii-pins 674 rgmii_pins: rgmii-pins {
815 pins = "PD8", 675 pins = "PD8", "PD9", "PD10", "PD11", "PD12",
816 "PD13", 676 "PD13", "PD15", "PD16", "PD17", "PD18",
817 "PD19", 677 "PD19", "PD20", "PD21", "PD22", "PD23";
818 function = "em 678 function = "emac";
819 drive-strength 679 drive-strength = <40>;
820 }; 680 };
821 681
822 spdif_tx_pin: spdif-tx 682 spdif_tx_pin: spdif-tx-pin {
823 pins = "PH8"; 683 pins = "PH8";
824 function = "sp 684 function = "spdif";
825 }; 685 };
826 686
827 spi0_pins: spi0-pins { 687 spi0_pins: spi0-pins {
828 pins = "PC0", 688 pins = "PC0", "PC1", "PC2", "PC3";
829 function = "sp 689 function = "spi0";
830 }; 690 };
831 691
832 spi1_pins: spi1-pins { 692 spi1_pins: spi1-pins {
833 pins = "PD0", 693 pins = "PD0", "PD1", "PD2", "PD3";
834 function = "sp 694 function = "spi1";
835 }; 695 };
836 696
837 uart0_pb_pins: uart0-p 697 uart0_pb_pins: uart0-pb-pins {
838 pins = "PB8", 698 pins = "PB8", "PB9";
839 function = "ua 699 function = "uart0";
840 }; 700 };
841 701
842 uart1_pins: uart1-pins 702 uart1_pins: uart1-pins {
843 pins = "PG6", 703 pins = "PG6", "PG7";
844 function = "ua 704 function = "uart1";
845 }; 705 };
846 706
847 uart1_rts_cts_pins: ua 707 uart1_rts_cts_pins: uart1-rts-cts-pins {
848 pins = "PG8", 708 pins = "PG8", "PG9";
849 function = "ua 709 function = "uart1";
850 }; 710 };
851 711
852 uart2_pins: uart2-pins 712 uart2_pins: uart2-pins {
853 pins = "PB0", 713 pins = "PB0", "PB1";
854 function = "ua 714 function = "uart2";
855 }; 715 };
856 716
857 uart3_pins: uart3-pins 717 uart3_pins: uart3-pins {
858 pins = "PD0", 718 pins = "PD0", "PD1";
859 function = "ua 719 function = "uart3";
860 }; 720 };
861 721
862 uart4_pins: uart4-pins 722 uart4_pins: uart4-pins {
863 pins = "PD2", 723 pins = "PD2", "PD3";
864 function = "ua 724 function = "uart4";
865 }; 725 };
866 726
867 uart4_rts_cts_pins: ua 727 uart4_rts_cts_pins: uart4-rts-cts-pins {
868 pins = "PD4", 728 pins = "PD4", "PD5";
869 function = "ua 729 function = "uart4";
870 }; 730 };
871 }; 731 };
872 732
873 timer@1c20c00 { <<
874 compatible = "allwinne <<
875 "allwinne <<
876 reg = <0x01c20c00 0xa0 <<
877 interrupts = <GIC_SPI <<
878 <GIC_SPI <<
879 clocks = <&osc24M>; <<
880 }; <<
881 <<
882 wdt0: watchdog@1c20ca0 { <<
883 compatible = "allwinne <<
884 "allwinne <<
885 reg = <0x01c20ca0 0x20 <<
886 interrupts = <GIC_SPI <<
887 clocks = <&osc24M>; <<
888 }; <<
889 <<
890 spdif: spdif@1c21000 { 733 spdif: spdif@1c21000 {
891 #sound-dai-cells = <0> 734 #sound-dai-cells = <0>;
892 compatible = "allwinne 735 compatible = "allwinner,sun50i-a64-spdif",
893 "allwinne 736 "allwinner,sun8i-h3-spdif";
894 reg = <0x01c21000 0x40 737 reg = <0x01c21000 0x400>;
895 interrupts = <GIC_SPI 738 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
896 clocks = <&ccu CLK_BUS 739 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
897 resets = <&ccu RST_BUS 740 resets = <&ccu RST_BUS_SPDIF>;
898 clock-names = "apb", " 741 clock-names = "apb", "spdif";
899 dmas = <&dma 2>; 742 dmas = <&dma 2>;
900 dma-names = "tx"; 743 dma-names = "tx";
901 pinctrl-names = "defau 744 pinctrl-names = "default";
902 pinctrl-0 = <&spdif_tx 745 pinctrl-0 = <&spdif_tx_pin>;
903 status = "disabled"; 746 status = "disabled";
904 }; 747 };
905 748
906 lradc: lradc@1c21800 { 749 lradc: lradc@1c21800 {
907 compatible = "allwinne 750 compatible = "allwinner,sun50i-a64-lradc",
908 "allwinne 751 "allwinner,sun8i-a83t-r-lradc";
909 reg = <0x01c21800 0x40 752 reg = <0x01c21800 0x400>;
910 interrupt-parent = <&r <<
911 interrupts = <GIC_SPI 753 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
912 status = "disabled"; 754 status = "disabled";
913 }; 755 };
914 756
915 i2s0: i2s@1c22000 { 757 i2s0: i2s@1c22000 {
916 #sound-dai-cells = <0> 758 #sound-dai-cells = <0>;
917 compatible = "allwinne 759 compatible = "allwinner,sun50i-a64-i2s",
918 "allwinne 760 "allwinner,sun8i-h3-i2s";
919 reg = <0x01c22000 0x40 761 reg = <0x01c22000 0x400>;
920 interrupts = <GIC_SPI 762 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
921 clocks = <&ccu CLK_BUS 763 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
922 clock-names = "apb", " 764 clock-names = "apb", "mod";
923 resets = <&ccu RST_BUS 765 resets = <&ccu RST_BUS_I2S0>;
924 dma-names = "rx", "tx" 766 dma-names = "rx", "tx";
925 dmas = <&dma 3>, <&dma 767 dmas = <&dma 3>, <&dma 3>;
926 status = "disabled"; 768 status = "disabled";
927 }; 769 };
928 770
929 i2s1: i2s@1c22400 { 771 i2s1: i2s@1c22400 {
930 #sound-dai-cells = <0> 772 #sound-dai-cells = <0>;
931 compatible = "allwinne 773 compatible = "allwinner,sun50i-a64-i2s",
932 "allwinne 774 "allwinner,sun8i-h3-i2s";
933 reg = <0x01c22400 0x40 775 reg = <0x01c22400 0x400>;
934 interrupts = <GIC_SPI 776 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
935 clocks = <&ccu CLK_BUS 777 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
936 clock-names = "apb", " 778 clock-names = "apb", "mod";
937 resets = <&ccu RST_BUS 779 resets = <&ccu RST_BUS_I2S1>;
938 dma-names = "rx", "tx" 780 dma-names = "rx", "tx";
939 dmas = <&dma 4>, <&dma 781 dmas = <&dma 4>, <&dma 4>;
940 status = "disabled"; 782 status = "disabled";
941 }; 783 };
942 784
943 i2s2: i2s@1c22800 { <<
944 #sound-dai-cells = <0> <<
945 compatible = "allwinne <<
946 "allwinne <<
947 reg = <0x01c22800 0x40 <<
948 interrupts = <GIC_SPI <<
949 clocks = <&ccu CLK_BUS <<
950 clock-names = "apb", " <<
951 resets = <&ccu RST_BUS <<
952 dma-names = "rx", "tx" <<
953 dmas = <&dma 27>, <&dm <<
954 status = "disabled"; <<
955 }; <<
956 <<
957 dai: dai@1c22c00 { 785 dai: dai@1c22c00 {
958 #sound-dai-cells = <0> 786 #sound-dai-cells = <0>;
959 compatible = "allwinne 787 compatible = "allwinner,sun50i-a64-codec-i2s";
960 reg = <0x01c22c00 0x20 788 reg = <0x01c22c00 0x200>;
961 interrupts = <GIC_SPI 789 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
962 clocks = <&ccu CLK_BUS 790 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
963 clock-names = "apb", " 791 clock-names = "apb", "mod";
964 resets = <&ccu RST_BUS 792 resets = <&ccu RST_BUS_CODEC>;
965 dmas = <&dma 15>, <&dm 793 dmas = <&dma 15>, <&dma 15>;
966 dma-names = "rx", "tx" 794 dma-names = "rx", "tx";
967 status = "disabled"; 795 status = "disabled";
968 }; 796 };
969 797
970 codec: codec@1c22e00 { 798 codec: codec@1c22e00 {
971 #sound-dai-cells = <1> !! 799 #sound-dai-cells = <0>;
972 compatible = "allwinne !! 800 compatible = "allwinner,sun8i-a33-codec";
973 "allwinne <<
974 reg = <0x01c22e00 0x60 801 reg = <0x01c22e00 0x600>;
975 interrupts = <GIC_SPI 802 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
976 clocks = <&ccu CLK_BUS 803 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
977 clock-names = "bus", " 804 clock-names = "bus", "mod";
978 status = "disabled"; 805 status = "disabled";
979 }; 806 };
980 807
981 ths: thermal-sensor@1c25000 { <<
982 compatible = "allwinne <<
983 reg = <0x01c25000 0x10 <<
984 clocks = <&ccu CLK_BUS <<
985 clock-names = "bus", " <<
986 interrupts = <GIC_SPI <<
987 resets = <&ccu RST_BUS <<
988 nvmem-cells = <&ths_ca <<
989 nvmem-cell-names = "ca <<
990 #thermal-sensor-cells <<
991 }; <<
992 <<
993 uart0: serial@1c28000 { 808 uart0: serial@1c28000 {
994 compatible = "snps,dw- 809 compatible = "snps,dw-apb-uart";
995 reg = <0x01c28000 0x40 810 reg = <0x01c28000 0x400>;
996 interrupts = <GIC_SPI 811 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
997 reg-shift = <2>; 812 reg-shift = <2>;
998 reg-io-width = <4>; 813 reg-io-width = <4>;
999 clocks = <&ccu CLK_BUS 814 clocks = <&ccu CLK_BUS_UART0>;
1000 resets = <&ccu RST_BU 815 resets = <&ccu RST_BUS_UART0>;
1001 status = "disabled"; 816 status = "disabled";
1002 }; 817 };
1003 818
1004 uart1: serial@1c28400 { 819 uart1: serial@1c28400 {
1005 compatible = "snps,dw 820 compatible = "snps,dw-apb-uart";
1006 reg = <0x01c28400 0x4 821 reg = <0x01c28400 0x400>;
1007 interrupts = <GIC_SPI 822 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1008 reg-shift = <2>; 823 reg-shift = <2>;
1009 reg-io-width = <4>; 824 reg-io-width = <4>;
1010 clocks = <&ccu CLK_BU 825 clocks = <&ccu CLK_BUS_UART1>;
1011 resets = <&ccu RST_BU 826 resets = <&ccu RST_BUS_UART1>;
1012 status = "disabled"; 827 status = "disabled";
1013 }; 828 };
1014 829
1015 uart2: serial@1c28800 { 830 uart2: serial@1c28800 {
1016 compatible = "snps,dw 831 compatible = "snps,dw-apb-uart";
1017 reg = <0x01c28800 0x4 832 reg = <0x01c28800 0x400>;
1018 interrupts = <GIC_SPI 833 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1019 reg-shift = <2>; 834 reg-shift = <2>;
1020 reg-io-width = <4>; 835 reg-io-width = <4>;
1021 clocks = <&ccu CLK_BU 836 clocks = <&ccu CLK_BUS_UART2>;
1022 resets = <&ccu RST_BU 837 resets = <&ccu RST_BUS_UART2>;
1023 status = "disabled"; 838 status = "disabled";
1024 }; 839 };
1025 840
1026 uart3: serial@1c28c00 { 841 uart3: serial@1c28c00 {
1027 compatible = "snps,dw 842 compatible = "snps,dw-apb-uart";
1028 reg = <0x01c28c00 0x4 843 reg = <0x01c28c00 0x400>;
1029 interrupts = <GIC_SPI 844 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1030 reg-shift = <2>; 845 reg-shift = <2>;
1031 reg-io-width = <4>; 846 reg-io-width = <4>;
1032 clocks = <&ccu CLK_BU 847 clocks = <&ccu CLK_BUS_UART3>;
1033 resets = <&ccu RST_BU 848 resets = <&ccu RST_BUS_UART3>;
1034 status = "disabled"; 849 status = "disabled";
1035 }; 850 };
1036 851
1037 uart4: serial@1c29000 { 852 uart4: serial@1c29000 {
1038 compatible = "snps,dw 853 compatible = "snps,dw-apb-uart";
1039 reg = <0x01c29000 0x4 854 reg = <0x01c29000 0x400>;
1040 interrupts = <GIC_SPI 855 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1041 reg-shift = <2>; 856 reg-shift = <2>;
1042 reg-io-width = <4>; 857 reg-io-width = <4>;
1043 clocks = <&ccu CLK_BU 858 clocks = <&ccu CLK_BUS_UART4>;
1044 resets = <&ccu RST_BU 859 resets = <&ccu RST_BUS_UART4>;
1045 status = "disabled"; 860 status = "disabled";
1046 }; 861 };
1047 862
1048 i2c0: i2c@1c2ac00 { 863 i2c0: i2c@1c2ac00 {
1049 compatible = "allwinn 864 compatible = "allwinner,sun6i-a31-i2c";
1050 reg = <0x01c2ac00 0x4 865 reg = <0x01c2ac00 0x400>;
1051 interrupts = <GIC_SPI 866 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1052 clocks = <&ccu CLK_BU 867 clocks = <&ccu CLK_BUS_I2C0>;
1053 resets = <&ccu RST_BU 868 resets = <&ccu RST_BUS_I2C0>;
1054 pinctrl-names = "defa 869 pinctrl-names = "default";
1055 pinctrl-0 = <&i2c0_pi 870 pinctrl-0 = <&i2c0_pins>;
1056 status = "disabled"; 871 status = "disabled";
1057 #address-cells = <1>; 872 #address-cells = <1>;
1058 #size-cells = <0>; 873 #size-cells = <0>;
1059 }; 874 };
1060 875
1061 i2c1: i2c@1c2b000 { 876 i2c1: i2c@1c2b000 {
1062 compatible = "allwinn 877 compatible = "allwinner,sun6i-a31-i2c";
1063 reg = <0x01c2b000 0x4 878 reg = <0x01c2b000 0x400>;
1064 interrupts = <GIC_SPI 879 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1065 clocks = <&ccu CLK_BU 880 clocks = <&ccu CLK_BUS_I2C1>;
1066 resets = <&ccu RST_BU 881 resets = <&ccu RST_BUS_I2C1>;
1067 pinctrl-names = "defa 882 pinctrl-names = "default";
1068 pinctrl-0 = <&i2c1_pi 883 pinctrl-0 = <&i2c1_pins>;
1069 status = "disabled"; 884 status = "disabled";
1070 #address-cells = <1>; 885 #address-cells = <1>;
1071 #size-cells = <0>; 886 #size-cells = <0>;
1072 }; 887 };
1073 888
1074 i2c2: i2c@1c2b400 { 889 i2c2: i2c@1c2b400 {
1075 compatible = "allwinn 890 compatible = "allwinner,sun6i-a31-i2c";
1076 reg = <0x01c2b400 0x4 891 reg = <0x01c2b400 0x400>;
1077 interrupts = <GIC_SPI 892 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1078 clocks = <&ccu CLK_BU 893 clocks = <&ccu CLK_BUS_I2C2>;
1079 resets = <&ccu RST_BU 894 resets = <&ccu RST_BUS_I2C2>;
1080 pinctrl-names = "defa <<
1081 pinctrl-0 = <&i2c2_pi <<
1082 status = "disabled"; 895 status = "disabled";
1083 #address-cells = <1>; 896 #address-cells = <1>;
1084 #size-cells = <0>; 897 #size-cells = <0>;
1085 }; 898 };
1086 899
>> 900
1087 spi0: spi@1c68000 { 901 spi0: spi@1c68000 {
1088 compatible = "allwinn 902 compatible = "allwinner,sun8i-h3-spi";
1089 reg = <0x01c68000 0x1 903 reg = <0x01c68000 0x1000>;
1090 interrupts = <GIC_SPI 904 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1091 clocks = <&ccu CLK_BU 905 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
1092 clock-names = "ahb", 906 clock-names = "ahb", "mod";
1093 dmas = <&dma 23>, <&d 907 dmas = <&dma 23>, <&dma 23>;
1094 dma-names = "rx", "tx 908 dma-names = "rx", "tx";
1095 pinctrl-names = "defa 909 pinctrl-names = "default";
1096 pinctrl-0 = <&spi0_pi 910 pinctrl-0 = <&spi0_pins>;
1097 resets = <&ccu RST_BU 911 resets = <&ccu RST_BUS_SPI0>;
1098 status = "disabled"; 912 status = "disabled";
1099 num-cs = <1>; 913 num-cs = <1>;
1100 #address-cells = <1>; 914 #address-cells = <1>;
1101 #size-cells = <0>; 915 #size-cells = <0>;
1102 }; 916 };
1103 917
1104 spi1: spi@1c69000 { 918 spi1: spi@1c69000 {
1105 compatible = "allwinn 919 compatible = "allwinner,sun8i-h3-spi";
1106 reg = <0x01c69000 0x1 920 reg = <0x01c69000 0x1000>;
1107 interrupts = <GIC_SPI 921 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1108 clocks = <&ccu CLK_BU 922 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
1109 clock-names = "ahb", 923 clock-names = "ahb", "mod";
1110 dmas = <&dma 24>, <&d 924 dmas = <&dma 24>, <&dma 24>;
1111 dma-names = "rx", "tx 925 dma-names = "rx", "tx";
1112 pinctrl-names = "defa 926 pinctrl-names = "default";
1113 pinctrl-0 = <&spi1_pi 927 pinctrl-0 = <&spi1_pins>;
1114 resets = <&ccu RST_BU 928 resets = <&ccu RST_BUS_SPI1>;
1115 status = "disabled"; 929 status = "disabled";
1116 num-cs = <1>; 930 num-cs = <1>;
1117 #address-cells = <1>; 931 #address-cells = <1>;
1118 #size-cells = <0>; 932 #size-cells = <0>;
1119 }; 933 };
1120 934
1121 emac: ethernet@1c30000 { 935 emac: ethernet@1c30000 {
1122 compatible = "allwinn 936 compatible = "allwinner,sun50i-a64-emac";
1123 syscon = <&syscon>; 937 syscon = <&syscon>;
1124 reg = <0x01c30000 0x1 938 reg = <0x01c30000 0x10000>;
1125 interrupts = <GIC_SPI 939 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1126 interrupt-names = "ma 940 interrupt-names = "macirq";
1127 resets = <&ccu RST_BU 941 resets = <&ccu RST_BUS_EMAC>;
1128 reset-names = "stmmac 942 reset-names = "stmmaceth";
1129 clocks = <&ccu CLK_BU 943 clocks = <&ccu CLK_BUS_EMAC>;
1130 clock-names = "stmmac 944 clock-names = "stmmaceth";
1131 status = "disabled"; 945 status = "disabled";
1132 946
1133 mdio: mdio { 947 mdio: mdio {
1134 compatible = 948 compatible = "snps,dwmac-mdio";
1135 #address-cell 949 #address-cells = <1>;
1136 #size-cells = 950 #size-cells = <0>;
1137 }; 951 };
1138 }; 952 };
1139 953
1140 mali: gpu@1c40000 { 954 mali: gpu@1c40000 {
1141 compatible = "allwinn 955 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400";
1142 reg = <0x01c40000 0x1 956 reg = <0x01c40000 0x10000>;
1143 interrupts = <GIC_SPI 957 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1144 <GIC_SPI 958 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1145 <GIC_SPI 959 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1146 <GIC_SPI 960 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1147 <GIC_SPI 961 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1148 <GIC_SPI 962 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1149 <GIC_SPI 963 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1150 interrupt-names = "gp 964 interrupt-names = "gp",
1151 "gp 965 "gpmmu",
1152 "pp 966 "pp0",
1153 "pp 967 "ppmmu0",
1154 "pp 968 "pp1",
1155 "pp 969 "ppmmu1",
1156 "pm 970 "pmu";
1157 clocks = <&ccu CLK_BU 971 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
1158 clock-names = "bus", 972 clock-names = "bus", "core";
1159 resets = <&ccu RST_BU 973 resets = <&ccu RST_BUS_GPU>;
1160 operating-points-v2 = <<
1161 }; 974 };
1162 975
1163 gic: interrupt-controller@1c8 976 gic: interrupt-controller@1c81000 {
1164 compatible = "arm,gic 977 compatible = "arm,gic-400";
1165 reg = <0x01c81000 0x1 978 reg = <0x01c81000 0x1000>,
1166 <0x01c82000 0x2 979 <0x01c82000 0x2000>,
1167 <0x01c84000 0x2 980 <0x01c84000 0x2000>,
1168 <0x01c86000 0x2 981 <0x01c86000 0x2000>;
1169 interrupts = <GIC_PPI 982 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1170 interrupt-controller; 983 interrupt-controller;
1171 #interrupt-cells = <3 984 #interrupt-cells = <3>;
1172 }; 985 };
1173 986
1174 pwm: pwm@1c21400 { 987 pwm: pwm@1c21400 {
1175 compatible = "allwinn 988 compatible = "allwinner,sun50i-a64-pwm",
1176 "allwinn 989 "allwinner,sun5i-a13-pwm";
1177 reg = <0x01c21400 0x4 990 reg = <0x01c21400 0x400>;
1178 clocks = <&osc24M>; 991 clocks = <&osc24M>;
1179 pinctrl-names = "defa 992 pinctrl-names = "default";
1180 pinctrl-0 = <&pwm_pin 993 pinctrl-0 = <&pwm_pin>;
1181 #pwm-cells = <3>; 994 #pwm-cells = <3>;
1182 status = "disabled"; 995 status = "disabled";
1183 }; 996 };
1184 997
1185 mbus: dram-controller@1c62000 <<
1186 compatible = "allwinn <<
1187 reg = <0x01c62000 0x1 <<
1188 <0x01c63000 0x1 <<
1189 reg-names = "mbus", " <<
1190 clocks = <&ccu CLK_MB <<
1191 <&ccu CLK_DR <<
1192 <&ccu CLK_BU <<
1193 clock-names = "mbus", <<
1194 interrupts = <GIC_SPI <<
1195 #address-cells = <1>; <<
1196 #size-cells = <1>; <<
1197 dma-ranges = <0x00000 <<
1198 #interconnect-cells = <<
1199 }; <<
1200 <<
1201 csi: csi@1cb0000 { 998 csi: csi@1cb0000 {
1202 compatible = "allwinn 999 compatible = "allwinner,sun50i-a64-csi";
1203 reg = <0x01cb0000 0x1 1000 reg = <0x01cb0000 0x1000>;
1204 interrupts = <GIC_SPI 1001 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1205 clocks = <&ccu CLK_BU 1002 clocks = <&ccu CLK_BUS_CSI>,
1206 <&ccu CLK_CS 1003 <&ccu CLK_CSI_SCLK>,
1207 <&ccu CLK_DR 1004 <&ccu CLK_DRAM_CSI>;
1208 clock-names = "bus", 1005 clock-names = "bus", "mod", "ram";
1209 resets = <&ccu RST_BU 1006 resets = <&ccu RST_BUS_CSI>;
1210 pinctrl-names = "defa 1007 pinctrl-names = "default";
1211 pinctrl-0 = <&csi_pin 1008 pinctrl-0 = <&csi_pins>;
1212 status = "disabled"; 1009 status = "disabled";
1213 }; 1010 };
1214 1011
1215 dsi: dsi@1ca0000 { <<
1216 compatible = "allwinn <<
1217 reg = <0x01ca0000 0x1 <<
1218 interrupts = <GIC_SPI <<
1219 clocks = <&ccu CLK_BU <<
1220 resets = <&ccu RST_BU <<
1221 phys = <&dphy>; <<
1222 phy-names = "dphy"; <<
1223 status = "disabled"; <<
1224 #address-cells = <1>; <<
1225 #size-cells = <0>; <<
1226 <<
1227 port { <<
1228 dsi_in_tcon0: <<
1229 remot <<
1230 }; <<
1231 }; <<
1232 }; <<
1233 <<
1234 dphy: d-phy@1ca1000 { <<
1235 compatible = "allwinn <<
1236 "allwinn <<
1237 reg = <0x01ca1000 0x1 <<
1238 interrupts = <GIC_SPI <<
1239 clocks = <&ccu CLK_BU <<
1240 <&ccu CLK_DS <<
1241 clock-names = "bus", <<
1242 resets = <&ccu RST_BU <<
1243 status = "disabled"; <<
1244 #phy-cells = <0>; <<
1245 }; <<
1246 <<
1247 deinterlace: deinterlace@1e00 <<
1248 compatible = "allwinn <<
1249 "allwinn <<
1250 reg = <0x01e00000 0x2 <<
1251 clocks = <&ccu CLK_BU <<
1252 <&ccu CLK_DE <<
1253 <&ccu CLK_DR <<
1254 clock-names = "bus", <<
1255 resets = <&ccu RST_BU <<
1256 interrupts = <GIC_SPI <<
1257 interconnects = <&mbu <<
1258 interconnect-names = <<
1259 }; <<
1260 <<
1261 hdmi: hdmi@1ee0000 { 1012 hdmi: hdmi@1ee0000 {
1262 compatible = "allwinn 1013 compatible = "allwinner,sun50i-a64-dw-hdmi",
1263 "allwinn 1014 "allwinner,sun8i-a83t-dw-hdmi";
1264 reg = <0x01ee0000 0x1 1015 reg = <0x01ee0000 0x10000>;
1265 reg-io-width = <1>; 1016 reg-io-width = <1>;
1266 interrupts = <GIC_SPI 1017 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1267 clocks = <&ccu CLK_BU 1018 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1268 <&ccu CLK_HD !! 1019 <&ccu CLK_HDMI>;
1269 clock-names = "iahb", !! 1020 clock-names = "iahb", "isfr", "tmds";
1270 resets = <&ccu RST_BU 1021 resets = <&ccu RST_BUS_HDMI1>;
1271 reset-names = "ctrl"; 1022 reset-names = "ctrl";
1272 phys = <&hdmi_phy>; 1023 phys = <&hdmi_phy>;
1273 phy-names = "phy"; 1024 phy-names = "phy";
1274 status = "disabled"; 1025 status = "disabled";
1275 1026
1276 ports { 1027 ports {
1277 #address-cell 1028 #address-cells = <1>;
1278 #size-cells = 1029 #size-cells = <0>;
1279 1030
1280 hdmi_in: port 1031 hdmi_in: port@0 {
1281 reg = 1032 reg = <0>;
1282 1033
1283 hdmi_ 1034 hdmi_in_tcon1: endpoint {
1284 1035 remote-endpoint = <&tcon1_out_hdmi>;
1285 }; 1036 };
1286 }; 1037 };
1287 1038
1288 hdmi_out: por 1039 hdmi_out: port@1 {
1289 reg = 1040 reg = <1>;
1290 }; 1041 };
1291 }; 1042 };
1292 }; 1043 };
1293 1044
1294 hdmi_phy: hdmi-phy@1ef0000 { 1045 hdmi_phy: hdmi-phy@1ef0000 {
1295 compatible = "allwinn 1046 compatible = "allwinner,sun50i-a64-hdmi-phy";
1296 reg = <0x01ef0000 0x1 1047 reg = <0x01ef0000 0x10000>;
1297 clocks = <&ccu CLK_BU 1048 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1298 <&ccu CLK_PL !! 1049 <&ccu 7>;
1299 clock-names = "bus", 1050 clock-names = "bus", "mod", "pll-0";
1300 resets = <&ccu RST_BU 1051 resets = <&ccu RST_BUS_HDMI0>;
1301 reset-names = "phy"; 1052 reset-names = "phy";
1302 #phy-cells = <0>; 1053 #phy-cells = <0>;
1303 }; 1054 };
1304 1055
1305 rtc: rtc@1f00000 { 1056 rtc: rtc@1f00000 {
1306 compatible = "allwinn 1057 compatible = "allwinner,sun50i-a64-rtc",
1307 "allwinn 1058 "allwinner,sun8i-h3-rtc";
1308 reg = <0x01f00000 0x4 1059 reg = <0x01f00000 0x400>;
1309 interrupt-parent = <& <<
1310 interrupts = <GIC_SPI 1060 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1311 <GIC_SPI 1061 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1312 clock-output-names = 1062 clock-output-names = "osc32k", "osc32k-out", "iosc";
1313 clocks = <&osc32k>; 1063 clocks = <&osc32k>;
1314 #clock-cells = <1>; 1064 #clock-cells = <1>;
1315 }; 1065 };
1316 1066
1317 r_intc: interrupt-controller@ 1067 r_intc: interrupt-controller@1f00c00 {
1318 compatible = "allwinn 1068 compatible = "allwinner,sun50i-a64-r-intc",
1319 "allwinn 1069 "allwinner,sun6i-a31-r-intc";
1320 interrupt-controller; 1070 interrupt-controller;
1321 #interrupt-cells = <3 !! 1071 #interrupt-cells = <2>;
1322 reg = <0x01f00c00 0x4 1072 reg = <0x01f00c00 0x400>;
1323 interrupts = <GIC_SPI 1073 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1324 }; 1074 };
1325 1075
1326 r_ccu: clock@1f01400 { 1076 r_ccu: clock@1f01400 {
1327 compatible = "allwinn 1077 compatible = "allwinner,sun50i-a64-r-ccu";
1328 reg = <0x01f01400 0x1 1078 reg = <0x01f01400 0x100>;
1329 clocks = <&osc24M>, < !! 1079 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu 11>;
1330 <&ccu CLK_PL <<
1331 clock-names = "hosc", 1080 clock-names = "hosc", "losc", "iosc", "pll-periph";
1332 #clock-cells = <1>; 1081 #clock-cells = <1>;
1333 #reset-cells = <1>; 1082 #reset-cells = <1>;
1334 }; 1083 };
1335 1084
1336 codec_analog: codec-analog@1f 1085 codec_analog: codec-analog@1f015c0 {
1337 compatible = "allwinn 1086 compatible = "allwinner,sun50i-a64-codec-analog";
1338 reg = <0x01f015c0 0x4 1087 reg = <0x01f015c0 0x4>;
1339 status = "disabled"; 1088 status = "disabled";
1340 }; 1089 };
1341 1090
1342 r_i2c: i2c@1f02400 { 1091 r_i2c: i2c@1f02400 {
1343 compatible = "allwinn 1092 compatible = "allwinner,sun50i-a64-i2c",
1344 "allwinn 1093 "allwinner,sun6i-a31-i2c";
1345 reg = <0x01f02400 0x4 1094 reg = <0x01f02400 0x400>;
1346 interrupts = <GIC_SPI 1095 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1347 clocks = <&r_ccu CLK_ 1096 clocks = <&r_ccu CLK_APB0_I2C>;
1348 resets = <&r_ccu RST_ 1097 resets = <&r_ccu RST_APB0_I2C>;
1349 status = "disabled"; 1098 status = "disabled";
1350 #address-cells = <1>; 1099 #address-cells = <1>;
1351 #size-cells = <0>; 1100 #size-cells = <0>;
1352 }; 1101 };
1353 1102
1354 r_ir: ir@1f02000 { 1103 r_ir: ir@1f02000 {
1355 compatible = "allwinn 1104 compatible = "allwinner,sun50i-a64-ir",
1356 "allwinn 1105 "allwinner,sun6i-a31-ir";
1357 reg = <0x01f02000 0x4 1106 reg = <0x01f02000 0x400>;
1358 clocks = <&r_ccu CLK_ 1107 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
1359 clock-names = "apb", 1108 clock-names = "apb", "ir";
1360 resets = <&r_ccu RST_ 1109 resets = <&r_ccu RST_APB0_IR>;
1361 interrupts = <GIC_SPI 1110 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1362 pinctrl-names = "defa 1111 pinctrl-names = "default";
1363 pinctrl-0 = <&r_ir_rx 1112 pinctrl-0 = <&r_ir_rx_pin>;
1364 status = "disabled"; 1113 status = "disabled";
1365 }; 1114 };
1366 1115
1367 r_pwm: pwm@1f03800 { 1116 r_pwm: pwm@1f03800 {
1368 compatible = "allwinn 1117 compatible = "allwinner,sun50i-a64-pwm",
1369 "allwinn 1118 "allwinner,sun5i-a13-pwm";
1370 reg = <0x01f03800 0x4 1119 reg = <0x01f03800 0x400>;
1371 clocks = <&osc24M>; 1120 clocks = <&osc24M>;
1372 pinctrl-names = "defa 1121 pinctrl-names = "default";
1373 pinctrl-0 = <&r_pwm_p 1122 pinctrl-0 = <&r_pwm_pin>;
1374 #pwm-cells = <3>; 1123 #pwm-cells = <3>;
1375 status = "disabled"; 1124 status = "disabled";
1376 }; 1125 };
1377 1126
1378 r_pio: pinctrl@1f02c00 { 1127 r_pio: pinctrl@1f02c00 {
1379 compatible = "allwinn 1128 compatible = "allwinner,sun50i-a64-r-pinctrl";
1380 reg = <0x01f02c00 0x4 1129 reg = <0x01f02c00 0x400>;
1381 interrupt-parent = <& <<
1382 interrupts = <GIC_SPI 1130 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1383 clocks = <&r_ccu CLK_ 1131 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
1384 clock-names = "apb", 1132 clock-names = "apb", "hosc", "losc";
1385 gpio-controller; 1133 gpio-controller;
1386 #gpio-cells = <3>; 1134 #gpio-cells = <3>;
1387 interrupt-controller; 1135 interrupt-controller;
1388 #interrupt-cells = <3 1136 #interrupt-cells = <3>;
1389 1137
1390 r_i2c_pl89_pins: r-i2 1138 r_i2c_pl89_pins: r-i2c-pl89-pins {
1391 pins = "PL8", 1139 pins = "PL8", "PL9";
1392 function = "s 1140 function = "s_i2c";
1393 }; 1141 };
1394 1142
1395 r_ir_rx_pin: r-ir-rx- 1143 r_ir_rx_pin: r-ir-rx-pin {
1396 pins = "PL11" 1144 pins = "PL11";
1397 function = "s 1145 function = "s_cir_rx";
1398 }; 1146 };
1399 1147
1400 r_pwm_pin: r-pwm-pin 1148 r_pwm_pin: r-pwm-pin {
1401 pins = "PL10" 1149 pins = "PL10";
1402 function = "s 1150 function = "s_pwm";
1403 }; 1151 };
1404 1152
1405 r_rsb_pins: r-rsb-pin 1153 r_rsb_pins: r-rsb-pins {
1406 pins = "PL0", 1154 pins = "PL0", "PL1";
1407 function = "s 1155 function = "s_rsb";
1408 }; 1156 };
1409 }; 1157 };
1410 1158
1411 r_rsb: rsb@1f03400 { 1159 r_rsb: rsb@1f03400 {
1412 compatible = "allwinn 1160 compatible = "allwinner,sun8i-a23-rsb";
1413 reg = <0x01f03400 0x4 1161 reg = <0x01f03400 0x400>;
1414 interrupts = <GIC_SPI 1162 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1415 clocks = <&r_ccu 6>; 1163 clocks = <&r_ccu 6>;
1416 clock-frequency = <30 1164 clock-frequency = <3000000>;
1417 resets = <&r_ccu 2>; 1165 resets = <&r_ccu 2>;
1418 pinctrl-names = "defa 1166 pinctrl-names = "default";
1419 pinctrl-0 = <&r_rsb_p 1167 pinctrl-0 = <&r_rsb_pins>;
1420 status = "disabled"; 1168 status = "disabled";
1421 #address-cells = <1>; 1169 #address-cells = <1>;
1422 #size-cells = <0>; 1170 #size-cells = <0>;
>> 1171 };
>> 1172
>> 1173 wdt0: watchdog@1c20ca0 {
>> 1174 compatible = "allwinner,sun50i-a64-wdt",
>> 1175 "allwinner,sun6i-a31-wdt";
>> 1176 reg = <0x01c20ca0 0x20>;
>> 1177 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
>> 1178 clocks = <&osc24M>;
1423 }; 1179 };
1424 }; 1180 };
1425 }; 1181 };
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