1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2016 ARM Ltd. 2 // Copyright (C) 2016 ARM Ltd.
3 // based on the Allwinner H3 dtsi: 3 // based on the Allwinner H3 dtsi:
4 // Copyright (C) 2015 Jens Kuske <jenskuske@ 4 // Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
5 5
6 #include <dt-bindings/clock/sun50i-a64-ccu.h> 6 #include <dt-bindings/clock/sun50i-a64-ccu.h>
7 #include <dt-bindings/clock/sun6i-rtc.h> 7 #include <dt-bindings/clock/sun6i-rtc.h>
8 #include <dt-bindings/clock/sun8i-de2.h> 8 #include <dt-bindings/clock/sun8i-de2.h>
9 #include <dt-bindings/clock/sun8i-r-ccu.h> 9 #include <dt-bindings/clock/sun8i-r-ccu.h>
10 #include <dt-bindings/interrupt-controller/arm 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/sun50i-a64-ccu.h> 11 #include <dt-bindings/reset/sun50i-a64-ccu.h>
12 #include <dt-bindings/reset/sun8i-de2.h> 12 #include <dt-bindings/reset/sun8i-de2.h>
13 #include <dt-bindings/reset/sun8i-r-ccu.h> 13 #include <dt-bindings/reset/sun8i-r-ccu.h>
14 #include <dt-bindings/thermal/thermal.h> 14 #include <dt-bindings/thermal/thermal.h>
15 15
16 / { 16 / {
17 interrupt-parent = <&gic>; 17 interrupt-parent = <&gic>;
18 #address-cells = <1>; 18 #address-cells = <1>;
19 #size-cells = <1>; 19 #size-cells = <1>;
20 20
21 chosen { 21 chosen {
22 #address-cells = <1>; 22 #address-cells = <1>;
23 #size-cells = <1>; 23 #size-cells = <1>;
24 ranges; 24 ranges;
25 25
26 simplefb_lcd: framebuffer-lcd 26 simplefb_lcd: framebuffer-lcd {
27 compatible = "allwinne 27 compatible = "allwinner,simple-framebuffer",
28 "simple-f 28 "simple-framebuffer";
29 allwinner,pipeline = " 29 allwinner,pipeline = "mixer0-lcd0";
30 clocks = <&ccu CLK_TCO 30 clocks = <&ccu CLK_TCON0>,
31 <&display_clo 31 <&display_clocks CLK_MIXER0>;
32 status = "disabled"; 32 status = "disabled";
33 }; 33 };
34 34
35 simplefb_hdmi: framebuffer-hdm 35 simplefb_hdmi: framebuffer-hdmi {
36 compatible = "allwinne 36 compatible = "allwinner,simple-framebuffer",
37 "simple-f 37 "simple-framebuffer";
38 allwinner,pipeline = " 38 allwinner,pipeline = "mixer1-lcd1-hdmi";
39 clocks = <&display_clo 39 clocks = <&display_clocks CLK_MIXER1>,
40 <&ccu CLK_TCO 40 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
41 status = "disabled"; 41 status = "disabled";
42 }; 42 };
43 }; 43 };
44 44
45 cpus { 45 cpus {
46 #address-cells = <1>; 46 #address-cells = <1>;
47 #size-cells = <0>; 47 #size-cells = <0>;
48 48
49 cpu0: cpu@0 { 49 cpu0: cpu@0 {
50 compatible = "arm,cort 50 compatible = "arm,cortex-a53";
51 device_type = "cpu"; 51 device_type = "cpu";
52 reg = <0>; 52 reg = <0>;
53 enable-method = "psci" 53 enable-method = "psci";
>> 54 next-level-cache = <&L2>;
54 clocks = <&ccu CLK_CPU 55 clocks = <&ccu CLK_CPUX>;
55 clock-names = "cpu"; 56 clock-names = "cpu";
56 #cooling-cells = <2>; 57 #cooling-cells = <2>;
57 i-cache-size = <0x8000 <<
58 i-cache-line-size = <6 <<
59 i-cache-sets = <256>; <<
60 d-cache-size = <0x8000 <<
61 d-cache-line-size = <6 <<
62 d-cache-sets = <128>; <<
63 next-level-cache = <&l <<
64 }; 58 };
65 59
66 cpu1: cpu@1 { 60 cpu1: cpu@1 {
67 compatible = "arm,cort 61 compatible = "arm,cortex-a53";
68 device_type = "cpu"; 62 device_type = "cpu";
69 reg = <1>; 63 reg = <1>;
70 enable-method = "psci" 64 enable-method = "psci";
>> 65 next-level-cache = <&L2>;
71 clocks = <&ccu CLK_CPU 66 clocks = <&ccu CLK_CPUX>;
72 clock-names = "cpu"; 67 clock-names = "cpu";
73 #cooling-cells = <2>; 68 #cooling-cells = <2>;
74 i-cache-size = <0x8000 <<
75 i-cache-line-size = <6 <<
76 i-cache-sets = <256>; <<
77 d-cache-size = <0x8000 <<
78 d-cache-line-size = <6 <<
79 d-cache-sets = <128>; <<
80 next-level-cache = <&l <<
81 }; 69 };
82 70
83 cpu2: cpu@2 { 71 cpu2: cpu@2 {
84 compatible = "arm,cort 72 compatible = "arm,cortex-a53";
85 device_type = "cpu"; 73 device_type = "cpu";
86 reg = <2>; 74 reg = <2>;
87 enable-method = "psci" 75 enable-method = "psci";
>> 76 next-level-cache = <&L2>;
88 clocks = <&ccu CLK_CPU 77 clocks = <&ccu CLK_CPUX>;
89 clock-names = "cpu"; 78 clock-names = "cpu";
90 #cooling-cells = <2>; 79 #cooling-cells = <2>;
91 i-cache-size = <0x8000 <<
92 i-cache-line-size = <6 <<
93 i-cache-sets = <256>; <<
94 d-cache-size = <0x8000 <<
95 d-cache-line-size = <6 <<
96 d-cache-sets = <128>; <<
97 next-level-cache = <&l <<
98 }; 80 };
99 81
100 cpu3: cpu@3 { 82 cpu3: cpu@3 {
101 compatible = "arm,cort 83 compatible = "arm,cortex-a53";
102 device_type = "cpu"; 84 device_type = "cpu";
103 reg = <3>; 85 reg = <3>;
104 enable-method = "psci" 86 enable-method = "psci";
>> 87 next-level-cache = <&L2>;
105 clocks = <&ccu CLK_CPU 88 clocks = <&ccu CLK_CPUX>;
106 clock-names = "cpu"; 89 clock-names = "cpu";
107 #cooling-cells = <2>; 90 #cooling-cells = <2>;
108 i-cache-size = <0x8000 <<
109 i-cache-line-size = <6 <<
110 i-cache-sets = <256>; <<
111 d-cache-size = <0x8000 <<
112 d-cache-line-size = <6 <<
113 d-cache-sets = <128>; <<
114 next-level-cache = <&l <<
115 }; 91 };
116 92
117 l2_cache: l2-cache { !! 93 L2: l2-cache {
118 compatible = "cache"; 94 compatible = "cache";
119 cache-level = <2>; 95 cache-level = <2>;
120 cache-unified; <<
121 cache-size = <0x80000> <<
122 cache-line-size = <64> <<
123 cache-sets = <512>; <<
124 }; 96 };
125 }; 97 };
126 98
127 de: display-engine { 99 de: display-engine {
128 compatible = "allwinner,sun50i 100 compatible = "allwinner,sun50i-a64-display-engine";
129 allwinner,pipelines = <&mixer0 101 allwinner,pipelines = <&mixer0>,
130 <&mixer1 102 <&mixer1>;
131 status = "disabled"; 103 status = "disabled";
132 }; 104 };
133 105
134 gpu_opp_table: opp-table-gpu { 106 gpu_opp_table: opp-table-gpu {
135 compatible = "operating-points 107 compatible = "operating-points-v2";
136 108
>> 109 opp-120000000 {
>> 110 opp-hz = /bits/ 64 <120000000>;
>> 111 };
>> 112
>> 113 opp-312000000 {
>> 114 opp-hz = /bits/ 64 <312000000>;
>> 115 };
>> 116
137 opp-432000000 { 117 opp-432000000 {
138 opp-hz = /bits/ 64 <43 118 opp-hz = /bits/ 64 <432000000>;
139 }; 119 };
140 }; 120 };
141 121
142 osc24M: osc24M-clk { !! 122 osc24M: osc24M_clk {
143 #clock-cells = <0>; 123 #clock-cells = <0>;
144 compatible = "fixed-clock"; 124 compatible = "fixed-clock";
145 clock-frequency = <24000000>; 125 clock-frequency = <24000000>;
146 clock-output-names = "osc24M"; 126 clock-output-names = "osc24M";
147 }; 127 };
148 128
149 osc32k: osc32k-clk { !! 129 osc32k: osc32k_clk {
150 #clock-cells = <0>; 130 #clock-cells = <0>;
151 compatible = "fixed-clock"; 131 compatible = "fixed-clock";
152 clock-frequency = <32768>; 132 clock-frequency = <32768>;
153 clock-output-names = "ext-osc3 133 clock-output-names = "ext-osc32k";
154 }; 134 };
155 135
156 pmu { 136 pmu {
157 compatible = "arm,cortex-a53-p 137 compatible = "arm,cortex-a53-pmu";
158 interrupts = <GIC_SPI 116 IRQ_ 138 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 117 IRQ_ 139 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 118 IRQ_ 140 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 119 IRQ_ 141 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
162 interrupt-affinity = <&cpu0>, 142 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
163 }; 143 };
164 144
165 psci { 145 psci {
166 compatible = "arm,psci-0.2"; 146 compatible = "arm,psci-0.2";
167 method = "smc"; 147 method = "smc";
168 }; 148 };
169 149
170 sound: sound { 150 sound: sound {
171 #address-cells = <1>; 151 #address-cells = <1>;
172 #size-cells = <0>; 152 #size-cells = <0>;
173 compatible = "simple-audio-car 153 compatible = "simple-audio-card";
174 simple-audio-card,name = "sun5 154 simple-audio-card,name = "sun50i-a64-audio";
175 simple-audio-card,aux-devs = < 155 simple-audio-card,aux-devs = <&codec_analog>;
176 simple-audio-card,routing = 156 simple-audio-card,routing =
177 "Left DAC", "D 157 "Left DAC", "DACL",
178 "Right DAC", " 158 "Right DAC", "DACR",
179 "ADCL", "Left 159 "ADCL", "Left ADC",
180 "ADCR", "Right 160 "ADCR", "Right ADC";
181 status = "disabled"; 161 status = "disabled";
182 162
183 simple-audio-card,dai-link@0 { 163 simple-audio-card,dai-link@0 {
184 format = "i2s"; 164 format = "i2s";
185 frame-master = <&link0 165 frame-master = <&link0_cpu>;
186 bitclock-master = <&li 166 bitclock-master = <&link0_cpu>;
187 mclk-fs = <128>; 167 mclk-fs = <128>;
188 168
189 link0_cpu: cpu { 169 link0_cpu: cpu {
190 sound-dai = <& 170 sound-dai = <&dai>;
191 }; 171 };
192 172
193 link0_codec: codec { 173 link0_codec: codec {
194 sound-dai = <& 174 sound-dai = <&codec 0>;
195 }; 175 };
196 }; 176 };
197 }; 177 };
198 178
199 timer { 179 timer {
200 compatible = "arm,armv8-timer" 180 compatible = "arm,armv8-timer";
201 allwinner,erratum-unknown1; 181 allwinner,erratum-unknown1;
202 arm,no-tick-in-suspend; 182 arm,no-tick-in-suspend;
203 interrupts = <GIC_PPI 13 183 interrupts = <GIC_PPI 13
204 (GIC_CPU_MASK_SIMPLE(4 184 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
205 <GIC_PPI 14 185 <GIC_PPI 14
206 (GIC_CPU_MASK_SIMPLE(4 186 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
207 <GIC_PPI 11 187 <GIC_PPI 11
208 (GIC_CPU_MASK_SIMPLE(4 188 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
209 <GIC_PPI 10 189 <GIC_PPI 10
210 (GIC_CPU_MASK_SIMPLE(4 190 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
211 }; 191 };
212 192
213 thermal-zones { 193 thermal-zones {
214 cpu_thermal: cpu0-thermal { 194 cpu_thermal: cpu0-thermal {
215 /* milliseconds */ 195 /* milliseconds */
216 polling-delay-passive 196 polling-delay-passive = <0>;
217 polling-delay = <0>; 197 polling-delay = <0>;
218 thermal-sensors = <&th 198 thermal-sensors = <&ths 0>;
219 199
220 cooling-maps { 200 cooling-maps {
221 map0 { 201 map0 {
222 trip = 202 trip = <&cpu_alert0>;
223 coolin 203 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
224 204 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
225 205 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
226 206 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
227 }; 207 };
228 map1 { 208 map1 {
229 trip = 209 trip = <&cpu_alert1>;
230 coolin 210 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
231 211 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
232 212 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
233 213 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
234 }; 214 };
235 }; 215 };
236 216
237 trips { 217 trips {
238 cpu_alert0: cp !! 218 cpu_alert0: cpu_alert0 {
239 /* mil 219 /* milliCelsius */
240 temper 220 temperature = <75000>;
241 hyster 221 hysteresis = <2000>;
242 type = 222 type = "passive";
243 }; 223 };
244 224
245 cpu_alert1: cp !! 225 cpu_alert1: cpu_alert1 {
246 /* mil 226 /* milliCelsius */
247 temper 227 temperature = <90000>;
248 hyster 228 hysteresis = <2000>;
249 type = 229 type = "hot";
250 }; 230 };
251 231
252 cpu_crit: cpu- !! 232 cpu_crit: cpu_crit {
253 /* mil 233 /* milliCelsius */
254 temper 234 temperature = <110000>;
255 hyster 235 hysteresis = <2000>;
256 type = 236 type = "critical";
257 }; 237 };
258 }; 238 };
259 }; 239 };
260 240
261 gpu0_thermal: gpu0-thermal { 241 gpu0_thermal: gpu0-thermal {
262 /* milliseconds */ 242 /* milliseconds */
263 polling-delay-passive 243 polling-delay-passive = <0>;
264 polling-delay = <0>; 244 polling-delay = <0>;
265 thermal-sensors = <&th 245 thermal-sensors = <&ths 1>;
266 <<
267 trips { <<
268 gpu0_crit: gpu <<
269 temper <<
270 hyster <<
271 type = <<
272 }; <<
273 }; <<
274 }; 246 };
275 247
276 gpu1_thermal: gpu1-thermal { 248 gpu1_thermal: gpu1-thermal {
277 /* milliseconds */ 249 /* milliseconds */
278 polling-delay-passive 250 polling-delay-passive = <0>;
279 polling-delay = <0>; 251 polling-delay = <0>;
280 thermal-sensors = <&th 252 thermal-sensors = <&ths 2>;
281 <<
282 trips { <<
283 gpu1_crit: gpu <<
284 temper <<
285 hyster <<
286 type = <<
287 }; <<
288 }; <<
289 }; 253 };
290 }; 254 };
291 255
292 soc { 256 soc {
293 compatible = "simple-bus"; 257 compatible = "simple-bus";
294 #address-cells = <1>; 258 #address-cells = <1>;
295 #size-cells = <1>; 259 #size-cells = <1>;
296 ranges; 260 ranges;
297 261
298 bus@1000000 { 262 bus@1000000 {
299 compatible = "allwinne 263 compatible = "allwinner,sun50i-a64-de2";
300 reg = <0x1000000 0x400 264 reg = <0x1000000 0x400000>;
301 allwinner,sram = <&de2 265 allwinner,sram = <&de2_sram 1>;
302 #address-cells = <1>; 266 #address-cells = <1>;
303 #size-cells = <1>; 267 #size-cells = <1>;
304 ranges = <0 0x1000000 268 ranges = <0 0x1000000 0x400000>;
305 269
306 display_clocks: clock@ 270 display_clocks: clock@0 {
307 compatible = " 271 compatible = "allwinner,sun50i-a64-de2-clk";
308 reg = <0x0 0x1 272 reg = <0x0 0x10000>;
309 clocks = <&ccu 273 clocks = <&ccu CLK_BUS_DE>,
310 <&ccu 274 <&ccu CLK_DE>;
311 clock-names = 275 clock-names = "bus",
312 276 "mod";
313 resets = <&ccu 277 resets = <&ccu RST_BUS_DE>;
314 #clock-cells = 278 #clock-cells = <1>;
315 #reset-cells = 279 #reset-cells = <1>;
316 }; 280 };
317 281
318 rotate: rotate@20000 { 282 rotate: rotate@20000 {
319 compatible = " 283 compatible = "allwinner,sun50i-a64-de2-rotate",
320 " 284 "allwinner,sun8i-a83t-de2-rotate";
321 reg = <0x20000 285 reg = <0x20000 0x10000>;
322 interrupts = < 286 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&dis 287 clocks = <&display_clocks CLK_BUS_ROT>,
324 <&dis 288 <&display_clocks CLK_ROT>;
325 clock-names = 289 clock-names = "bus",
326 290 "mod";
327 resets = <&dis 291 resets = <&display_clocks RST_ROT>;
328 }; 292 };
329 293
330 mixer0: mixer@100000 { 294 mixer0: mixer@100000 {
331 compatible = " 295 compatible = "allwinner,sun50i-a64-de2-mixer-0";
332 reg = <0x10000 296 reg = <0x100000 0x100000>;
333 clocks = <&dis 297 clocks = <&display_clocks CLK_BUS_MIXER0>,
334 <&dis 298 <&display_clocks CLK_MIXER0>;
335 clock-names = 299 clock-names = "bus",
336 300 "mod";
337 resets = <&dis 301 resets = <&display_clocks RST_MIXER0>;
338 302
339 ports { 303 ports {
340 #addre 304 #address-cells = <1>;
341 #size- 305 #size-cells = <0>;
342 306
343 mixer0 307 mixer0_out: port@1 {
344 308 #address-cells = <1>;
345 309 #size-cells = <0>;
346 310 reg = <1>;
347 311
348 312 mixer0_out_tcon0: endpoint@0 {
349 313 reg = <0>;
350 314 remote-endpoint = <&tcon0_in_mixer0>;
351 315 };
352 316
353 317 mixer0_out_tcon1: endpoint@1 {
354 318 reg = <1>;
355 319 remote-endpoint = <&tcon1_in_mixer0>;
356 320 };
357 }; 321 };
358 }; 322 };
359 }; 323 };
360 324
361 mixer1: mixer@200000 { 325 mixer1: mixer@200000 {
362 compatible = " 326 compatible = "allwinner,sun50i-a64-de2-mixer-1";
363 reg = <0x20000 327 reg = <0x200000 0x100000>;
364 clocks = <&dis 328 clocks = <&display_clocks CLK_BUS_MIXER1>,
365 <&dis 329 <&display_clocks CLK_MIXER1>;
366 clock-names = 330 clock-names = "bus",
367 331 "mod";
368 resets = <&dis 332 resets = <&display_clocks RST_MIXER1>;
369 333
370 ports { 334 ports {
371 #addre 335 #address-cells = <1>;
372 #size- 336 #size-cells = <0>;
373 337
374 mixer1 338 mixer1_out: port@1 {
375 339 #address-cells = <1>;
376 340 #size-cells = <0>;
377 341 reg = <1>;
378 342
379 343 mixer1_out_tcon0: endpoint@0 {
380 344 reg = <0>;
381 345 remote-endpoint = <&tcon0_in_mixer1>;
382 346 };
383 347
384 348 mixer1_out_tcon1: endpoint@1 {
385 349 reg = <1>;
386 350 remote-endpoint = <&tcon1_in_mixer1>;
387 351 };
388 }; 352 };
389 }; 353 };
390 }; 354 };
391 }; 355 };
392 356
393 syscon: syscon@1c00000 { 357 syscon: syscon@1c00000 {
394 compatible = "allwinne 358 compatible = "allwinner,sun50i-a64-system-control";
395 reg = <0x01c00000 0x10 359 reg = <0x01c00000 0x1000>;
396 #address-cells = <1>; 360 #address-cells = <1>;
397 #size-cells = <1>; 361 #size-cells = <1>;
398 ranges; 362 ranges;
399 363
400 sram_c: sram@18000 { 364 sram_c: sram@18000 {
401 compatible = " 365 compatible = "mmio-sram";
402 reg = <0x00018 366 reg = <0x00018000 0x28000>;
403 #address-cells 367 #address-cells = <1>;
404 #size-cells = 368 #size-cells = <1>;
405 ranges = <0 0x 369 ranges = <0 0x00018000 0x28000>;
406 370
407 de2_sram: sram 371 de2_sram: sram-section@0 {
408 compat 372 compatible = "allwinner,sun50i-a64-sram-c";
409 reg = 373 reg = <0x0000 0x28000>;
410 }; 374 };
411 }; 375 };
412 376
413 sram_c1: sram@1d00000 377 sram_c1: sram@1d00000 {
414 compatible = " 378 compatible = "mmio-sram";
415 reg = <0x01d00 379 reg = <0x01d00000 0x40000>;
416 #address-cells 380 #address-cells = <1>;
417 #size-cells = 381 #size-cells = <1>;
418 ranges = <0 0x 382 ranges = <0 0x01d00000 0x40000>;
419 383
420 ve_sram: sram- 384 ve_sram: sram-section@0 {
421 compat 385 compatible = "allwinner,sun50i-a64-sram-c1",
422 386 "allwinner,sun4i-a10-sram-c1";
423 reg = 387 reg = <0x000000 0x40000>;
424 }; 388 };
425 }; 389 };
426 }; 390 };
427 391
428 dma: dma-controller@1c02000 { 392 dma: dma-controller@1c02000 {
429 compatible = "allwinne 393 compatible = "allwinner,sun50i-a64-dma";
430 reg = <0x01c02000 0x10 394 reg = <0x01c02000 0x1000>;
431 interrupts = <GIC_SPI 395 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&ccu CLK_BUS 396 clocks = <&ccu CLK_BUS_DMA>;
433 dma-channels = <8>; 397 dma-channels = <8>;
434 dma-requests = <27>; 398 dma-requests = <27>;
435 resets = <&ccu RST_BUS 399 resets = <&ccu RST_BUS_DMA>;
436 #dma-cells = <1>; 400 #dma-cells = <1>;
437 }; 401 };
438 402
439 tcon0: lcd-controller@1c0c000 403 tcon0: lcd-controller@1c0c000 {
440 compatible = "allwinne 404 compatible = "allwinner,sun50i-a64-tcon-lcd",
441 "allwinne 405 "allwinner,sun8i-a83t-tcon-lcd";
442 reg = <0x01c0c000 0x10 406 reg = <0x01c0c000 0x1000>;
443 interrupts = <GIC_SPI 407 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
444 clocks = <&ccu CLK_BUS 408 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
445 clock-names = "ahb", " 409 clock-names = "ahb", "tcon-ch0";
446 clock-output-names = " !! 410 clock-output-names = "tcon-pixel-clock";
447 #clock-cells = <0>; 411 #clock-cells = <0>;
448 resets = <&ccu RST_BUS 412 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
449 reset-names = "lcd", " 413 reset-names = "lcd", "lvds";
450 414
451 ports { 415 ports {
452 #address-cells 416 #address-cells = <1>;
453 #size-cells = 417 #size-cells = <0>;
454 418
455 tcon0_in: port 419 tcon0_in: port@0 {
456 #addre 420 #address-cells = <1>;
457 #size- 421 #size-cells = <0>;
458 reg = 422 reg = <0>;
459 423
460 tcon0_ 424 tcon0_in_mixer0: endpoint@0 {
461 425 reg = <0>;
462 426 remote-endpoint = <&mixer0_out_tcon0>;
463 }; 427 };
464 428
465 tcon0_ 429 tcon0_in_mixer1: endpoint@1 {
466 430 reg = <1>;
467 431 remote-endpoint = <&mixer1_out_tcon0>;
468 }; 432 };
469 }; 433 };
470 434
471 tcon0_out: por 435 tcon0_out: port@1 {
472 #addre 436 #address-cells = <1>;
473 #size- 437 #size-cells = <0>;
474 reg = 438 reg = <1>;
475 439
476 tcon0_ 440 tcon0_out_dsi: endpoint@1 {
477 441 reg = <1>;
478 442 remote-endpoint = <&dsi_in_tcon0>;
479 443 allwinner,tcon-channel = <1>;
480 }; 444 };
481 }; 445 };
482 }; 446 };
483 }; 447 };
484 448
485 tcon1: lcd-controller@1c0d000 449 tcon1: lcd-controller@1c0d000 {
486 compatible = "allwinne 450 compatible = "allwinner,sun50i-a64-tcon-tv",
487 "allwinne 451 "allwinner,sun8i-a83t-tcon-tv";
488 reg = <0x01c0d000 0x10 452 reg = <0x01c0d000 0x1000>;
489 interrupts = <GIC_SPI 453 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&ccu CLK_BUS 454 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
491 clock-names = "ahb", " 455 clock-names = "ahb", "tcon-ch1";
492 resets = <&ccu RST_BUS 456 resets = <&ccu RST_BUS_TCON1>;
493 reset-names = "lcd"; 457 reset-names = "lcd";
494 458
495 ports { 459 ports {
496 #address-cells 460 #address-cells = <1>;
497 #size-cells = 461 #size-cells = <0>;
498 462
499 tcon1_in: port 463 tcon1_in: port@0 {
500 #addre 464 #address-cells = <1>;
501 #size- 465 #size-cells = <0>;
502 reg = 466 reg = <0>;
503 467
504 tcon1_ 468 tcon1_in_mixer0: endpoint@0 {
505 469 reg = <0>;
506 470 remote-endpoint = <&mixer0_out_tcon1>;
507 }; 471 };
508 472
509 tcon1_ 473 tcon1_in_mixer1: endpoint@1 {
510 474 reg = <1>;
511 475 remote-endpoint = <&mixer1_out_tcon1>;
512 }; 476 };
513 }; 477 };
514 478
515 tcon1_out: por 479 tcon1_out: port@1 {
516 #addre 480 #address-cells = <1>;
517 #size- 481 #size-cells = <0>;
518 reg = 482 reg = <1>;
519 483
520 tcon1_ 484 tcon1_out_hdmi: endpoint@1 {
521 485 reg = <1>;
522 486 remote-endpoint = <&hdmi_in_tcon1>;
523 }; 487 };
524 }; 488 };
525 }; 489 };
526 }; 490 };
527 491
528 video-codec@1c0e000 { 492 video-codec@1c0e000 {
529 compatible = "allwinne 493 compatible = "allwinner,sun50i-a64-video-engine";
530 reg = <0x01c0e000 0x10 494 reg = <0x01c0e000 0x1000>;
531 clocks = <&ccu CLK_BUS 495 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
532 <&ccu CLK_DRA 496 <&ccu CLK_DRAM_VE>;
533 clock-names = "ahb", " 497 clock-names = "ahb", "mod", "ram";
534 resets = <&ccu RST_BUS 498 resets = <&ccu RST_BUS_VE>;
535 interrupts = <GIC_SPI 499 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
536 allwinner,sram = <&ve_ 500 allwinner,sram = <&ve_sram 1>;
537 }; 501 };
538 502
539 mmc0: mmc@1c0f000 { 503 mmc0: mmc@1c0f000 {
540 compatible = "allwinne 504 compatible = "allwinner,sun50i-a64-mmc";
541 reg = <0x01c0f000 0x10 505 reg = <0x01c0f000 0x1000>;
542 clocks = <&ccu CLK_BUS 506 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
543 clock-names = "ahb", " 507 clock-names = "ahb", "mmc";
544 resets = <&ccu RST_BUS 508 resets = <&ccu RST_BUS_MMC0>;
545 reset-names = "ahb"; 509 reset-names = "ahb";
546 interrupts = <GIC_SPI 510 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
547 max-frequency = <15000 511 max-frequency = <150000000>;
548 status = "disabled"; 512 status = "disabled";
549 #address-cells = <1>; 513 #address-cells = <1>;
550 #size-cells = <0>; 514 #size-cells = <0>;
551 }; 515 };
552 516
553 mmc1: mmc@1c10000 { 517 mmc1: mmc@1c10000 {
554 compatible = "allwinne 518 compatible = "allwinner,sun50i-a64-mmc";
555 reg = <0x01c10000 0x10 519 reg = <0x01c10000 0x1000>;
556 clocks = <&ccu CLK_BUS 520 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
557 clock-names = "ahb", " 521 clock-names = "ahb", "mmc";
558 resets = <&ccu RST_BUS 522 resets = <&ccu RST_BUS_MMC1>;
559 reset-names = "ahb"; 523 reset-names = "ahb";
560 interrupts = <GIC_SPI 524 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
561 max-frequency = <15000 525 max-frequency = <150000000>;
562 status = "disabled"; 526 status = "disabled";
563 #address-cells = <1>; 527 #address-cells = <1>;
564 #size-cells = <0>; 528 #size-cells = <0>;
565 }; 529 };
566 530
567 mmc2: mmc@1c11000 { 531 mmc2: mmc@1c11000 {
568 compatible = "allwinne 532 compatible = "allwinner,sun50i-a64-emmc";
569 reg = <0x01c11000 0x10 533 reg = <0x01c11000 0x1000>;
570 clocks = <&ccu CLK_BUS 534 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
571 clock-names = "ahb", " 535 clock-names = "ahb", "mmc";
572 resets = <&ccu RST_BUS 536 resets = <&ccu RST_BUS_MMC2>;
573 reset-names = "ahb"; 537 reset-names = "ahb";
574 interrupts = <GIC_SPI 538 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
575 max-frequency = <15000 539 max-frequency = <150000000>;
576 status = "disabled"; 540 status = "disabled";
577 #address-cells = <1>; 541 #address-cells = <1>;
578 #size-cells = <0>; 542 #size-cells = <0>;
579 }; 543 };
580 544
581 sid: eeprom@1c14000 { 545 sid: eeprom@1c14000 {
582 compatible = "allwinne 546 compatible = "allwinner,sun50i-a64-sid";
583 reg = <0x1c14000 0x400 547 reg = <0x1c14000 0x400>;
584 #address-cells = <1>; 548 #address-cells = <1>;
585 #size-cells = <1>; 549 #size-cells = <1>;
586 550
587 ths_calibration: therm 551 ths_calibration: thermal-sensor-calibration@34 {
588 reg = <0x34 0x 552 reg = <0x34 0x8>;
589 }; 553 };
590 }; 554 };
591 555
592 crypto: crypto@1c15000 { 556 crypto: crypto@1c15000 {
593 compatible = "allwinne 557 compatible = "allwinner,sun50i-a64-crypto";
594 reg = <0x01c15000 0x10 558 reg = <0x01c15000 0x1000>;
595 interrupts = <GIC_SPI 559 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
596 clocks = <&ccu CLK_BUS 560 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
597 clock-names = "bus", " 561 clock-names = "bus", "mod";
598 resets = <&ccu RST_BUS 562 resets = <&ccu RST_BUS_CE>;
599 }; 563 };
600 564
601 msgbox: mailbox@1c17000 { 565 msgbox: mailbox@1c17000 {
602 compatible = "allwinne 566 compatible = "allwinner,sun50i-a64-msgbox",
603 "allwinne 567 "allwinner,sun6i-a31-msgbox";
604 reg = <0x01c17000 0x10 568 reg = <0x01c17000 0x1000>;
605 clocks = <&ccu CLK_BUS 569 clocks = <&ccu CLK_BUS_MSGBOX>;
606 resets = <&ccu RST_BUS 570 resets = <&ccu RST_BUS_MSGBOX>;
607 interrupts = <GIC_SPI 571 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
608 #mbox-cells = <1>; 572 #mbox-cells = <1>;
609 }; 573 };
610 574
611 usb_otg: usb@1c19000 { 575 usb_otg: usb@1c19000 {
612 compatible = "allwinne 576 compatible = "allwinner,sun8i-a33-musb";
613 reg = <0x01c19000 0x04 577 reg = <0x01c19000 0x0400>;
614 clocks = <&ccu CLK_BUS 578 clocks = <&ccu CLK_BUS_OTG>;
615 resets = <&ccu RST_BUS 579 resets = <&ccu RST_BUS_OTG>;
616 interrupts = <GIC_SPI 580 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
617 interrupt-names = "mc" 581 interrupt-names = "mc";
618 phys = <&usbphy 0>; 582 phys = <&usbphy 0>;
619 phy-names = "usb"; 583 phy-names = "usb";
620 extcon = <&usbphy 0>; 584 extcon = <&usbphy 0>;
621 dr_mode = "otg"; 585 dr_mode = "otg";
622 status = "disabled"; 586 status = "disabled";
623 }; 587 };
624 588
625 usbphy: phy@1c19400 { 589 usbphy: phy@1c19400 {
626 compatible = "allwinne 590 compatible = "allwinner,sun50i-a64-usb-phy";
627 reg = <0x01c19400 0x14 591 reg = <0x01c19400 0x14>,
628 <0x01c1a800 0x4> 592 <0x01c1a800 0x4>,
629 <0x01c1b800 0x4> 593 <0x01c1b800 0x4>;
630 reg-names = "phy_ctrl" 594 reg-names = "phy_ctrl",
631 "pmu0", 595 "pmu0",
632 "pmu1"; 596 "pmu1";
633 clocks = <&ccu CLK_USB 597 clocks = <&ccu CLK_USB_PHY0>,
634 <&ccu CLK_USB 598 <&ccu CLK_USB_PHY1>;
635 clock-names = "usb0_ph 599 clock-names = "usb0_phy",
636 "usb1_ph 600 "usb1_phy";
637 resets = <&ccu RST_USB 601 resets = <&ccu RST_USB_PHY0>,
638 <&ccu RST_USB 602 <&ccu RST_USB_PHY1>;
639 reset-names = "usb0_re 603 reset-names = "usb0_reset",
640 "usb1_re 604 "usb1_reset";
641 status = "disabled"; 605 status = "disabled";
642 #phy-cells = <1>; 606 #phy-cells = <1>;
643 }; 607 };
644 608
645 ehci0: usb@1c1a000 { 609 ehci0: usb@1c1a000 {
646 compatible = "allwinne 610 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
647 reg = <0x01c1a000 0x10 611 reg = <0x01c1a000 0x100>;
648 interrupts = <GIC_SPI 612 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
649 clocks = <&ccu CLK_BUS 613 clocks = <&ccu CLK_BUS_OHCI0>,
650 <&ccu CLK_BUS 614 <&ccu CLK_BUS_EHCI0>,
651 <&ccu CLK_USB 615 <&ccu CLK_USB_OHCI0>;
652 resets = <&ccu RST_BUS 616 resets = <&ccu RST_BUS_OHCI0>,
653 <&ccu RST_BUS 617 <&ccu RST_BUS_EHCI0>;
654 phys = <&usbphy 0>; 618 phys = <&usbphy 0>;
655 phy-names = "usb"; 619 phy-names = "usb";
656 status = "disabled"; 620 status = "disabled";
657 }; 621 };
658 622
659 ohci0: usb@1c1a400 { 623 ohci0: usb@1c1a400 {
660 compatible = "allwinne 624 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
661 reg = <0x01c1a400 0x10 625 reg = <0x01c1a400 0x100>;
662 interrupts = <GIC_SPI 626 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
663 clocks = <&ccu CLK_BUS 627 clocks = <&ccu CLK_BUS_OHCI0>,
664 <&ccu CLK_USB 628 <&ccu CLK_USB_OHCI0>;
665 resets = <&ccu RST_BUS 629 resets = <&ccu RST_BUS_OHCI0>;
666 phys = <&usbphy 0>; 630 phys = <&usbphy 0>;
667 phy-names = "usb"; 631 phy-names = "usb";
668 status = "disabled"; 632 status = "disabled";
669 }; 633 };
670 634
671 ehci1: usb@1c1b000 { 635 ehci1: usb@1c1b000 {
672 compatible = "allwinne 636 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
673 reg = <0x01c1b000 0x10 637 reg = <0x01c1b000 0x100>;
674 interrupts = <GIC_SPI 638 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
675 clocks = <&ccu CLK_BUS 639 clocks = <&ccu CLK_BUS_OHCI1>,
676 <&ccu CLK_BUS 640 <&ccu CLK_BUS_EHCI1>,
677 <&ccu CLK_USB 641 <&ccu CLK_USB_OHCI1>;
678 resets = <&ccu RST_BUS 642 resets = <&ccu RST_BUS_OHCI1>,
679 <&ccu RST_BUS 643 <&ccu RST_BUS_EHCI1>;
680 phys = <&usbphy 1>; 644 phys = <&usbphy 1>;
681 phy-names = "usb"; 645 phy-names = "usb";
682 status = "disabled"; 646 status = "disabled";
683 }; 647 };
684 648
685 ohci1: usb@1c1b400 { 649 ohci1: usb@1c1b400 {
686 compatible = "allwinne 650 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
687 reg = <0x01c1b400 0x10 651 reg = <0x01c1b400 0x100>;
688 interrupts = <GIC_SPI 652 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
689 clocks = <&ccu CLK_BUS 653 clocks = <&ccu CLK_BUS_OHCI1>,
690 <&ccu CLK_USB 654 <&ccu CLK_USB_OHCI1>;
691 resets = <&ccu RST_BUS 655 resets = <&ccu RST_BUS_OHCI1>;
692 phys = <&usbphy 1>; 656 phys = <&usbphy 1>;
693 phy-names = "usb"; 657 phy-names = "usb";
694 status = "disabled"; 658 status = "disabled";
695 }; 659 };
696 660
697 ccu: clock@1c20000 { 661 ccu: clock@1c20000 {
698 compatible = "allwinne 662 compatible = "allwinner,sun50i-a64-ccu";
699 reg = <0x01c20000 0x40 663 reg = <0x01c20000 0x400>;
700 clocks = <&osc24M>, <& 664 clocks = <&osc24M>, <&rtc CLK_OSC32K>;
701 clock-names = "hosc", 665 clock-names = "hosc", "losc";
702 #clock-cells = <1>; 666 #clock-cells = <1>;
703 #reset-cells = <1>; 667 #reset-cells = <1>;
704 }; 668 };
705 669
706 pio: pinctrl@1c20800 { 670 pio: pinctrl@1c20800 {
707 compatible = "allwinne 671 compatible = "allwinner,sun50i-a64-pinctrl";
708 reg = <0x01c20800 0x40 672 reg = <0x01c20800 0x400>;
709 interrupt-parent = <&r 673 interrupt-parent = <&r_intc>;
710 interrupts = <GIC_SPI 674 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
711 <GIC_SPI 675 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
712 <GIC_SPI 676 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&ccu CLK_BUS 677 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
714 <&rtc CLK_OSC 678 <&rtc CLK_OSC32K>;
715 clock-names = "apb", " 679 clock-names = "apb", "hosc", "losc";
716 gpio-controller; 680 gpio-controller;
717 #gpio-cells = <3>; 681 #gpio-cells = <3>;
718 interrupt-controller; 682 interrupt-controller;
719 #interrupt-cells = <3> 683 #interrupt-cells = <3>;
720 684
721 /omit-if-no-ref/ 685 /omit-if-no-ref/
722 aif2_pins: aif2-pins { 686 aif2_pins: aif2-pins {
723 pins = "PB4", 687 pins = "PB4", "PB5", "PB6", "PB7";
724 function = "ai 688 function = "aif2";
725 }; 689 };
726 690
727 /omit-if-no-ref/ 691 /omit-if-no-ref/
728 aif3_pins: aif3-pins { 692 aif3_pins: aif3-pins {
729 pins = "PG10", 693 pins = "PG10", "PG11", "PG12", "PG13";
730 function = "ai 694 function = "aif3";
731 }; 695 };
732 696
733 csi_pins: csi-pins { 697 csi_pins: csi-pins {
734 pins = "PE0", 698 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
735 "PE7", 699 "PE7", "PE8", "PE9", "PE10", "PE11";
736 function = "cs 700 function = "csi";
737 }; 701 };
738 702
739 /omit-if-no-ref/ 703 /omit-if-no-ref/
740 csi_mclk_pin: csi-mclk 704 csi_mclk_pin: csi-mclk-pin {
741 pins = "PE1"; 705 pins = "PE1";
742 function = "cs 706 function = "csi";
743 }; 707 };
744 708
745 i2c0_pins: i2c0-pins { 709 i2c0_pins: i2c0-pins {
746 pins = "PH0", 710 pins = "PH0", "PH1";
747 function = "i2 711 function = "i2c0";
748 }; 712 };
749 713
750 i2c1_pins: i2c1-pins { 714 i2c1_pins: i2c1-pins {
751 pins = "PH2", 715 pins = "PH2", "PH3";
752 function = "i2 716 function = "i2c1";
753 }; 717 };
754 718
755 i2c2_pins: i2c2-pins { 719 i2c2_pins: i2c2-pins {
756 pins = "PE14", 720 pins = "PE14", "PE15";
757 function = "i2 721 function = "i2c2";
758 }; 722 };
759 723
760 /omit-if-no-ref/ 724 /omit-if-no-ref/
761 lcd_rgb666_pins: lcd-r 725 lcd_rgb666_pins: lcd-rgb666-pins {
762 pins = "PD0", 726 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
763 "PD5", 727 "PD5", "PD6", "PD7", "PD8", "PD9",
764 "PD10", 728 "PD10", "PD11", "PD12", "PD13",
765 "PD14", 729 "PD14", "PD15", "PD16", "PD17",
766 "PD18", 730 "PD18", "PD19", "PD20", "PD21";
767 function = "lc 731 function = "lcd0";
768 }; 732 };
769 733
770 mmc0_pins: mmc0-pins { 734 mmc0_pins: mmc0-pins {
771 pins = "PF0", 735 pins = "PF0", "PF1", "PF2", "PF3",
772 "PF4", 736 "PF4", "PF5";
773 function = "mm 737 function = "mmc0";
774 drive-strength 738 drive-strength = <30>;
775 bias-pull-up; 739 bias-pull-up;
776 }; 740 };
777 741
778 mmc1_pins: mmc1-pins { 742 mmc1_pins: mmc1-pins {
779 pins = "PG0", 743 pins = "PG0", "PG1", "PG2", "PG3",
780 "PG4", 744 "PG4", "PG5";
781 function = "mm 745 function = "mmc1";
782 drive-strength 746 drive-strength = <30>;
783 bias-pull-up; 747 bias-pull-up;
784 }; 748 };
785 749
786 mmc2_pins: mmc2-pins { 750 mmc2_pins: mmc2-pins {
787 pins = "PC5", 751 pins = "PC5", "PC6", "PC8", "PC9",
788 "PC10", 752 "PC10","PC11", "PC12", "PC13",
789 "PC14", 753 "PC14", "PC15", "PC16";
790 function = "mm 754 function = "mmc2";
791 drive-strength 755 drive-strength = <30>;
792 bias-pull-up; 756 bias-pull-up;
793 }; 757 };
794 758
795 mmc2_ds_pin: mmc2-ds-p 759 mmc2_ds_pin: mmc2-ds-pin {
796 pins = "PC1"; 760 pins = "PC1";
797 function = "mm 761 function = "mmc2";
798 drive-strength 762 drive-strength = <30>;
799 bias-pull-up; 763 bias-pull-up;
800 }; 764 };
801 765
802 pwm_pin: pwm-pin { 766 pwm_pin: pwm-pin {
803 pins = "PD22"; 767 pins = "PD22";
804 function = "pw 768 function = "pwm";
805 }; 769 };
806 770
807 rmii_pins: rmii-pins { 771 rmii_pins: rmii-pins {
808 pins = "PD10", 772 pins = "PD10", "PD11", "PD13", "PD14", "PD17",
809 "PD18", 773 "PD18", "PD19", "PD20", "PD22", "PD23";
810 function = "em 774 function = "emac";
811 drive-strength 775 drive-strength = <40>;
812 }; 776 };
813 777
814 rgmii_pins: rgmii-pins 778 rgmii_pins: rgmii-pins {
815 pins = "PD8", 779 pins = "PD8", "PD9", "PD10", "PD11", "PD12",
816 "PD13", 780 "PD13", "PD15", "PD16", "PD17", "PD18",
817 "PD19", 781 "PD19", "PD20", "PD21", "PD22", "PD23";
818 function = "em 782 function = "emac";
819 drive-strength 783 drive-strength = <40>;
820 }; 784 };
821 785
822 spdif_tx_pin: spdif-tx 786 spdif_tx_pin: spdif-tx-pin {
823 pins = "PH8"; 787 pins = "PH8";
824 function = "sp 788 function = "spdif";
825 }; 789 };
826 790
827 spi0_pins: spi0-pins { 791 spi0_pins: spi0-pins {
828 pins = "PC0", 792 pins = "PC0", "PC1", "PC2", "PC3";
829 function = "sp 793 function = "spi0";
830 }; 794 };
831 795
832 spi1_pins: spi1-pins { 796 spi1_pins: spi1-pins {
833 pins = "PD0", 797 pins = "PD0", "PD1", "PD2", "PD3";
834 function = "sp 798 function = "spi1";
835 }; 799 };
836 800
837 uart0_pb_pins: uart0-p 801 uart0_pb_pins: uart0-pb-pins {
838 pins = "PB8", 802 pins = "PB8", "PB9";
839 function = "ua 803 function = "uart0";
840 }; 804 };
841 805
842 uart1_pins: uart1-pins 806 uart1_pins: uart1-pins {
843 pins = "PG6", 807 pins = "PG6", "PG7";
844 function = "ua 808 function = "uart1";
845 }; 809 };
846 810
847 uart1_rts_cts_pins: ua 811 uart1_rts_cts_pins: uart1-rts-cts-pins {
848 pins = "PG8", 812 pins = "PG8", "PG9";
849 function = "ua 813 function = "uart1";
850 }; 814 };
851 815
852 uart2_pins: uart2-pins 816 uart2_pins: uart2-pins {
853 pins = "PB0", 817 pins = "PB0", "PB1";
854 function = "ua 818 function = "uart2";
855 }; 819 };
856 820
857 uart3_pins: uart3-pins 821 uart3_pins: uart3-pins {
858 pins = "PD0", 822 pins = "PD0", "PD1";
859 function = "ua 823 function = "uart3";
860 }; 824 };
861 825
862 uart4_pins: uart4-pins 826 uart4_pins: uart4-pins {
863 pins = "PD2", 827 pins = "PD2", "PD3";
864 function = "ua 828 function = "uart4";
865 }; 829 };
866 830
867 uart4_rts_cts_pins: ua 831 uart4_rts_cts_pins: uart4-rts-cts-pins {
868 pins = "PD4", 832 pins = "PD4", "PD5";
869 function = "ua 833 function = "uart4";
870 }; 834 };
871 }; 835 };
872 836
873 timer@1c20c00 { 837 timer@1c20c00 {
874 compatible = "allwinne 838 compatible = "allwinner,sun50i-a64-timer",
875 "allwinne 839 "allwinner,sun8i-a23-timer";
876 reg = <0x01c20c00 0xa0 840 reg = <0x01c20c00 0xa0>;
877 interrupts = <GIC_SPI 841 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
878 <GIC_SPI 842 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
879 clocks = <&osc24M>; 843 clocks = <&osc24M>;
880 }; 844 };
881 845
882 wdt0: watchdog@1c20ca0 { 846 wdt0: watchdog@1c20ca0 {
883 compatible = "allwinne 847 compatible = "allwinner,sun50i-a64-wdt",
884 "allwinne 848 "allwinner,sun6i-a31-wdt";
885 reg = <0x01c20ca0 0x20 849 reg = <0x01c20ca0 0x20>;
886 interrupts = <GIC_SPI 850 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
887 clocks = <&osc24M>; 851 clocks = <&osc24M>;
888 }; 852 };
889 853
890 spdif: spdif@1c21000 { 854 spdif: spdif@1c21000 {
891 #sound-dai-cells = <0> 855 #sound-dai-cells = <0>;
892 compatible = "allwinne 856 compatible = "allwinner,sun50i-a64-spdif",
893 "allwinne 857 "allwinner,sun8i-h3-spdif";
894 reg = <0x01c21000 0x40 858 reg = <0x01c21000 0x400>;
895 interrupts = <GIC_SPI 859 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
896 clocks = <&ccu CLK_BUS 860 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
897 resets = <&ccu RST_BUS 861 resets = <&ccu RST_BUS_SPDIF>;
898 clock-names = "apb", " 862 clock-names = "apb", "spdif";
899 dmas = <&dma 2>; 863 dmas = <&dma 2>;
900 dma-names = "tx"; 864 dma-names = "tx";
901 pinctrl-names = "defau 865 pinctrl-names = "default";
902 pinctrl-0 = <&spdif_tx 866 pinctrl-0 = <&spdif_tx_pin>;
903 status = "disabled"; 867 status = "disabled";
904 }; 868 };
905 869
906 lradc: lradc@1c21800 { 870 lradc: lradc@1c21800 {
907 compatible = "allwinne 871 compatible = "allwinner,sun50i-a64-lradc",
908 "allwinne 872 "allwinner,sun8i-a83t-r-lradc";
909 reg = <0x01c21800 0x40 873 reg = <0x01c21800 0x400>;
910 interrupt-parent = <&r 874 interrupt-parent = <&r_intc>;
911 interrupts = <GIC_SPI 875 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
912 status = "disabled"; 876 status = "disabled";
913 }; 877 };
914 878
915 i2s0: i2s@1c22000 { 879 i2s0: i2s@1c22000 {
916 #sound-dai-cells = <0> 880 #sound-dai-cells = <0>;
917 compatible = "allwinne 881 compatible = "allwinner,sun50i-a64-i2s",
918 "allwinne 882 "allwinner,sun8i-h3-i2s";
919 reg = <0x01c22000 0x40 883 reg = <0x01c22000 0x400>;
920 interrupts = <GIC_SPI 884 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
921 clocks = <&ccu CLK_BUS 885 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
922 clock-names = "apb", " 886 clock-names = "apb", "mod";
923 resets = <&ccu RST_BUS 887 resets = <&ccu RST_BUS_I2S0>;
924 dma-names = "rx", "tx" 888 dma-names = "rx", "tx";
925 dmas = <&dma 3>, <&dma 889 dmas = <&dma 3>, <&dma 3>;
926 status = "disabled"; 890 status = "disabled";
927 }; 891 };
928 892
929 i2s1: i2s@1c22400 { 893 i2s1: i2s@1c22400 {
930 #sound-dai-cells = <0> 894 #sound-dai-cells = <0>;
931 compatible = "allwinne 895 compatible = "allwinner,sun50i-a64-i2s",
932 "allwinne 896 "allwinner,sun8i-h3-i2s";
933 reg = <0x01c22400 0x40 897 reg = <0x01c22400 0x400>;
934 interrupts = <GIC_SPI 898 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
935 clocks = <&ccu CLK_BUS 899 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
936 clock-names = "apb", " 900 clock-names = "apb", "mod";
937 resets = <&ccu RST_BUS 901 resets = <&ccu RST_BUS_I2S1>;
938 dma-names = "rx", "tx" 902 dma-names = "rx", "tx";
939 dmas = <&dma 4>, <&dma 903 dmas = <&dma 4>, <&dma 4>;
940 status = "disabled"; 904 status = "disabled";
941 }; 905 };
942 906
943 i2s2: i2s@1c22800 { 907 i2s2: i2s@1c22800 {
944 #sound-dai-cells = <0> 908 #sound-dai-cells = <0>;
945 compatible = "allwinne 909 compatible = "allwinner,sun50i-a64-i2s",
946 "allwinne 910 "allwinner,sun8i-h3-i2s";
947 reg = <0x01c22800 0x40 911 reg = <0x01c22800 0x400>;
948 interrupts = <GIC_SPI 912 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
949 clocks = <&ccu CLK_BUS 913 clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
950 clock-names = "apb", " 914 clock-names = "apb", "mod";
951 resets = <&ccu RST_BUS 915 resets = <&ccu RST_BUS_I2S2>;
952 dma-names = "rx", "tx" 916 dma-names = "rx", "tx";
953 dmas = <&dma 27>, <&dm 917 dmas = <&dma 27>, <&dma 27>;
954 status = "disabled"; 918 status = "disabled";
955 }; 919 };
956 920
957 dai: dai@1c22c00 { 921 dai: dai@1c22c00 {
958 #sound-dai-cells = <0> 922 #sound-dai-cells = <0>;
959 compatible = "allwinne 923 compatible = "allwinner,sun50i-a64-codec-i2s";
960 reg = <0x01c22c00 0x20 924 reg = <0x01c22c00 0x200>;
961 interrupts = <GIC_SPI 925 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
962 clocks = <&ccu CLK_BUS 926 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
963 clock-names = "apb", " 927 clock-names = "apb", "mod";
964 resets = <&ccu RST_BUS 928 resets = <&ccu RST_BUS_CODEC>;
965 dmas = <&dma 15>, <&dm 929 dmas = <&dma 15>, <&dma 15>;
966 dma-names = "rx", "tx" 930 dma-names = "rx", "tx";
967 status = "disabled"; 931 status = "disabled";
968 }; 932 };
969 933
970 codec: codec@1c22e00 { 934 codec: codec@1c22e00 {
971 #sound-dai-cells = <1> 935 #sound-dai-cells = <1>;
972 compatible = "allwinne 936 compatible = "allwinner,sun50i-a64-codec",
973 "allwinne 937 "allwinner,sun8i-a33-codec";
974 reg = <0x01c22e00 0x60 938 reg = <0x01c22e00 0x600>;
975 interrupts = <GIC_SPI 939 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
976 clocks = <&ccu CLK_BUS 940 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
977 clock-names = "bus", " 941 clock-names = "bus", "mod";
978 status = "disabled"; 942 status = "disabled";
979 }; 943 };
980 944
981 ths: thermal-sensor@1c25000 { 945 ths: thermal-sensor@1c25000 {
982 compatible = "allwinne 946 compatible = "allwinner,sun50i-a64-ths";
983 reg = <0x01c25000 0x10 947 reg = <0x01c25000 0x100>;
984 clocks = <&ccu CLK_BUS 948 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
985 clock-names = "bus", " 949 clock-names = "bus", "mod";
986 interrupts = <GIC_SPI 950 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
987 resets = <&ccu RST_BUS 951 resets = <&ccu RST_BUS_THS>;
988 nvmem-cells = <&ths_ca 952 nvmem-cells = <&ths_calibration>;
989 nvmem-cell-names = "ca 953 nvmem-cell-names = "calibration";
990 #thermal-sensor-cells 954 #thermal-sensor-cells = <1>;
991 }; 955 };
992 956
993 uart0: serial@1c28000 { 957 uart0: serial@1c28000 {
994 compatible = "snps,dw- 958 compatible = "snps,dw-apb-uart";
995 reg = <0x01c28000 0x40 959 reg = <0x01c28000 0x400>;
996 interrupts = <GIC_SPI 960 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
997 reg-shift = <2>; 961 reg-shift = <2>;
998 reg-io-width = <4>; 962 reg-io-width = <4>;
999 clocks = <&ccu CLK_BUS 963 clocks = <&ccu CLK_BUS_UART0>;
1000 resets = <&ccu RST_BU 964 resets = <&ccu RST_BUS_UART0>;
1001 status = "disabled"; 965 status = "disabled";
1002 }; 966 };
1003 967
1004 uart1: serial@1c28400 { 968 uart1: serial@1c28400 {
1005 compatible = "snps,dw 969 compatible = "snps,dw-apb-uart";
1006 reg = <0x01c28400 0x4 970 reg = <0x01c28400 0x400>;
1007 interrupts = <GIC_SPI 971 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1008 reg-shift = <2>; 972 reg-shift = <2>;
1009 reg-io-width = <4>; 973 reg-io-width = <4>;
1010 clocks = <&ccu CLK_BU 974 clocks = <&ccu CLK_BUS_UART1>;
1011 resets = <&ccu RST_BU 975 resets = <&ccu RST_BUS_UART1>;
1012 status = "disabled"; 976 status = "disabled";
1013 }; 977 };
1014 978
1015 uart2: serial@1c28800 { 979 uart2: serial@1c28800 {
1016 compatible = "snps,dw 980 compatible = "snps,dw-apb-uart";
1017 reg = <0x01c28800 0x4 981 reg = <0x01c28800 0x400>;
1018 interrupts = <GIC_SPI 982 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1019 reg-shift = <2>; 983 reg-shift = <2>;
1020 reg-io-width = <4>; 984 reg-io-width = <4>;
1021 clocks = <&ccu CLK_BU 985 clocks = <&ccu CLK_BUS_UART2>;
1022 resets = <&ccu RST_BU 986 resets = <&ccu RST_BUS_UART2>;
1023 status = "disabled"; 987 status = "disabled";
1024 }; 988 };
1025 989
1026 uart3: serial@1c28c00 { 990 uart3: serial@1c28c00 {
1027 compatible = "snps,dw 991 compatible = "snps,dw-apb-uart";
1028 reg = <0x01c28c00 0x4 992 reg = <0x01c28c00 0x400>;
1029 interrupts = <GIC_SPI 993 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1030 reg-shift = <2>; 994 reg-shift = <2>;
1031 reg-io-width = <4>; 995 reg-io-width = <4>;
1032 clocks = <&ccu CLK_BU 996 clocks = <&ccu CLK_BUS_UART3>;
1033 resets = <&ccu RST_BU 997 resets = <&ccu RST_BUS_UART3>;
1034 status = "disabled"; 998 status = "disabled";
1035 }; 999 };
1036 1000
1037 uart4: serial@1c29000 { 1001 uart4: serial@1c29000 {
1038 compatible = "snps,dw 1002 compatible = "snps,dw-apb-uart";
1039 reg = <0x01c29000 0x4 1003 reg = <0x01c29000 0x400>;
1040 interrupts = <GIC_SPI 1004 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1041 reg-shift = <2>; 1005 reg-shift = <2>;
1042 reg-io-width = <4>; 1006 reg-io-width = <4>;
1043 clocks = <&ccu CLK_BU 1007 clocks = <&ccu CLK_BUS_UART4>;
1044 resets = <&ccu RST_BU 1008 resets = <&ccu RST_BUS_UART4>;
1045 status = "disabled"; 1009 status = "disabled";
1046 }; 1010 };
1047 1011
1048 i2c0: i2c@1c2ac00 { 1012 i2c0: i2c@1c2ac00 {
1049 compatible = "allwinn 1013 compatible = "allwinner,sun6i-a31-i2c";
1050 reg = <0x01c2ac00 0x4 1014 reg = <0x01c2ac00 0x400>;
1051 interrupts = <GIC_SPI 1015 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1052 clocks = <&ccu CLK_BU 1016 clocks = <&ccu CLK_BUS_I2C0>;
1053 resets = <&ccu RST_BU 1017 resets = <&ccu RST_BUS_I2C0>;
1054 pinctrl-names = "defa 1018 pinctrl-names = "default";
1055 pinctrl-0 = <&i2c0_pi 1019 pinctrl-0 = <&i2c0_pins>;
1056 status = "disabled"; 1020 status = "disabled";
1057 #address-cells = <1>; 1021 #address-cells = <1>;
1058 #size-cells = <0>; 1022 #size-cells = <0>;
1059 }; 1023 };
1060 1024
1061 i2c1: i2c@1c2b000 { 1025 i2c1: i2c@1c2b000 {
1062 compatible = "allwinn 1026 compatible = "allwinner,sun6i-a31-i2c";
1063 reg = <0x01c2b000 0x4 1027 reg = <0x01c2b000 0x400>;
1064 interrupts = <GIC_SPI 1028 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1065 clocks = <&ccu CLK_BU 1029 clocks = <&ccu CLK_BUS_I2C1>;
1066 resets = <&ccu RST_BU 1030 resets = <&ccu RST_BUS_I2C1>;
1067 pinctrl-names = "defa 1031 pinctrl-names = "default";
1068 pinctrl-0 = <&i2c1_pi 1032 pinctrl-0 = <&i2c1_pins>;
1069 status = "disabled"; 1033 status = "disabled";
1070 #address-cells = <1>; 1034 #address-cells = <1>;
1071 #size-cells = <0>; 1035 #size-cells = <0>;
1072 }; 1036 };
1073 1037
1074 i2c2: i2c@1c2b400 { 1038 i2c2: i2c@1c2b400 {
1075 compatible = "allwinn 1039 compatible = "allwinner,sun6i-a31-i2c";
1076 reg = <0x01c2b400 0x4 1040 reg = <0x01c2b400 0x400>;
1077 interrupts = <GIC_SPI 1041 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1078 clocks = <&ccu CLK_BU 1042 clocks = <&ccu CLK_BUS_I2C2>;
1079 resets = <&ccu RST_BU 1043 resets = <&ccu RST_BUS_I2C2>;
1080 pinctrl-names = "defa 1044 pinctrl-names = "default";
1081 pinctrl-0 = <&i2c2_pi 1045 pinctrl-0 = <&i2c2_pins>;
1082 status = "disabled"; 1046 status = "disabled";
1083 #address-cells = <1>; 1047 #address-cells = <1>;
1084 #size-cells = <0>; 1048 #size-cells = <0>;
1085 }; 1049 };
1086 1050
1087 spi0: spi@1c68000 { 1051 spi0: spi@1c68000 {
1088 compatible = "allwinn 1052 compatible = "allwinner,sun8i-h3-spi";
1089 reg = <0x01c68000 0x1 1053 reg = <0x01c68000 0x1000>;
1090 interrupts = <GIC_SPI 1054 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1091 clocks = <&ccu CLK_BU 1055 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
1092 clock-names = "ahb", 1056 clock-names = "ahb", "mod";
1093 dmas = <&dma 23>, <&d 1057 dmas = <&dma 23>, <&dma 23>;
1094 dma-names = "rx", "tx 1058 dma-names = "rx", "tx";
1095 pinctrl-names = "defa 1059 pinctrl-names = "default";
1096 pinctrl-0 = <&spi0_pi 1060 pinctrl-0 = <&spi0_pins>;
1097 resets = <&ccu RST_BU 1061 resets = <&ccu RST_BUS_SPI0>;
1098 status = "disabled"; 1062 status = "disabled";
1099 num-cs = <1>; 1063 num-cs = <1>;
1100 #address-cells = <1>; 1064 #address-cells = <1>;
1101 #size-cells = <0>; 1065 #size-cells = <0>;
1102 }; 1066 };
1103 1067
1104 spi1: spi@1c69000 { 1068 spi1: spi@1c69000 {
1105 compatible = "allwinn 1069 compatible = "allwinner,sun8i-h3-spi";
1106 reg = <0x01c69000 0x1 1070 reg = <0x01c69000 0x1000>;
1107 interrupts = <GIC_SPI 1071 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1108 clocks = <&ccu CLK_BU 1072 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
1109 clock-names = "ahb", 1073 clock-names = "ahb", "mod";
1110 dmas = <&dma 24>, <&d 1074 dmas = <&dma 24>, <&dma 24>;
1111 dma-names = "rx", "tx 1075 dma-names = "rx", "tx";
1112 pinctrl-names = "defa 1076 pinctrl-names = "default";
1113 pinctrl-0 = <&spi1_pi 1077 pinctrl-0 = <&spi1_pins>;
1114 resets = <&ccu RST_BU 1078 resets = <&ccu RST_BUS_SPI1>;
1115 status = "disabled"; 1079 status = "disabled";
1116 num-cs = <1>; 1080 num-cs = <1>;
1117 #address-cells = <1>; 1081 #address-cells = <1>;
1118 #size-cells = <0>; 1082 #size-cells = <0>;
1119 }; 1083 };
1120 1084
1121 emac: ethernet@1c30000 { 1085 emac: ethernet@1c30000 {
1122 compatible = "allwinn 1086 compatible = "allwinner,sun50i-a64-emac";
1123 syscon = <&syscon>; 1087 syscon = <&syscon>;
1124 reg = <0x01c30000 0x1 1088 reg = <0x01c30000 0x10000>;
1125 interrupts = <GIC_SPI 1089 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1126 interrupt-names = "ma 1090 interrupt-names = "macirq";
1127 resets = <&ccu RST_BU 1091 resets = <&ccu RST_BUS_EMAC>;
1128 reset-names = "stmmac 1092 reset-names = "stmmaceth";
1129 clocks = <&ccu CLK_BU 1093 clocks = <&ccu CLK_BUS_EMAC>;
1130 clock-names = "stmmac 1094 clock-names = "stmmaceth";
1131 status = "disabled"; 1095 status = "disabled";
1132 1096
1133 mdio: mdio { 1097 mdio: mdio {
1134 compatible = 1098 compatible = "snps,dwmac-mdio";
1135 #address-cell 1099 #address-cells = <1>;
1136 #size-cells = 1100 #size-cells = <0>;
1137 }; 1101 };
1138 }; 1102 };
1139 1103
1140 mali: gpu@1c40000 { 1104 mali: gpu@1c40000 {
1141 compatible = "allwinn 1105 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400";
1142 reg = <0x01c40000 0x1 1106 reg = <0x01c40000 0x10000>;
1143 interrupts = <GIC_SPI 1107 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1144 <GIC_SPI 1108 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1145 <GIC_SPI 1109 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1146 <GIC_SPI 1110 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1147 <GIC_SPI 1111 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1148 <GIC_SPI 1112 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1149 <GIC_SPI 1113 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1150 interrupt-names = "gp 1114 interrupt-names = "gp",
1151 "gp 1115 "gpmmu",
1152 "pp 1116 "pp0",
1153 "pp 1117 "ppmmu0",
1154 "pp 1118 "pp1",
1155 "pp 1119 "ppmmu1",
1156 "pm 1120 "pmu";
1157 clocks = <&ccu CLK_BU 1121 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
1158 clock-names = "bus", 1122 clock-names = "bus", "core";
1159 resets = <&ccu RST_BU 1123 resets = <&ccu RST_BUS_GPU>;
1160 operating-points-v2 = 1124 operating-points-v2 = <&gpu_opp_table>;
1161 }; 1125 };
1162 1126
1163 gic: interrupt-controller@1c8 1127 gic: interrupt-controller@1c81000 {
1164 compatible = "arm,gic 1128 compatible = "arm,gic-400";
1165 reg = <0x01c81000 0x1 1129 reg = <0x01c81000 0x1000>,
1166 <0x01c82000 0x2 1130 <0x01c82000 0x2000>,
1167 <0x01c84000 0x2 1131 <0x01c84000 0x2000>,
1168 <0x01c86000 0x2 1132 <0x01c86000 0x2000>;
1169 interrupts = <GIC_PPI 1133 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1170 interrupt-controller; 1134 interrupt-controller;
1171 #interrupt-cells = <3 1135 #interrupt-cells = <3>;
1172 }; 1136 };
1173 1137
1174 pwm: pwm@1c21400 { 1138 pwm: pwm@1c21400 {
1175 compatible = "allwinn 1139 compatible = "allwinner,sun50i-a64-pwm",
1176 "allwinn 1140 "allwinner,sun5i-a13-pwm";
1177 reg = <0x01c21400 0x4 1141 reg = <0x01c21400 0x400>;
1178 clocks = <&osc24M>; 1142 clocks = <&osc24M>;
1179 pinctrl-names = "defa 1143 pinctrl-names = "default";
1180 pinctrl-0 = <&pwm_pin 1144 pinctrl-0 = <&pwm_pin>;
1181 #pwm-cells = <3>; 1145 #pwm-cells = <3>;
1182 status = "disabled"; 1146 status = "disabled";
1183 }; 1147 };
1184 1148
1185 mbus: dram-controller@1c62000 1149 mbus: dram-controller@1c62000 {
1186 compatible = "allwinn 1150 compatible = "allwinner,sun50i-a64-mbus";
1187 reg = <0x01c62000 0x1 1151 reg = <0x01c62000 0x1000>,
1188 <0x01c63000 0x1 1152 <0x01c63000 0x1000>;
1189 reg-names = "mbus", " 1153 reg-names = "mbus", "dram";
1190 clocks = <&ccu CLK_MB 1154 clocks = <&ccu CLK_MBUS>,
1191 <&ccu CLK_DR 1155 <&ccu CLK_DRAM>,
1192 <&ccu CLK_BU 1156 <&ccu CLK_BUS_DRAM>;
1193 clock-names = "mbus", 1157 clock-names = "mbus", "dram", "bus";
1194 interrupts = <GIC_SPI 1158 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
1195 #address-cells = <1>; 1159 #address-cells = <1>;
1196 #size-cells = <1>; 1160 #size-cells = <1>;
1197 dma-ranges = <0x00000 1161 dma-ranges = <0x00000000 0x40000000 0xc0000000>;
1198 #interconnect-cells = 1162 #interconnect-cells = <1>;
1199 }; 1163 };
1200 1164
1201 csi: csi@1cb0000 { 1165 csi: csi@1cb0000 {
1202 compatible = "allwinn 1166 compatible = "allwinner,sun50i-a64-csi";
1203 reg = <0x01cb0000 0x1 1167 reg = <0x01cb0000 0x1000>;
1204 interrupts = <GIC_SPI 1168 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1205 clocks = <&ccu CLK_BU 1169 clocks = <&ccu CLK_BUS_CSI>,
1206 <&ccu CLK_CS 1170 <&ccu CLK_CSI_SCLK>,
1207 <&ccu CLK_DR 1171 <&ccu CLK_DRAM_CSI>;
1208 clock-names = "bus", 1172 clock-names = "bus", "mod", "ram";
1209 resets = <&ccu RST_BU 1173 resets = <&ccu RST_BUS_CSI>;
1210 pinctrl-names = "defa 1174 pinctrl-names = "default";
1211 pinctrl-0 = <&csi_pin 1175 pinctrl-0 = <&csi_pins>;
1212 status = "disabled"; 1176 status = "disabled";
1213 }; 1177 };
1214 1178
1215 dsi: dsi@1ca0000 { 1179 dsi: dsi@1ca0000 {
1216 compatible = "allwinn 1180 compatible = "allwinner,sun50i-a64-mipi-dsi";
1217 reg = <0x01ca0000 0x1 1181 reg = <0x01ca0000 0x1000>;
1218 interrupts = <GIC_SPI 1182 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1219 clocks = <&ccu CLK_BU 1183 clocks = <&ccu CLK_BUS_MIPI_DSI>;
1220 resets = <&ccu RST_BU 1184 resets = <&ccu RST_BUS_MIPI_DSI>;
1221 phys = <&dphy>; 1185 phys = <&dphy>;
1222 phy-names = "dphy"; 1186 phy-names = "dphy";
1223 status = "disabled"; 1187 status = "disabled";
1224 #address-cells = <1>; 1188 #address-cells = <1>;
1225 #size-cells = <0>; 1189 #size-cells = <0>;
1226 1190
1227 port { 1191 port {
1228 dsi_in_tcon0: 1192 dsi_in_tcon0: endpoint {
1229 remot 1193 remote-endpoint = <&tcon0_out_dsi>;
1230 }; 1194 };
1231 }; 1195 };
1232 }; 1196 };
1233 1197
1234 dphy: d-phy@1ca1000 { 1198 dphy: d-phy@1ca1000 {
1235 compatible = "allwinn 1199 compatible = "allwinner,sun50i-a64-mipi-dphy",
1236 "allwinn 1200 "allwinner,sun6i-a31-mipi-dphy";
1237 reg = <0x01ca1000 0x1 1201 reg = <0x01ca1000 0x1000>;
1238 interrupts = <GIC_SPI <<
1239 clocks = <&ccu CLK_BU 1202 clocks = <&ccu CLK_BUS_MIPI_DSI>,
1240 <&ccu CLK_DS 1203 <&ccu CLK_DSI_DPHY>;
1241 clock-names = "bus", 1204 clock-names = "bus", "mod";
1242 resets = <&ccu RST_BU 1205 resets = <&ccu RST_BUS_MIPI_DSI>;
1243 status = "disabled"; 1206 status = "disabled";
1244 #phy-cells = <0>; 1207 #phy-cells = <0>;
1245 }; 1208 };
1246 1209
1247 deinterlace: deinterlace@1e00 1210 deinterlace: deinterlace@1e00000 {
1248 compatible = "allwinn 1211 compatible = "allwinner,sun50i-a64-deinterlace",
1249 "allwinn 1212 "allwinner,sun8i-h3-deinterlace";
1250 reg = <0x01e00000 0x2 1213 reg = <0x01e00000 0x20000>;
1251 clocks = <&ccu CLK_BU 1214 clocks = <&ccu CLK_BUS_DEINTERLACE>,
1252 <&ccu CLK_DE 1215 <&ccu CLK_DEINTERLACE>,
1253 <&ccu CLK_DR 1216 <&ccu CLK_DRAM_DEINTERLACE>;
1254 clock-names = "bus", 1217 clock-names = "bus", "mod", "ram";
1255 resets = <&ccu RST_BU 1218 resets = <&ccu RST_BUS_DEINTERLACE>;
1256 interrupts = <GIC_SPI 1219 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1257 interconnects = <&mbu 1220 interconnects = <&mbus 9>;
1258 interconnect-names = 1221 interconnect-names = "dma-mem";
1259 }; 1222 };
1260 1223
1261 hdmi: hdmi@1ee0000 { 1224 hdmi: hdmi@1ee0000 {
1262 compatible = "allwinn 1225 compatible = "allwinner,sun50i-a64-dw-hdmi",
1263 "allwinn 1226 "allwinner,sun8i-a83t-dw-hdmi";
1264 reg = <0x01ee0000 0x1 1227 reg = <0x01ee0000 0x10000>;
1265 reg-io-width = <1>; 1228 reg-io-width = <1>;
1266 interrupts = <GIC_SPI 1229 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1267 clocks = <&ccu CLK_BU 1230 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1268 <&ccu CLK_HD 1231 <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>;
1269 clock-names = "iahb", 1232 clock-names = "iahb", "isfr", "tmds", "cec";
1270 resets = <&ccu RST_BU 1233 resets = <&ccu RST_BUS_HDMI1>;
1271 reset-names = "ctrl"; 1234 reset-names = "ctrl";
1272 phys = <&hdmi_phy>; 1235 phys = <&hdmi_phy>;
1273 phy-names = "phy"; 1236 phy-names = "phy";
1274 status = "disabled"; 1237 status = "disabled";
1275 1238
1276 ports { 1239 ports {
1277 #address-cell 1240 #address-cells = <1>;
1278 #size-cells = 1241 #size-cells = <0>;
1279 1242
1280 hdmi_in: port 1243 hdmi_in: port@0 {
1281 reg = 1244 reg = <0>;
1282 1245
1283 hdmi_ 1246 hdmi_in_tcon1: endpoint {
1284 1247 remote-endpoint = <&tcon1_out_hdmi>;
1285 }; 1248 };
1286 }; 1249 };
1287 1250
1288 hdmi_out: por 1251 hdmi_out: port@1 {
1289 reg = 1252 reg = <1>;
1290 }; 1253 };
1291 }; 1254 };
1292 }; 1255 };
1293 1256
1294 hdmi_phy: hdmi-phy@1ef0000 { 1257 hdmi_phy: hdmi-phy@1ef0000 {
1295 compatible = "allwinn 1258 compatible = "allwinner,sun50i-a64-hdmi-phy";
1296 reg = <0x01ef0000 0x1 1259 reg = <0x01ef0000 0x10000>;
1297 clocks = <&ccu CLK_BU 1260 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1298 <&ccu CLK_PL 1261 <&ccu CLK_PLL_VIDEO0>;
1299 clock-names = "bus", 1262 clock-names = "bus", "mod", "pll-0";
1300 resets = <&ccu RST_BU 1263 resets = <&ccu RST_BUS_HDMI0>;
1301 reset-names = "phy"; 1264 reset-names = "phy";
1302 #phy-cells = <0>; 1265 #phy-cells = <0>;
1303 }; 1266 };
1304 1267
1305 rtc: rtc@1f00000 { 1268 rtc: rtc@1f00000 {
1306 compatible = "allwinn 1269 compatible = "allwinner,sun50i-a64-rtc",
1307 "allwinn 1270 "allwinner,sun8i-h3-rtc";
1308 reg = <0x01f00000 0x4 1271 reg = <0x01f00000 0x400>;
1309 interrupt-parent = <& 1272 interrupt-parent = <&r_intc>;
1310 interrupts = <GIC_SPI 1273 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1311 <GIC_SPI 1274 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1312 clock-output-names = 1275 clock-output-names = "osc32k", "osc32k-out", "iosc";
1313 clocks = <&osc32k>; 1276 clocks = <&osc32k>;
1314 #clock-cells = <1>; 1277 #clock-cells = <1>;
1315 }; 1278 };
1316 1279
1317 r_intc: interrupt-controller@ 1280 r_intc: interrupt-controller@1f00c00 {
1318 compatible = "allwinn 1281 compatible = "allwinner,sun50i-a64-r-intc",
1319 "allwinn 1282 "allwinner,sun6i-a31-r-intc";
1320 interrupt-controller; 1283 interrupt-controller;
1321 #interrupt-cells = <3 1284 #interrupt-cells = <3>;
1322 reg = <0x01f00c00 0x4 1285 reg = <0x01f00c00 0x400>;
1323 interrupts = <GIC_SPI 1286 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1324 }; 1287 };
1325 1288
1326 r_ccu: clock@1f01400 { 1289 r_ccu: clock@1f01400 {
1327 compatible = "allwinn 1290 compatible = "allwinner,sun50i-a64-r-ccu";
1328 reg = <0x01f01400 0x1 1291 reg = <0x01f01400 0x100>;
1329 clocks = <&osc24M>, < 1292 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
1330 <&ccu CLK_PL 1293 <&ccu CLK_PLL_PERIPH0>;
1331 clock-names = "hosc", 1294 clock-names = "hosc", "losc", "iosc", "pll-periph";
1332 #clock-cells = <1>; 1295 #clock-cells = <1>;
1333 #reset-cells = <1>; 1296 #reset-cells = <1>;
1334 }; 1297 };
1335 1298
1336 codec_analog: codec-analog@1f 1299 codec_analog: codec-analog@1f015c0 {
1337 compatible = "allwinn 1300 compatible = "allwinner,sun50i-a64-codec-analog";
1338 reg = <0x01f015c0 0x4 1301 reg = <0x01f015c0 0x4>;
1339 status = "disabled"; 1302 status = "disabled";
1340 }; 1303 };
1341 1304
1342 r_i2c: i2c@1f02400 { 1305 r_i2c: i2c@1f02400 {
1343 compatible = "allwinn 1306 compatible = "allwinner,sun50i-a64-i2c",
1344 "allwinn 1307 "allwinner,sun6i-a31-i2c";
1345 reg = <0x01f02400 0x4 1308 reg = <0x01f02400 0x400>;
1346 interrupts = <GIC_SPI 1309 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1347 clocks = <&r_ccu CLK_ 1310 clocks = <&r_ccu CLK_APB0_I2C>;
1348 resets = <&r_ccu RST_ 1311 resets = <&r_ccu RST_APB0_I2C>;
1349 status = "disabled"; 1312 status = "disabled";
1350 #address-cells = <1>; 1313 #address-cells = <1>;
1351 #size-cells = <0>; 1314 #size-cells = <0>;
1352 }; 1315 };
1353 1316
1354 r_ir: ir@1f02000 { 1317 r_ir: ir@1f02000 {
1355 compatible = "allwinn 1318 compatible = "allwinner,sun50i-a64-ir",
1356 "allwinn 1319 "allwinner,sun6i-a31-ir";
1357 reg = <0x01f02000 0x4 1320 reg = <0x01f02000 0x400>;
1358 clocks = <&r_ccu CLK_ 1321 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
1359 clock-names = "apb", 1322 clock-names = "apb", "ir";
1360 resets = <&r_ccu RST_ 1323 resets = <&r_ccu RST_APB0_IR>;
1361 interrupts = <GIC_SPI 1324 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1362 pinctrl-names = "defa 1325 pinctrl-names = "default";
1363 pinctrl-0 = <&r_ir_rx 1326 pinctrl-0 = <&r_ir_rx_pin>;
1364 status = "disabled"; 1327 status = "disabled";
1365 }; 1328 };
1366 1329
1367 r_pwm: pwm@1f03800 { 1330 r_pwm: pwm@1f03800 {
1368 compatible = "allwinn 1331 compatible = "allwinner,sun50i-a64-pwm",
1369 "allwinn 1332 "allwinner,sun5i-a13-pwm";
1370 reg = <0x01f03800 0x4 1333 reg = <0x01f03800 0x400>;
1371 clocks = <&osc24M>; 1334 clocks = <&osc24M>;
1372 pinctrl-names = "defa 1335 pinctrl-names = "default";
1373 pinctrl-0 = <&r_pwm_p 1336 pinctrl-0 = <&r_pwm_pin>;
1374 #pwm-cells = <3>; 1337 #pwm-cells = <3>;
1375 status = "disabled"; 1338 status = "disabled";
1376 }; 1339 };
1377 1340
1378 r_pio: pinctrl@1f02c00 { 1341 r_pio: pinctrl@1f02c00 {
1379 compatible = "allwinn 1342 compatible = "allwinner,sun50i-a64-r-pinctrl";
1380 reg = <0x01f02c00 0x4 1343 reg = <0x01f02c00 0x400>;
1381 interrupt-parent = <& 1344 interrupt-parent = <&r_intc>;
1382 interrupts = <GIC_SPI 1345 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1383 clocks = <&r_ccu CLK_ 1346 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
1384 clock-names = "apb", 1347 clock-names = "apb", "hosc", "losc";
1385 gpio-controller; 1348 gpio-controller;
1386 #gpio-cells = <3>; 1349 #gpio-cells = <3>;
1387 interrupt-controller; 1350 interrupt-controller;
1388 #interrupt-cells = <3 1351 #interrupt-cells = <3>;
1389 1352
1390 r_i2c_pl89_pins: r-i2 1353 r_i2c_pl89_pins: r-i2c-pl89-pins {
1391 pins = "PL8", 1354 pins = "PL8", "PL9";
1392 function = "s 1355 function = "s_i2c";
1393 }; 1356 };
1394 1357
1395 r_ir_rx_pin: r-ir-rx- 1358 r_ir_rx_pin: r-ir-rx-pin {
1396 pins = "PL11" 1359 pins = "PL11";
1397 function = "s 1360 function = "s_cir_rx";
1398 }; 1361 };
1399 1362
1400 r_pwm_pin: r-pwm-pin 1363 r_pwm_pin: r-pwm-pin {
1401 pins = "PL10" 1364 pins = "PL10";
1402 function = "s 1365 function = "s_pwm";
1403 }; 1366 };
1404 1367
1405 r_rsb_pins: r-rsb-pin 1368 r_rsb_pins: r-rsb-pins {
1406 pins = "PL0", 1369 pins = "PL0", "PL1";
1407 function = "s 1370 function = "s_rsb";
1408 }; 1371 };
1409 }; 1372 };
1410 1373
1411 r_rsb: rsb@1f03400 { 1374 r_rsb: rsb@1f03400 {
1412 compatible = "allwinn 1375 compatible = "allwinner,sun8i-a23-rsb";
1413 reg = <0x01f03400 0x4 1376 reg = <0x01f03400 0x400>;
1414 interrupts = <GIC_SPI 1377 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1415 clocks = <&r_ccu 6>; 1378 clocks = <&r_ccu 6>;
1416 clock-frequency = <30 1379 clock-frequency = <3000000>;
1417 resets = <&r_ccu 2>; 1380 resets = <&r_ccu 2>;
1418 pinctrl-names = "defa 1381 pinctrl-names = "default";
1419 pinctrl-0 = <&r_rsb_p 1382 pinctrl-0 = <&r_rsb_pins>;
1420 status = "disabled"; 1383 status = "disabled";
1421 #address-cells = <1>; 1384 #address-cells = <1>;
1422 #size-cells = <0>; 1385 #size-cells = <0>;
1423 }; 1386 };
1424 }; 1387 };
1425 }; 1388 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.