1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2016 ARM Ltd. 2 // Copyright (C) 2016 ARM Ltd.
3 // based on the Allwinner H3 dtsi: 3 // based on the Allwinner H3 dtsi:
4 // Copyright (C) 2015 Jens Kuske <jenskuske@ 4 // Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
5 5
6 #include <dt-bindings/clock/sun50i-a64-ccu.h> 6 #include <dt-bindings/clock/sun50i-a64-ccu.h>
7 #include <dt-bindings/clock/sun6i-rtc.h> 7 #include <dt-bindings/clock/sun6i-rtc.h>
8 #include <dt-bindings/clock/sun8i-de2.h> 8 #include <dt-bindings/clock/sun8i-de2.h>
9 #include <dt-bindings/clock/sun8i-r-ccu.h> 9 #include <dt-bindings/clock/sun8i-r-ccu.h>
10 #include <dt-bindings/interrupt-controller/arm 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/sun50i-a64-ccu.h> 11 #include <dt-bindings/reset/sun50i-a64-ccu.h>
12 #include <dt-bindings/reset/sun8i-de2.h> 12 #include <dt-bindings/reset/sun8i-de2.h>
13 #include <dt-bindings/reset/sun8i-r-ccu.h> 13 #include <dt-bindings/reset/sun8i-r-ccu.h>
14 #include <dt-bindings/thermal/thermal.h> 14 #include <dt-bindings/thermal/thermal.h>
15 15
16 / { 16 / {
17 interrupt-parent = <&gic>; 17 interrupt-parent = <&gic>;
18 #address-cells = <1>; 18 #address-cells = <1>;
19 #size-cells = <1>; 19 #size-cells = <1>;
20 20
21 chosen { 21 chosen {
22 #address-cells = <1>; 22 #address-cells = <1>;
23 #size-cells = <1>; 23 #size-cells = <1>;
24 ranges; 24 ranges;
25 25
26 simplefb_lcd: framebuffer-lcd 26 simplefb_lcd: framebuffer-lcd {
27 compatible = "allwinne 27 compatible = "allwinner,simple-framebuffer",
28 "simple-f 28 "simple-framebuffer";
29 allwinner,pipeline = " 29 allwinner,pipeline = "mixer0-lcd0";
30 clocks = <&ccu CLK_TCO 30 clocks = <&ccu CLK_TCON0>,
31 <&display_clo 31 <&display_clocks CLK_MIXER0>;
32 status = "disabled"; 32 status = "disabled";
33 }; 33 };
34 34
35 simplefb_hdmi: framebuffer-hdm 35 simplefb_hdmi: framebuffer-hdmi {
36 compatible = "allwinne 36 compatible = "allwinner,simple-framebuffer",
37 "simple-f 37 "simple-framebuffer";
38 allwinner,pipeline = " 38 allwinner,pipeline = "mixer1-lcd1-hdmi";
39 clocks = <&display_clo 39 clocks = <&display_clocks CLK_MIXER1>,
40 <&ccu CLK_TCO 40 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
41 status = "disabled"; 41 status = "disabled";
42 }; 42 };
43 }; 43 };
44 44
45 cpus { 45 cpus {
46 #address-cells = <1>; 46 #address-cells = <1>;
47 #size-cells = <0>; 47 #size-cells = <0>;
48 48
49 cpu0: cpu@0 { 49 cpu0: cpu@0 {
50 compatible = "arm,cort 50 compatible = "arm,cortex-a53";
51 device_type = "cpu"; 51 device_type = "cpu";
52 reg = <0>; 52 reg = <0>;
53 enable-method = "psci" 53 enable-method = "psci";
>> 54 next-level-cache = <&L2>;
54 clocks = <&ccu CLK_CPU 55 clocks = <&ccu CLK_CPUX>;
55 clock-names = "cpu"; 56 clock-names = "cpu";
56 #cooling-cells = <2>; 57 #cooling-cells = <2>;
57 i-cache-size = <0x8000 <<
58 i-cache-line-size = <6 <<
59 i-cache-sets = <256>; <<
60 d-cache-size = <0x8000 <<
61 d-cache-line-size = <6 <<
62 d-cache-sets = <128>; <<
63 next-level-cache = <&l <<
64 }; 58 };
65 59
66 cpu1: cpu@1 { 60 cpu1: cpu@1 {
67 compatible = "arm,cort 61 compatible = "arm,cortex-a53";
68 device_type = "cpu"; 62 device_type = "cpu";
69 reg = <1>; 63 reg = <1>;
70 enable-method = "psci" 64 enable-method = "psci";
>> 65 next-level-cache = <&L2>;
71 clocks = <&ccu CLK_CPU 66 clocks = <&ccu CLK_CPUX>;
72 clock-names = "cpu"; 67 clock-names = "cpu";
73 #cooling-cells = <2>; 68 #cooling-cells = <2>;
74 i-cache-size = <0x8000 <<
75 i-cache-line-size = <6 <<
76 i-cache-sets = <256>; <<
77 d-cache-size = <0x8000 <<
78 d-cache-line-size = <6 <<
79 d-cache-sets = <128>; <<
80 next-level-cache = <&l <<
81 }; 69 };
82 70
83 cpu2: cpu@2 { 71 cpu2: cpu@2 {
84 compatible = "arm,cort 72 compatible = "arm,cortex-a53";
85 device_type = "cpu"; 73 device_type = "cpu";
86 reg = <2>; 74 reg = <2>;
87 enable-method = "psci" 75 enable-method = "psci";
>> 76 next-level-cache = <&L2>;
88 clocks = <&ccu CLK_CPU 77 clocks = <&ccu CLK_CPUX>;
89 clock-names = "cpu"; 78 clock-names = "cpu";
90 #cooling-cells = <2>; 79 #cooling-cells = <2>;
91 i-cache-size = <0x8000 <<
92 i-cache-line-size = <6 <<
93 i-cache-sets = <256>; <<
94 d-cache-size = <0x8000 <<
95 d-cache-line-size = <6 <<
96 d-cache-sets = <128>; <<
97 next-level-cache = <&l <<
98 }; 80 };
99 81
100 cpu3: cpu@3 { 82 cpu3: cpu@3 {
101 compatible = "arm,cort 83 compatible = "arm,cortex-a53";
102 device_type = "cpu"; 84 device_type = "cpu";
103 reg = <3>; 85 reg = <3>;
104 enable-method = "psci" 86 enable-method = "psci";
>> 87 next-level-cache = <&L2>;
105 clocks = <&ccu CLK_CPU 88 clocks = <&ccu CLK_CPUX>;
106 clock-names = "cpu"; 89 clock-names = "cpu";
107 #cooling-cells = <2>; 90 #cooling-cells = <2>;
108 i-cache-size = <0x8000 <<
109 i-cache-line-size = <6 <<
110 i-cache-sets = <256>; <<
111 d-cache-size = <0x8000 <<
112 d-cache-line-size = <6 <<
113 d-cache-sets = <128>; <<
114 next-level-cache = <&l <<
115 }; 91 };
116 92
117 l2_cache: l2-cache { !! 93 L2: l2-cache {
118 compatible = "cache"; 94 compatible = "cache";
119 cache-level = <2>; 95 cache-level = <2>;
120 cache-unified; 96 cache-unified;
121 cache-size = <0x80000> <<
122 cache-line-size = <64> <<
123 cache-sets = <512>; <<
124 }; 97 };
125 }; 98 };
126 99
127 de: display-engine { 100 de: display-engine {
128 compatible = "allwinner,sun50i 101 compatible = "allwinner,sun50i-a64-display-engine";
129 allwinner,pipelines = <&mixer0 102 allwinner,pipelines = <&mixer0>,
130 <&mixer1 103 <&mixer1>;
131 status = "disabled"; 104 status = "disabled";
132 }; 105 };
133 106
134 gpu_opp_table: opp-table-gpu { 107 gpu_opp_table: opp-table-gpu {
135 compatible = "operating-points 108 compatible = "operating-points-v2";
136 109
137 opp-432000000 { 110 opp-432000000 {
138 opp-hz = /bits/ 64 <43 111 opp-hz = /bits/ 64 <432000000>;
139 }; 112 };
140 }; 113 };
141 114
142 osc24M: osc24M-clk { 115 osc24M: osc24M-clk {
143 #clock-cells = <0>; 116 #clock-cells = <0>;
144 compatible = "fixed-clock"; 117 compatible = "fixed-clock";
145 clock-frequency = <24000000>; 118 clock-frequency = <24000000>;
146 clock-output-names = "osc24M"; 119 clock-output-names = "osc24M";
147 }; 120 };
148 121
149 osc32k: osc32k-clk { 122 osc32k: osc32k-clk {
150 #clock-cells = <0>; 123 #clock-cells = <0>;
151 compatible = "fixed-clock"; 124 compatible = "fixed-clock";
152 clock-frequency = <32768>; 125 clock-frequency = <32768>;
153 clock-output-names = "ext-osc3 126 clock-output-names = "ext-osc32k";
154 }; 127 };
155 128
156 pmu { 129 pmu {
157 compatible = "arm,cortex-a53-p 130 compatible = "arm,cortex-a53-pmu";
158 interrupts = <GIC_SPI 116 IRQ_ 131 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 117 IRQ_ 132 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 118 IRQ_ 133 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 119 IRQ_ 134 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
162 interrupt-affinity = <&cpu0>, 135 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
163 }; 136 };
164 137
165 psci { 138 psci {
166 compatible = "arm,psci-0.2"; 139 compatible = "arm,psci-0.2";
167 method = "smc"; 140 method = "smc";
168 }; 141 };
169 142
170 sound: sound { 143 sound: sound {
171 #address-cells = <1>; 144 #address-cells = <1>;
172 #size-cells = <0>; 145 #size-cells = <0>;
173 compatible = "simple-audio-car 146 compatible = "simple-audio-card";
174 simple-audio-card,name = "sun5 147 simple-audio-card,name = "sun50i-a64-audio";
175 simple-audio-card,aux-devs = < 148 simple-audio-card,aux-devs = <&codec_analog>;
176 simple-audio-card,routing = 149 simple-audio-card,routing =
177 "Left DAC", "D 150 "Left DAC", "DACL",
178 "Right DAC", " 151 "Right DAC", "DACR",
179 "ADCL", "Left 152 "ADCL", "Left ADC",
180 "ADCR", "Right 153 "ADCR", "Right ADC";
181 status = "disabled"; 154 status = "disabled";
182 155
183 simple-audio-card,dai-link@0 { 156 simple-audio-card,dai-link@0 {
184 format = "i2s"; 157 format = "i2s";
185 frame-master = <&link0 158 frame-master = <&link0_cpu>;
186 bitclock-master = <&li 159 bitclock-master = <&link0_cpu>;
187 mclk-fs = <128>; 160 mclk-fs = <128>;
188 161
189 link0_cpu: cpu { 162 link0_cpu: cpu {
190 sound-dai = <& 163 sound-dai = <&dai>;
191 }; 164 };
192 165
193 link0_codec: codec { 166 link0_codec: codec {
194 sound-dai = <& 167 sound-dai = <&codec 0>;
195 }; 168 };
196 }; 169 };
197 }; 170 };
198 171
199 timer { 172 timer {
200 compatible = "arm,armv8-timer" 173 compatible = "arm,armv8-timer";
201 allwinner,erratum-unknown1; 174 allwinner,erratum-unknown1;
202 arm,no-tick-in-suspend; 175 arm,no-tick-in-suspend;
203 interrupts = <GIC_PPI 13 176 interrupts = <GIC_PPI 13
204 (GIC_CPU_MASK_SIMPLE(4 177 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
205 <GIC_PPI 14 178 <GIC_PPI 14
206 (GIC_CPU_MASK_SIMPLE(4 179 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
207 <GIC_PPI 11 180 <GIC_PPI 11
208 (GIC_CPU_MASK_SIMPLE(4 181 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
209 <GIC_PPI 10 182 <GIC_PPI 10
210 (GIC_CPU_MASK_SIMPLE(4 183 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
211 }; 184 };
212 185
213 thermal-zones { 186 thermal-zones {
214 cpu_thermal: cpu0-thermal { 187 cpu_thermal: cpu0-thermal {
215 /* milliseconds */ 188 /* milliseconds */
216 polling-delay-passive 189 polling-delay-passive = <0>;
217 polling-delay = <0>; 190 polling-delay = <0>;
218 thermal-sensors = <&th 191 thermal-sensors = <&ths 0>;
219 192
220 cooling-maps { 193 cooling-maps {
221 map0 { 194 map0 {
222 trip = 195 trip = <&cpu_alert0>;
223 coolin 196 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
224 197 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
225 198 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
226 199 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
227 }; 200 };
228 map1 { 201 map1 {
229 trip = 202 trip = <&cpu_alert1>;
230 coolin 203 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
231 204 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
232 205 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
233 206 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
234 }; 207 };
235 }; 208 };
236 209
237 trips { 210 trips {
238 cpu_alert0: cp 211 cpu_alert0: cpu-alert0 {
239 /* mil 212 /* milliCelsius */
240 temper 213 temperature = <75000>;
241 hyster 214 hysteresis = <2000>;
242 type = 215 type = "passive";
243 }; 216 };
244 217
245 cpu_alert1: cp 218 cpu_alert1: cpu-alert1 {
246 /* mil 219 /* milliCelsius */
247 temper 220 temperature = <90000>;
248 hyster 221 hysteresis = <2000>;
249 type = 222 type = "hot";
250 }; 223 };
251 224
252 cpu_crit: cpu- 225 cpu_crit: cpu-crit {
253 /* mil 226 /* milliCelsius */
254 temper 227 temperature = <110000>;
255 hyster 228 hysteresis = <2000>;
256 type = 229 type = "critical";
257 }; 230 };
258 }; 231 };
259 }; 232 };
260 233
261 gpu0_thermal: gpu0-thermal { 234 gpu0_thermal: gpu0-thermal {
262 /* milliseconds */ 235 /* milliseconds */
263 polling-delay-passive 236 polling-delay-passive = <0>;
264 polling-delay = <0>; 237 polling-delay = <0>;
265 thermal-sensors = <&th 238 thermal-sensors = <&ths 1>;
266 <<
267 trips { <<
268 gpu0_crit: gpu <<
269 temper <<
270 hyster <<
271 type = <<
272 }; <<
273 }; <<
274 }; 239 };
275 240
276 gpu1_thermal: gpu1-thermal { 241 gpu1_thermal: gpu1-thermal {
277 /* milliseconds */ 242 /* milliseconds */
278 polling-delay-passive 243 polling-delay-passive = <0>;
279 polling-delay = <0>; 244 polling-delay = <0>;
280 thermal-sensors = <&th 245 thermal-sensors = <&ths 2>;
281 <<
282 trips { <<
283 gpu1_crit: gpu <<
284 temper <<
285 hyster <<
286 type = <<
287 }; <<
288 }; <<
289 }; 246 };
290 }; 247 };
291 248
292 soc { 249 soc {
293 compatible = "simple-bus"; 250 compatible = "simple-bus";
294 #address-cells = <1>; 251 #address-cells = <1>;
295 #size-cells = <1>; 252 #size-cells = <1>;
296 ranges; 253 ranges;
297 254
298 bus@1000000 { 255 bus@1000000 {
299 compatible = "allwinne 256 compatible = "allwinner,sun50i-a64-de2";
300 reg = <0x1000000 0x400 257 reg = <0x1000000 0x400000>;
301 allwinner,sram = <&de2 258 allwinner,sram = <&de2_sram 1>;
302 #address-cells = <1>; 259 #address-cells = <1>;
303 #size-cells = <1>; 260 #size-cells = <1>;
304 ranges = <0 0x1000000 261 ranges = <0 0x1000000 0x400000>;
305 262
306 display_clocks: clock@ 263 display_clocks: clock@0 {
307 compatible = " 264 compatible = "allwinner,sun50i-a64-de2-clk";
308 reg = <0x0 0x1 265 reg = <0x0 0x10000>;
309 clocks = <&ccu 266 clocks = <&ccu CLK_BUS_DE>,
310 <&ccu 267 <&ccu CLK_DE>;
311 clock-names = 268 clock-names = "bus",
312 269 "mod";
313 resets = <&ccu 270 resets = <&ccu RST_BUS_DE>;
314 #clock-cells = 271 #clock-cells = <1>;
315 #reset-cells = 272 #reset-cells = <1>;
316 }; 273 };
317 274
318 rotate: rotate@20000 { 275 rotate: rotate@20000 {
319 compatible = " 276 compatible = "allwinner,sun50i-a64-de2-rotate",
320 " 277 "allwinner,sun8i-a83t-de2-rotate";
321 reg = <0x20000 278 reg = <0x20000 0x10000>;
322 interrupts = < 279 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&dis 280 clocks = <&display_clocks CLK_BUS_ROT>,
324 <&dis 281 <&display_clocks CLK_ROT>;
325 clock-names = 282 clock-names = "bus",
326 283 "mod";
327 resets = <&dis 284 resets = <&display_clocks RST_ROT>;
328 }; 285 };
329 286
330 mixer0: mixer@100000 { 287 mixer0: mixer@100000 {
331 compatible = " 288 compatible = "allwinner,sun50i-a64-de2-mixer-0";
332 reg = <0x10000 289 reg = <0x100000 0x100000>;
333 clocks = <&dis 290 clocks = <&display_clocks CLK_BUS_MIXER0>,
334 <&dis 291 <&display_clocks CLK_MIXER0>;
335 clock-names = 292 clock-names = "bus",
336 293 "mod";
337 resets = <&dis 294 resets = <&display_clocks RST_MIXER0>;
338 295
339 ports { 296 ports {
340 #addre 297 #address-cells = <1>;
341 #size- 298 #size-cells = <0>;
342 299
343 mixer0 300 mixer0_out: port@1 {
344 301 #address-cells = <1>;
345 302 #size-cells = <0>;
346 303 reg = <1>;
347 304
348 305 mixer0_out_tcon0: endpoint@0 {
349 306 reg = <0>;
350 307 remote-endpoint = <&tcon0_in_mixer0>;
351 308 };
352 309
353 310 mixer0_out_tcon1: endpoint@1 {
354 311 reg = <1>;
355 312 remote-endpoint = <&tcon1_in_mixer0>;
356 313 };
357 }; 314 };
358 }; 315 };
359 }; 316 };
360 317
361 mixer1: mixer@200000 { 318 mixer1: mixer@200000 {
362 compatible = " 319 compatible = "allwinner,sun50i-a64-de2-mixer-1";
363 reg = <0x20000 320 reg = <0x200000 0x100000>;
364 clocks = <&dis 321 clocks = <&display_clocks CLK_BUS_MIXER1>,
365 <&dis 322 <&display_clocks CLK_MIXER1>;
366 clock-names = 323 clock-names = "bus",
367 324 "mod";
368 resets = <&dis 325 resets = <&display_clocks RST_MIXER1>;
369 326
370 ports { 327 ports {
371 #addre 328 #address-cells = <1>;
372 #size- 329 #size-cells = <0>;
373 330
374 mixer1 331 mixer1_out: port@1 {
375 332 #address-cells = <1>;
376 333 #size-cells = <0>;
377 334 reg = <1>;
378 335
379 336 mixer1_out_tcon0: endpoint@0 {
380 337 reg = <0>;
381 338 remote-endpoint = <&tcon0_in_mixer1>;
382 339 };
383 340
384 341 mixer1_out_tcon1: endpoint@1 {
385 342 reg = <1>;
386 343 remote-endpoint = <&tcon1_in_mixer1>;
387 344 };
388 }; 345 };
389 }; 346 };
390 }; 347 };
391 }; 348 };
392 349
393 syscon: syscon@1c00000 { 350 syscon: syscon@1c00000 {
394 compatible = "allwinne 351 compatible = "allwinner,sun50i-a64-system-control";
395 reg = <0x01c00000 0x10 352 reg = <0x01c00000 0x1000>;
396 #address-cells = <1>; 353 #address-cells = <1>;
397 #size-cells = <1>; 354 #size-cells = <1>;
398 ranges; 355 ranges;
399 356
400 sram_c: sram@18000 { 357 sram_c: sram@18000 {
401 compatible = " 358 compatible = "mmio-sram";
402 reg = <0x00018 359 reg = <0x00018000 0x28000>;
403 #address-cells 360 #address-cells = <1>;
404 #size-cells = 361 #size-cells = <1>;
405 ranges = <0 0x 362 ranges = <0 0x00018000 0x28000>;
406 363
407 de2_sram: sram 364 de2_sram: sram-section@0 {
408 compat 365 compatible = "allwinner,sun50i-a64-sram-c";
409 reg = 366 reg = <0x0000 0x28000>;
410 }; 367 };
411 }; 368 };
412 369
413 sram_c1: sram@1d00000 370 sram_c1: sram@1d00000 {
414 compatible = " 371 compatible = "mmio-sram";
415 reg = <0x01d00 372 reg = <0x01d00000 0x40000>;
416 #address-cells 373 #address-cells = <1>;
417 #size-cells = 374 #size-cells = <1>;
418 ranges = <0 0x 375 ranges = <0 0x01d00000 0x40000>;
419 376
420 ve_sram: sram- 377 ve_sram: sram-section@0 {
421 compat 378 compatible = "allwinner,sun50i-a64-sram-c1",
422 379 "allwinner,sun4i-a10-sram-c1";
423 reg = 380 reg = <0x000000 0x40000>;
424 }; 381 };
425 }; 382 };
426 }; 383 };
427 384
428 dma: dma-controller@1c02000 { 385 dma: dma-controller@1c02000 {
429 compatible = "allwinne 386 compatible = "allwinner,sun50i-a64-dma";
430 reg = <0x01c02000 0x10 387 reg = <0x01c02000 0x1000>;
431 interrupts = <GIC_SPI 388 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&ccu CLK_BUS 389 clocks = <&ccu CLK_BUS_DMA>;
433 dma-channels = <8>; 390 dma-channels = <8>;
434 dma-requests = <27>; 391 dma-requests = <27>;
435 resets = <&ccu RST_BUS 392 resets = <&ccu RST_BUS_DMA>;
436 #dma-cells = <1>; 393 #dma-cells = <1>;
437 }; 394 };
438 395
439 tcon0: lcd-controller@1c0c000 396 tcon0: lcd-controller@1c0c000 {
440 compatible = "allwinne 397 compatible = "allwinner,sun50i-a64-tcon-lcd",
441 "allwinne 398 "allwinner,sun8i-a83t-tcon-lcd";
442 reg = <0x01c0c000 0x10 399 reg = <0x01c0c000 0x1000>;
443 interrupts = <GIC_SPI 400 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
444 clocks = <&ccu CLK_BUS 401 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
445 clock-names = "ahb", " 402 clock-names = "ahb", "tcon-ch0";
446 clock-output-names = " 403 clock-output-names = "tcon-data-clock";
447 #clock-cells = <0>; 404 #clock-cells = <0>;
448 resets = <&ccu RST_BUS 405 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
449 reset-names = "lcd", " 406 reset-names = "lcd", "lvds";
450 407
451 ports { 408 ports {
452 #address-cells 409 #address-cells = <1>;
453 #size-cells = 410 #size-cells = <0>;
454 411
455 tcon0_in: port 412 tcon0_in: port@0 {
456 #addre 413 #address-cells = <1>;
457 #size- 414 #size-cells = <0>;
458 reg = 415 reg = <0>;
459 416
460 tcon0_ 417 tcon0_in_mixer0: endpoint@0 {
461 418 reg = <0>;
462 419 remote-endpoint = <&mixer0_out_tcon0>;
463 }; 420 };
464 421
465 tcon0_ 422 tcon0_in_mixer1: endpoint@1 {
466 423 reg = <1>;
467 424 remote-endpoint = <&mixer1_out_tcon0>;
468 }; 425 };
469 }; 426 };
470 427
471 tcon0_out: por 428 tcon0_out: port@1 {
472 #addre 429 #address-cells = <1>;
473 #size- 430 #size-cells = <0>;
474 reg = 431 reg = <1>;
475 432
476 tcon0_ 433 tcon0_out_dsi: endpoint@1 {
477 434 reg = <1>;
478 435 remote-endpoint = <&dsi_in_tcon0>;
479 436 allwinner,tcon-channel = <1>;
480 }; 437 };
481 }; 438 };
482 }; 439 };
483 }; 440 };
484 441
485 tcon1: lcd-controller@1c0d000 442 tcon1: lcd-controller@1c0d000 {
486 compatible = "allwinne 443 compatible = "allwinner,sun50i-a64-tcon-tv",
487 "allwinne 444 "allwinner,sun8i-a83t-tcon-tv";
488 reg = <0x01c0d000 0x10 445 reg = <0x01c0d000 0x1000>;
489 interrupts = <GIC_SPI 446 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&ccu CLK_BUS 447 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
491 clock-names = "ahb", " 448 clock-names = "ahb", "tcon-ch1";
492 resets = <&ccu RST_BUS 449 resets = <&ccu RST_BUS_TCON1>;
493 reset-names = "lcd"; 450 reset-names = "lcd";
494 451
495 ports { 452 ports {
496 #address-cells 453 #address-cells = <1>;
497 #size-cells = 454 #size-cells = <0>;
498 455
499 tcon1_in: port 456 tcon1_in: port@0 {
500 #addre 457 #address-cells = <1>;
501 #size- 458 #size-cells = <0>;
502 reg = 459 reg = <0>;
503 460
504 tcon1_ 461 tcon1_in_mixer0: endpoint@0 {
505 462 reg = <0>;
506 463 remote-endpoint = <&mixer0_out_tcon1>;
507 }; 464 };
508 465
509 tcon1_ 466 tcon1_in_mixer1: endpoint@1 {
510 467 reg = <1>;
511 468 remote-endpoint = <&mixer1_out_tcon1>;
512 }; 469 };
513 }; 470 };
514 471
515 tcon1_out: por 472 tcon1_out: port@1 {
516 #addre 473 #address-cells = <1>;
517 #size- 474 #size-cells = <0>;
518 reg = 475 reg = <1>;
519 476
520 tcon1_ 477 tcon1_out_hdmi: endpoint@1 {
521 478 reg = <1>;
522 479 remote-endpoint = <&hdmi_in_tcon1>;
523 }; 480 };
524 }; 481 };
525 }; 482 };
526 }; 483 };
527 484
528 video-codec@1c0e000 { 485 video-codec@1c0e000 {
529 compatible = "allwinne 486 compatible = "allwinner,sun50i-a64-video-engine";
530 reg = <0x01c0e000 0x10 487 reg = <0x01c0e000 0x1000>;
531 clocks = <&ccu CLK_BUS 488 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
532 <&ccu CLK_DRA 489 <&ccu CLK_DRAM_VE>;
533 clock-names = "ahb", " 490 clock-names = "ahb", "mod", "ram";
534 resets = <&ccu RST_BUS 491 resets = <&ccu RST_BUS_VE>;
535 interrupts = <GIC_SPI 492 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
536 allwinner,sram = <&ve_ 493 allwinner,sram = <&ve_sram 1>;
537 }; 494 };
538 495
539 mmc0: mmc@1c0f000 { 496 mmc0: mmc@1c0f000 {
540 compatible = "allwinne 497 compatible = "allwinner,sun50i-a64-mmc";
541 reg = <0x01c0f000 0x10 498 reg = <0x01c0f000 0x1000>;
542 clocks = <&ccu CLK_BUS 499 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
543 clock-names = "ahb", " 500 clock-names = "ahb", "mmc";
544 resets = <&ccu RST_BUS 501 resets = <&ccu RST_BUS_MMC0>;
545 reset-names = "ahb"; 502 reset-names = "ahb";
546 interrupts = <GIC_SPI 503 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
547 max-frequency = <15000 504 max-frequency = <150000000>;
548 status = "disabled"; 505 status = "disabled";
549 #address-cells = <1>; 506 #address-cells = <1>;
550 #size-cells = <0>; 507 #size-cells = <0>;
551 }; 508 };
552 509
553 mmc1: mmc@1c10000 { 510 mmc1: mmc@1c10000 {
554 compatible = "allwinne 511 compatible = "allwinner,sun50i-a64-mmc";
555 reg = <0x01c10000 0x10 512 reg = <0x01c10000 0x1000>;
556 clocks = <&ccu CLK_BUS 513 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
557 clock-names = "ahb", " 514 clock-names = "ahb", "mmc";
558 resets = <&ccu RST_BUS 515 resets = <&ccu RST_BUS_MMC1>;
559 reset-names = "ahb"; 516 reset-names = "ahb";
560 interrupts = <GIC_SPI 517 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
561 max-frequency = <15000 518 max-frequency = <150000000>;
562 status = "disabled"; 519 status = "disabled";
563 #address-cells = <1>; 520 #address-cells = <1>;
564 #size-cells = <0>; 521 #size-cells = <0>;
565 }; 522 };
566 523
567 mmc2: mmc@1c11000 { 524 mmc2: mmc@1c11000 {
568 compatible = "allwinne 525 compatible = "allwinner,sun50i-a64-emmc";
569 reg = <0x01c11000 0x10 526 reg = <0x01c11000 0x1000>;
570 clocks = <&ccu CLK_BUS 527 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
571 clock-names = "ahb", " 528 clock-names = "ahb", "mmc";
572 resets = <&ccu RST_BUS 529 resets = <&ccu RST_BUS_MMC2>;
573 reset-names = "ahb"; 530 reset-names = "ahb";
574 interrupts = <GIC_SPI 531 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
575 max-frequency = <15000 532 max-frequency = <150000000>;
576 status = "disabled"; 533 status = "disabled";
577 #address-cells = <1>; 534 #address-cells = <1>;
578 #size-cells = <0>; 535 #size-cells = <0>;
579 }; 536 };
580 537
581 sid: eeprom@1c14000 { 538 sid: eeprom@1c14000 {
582 compatible = "allwinne 539 compatible = "allwinner,sun50i-a64-sid";
583 reg = <0x1c14000 0x400 540 reg = <0x1c14000 0x400>;
584 #address-cells = <1>; 541 #address-cells = <1>;
585 #size-cells = <1>; 542 #size-cells = <1>;
586 543
587 ths_calibration: therm 544 ths_calibration: thermal-sensor-calibration@34 {
588 reg = <0x34 0x 545 reg = <0x34 0x8>;
589 }; 546 };
590 }; 547 };
591 548
592 crypto: crypto@1c15000 { 549 crypto: crypto@1c15000 {
593 compatible = "allwinne 550 compatible = "allwinner,sun50i-a64-crypto";
594 reg = <0x01c15000 0x10 551 reg = <0x01c15000 0x1000>;
595 interrupts = <GIC_SPI 552 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
596 clocks = <&ccu CLK_BUS 553 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
597 clock-names = "bus", " 554 clock-names = "bus", "mod";
598 resets = <&ccu RST_BUS 555 resets = <&ccu RST_BUS_CE>;
599 }; 556 };
600 557
601 msgbox: mailbox@1c17000 { 558 msgbox: mailbox@1c17000 {
602 compatible = "allwinne 559 compatible = "allwinner,sun50i-a64-msgbox",
603 "allwinne 560 "allwinner,sun6i-a31-msgbox";
604 reg = <0x01c17000 0x10 561 reg = <0x01c17000 0x1000>;
605 clocks = <&ccu CLK_BUS 562 clocks = <&ccu CLK_BUS_MSGBOX>;
606 resets = <&ccu RST_BUS 563 resets = <&ccu RST_BUS_MSGBOX>;
607 interrupts = <GIC_SPI 564 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
608 #mbox-cells = <1>; 565 #mbox-cells = <1>;
609 }; 566 };
610 567
611 usb_otg: usb@1c19000 { 568 usb_otg: usb@1c19000 {
612 compatible = "allwinne 569 compatible = "allwinner,sun8i-a33-musb";
613 reg = <0x01c19000 0x04 570 reg = <0x01c19000 0x0400>;
614 clocks = <&ccu CLK_BUS 571 clocks = <&ccu CLK_BUS_OTG>;
615 resets = <&ccu RST_BUS 572 resets = <&ccu RST_BUS_OTG>;
616 interrupts = <GIC_SPI 573 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
617 interrupt-names = "mc" 574 interrupt-names = "mc";
618 phys = <&usbphy 0>; 575 phys = <&usbphy 0>;
619 phy-names = "usb"; 576 phy-names = "usb";
620 extcon = <&usbphy 0>; 577 extcon = <&usbphy 0>;
621 dr_mode = "otg"; 578 dr_mode = "otg";
622 status = "disabled"; 579 status = "disabled";
623 }; 580 };
624 581
625 usbphy: phy@1c19400 { 582 usbphy: phy@1c19400 {
626 compatible = "allwinne 583 compatible = "allwinner,sun50i-a64-usb-phy";
627 reg = <0x01c19400 0x14 584 reg = <0x01c19400 0x14>,
628 <0x01c1a800 0x4> 585 <0x01c1a800 0x4>,
629 <0x01c1b800 0x4> 586 <0x01c1b800 0x4>;
630 reg-names = "phy_ctrl" 587 reg-names = "phy_ctrl",
631 "pmu0", 588 "pmu0",
632 "pmu1"; 589 "pmu1";
633 clocks = <&ccu CLK_USB 590 clocks = <&ccu CLK_USB_PHY0>,
634 <&ccu CLK_USB 591 <&ccu CLK_USB_PHY1>;
635 clock-names = "usb0_ph 592 clock-names = "usb0_phy",
636 "usb1_ph 593 "usb1_phy";
637 resets = <&ccu RST_USB 594 resets = <&ccu RST_USB_PHY0>,
638 <&ccu RST_USB 595 <&ccu RST_USB_PHY1>;
639 reset-names = "usb0_re 596 reset-names = "usb0_reset",
640 "usb1_re 597 "usb1_reset";
641 status = "disabled"; 598 status = "disabled";
642 #phy-cells = <1>; 599 #phy-cells = <1>;
643 }; 600 };
644 601
645 ehci0: usb@1c1a000 { 602 ehci0: usb@1c1a000 {
646 compatible = "allwinne 603 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
647 reg = <0x01c1a000 0x10 604 reg = <0x01c1a000 0x100>;
648 interrupts = <GIC_SPI 605 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
649 clocks = <&ccu CLK_BUS 606 clocks = <&ccu CLK_BUS_OHCI0>,
650 <&ccu CLK_BUS 607 <&ccu CLK_BUS_EHCI0>,
651 <&ccu CLK_USB 608 <&ccu CLK_USB_OHCI0>;
652 resets = <&ccu RST_BUS 609 resets = <&ccu RST_BUS_OHCI0>,
653 <&ccu RST_BUS 610 <&ccu RST_BUS_EHCI0>;
654 phys = <&usbphy 0>; 611 phys = <&usbphy 0>;
655 phy-names = "usb"; 612 phy-names = "usb";
656 status = "disabled"; 613 status = "disabled";
657 }; 614 };
658 615
659 ohci0: usb@1c1a400 { 616 ohci0: usb@1c1a400 {
660 compatible = "allwinne 617 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
661 reg = <0x01c1a400 0x10 618 reg = <0x01c1a400 0x100>;
662 interrupts = <GIC_SPI 619 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
663 clocks = <&ccu CLK_BUS 620 clocks = <&ccu CLK_BUS_OHCI0>,
664 <&ccu CLK_USB 621 <&ccu CLK_USB_OHCI0>;
665 resets = <&ccu RST_BUS 622 resets = <&ccu RST_BUS_OHCI0>;
666 phys = <&usbphy 0>; 623 phys = <&usbphy 0>;
667 phy-names = "usb"; 624 phy-names = "usb";
668 status = "disabled"; 625 status = "disabled";
669 }; 626 };
670 627
671 ehci1: usb@1c1b000 { 628 ehci1: usb@1c1b000 {
672 compatible = "allwinne 629 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
673 reg = <0x01c1b000 0x10 630 reg = <0x01c1b000 0x100>;
674 interrupts = <GIC_SPI 631 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
675 clocks = <&ccu CLK_BUS 632 clocks = <&ccu CLK_BUS_OHCI1>,
676 <&ccu CLK_BUS 633 <&ccu CLK_BUS_EHCI1>,
677 <&ccu CLK_USB 634 <&ccu CLK_USB_OHCI1>;
678 resets = <&ccu RST_BUS 635 resets = <&ccu RST_BUS_OHCI1>,
679 <&ccu RST_BUS 636 <&ccu RST_BUS_EHCI1>;
680 phys = <&usbphy 1>; 637 phys = <&usbphy 1>;
681 phy-names = "usb"; 638 phy-names = "usb";
682 status = "disabled"; 639 status = "disabled";
683 }; 640 };
684 641
685 ohci1: usb@1c1b400 { 642 ohci1: usb@1c1b400 {
686 compatible = "allwinne 643 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
687 reg = <0x01c1b400 0x10 644 reg = <0x01c1b400 0x100>;
688 interrupts = <GIC_SPI 645 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
689 clocks = <&ccu CLK_BUS 646 clocks = <&ccu CLK_BUS_OHCI1>,
690 <&ccu CLK_USB 647 <&ccu CLK_USB_OHCI1>;
691 resets = <&ccu RST_BUS 648 resets = <&ccu RST_BUS_OHCI1>;
692 phys = <&usbphy 1>; 649 phys = <&usbphy 1>;
693 phy-names = "usb"; 650 phy-names = "usb";
694 status = "disabled"; 651 status = "disabled";
695 }; 652 };
696 653
697 ccu: clock@1c20000 { 654 ccu: clock@1c20000 {
698 compatible = "allwinne 655 compatible = "allwinner,sun50i-a64-ccu";
699 reg = <0x01c20000 0x40 656 reg = <0x01c20000 0x400>;
700 clocks = <&osc24M>, <& 657 clocks = <&osc24M>, <&rtc CLK_OSC32K>;
701 clock-names = "hosc", 658 clock-names = "hosc", "losc";
702 #clock-cells = <1>; 659 #clock-cells = <1>;
703 #reset-cells = <1>; 660 #reset-cells = <1>;
704 }; 661 };
705 662
706 pio: pinctrl@1c20800 { 663 pio: pinctrl@1c20800 {
707 compatible = "allwinne 664 compatible = "allwinner,sun50i-a64-pinctrl";
708 reg = <0x01c20800 0x40 665 reg = <0x01c20800 0x400>;
709 interrupt-parent = <&r 666 interrupt-parent = <&r_intc>;
710 interrupts = <GIC_SPI 667 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
711 <GIC_SPI 668 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
712 <GIC_SPI 669 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&ccu CLK_BUS 670 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
714 <&rtc CLK_OSC 671 <&rtc CLK_OSC32K>;
715 clock-names = "apb", " 672 clock-names = "apb", "hosc", "losc";
716 gpio-controller; 673 gpio-controller;
717 #gpio-cells = <3>; 674 #gpio-cells = <3>;
718 interrupt-controller; 675 interrupt-controller;
719 #interrupt-cells = <3> 676 #interrupt-cells = <3>;
720 677
721 /omit-if-no-ref/ 678 /omit-if-no-ref/
722 aif2_pins: aif2-pins { 679 aif2_pins: aif2-pins {
723 pins = "PB4", 680 pins = "PB4", "PB5", "PB6", "PB7";
724 function = "ai 681 function = "aif2";
725 }; 682 };
726 683
727 /omit-if-no-ref/ 684 /omit-if-no-ref/
728 aif3_pins: aif3-pins { 685 aif3_pins: aif3-pins {
729 pins = "PG10", 686 pins = "PG10", "PG11", "PG12", "PG13";
730 function = "ai 687 function = "aif3";
731 }; 688 };
732 689
733 csi_pins: csi-pins { 690 csi_pins: csi-pins {
734 pins = "PE0", 691 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
735 "PE7", 692 "PE7", "PE8", "PE9", "PE10", "PE11";
736 function = "cs 693 function = "csi";
737 }; 694 };
738 695
739 /omit-if-no-ref/ 696 /omit-if-no-ref/
740 csi_mclk_pin: csi-mclk 697 csi_mclk_pin: csi-mclk-pin {
741 pins = "PE1"; 698 pins = "PE1";
742 function = "cs 699 function = "csi";
743 }; 700 };
744 701
745 i2c0_pins: i2c0-pins { 702 i2c0_pins: i2c0-pins {
746 pins = "PH0", 703 pins = "PH0", "PH1";
747 function = "i2 704 function = "i2c0";
748 }; 705 };
749 706
750 i2c1_pins: i2c1-pins { 707 i2c1_pins: i2c1-pins {
751 pins = "PH2", 708 pins = "PH2", "PH3";
752 function = "i2 709 function = "i2c1";
753 }; 710 };
754 711
755 i2c2_pins: i2c2-pins { 712 i2c2_pins: i2c2-pins {
756 pins = "PE14", 713 pins = "PE14", "PE15";
757 function = "i2 714 function = "i2c2";
758 }; 715 };
759 716
760 /omit-if-no-ref/ 717 /omit-if-no-ref/
761 lcd_rgb666_pins: lcd-r 718 lcd_rgb666_pins: lcd-rgb666-pins {
762 pins = "PD0", 719 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
763 "PD5", 720 "PD5", "PD6", "PD7", "PD8", "PD9",
764 "PD10", 721 "PD10", "PD11", "PD12", "PD13",
765 "PD14", 722 "PD14", "PD15", "PD16", "PD17",
766 "PD18", 723 "PD18", "PD19", "PD20", "PD21";
767 function = "lc 724 function = "lcd0";
768 }; 725 };
769 726
770 mmc0_pins: mmc0-pins { 727 mmc0_pins: mmc0-pins {
771 pins = "PF0", 728 pins = "PF0", "PF1", "PF2", "PF3",
772 "PF4", 729 "PF4", "PF5";
773 function = "mm 730 function = "mmc0";
774 drive-strength 731 drive-strength = <30>;
775 bias-pull-up; 732 bias-pull-up;
776 }; 733 };
777 734
778 mmc1_pins: mmc1-pins { 735 mmc1_pins: mmc1-pins {
779 pins = "PG0", 736 pins = "PG0", "PG1", "PG2", "PG3",
780 "PG4", 737 "PG4", "PG5";
781 function = "mm 738 function = "mmc1";
782 drive-strength 739 drive-strength = <30>;
783 bias-pull-up; 740 bias-pull-up;
784 }; 741 };
785 742
786 mmc2_pins: mmc2-pins { 743 mmc2_pins: mmc2-pins {
787 pins = "PC5", 744 pins = "PC5", "PC6", "PC8", "PC9",
788 "PC10", 745 "PC10","PC11", "PC12", "PC13",
789 "PC14", 746 "PC14", "PC15", "PC16";
790 function = "mm 747 function = "mmc2";
791 drive-strength 748 drive-strength = <30>;
792 bias-pull-up; 749 bias-pull-up;
793 }; 750 };
794 751
795 mmc2_ds_pin: mmc2-ds-p 752 mmc2_ds_pin: mmc2-ds-pin {
796 pins = "PC1"; 753 pins = "PC1";
797 function = "mm 754 function = "mmc2";
798 drive-strength 755 drive-strength = <30>;
799 bias-pull-up; 756 bias-pull-up;
800 }; 757 };
801 758
802 pwm_pin: pwm-pin { 759 pwm_pin: pwm-pin {
803 pins = "PD22"; 760 pins = "PD22";
804 function = "pw 761 function = "pwm";
805 }; 762 };
806 763
807 rmii_pins: rmii-pins { 764 rmii_pins: rmii-pins {
808 pins = "PD10", 765 pins = "PD10", "PD11", "PD13", "PD14", "PD17",
809 "PD18", 766 "PD18", "PD19", "PD20", "PD22", "PD23";
810 function = "em 767 function = "emac";
811 drive-strength 768 drive-strength = <40>;
812 }; 769 };
813 770
814 rgmii_pins: rgmii-pins 771 rgmii_pins: rgmii-pins {
815 pins = "PD8", 772 pins = "PD8", "PD9", "PD10", "PD11", "PD12",
816 "PD13", 773 "PD13", "PD15", "PD16", "PD17", "PD18",
817 "PD19", 774 "PD19", "PD20", "PD21", "PD22", "PD23";
818 function = "em 775 function = "emac";
819 drive-strength 776 drive-strength = <40>;
820 }; 777 };
821 778
822 spdif_tx_pin: spdif-tx 779 spdif_tx_pin: spdif-tx-pin {
823 pins = "PH8"; 780 pins = "PH8";
824 function = "sp 781 function = "spdif";
825 }; 782 };
826 783
827 spi0_pins: spi0-pins { 784 spi0_pins: spi0-pins {
828 pins = "PC0", 785 pins = "PC0", "PC1", "PC2", "PC3";
829 function = "sp 786 function = "spi0";
830 }; 787 };
831 788
832 spi1_pins: spi1-pins { 789 spi1_pins: spi1-pins {
833 pins = "PD0", 790 pins = "PD0", "PD1", "PD2", "PD3";
834 function = "sp 791 function = "spi1";
835 }; 792 };
836 793
837 uart0_pb_pins: uart0-p 794 uart0_pb_pins: uart0-pb-pins {
838 pins = "PB8", 795 pins = "PB8", "PB9";
839 function = "ua 796 function = "uart0";
840 }; 797 };
841 798
842 uart1_pins: uart1-pins 799 uart1_pins: uart1-pins {
843 pins = "PG6", 800 pins = "PG6", "PG7";
844 function = "ua 801 function = "uart1";
845 }; 802 };
846 803
847 uart1_rts_cts_pins: ua 804 uart1_rts_cts_pins: uart1-rts-cts-pins {
848 pins = "PG8", 805 pins = "PG8", "PG9";
849 function = "ua 806 function = "uart1";
850 }; 807 };
851 808
852 uart2_pins: uart2-pins 809 uart2_pins: uart2-pins {
853 pins = "PB0", 810 pins = "PB0", "PB1";
854 function = "ua 811 function = "uart2";
855 }; 812 };
856 813
857 uart3_pins: uart3-pins 814 uart3_pins: uart3-pins {
858 pins = "PD0", 815 pins = "PD0", "PD1";
859 function = "ua 816 function = "uart3";
860 }; 817 };
861 818
862 uart4_pins: uart4-pins 819 uart4_pins: uart4-pins {
863 pins = "PD2", 820 pins = "PD2", "PD3";
864 function = "ua 821 function = "uart4";
865 }; 822 };
866 823
867 uart4_rts_cts_pins: ua 824 uart4_rts_cts_pins: uart4-rts-cts-pins {
868 pins = "PD4", 825 pins = "PD4", "PD5";
869 function = "ua 826 function = "uart4";
870 }; 827 };
871 }; 828 };
872 829
873 timer@1c20c00 { 830 timer@1c20c00 {
874 compatible = "allwinne 831 compatible = "allwinner,sun50i-a64-timer",
875 "allwinne 832 "allwinner,sun8i-a23-timer";
876 reg = <0x01c20c00 0xa0 833 reg = <0x01c20c00 0xa0>;
877 interrupts = <GIC_SPI 834 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
878 <GIC_SPI 835 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
879 clocks = <&osc24M>; 836 clocks = <&osc24M>;
880 }; 837 };
881 838
882 wdt0: watchdog@1c20ca0 { 839 wdt0: watchdog@1c20ca0 {
883 compatible = "allwinne 840 compatible = "allwinner,sun50i-a64-wdt",
884 "allwinne 841 "allwinner,sun6i-a31-wdt";
885 reg = <0x01c20ca0 0x20 842 reg = <0x01c20ca0 0x20>;
886 interrupts = <GIC_SPI 843 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
887 clocks = <&osc24M>; 844 clocks = <&osc24M>;
888 }; 845 };
889 846
890 spdif: spdif@1c21000 { 847 spdif: spdif@1c21000 {
891 #sound-dai-cells = <0> 848 #sound-dai-cells = <0>;
892 compatible = "allwinne 849 compatible = "allwinner,sun50i-a64-spdif",
893 "allwinne 850 "allwinner,sun8i-h3-spdif";
894 reg = <0x01c21000 0x40 851 reg = <0x01c21000 0x400>;
895 interrupts = <GIC_SPI 852 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
896 clocks = <&ccu CLK_BUS 853 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
897 resets = <&ccu RST_BUS 854 resets = <&ccu RST_BUS_SPDIF>;
898 clock-names = "apb", " 855 clock-names = "apb", "spdif";
899 dmas = <&dma 2>; 856 dmas = <&dma 2>;
900 dma-names = "tx"; 857 dma-names = "tx";
901 pinctrl-names = "defau 858 pinctrl-names = "default";
902 pinctrl-0 = <&spdif_tx 859 pinctrl-0 = <&spdif_tx_pin>;
903 status = "disabled"; 860 status = "disabled";
904 }; 861 };
905 862
906 lradc: lradc@1c21800 { 863 lradc: lradc@1c21800 {
907 compatible = "allwinne 864 compatible = "allwinner,sun50i-a64-lradc",
908 "allwinne 865 "allwinner,sun8i-a83t-r-lradc";
909 reg = <0x01c21800 0x40 866 reg = <0x01c21800 0x400>;
910 interrupt-parent = <&r 867 interrupt-parent = <&r_intc>;
911 interrupts = <GIC_SPI 868 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
912 status = "disabled"; 869 status = "disabled";
913 }; 870 };
914 871
915 i2s0: i2s@1c22000 { 872 i2s0: i2s@1c22000 {
916 #sound-dai-cells = <0> 873 #sound-dai-cells = <0>;
917 compatible = "allwinne 874 compatible = "allwinner,sun50i-a64-i2s",
918 "allwinne 875 "allwinner,sun8i-h3-i2s";
919 reg = <0x01c22000 0x40 876 reg = <0x01c22000 0x400>;
920 interrupts = <GIC_SPI 877 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
921 clocks = <&ccu CLK_BUS 878 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
922 clock-names = "apb", " 879 clock-names = "apb", "mod";
923 resets = <&ccu RST_BUS 880 resets = <&ccu RST_BUS_I2S0>;
924 dma-names = "rx", "tx" 881 dma-names = "rx", "tx";
925 dmas = <&dma 3>, <&dma 882 dmas = <&dma 3>, <&dma 3>;
926 status = "disabled"; 883 status = "disabled";
927 }; 884 };
928 885
929 i2s1: i2s@1c22400 { 886 i2s1: i2s@1c22400 {
930 #sound-dai-cells = <0> 887 #sound-dai-cells = <0>;
931 compatible = "allwinne 888 compatible = "allwinner,sun50i-a64-i2s",
932 "allwinne 889 "allwinner,sun8i-h3-i2s";
933 reg = <0x01c22400 0x40 890 reg = <0x01c22400 0x400>;
934 interrupts = <GIC_SPI 891 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
935 clocks = <&ccu CLK_BUS 892 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
936 clock-names = "apb", " 893 clock-names = "apb", "mod";
937 resets = <&ccu RST_BUS 894 resets = <&ccu RST_BUS_I2S1>;
938 dma-names = "rx", "tx" 895 dma-names = "rx", "tx";
939 dmas = <&dma 4>, <&dma 896 dmas = <&dma 4>, <&dma 4>;
940 status = "disabled"; 897 status = "disabled";
941 }; 898 };
942 899
943 i2s2: i2s@1c22800 { 900 i2s2: i2s@1c22800 {
944 #sound-dai-cells = <0> 901 #sound-dai-cells = <0>;
945 compatible = "allwinne 902 compatible = "allwinner,sun50i-a64-i2s",
946 "allwinne 903 "allwinner,sun8i-h3-i2s";
947 reg = <0x01c22800 0x40 904 reg = <0x01c22800 0x400>;
948 interrupts = <GIC_SPI 905 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
949 clocks = <&ccu CLK_BUS 906 clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
950 clock-names = "apb", " 907 clock-names = "apb", "mod";
951 resets = <&ccu RST_BUS 908 resets = <&ccu RST_BUS_I2S2>;
952 dma-names = "rx", "tx" 909 dma-names = "rx", "tx";
953 dmas = <&dma 27>, <&dm 910 dmas = <&dma 27>, <&dma 27>;
954 status = "disabled"; 911 status = "disabled";
955 }; 912 };
956 913
957 dai: dai@1c22c00 { 914 dai: dai@1c22c00 {
958 #sound-dai-cells = <0> 915 #sound-dai-cells = <0>;
959 compatible = "allwinne 916 compatible = "allwinner,sun50i-a64-codec-i2s";
960 reg = <0x01c22c00 0x20 917 reg = <0x01c22c00 0x200>;
961 interrupts = <GIC_SPI 918 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
962 clocks = <&ccu CLK_BUS 919 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
963 clock-names = "apb", " 920 clock-names = "apb", "mod";
964 resets = <&ccu RST_BUS 921 resets = <&ccu RST_BUS_CODEC>;
965 dmas = <&dma 15>, <&dm 922 dmas = <&dma 15>, <&dma 15>;
966 dma-names = "rx", "tx" 923 dma-names = "rx", "tx";
967 status = "disabled"; 924 status = "disabled";
968 }; 925 };
969 926
970 codec: codec@1c22e00 { 927 codec: codec@1c22e00 {
971 #sound-dai-cells = <1> 928 #sound-dai-cells = <1>;
972 compatible = "allwinne 929 compatible = "allwinner,sun50i-a64-codec",
973 "allwinne 930 "allwinner,sun8i-a33-codec";
974 reg = <0x01c22e00 0x60 931 reg = <0x01c22e00 0x600>;
975 interrupts = <GIC_SPI 932 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
976 clocks = <&ccu CLK_BUS 933 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
977 clock-names = "bus", " 934 clock-names = "bus", "mod";
978 status = "disabled"; 935 status = "disabled";
979 }; 936 };
980 937
981 ths: thermal-sensor@1c25000 { 938 ths: thermal-sensor@1c25000 {
982 compatible = "allwinne 939 compatible = "allwinner,sun50i-a64-ths";
983 reg = <0x01c25000 0x10 940 reg = <0x01c25000 0x100>;
984 clocks = <&ccu CLK_BUS 941 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
985 clock-names = "bus", " 942 clock-names = "bus", "mod";
986 interrupts = <GIC_SPI 943 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
987 resets = <&ccu RST_BUS 944 resets = <&ccu RST_BUS_THS>;
988 nvmem-cells = <&ths_ca 945 nvmem-cells = <&ths_calibration>;
989 nvmem-cell-names = "ca 946 nvmem-cell-names = "calibration";
990 #thermal-sensor-cells 947 #thermal-sensor-cells = <1>;
991 }; 948 };
992 949
993 uart0: serial@1c28000 { 950 uart0: serial@1c28000 {
994 compatible = "snps,dw- 951 compatible = "snps,dw-apb-uart";
995 reg = <0x01c28000 0x40 952 reg = <0x01c28000 0x400>;
996 interrupts = <GIC_SPI 953 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
997 reg-shift = <2>; 954 reg-shift = <2>;
998 reg-io-width = <4>; 955 reg-io-width = <4>;
999 clocks = <&ccu CLK_BUS 956 clocks = <&ccu CLK_BUS_UART0>;
1000 resets = <&ccu RST_BU 957 resets = <&ccu RST_BUS_UART0>;
1001 status = "disabled"; 958 status = "disabled";
1002 }; 959 };
1003 960
1004 uart1: serial@1c28400 { 961 uart1: serial@1c28400 {
1005 compatible = "snps,dw 962 compatible = "snps,dw-apb-uart";
1006 reg = <0x01c28400 0x4 963 reg = <0x01c28400 0x400>;
1007 interrupts = <GIC_SPI 964 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1008 reg-shift = <2>; 965 reg-shift = <2>;
1009 reg-io-width = <4>; 966 reg-io-width = <4>;
1010 clocks = <&ccu CLK_BU 967 clocks = <&ccu CLK_BUS_UART1>;
1011 resets = <&ccu RST_BU 968 resets = <&ccu RST_BUS_UART1>;
1012 status = "disabled"; 969 status = "disabled";
1013 }; 970 };
1014 971
1015 uart2: serial@1c28800 { 972 uart2: serial@1c28800 {
1016 compatible = "snps,dw 973 compatible = "snps,dw-apb-uart";
1017 reg = <0x01c28800 0x4 974 reg = <0x01c28800 0x400>;
1018 interrupts = <GIC_SPI 975 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1019 reg-shift = <2>; 976 reg-shift = <2>;
1020 reg-io-width = <4>; 977 reg-io-width = <4>;
1021 clocks = <&ccu CLK_BU 978 clocks = <&ccu CLK_BUS_UART2>;
1022 resets = <&ccu RST_BU 979 resets = <&ccu RST_BUS_UART2>;
1023 status = "disabled"; 980 status = "disabled";
1024 }; 981 };
1025 982
1026 uart3: serial@1c28c00 { 983 uart3: serial@1c28c00 {
1027 compatible = "snps,dw 984 compatible = "snps,dw-apb-uart";
1028 reg = <0x01c28c00 0x4 985 reg = <0x01c28c00 0x400>;
1029 interrupts = <GIC_SPI 986 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1030 reg-shift = <2>; 987 reg-shift = <2>;
1031 reg-io-width = <4>; 988 reg-io-width = <4>;
1032 clocks = <&ccu CLK_BU 989 clocks = <&ccu CLK_BUS_UART3>;
1033 resets = <&ccu RST_BU 990 resets = <&ccu RST_BUS_UART3>;
1034 status = "disabled"; 991 status = "disabled";
1035 }; 992 };
1036 993
1037 uart4: serial@1c29000 { 994 uart4: serial@1c29000 {
1038 compatible = "snps,dw 995 compatible = "snps,dw-apb-uart";
1039 reg = <0x01c29000 0x4 996 reg = <0x01c29000 0x400>;
1040 interrupts = <GIC_SPI 997 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1041 reg-shift = <2>; 998 reg-shift = <2>;
1042 reg-io-width = <4>; 999 reg-io-width = <4>;
1043 clocks = <&ccu CLK_BU 1000 clocks = <&ccu CLK_BUS_UART4>;
1044 resets = <&ccu RST_BU 1001 resets = <&ccu RST_BUS_UART4>;
1045 status = "disabled"; 1002 status = "disabled";
1046 }; 1003 };
1047 1004
1048 i2c0: i2c@1c2ac00 { 1005 i2c0: i2c@1c2ac00 {
1049 compatible = "allwinn 1006 compatible = "allwinner,sun6i-a31-i2c";
1050 reg = <0x01c2ac00 0x4 1007 reg = <0x01c2ac00 0x400>;
1051 interrupts = <GIC_SPI 1008 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1052 clocks = <&ccu CLK_BU 1009 clocks = <&ccu CLK_BUS_I2C0>;
1053 resets = <&ccu RST_BU 1010 resets = <&ccu RST_BUS_I2C0>;
1054 pinctrl-names = "defa 1011 pinctrl-names = "default";
1055 pinctrl-0 = <&i2c0_pi 1012 pinctrl-0 = <&i2c0_pins>;
1056 status = "disabled"; 1013 status = "disabled";
1057 #address-cells = <1>; 1014 #address-cells = <1>;
1058 #size-cells = <0>; 1015 #size-cells = <0>;
1059 }; 1016 };
1060 1017
1061 i2c1: i2c@1c2b000 { 1018 i2c1: i2c@1c2b000 {
1062 compatible = "allwinn 1019 compatible = "allwinner,sun6i-a31-i2c";
1063 reg = <0x01c2b000 0x4 1020 reg = <0x01c2b000 0x400>;
1064 interrupts = <GIC_SPI 1021 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1065 clocks = <&ccu CLK_BU 1022 clocks = <&ccu CLK_BUS_I2C1>;
1066 resets = <&ccu RST_BU 1023 resets = <&ccu RST_BUS_I2C1>;
1067 pinctrl-names = "defa 1024 pinctrl-names = "default";
1068 pinctrl-0 = <&i2c1_pi 1025 pinctrl-0 = <&i2c1_pins>;
1069 status = "disabled"; 1026 status = "disabled";
1070 #address-cells = <1>; 1027 #address-cells = <1>;
1071 #size-cells = <0>; 1028 #size-cells = <0>;
1072 }; 1029 };
1073 1030
1074 i2c2: i2c@1c2b400 { 1031 i2c2: i2c@1c2b400 {
1075 compatible = "allwinn 1032 compatible = "allwinner,sun6i-a31-i2c";
1076 reg = <0x01c2b400 0x4 1033 reg = <0x01c2b400 0x400>;
1077 interrupts = <GIC_SPI 1034 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1078 clocks = <&ccu CLK_BU 1035 clocks = <&ccu CLK_BUS_I2C2>;
1079 resets = <&ccu RST_BU 1036 resets = <&ccu RST_BUS_I2C2>;
1080 pinctrl-names = "defa 1037 pinctrl-names = "default";
1081 pinctrl-0 = <&i2c2_pi 1038 pinctrl-0 = <&i2c2_pins>;
1082 status = "disabled"; 1039 status = "disabled";
1083 #address-cells = <1>; 1040 #address-cells = <1>;
1084 #size-cells = <0>; 1041 #size-cells = <0>;
1085 }; 1042 };
1086 1043
1087 spi0: spi@1c68000 { 1044 spi0: spi@1c68000 {
1088 compatible = "allwinn 1045 compatible = "allwinner,sun8i-h3-spi";
1089 reg = <0x01c68000 0x1 1046 reg = <0x01c68000 0x1000>;
1090 interrupts = <GIC_SPI 1047 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1091 clocks = <&ccu CLK_BU 1048 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
1092 clock-names = "ahb", 1049 clock-names = "ahb", "mod";
1093 dmas = <&dma 23>, <&d 1050 dmas = <&dma 23>, <&dma 23>;
1094 dma-names = "rx", "tx 1051 dma-names = "rx", "tx";
1095 pinctrl-names = "defa 1052 pinctrl-names = "default";
1096 pinctrl-0 = <&spi0_pi 1053 pinctrl-0 = <&spi0_pins>;
1097 resets = <&ccu RST_BU 1054 resets = <&ccu RST_BUS_SPI0>;
1098 status = "disabled"; 1055 status = "disabled";
1099 num-cs = <1>; 1056 num-cs = <1>;
1100 #address-cells = <1>; 1057 #address-cells = <1>;
1101 #size-cells = <0>; 1058 #size-cells = <0>;
1102 }; 1059 };
1103 1060
1104 spi1: spi@1c69000 { 1061 spi1: spi@1c69000 {
1105 compatible = "allwinn 1062 compatible = "allwinner,sun8i-h3-spi";
1106 reg = <0x01c69000 0x1 1063 reg = <0x01c69000 0x1000>;
1107 interrupts = <GIC_SPI 1064 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1108 clocks = <&ccu CLK_BU 1065 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
1109 clock-names = "ahb", 1066 clock-names = "ahb", "mod";
1110 dmas = <&dma 24>, <&d 1067 dmas = <&dma 24>, <&dma 24>;
1111 dma-names = "rx", "tx 1068 dma-names = "rx", "tx";
1112 pinctrl-names = "defa 1069 pinctrl-names = "default";
1113 pinctrl-0 = <&spi1_pi 1070 pinctrl-0 = <&spi1_pins>;
1114 resets = <&ccu RST_BU 1071 resets = <&ccu RST_BUS_SPI1>;
1115 status = "disabled"; 1072 status = "disabled";
1116 num-cs = <1>; 1073 num-cs = <1>;
1117 #address-cells = <1>; 1074 #address-cells = <1>;
1118 #size-cells = <0>; 1075 #size-cells = <0>;
1119 }; 1076 };
1120 1077
1121 emac: ethernet@1c30000 { 1078 emac: ethernet@1c30000 {
1122 compatible = "allwinn 1079 compatible = "allwinner,sun50i-a64-emac";
1123 syscon = <&syscon>; 1080 syscon = <&syscon>;
1124 reg = <0x01c30000 0x1 1081 reg = <0x01c30000 0x10000>;
1125 interrupts = <GIC_SPI 1082 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1126 interrupt-names = "ma 1083 interrupt-names = "macirq";
1127 resets = <&ccu RST_BU 1084 resets = <&ccu RST_BUS_EMAC>;
1128 reset-names = "stmmac 1085 reset-names = "stmmaceth";
1129 clocks = <&ccu CLK_BU 1086 clocks = <&ccu CLK_BUS_EMAC>;
1130 clock-names = "stmmac 1087 clock-names = "stmmaceth";
1131 status = "disabled"; 1088 status = "disabled";
1132 1089
1133 mdio: mdio { 1090 mdio: mdio {
1134 compatible = 1091 compatible = "snps,dwmac-mdio";
1135 #address-cell 1092 #address-cells = <1>;
1136 #size-cells = 1093 #size-cells = <0>;
1137 }; 1094 };
1138 }; 1095 };
1139 1096
1140 mali: gpu@1c40000 { 1097 mali: gpu@1c40000 {
1141 compatible = "allwinn 1098 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400";
1142 reg = <0x01c40000 0x1 1099 reg = <0x01c40000 0x10000>;
1143 interrupts = <GIC_SPI 1100 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1144 <GIC_SPI 1101 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1145 <GIC_SPI 1102 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1146 <GIC_SPI 1103 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1147 <GIC_SPI 1104 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1148 <GIC_SPI 1105 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1149 <GIC_SPI 1106 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1150 interrupt-names = "gp 1107 interrupt-names = "gp",
1151 "gp 1108 "gpmmu",
1152 "pp 1109 "pp0",
1153 "pp 1110 "ppmmu0",
1154 "pp 1111 "pp1",
1155 "pp 1112 "ppmmu1",
1156 "pm 1113 "pmu";
1157 clocks = <&ccu CLK_BU 1114 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
1158 clock-names = "bus", 1115 clock-names = "bus", "core";
1159 resets = <&ccu RST_BU 1116 resets = <&ccu RST_BUS_GPU>;
1160 operating-points-v2 = 1117 operating-points-v2 = <&gpu_opp_table>;
1161 }; 1118 };
1162 1119
1163 gic: interrupt-controller@1c8 1120 gic: interrupt-controller@1c81000 {
1164 compatible = "arm,gic 1121 compatible = "arm,gic-400";
1165 reg = <0x01c81000 0x1 1122 reg = <0x01c81000 0x1000>,
1166 <0x01c82000 0x2 1123 <0x01c82000 0x2000>,
1167 <0x01c84000 0x2 1124 <0x01c84000 0x2000>,
1168 <0x01c86000 0x2 1125 <0x01c86000 0x2000>;
1169 interrupts = <GIC_PPI 1126 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1170 interrupt-controller; 1127 interrupt-controller;
1171 #interrupt-cells = <3 1128 #interrupt-cells = <3>;
1172 }; 1129 };
1173 1130
1174 pwm: pwm@1c21400 { 1131 pwm: pwm@1c21400 {
1175 compatible = "allwinn 1132 compatible = "allwinner,sun50i-a64-pwm",
1176 "allwinn 1133 "allwinner,sun5i-a13-pwm";
1177 reg = <0x01c21400 0x4 1134 reg = <0x01c21400 0x400>;
1178 clocks = <&osc24M>; 1135 clocks = <&osc24M>;
1179 pinctrl-names = "defa 1136 pinctrl-names = "default";
1180 pinctrl-0 = <&pwm_pin 1137 pinctrl-0 = <&pwm_pin>;
1181 #pwm-cells = <3>; 1138 #pwm-cells = <3>;
1182 status = "disabled"; 1139 status = "disabled";
1183 }; 1140 };
1184 1141
1185 mbus: dram-controller@1c62000 1142 mbus: dram-controller@1c62000 {
1186 compatible = "allwinn 1143 compatible = "allwinner,sun50i-a64-mbus";
1187 reg = <0x01c62000 0x1 1144 reg = <0x01c62000 0x1000>,
1188 <0x01c63000 0x1 1145 <0x01c63000 0x1000>;
1189 reg-names = "mbus", " 1146 reg-names = "mbus", "dram";
1190 clocks = <&ccu CLK_MB 1147 clocks = <&ccu CLK_MBUS>,
1191 <&ccu CLK_DR 1148 <&ccu CLK_DRAM>,
1192 <&ccu CLK_BU 1149 <&ccu CLK_BUS_DRAM>;
1193 clock-names = "mbus", 1150 clock-names = "mbus", "dram", "bus";
1194 interrupts = <GIC_SPI 1151 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
1195 #address-cells = <1>; 1152 #address-cells = <1>;
1196 #size-cells = <1>; 1153 #size-cells = <1>;
1197 dma-ranges = <0x00000 1154 dma-ranges = <0x00000000 0x40000000 0xc0000000>;
1198 #interconnect-cells = 1155 #interconnect-cells = <1>;
1199 }; 1156 };
1200 1157
1201 csi: csi@1cb0000 { 1158 csi: csi@1cb0000 {
1202 compatible = "allwinn 1159 compatible = "allwinner,sun50i-a64-csi";
1203 reg = <0x01cb0000 0x1 1160 reg = <0x01cb0000 0x1000>;
1204 interrupts = <GIC_SPI 1161 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1205 clocks = <&ccu CLK_BU 1162 clocks = <&ccu CLK_BUS_CSI>,
1206 <&ccu CLK_CS 1163 <&ccu CLK_CSI_SCLK>,
1207 <&ccu CLK_DR 1164 <&ccu CLK_DRAM_CSI>;
1208 clock-names = "bus", 1165 clock-names = "bus", "mod", "ram";
1209 resets = <&ccu RST_BU 1166 resets = <&ccu RST_BUS_CSI>;
1210 pinctrl-names = "defa 1167 pinctrl-names = "default";
1211 pinctrl-0 = <&csi_pin 1168 pinctrl-0 = <&csi_pins>;
1212 status = "disabled"; 1169 status = "disabled";
1213 }; 1170 };
1214 1171
1215 dsi: dsi@1ca0000 { 1172 dsi: dsi@1ca0000 {
1216 compatible = "allwinn 1173 compatible = "allwinner,sun50i-a64-mipi-dsi";
1217 reg = <0x01ca0000 0x1 1174 reg = <0x01ca0000 0x1000>;
1218 interrupts = <GIC_SPI 1175 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1219 clocks = <&ccu CLK_BU 1176 clocks = <&ccu CLK_BUS_MIPI_DSI>;
1220 resets = <&ccu RST_BU 1177 resets = <&ccu RST_BUS_MIPI_DSI>;
1221 phys = <&dphy>; 1178 phys = <&dphy>;
1222 phy-names = "dphy"; 1179 phy-names = "dphy";
1223 status = "disabled"; 1180 status = "disabled";
1224 #address-cells = <1>; 1181 #address-cells = <1>;
1225 #size-cells = <0>; 1182 #size-cells = <0>;
1226 1183
1227 port { 1184 port {
1228 dsi_in_tcon0: 1185 dsi_in_tcon0: endpoint {
1229 remot 1186 remote-endpoint = <&tcon0_out_dsi>;
1230 }; 1187 };
1231 }; 1188 };
1232 }; 1189 };
1233 1190
1234 dphy: d-phy@1ca1000 { 1191 dphy: d-phy@1ca1000 {
1235 compatible = "allwinn 1192 compatible = "allwinner,sun50i-a64-mipi-dphy",
1236 "allwinn 1193 "allwinner,sun6i-a31-mipi-dphy";
1237 reg = <0x01ca1000 0x1 1194 reg = <0x01ca1000 0x1000>;
1238 interrupts = <GIC_SPI 1195 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1239 clocks = <&ccu CLK_BU 1196 clocks = <&ccu CLK_BUS_MIPI_DSI>,
1240 <&ccu CLK_DS 1197 <&ccu CLK_DSI_DPHY>;
1241 clock-names = "bus", 1198 clock-names = "bus", "mod";
1242 resets = <&ccu RST_BU 1199 resets = <&ccu RST_BUS_MIPI_DSI>;
1243 status = "disabled"; 1200 status = "disabled";
1244 #phy-cells = <0>; 1201 #phy-cells = <0>;
1245 }; 1202 };
1246 1203
1247 deinterlace: deinterlace@1e00 1204 deinterlace: deinterlace@1e00000 {
1248 compatible = "allwinn 1205 compatible = "allwinner,sun50i-a64-deinterlace",
1249 "allwinn 1206 "allwinner,sun8i-h3-deinterlace";
1250 reg = <0x01e00000 0x2 1207 reg = <0x01e00000 0x20000>;
1251 clocks = <&ccu CLK_BU 1208 clocks = <&ccu CLK_BUS_DEINTERLACE>,
1252 <&ccu CLK_DE 1209 <&ccu CLK_DEINTERLACE>,
1253 <&ccu CLK_DR 1210 <&ccu CLK_DRAM_DEINTERLACE>;
1254 clock-names = "bus", 1211 clock-names = "bus", "mod", "ram";
1255 resets = <&ccu RST_BU 1212 resets = <&ccu RST_BUS_DEINTERLACE>;
1256 interrupts = <GIC_SPI 1213 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1257 interconnects = <&mbu 1214 interconnects = <&mbus 9>;
1258 interconnect-names = 1215 interconnect-names = "dma-mem";
1259 }; 1216 };
1260 1217
1261 hdmi: hdmi@1ee0000 { 1218 hdmi: hdmi@1ee0000 {
1262 compatible = "allwinn 1219 compatible = "allwinner,sun50i-a64-dw-hdmi",
1263 "allwinn 1220 "allwinner,sun8i-a83t-dw-hdmi";
1264 reg = <0x01ee0000 0x1 1221 reg = <0x01ee0000 0x10000>;
1265 reg-io-width = <1>; 1222 reg-io-width = <1>;
1266 interrupts = <GIC_SPI 1223 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1267 clocks = <&ccu CLK_BU 1224 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1268 <&ccu CLK_HD 1225 <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>;
1269 clock-names = "iahb", 1226 clock-names = "iahb", "isfr", "tmds", "cec";
1270 resets = <&ccu RST_BU 1227 resets = <&ccu RST_BUS_HDMI1>;
1271 reset-names = "ctrl"; 1228 reset-names = "ctrl";
1272 phys = <&hdmi_phy>; 1229 phys = <&hdmi_phy>;
1273 phy-names = "phy"; 1230 phy-names = "phy";
1274 status = "disabled"; 1231 status = "disabled";
1275 1232
1276 ports { 1233 ports {
1277 #address-cell 1234 #address-cells = <1>;
1278 #size-cells = 1235 #size-cells = <0>;
1279 1236
1280 hdmi_in: port 1237 hdmi_in: port@0 {
1281 reg = 1238 reg = <0>;
1282 1239
1283 hdmi_ 1240 hdmi_in_tcon1: endpoint {
1284 1241 remote-endpoint = <&tcon1_out_hdmi>;
1285 }; 1242 };
1286 }; 1243 };
1287 1244
1288 hdmi_out: por 1245 hdmi_out: port@1 {
1289 reg = 1246 reg = <1>;
1290 }; 1247 };
1291 }; 1248 };
1292 }; 1249 };
1293 1250
1294 hdmi_phy: hdmi-phy@1ef0000 { 1251 hdmi_phy: hdmi-phy@1ef0000 {
1295 compatible = "allwinn 1252 compatible = "allwinner,sun50i-a64-hdmi-phy";
1296 reg = <0x01ef0000 0x1 1253 reg = <0x01ef0000 0x10000>;
1297 clocks = <&ccu CLK_BU 1254 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1298 <&ccu CLK_PL 1255 <&ccu CLK_PLL_VIDEO0>;
1299 clock-names = "bus", 1256 clock-names = "bus", "mod", "pll-0";
1300 resets = <&ccu RST_BU 1257 resets = <&ccu RST_BUS_HDMI0>;
1301 reset-names = "phy"; 1258 reset-names = "phy";
1302 #phy-cells = <0>; 1259 #phy-cells = <0>;
1303 }; 1260 };
1304 1261
1305 rtc: rtc@1f00000 { 1262 rtc: rtc@1f00000 {
1306 compatible = "allwinn 1263 compatible = "allwinner,sun50i-a64-rtc",
1307 "allwinn 1264 "allwinner,sun8i-h3-rtc";
1308 reg = <0x01f00000 0x4 1265 reg = <0x01f00000 0x400>;
1309 interrupt-parent = <& 1266 interrupt-parent = <&r_intc>;
1310 interrupts = <GIC_SPI 1267 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1311 <GIC_SPI 1268 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1312 clock-output-names = 1269 clock-output-names = "osc32k", "osc32k-out", "iosc";
1313 clocks = <&osc32k>; 1270 clocks = <&osc32k>;
1314 #clock-cells = <1>; 1271 #clock-cells = <1>;
1315 }; 1272 };
1316 1273
1317 r_intc: interrupt-controller@ 1274 r_intc: interrupt-controller@1f00c00 {
1318 compatible = "allwinn 1275 compatible = "allwinner,sun50i-a64-r-intc",
1319 "allwinn 1276 "allwinner,sun6i-a31-r-intc";
1320 interrupt-controller; 1277 interrupt-controller;
1321 #interrupt-cells = <3 1278 #interrupt-cells = <3>;
1322 reg = <0x01f00c00 0x4 1279 reg = <0x01f00c00 0x400>;
1323 interrupts = <GIC_SPI 1280 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1324 }; 1281 };
1325 1282
1326 r_ccu: clock@1f01400 { 1283 r_ccu: clock@1f01400 {
1327 compatible = "allwinn 1284 compatible = "allwinner,sun50i-a64-r-ccu";
1328 reg = <0x01f01400 0x1 1285 reg = <0x01f01400 0x100>;
1329 clocks = <&osc24M>, < 1286 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
1330 <&ccu CLK_PL 1287 <&ccu CLK_PLL_PERIPH0>;
1331 clock-names = "hosc", 1288 clock-names = "hosc", "losc", "iosc", "pll-periph";
1332 #clock-cells = <1>; 1289 #clock-cells = <1>;
1333 #reset-cells = <1>; 1290 #reset-cells = <1>;
1334 }; 1291 };
1335 1292
1336 codec_analog: codec-analog@1f 1293 codec_analog: codec-analog@1f015c0 {
1337 compatible = "allwinn 1294 compatible = "allwinner,sun50i-a64-codec-analog";
1338 reg = <0x01f015c0 0x4 1295 reg = <0x01f015c0 0x4>;
1339 status = "disabled"; 1296 status = "disabled";
1340 }; 1297 };
1341 1298
1342 r_i2c: i2c@1f02400 { 1299 r_i2c: i2c@1f02400 {
1343 compatible = "allwinn 1300 compatible = "allwinner,sun50i-a64-i2c",
1344 "allwinn 1301 "allwinner,sun6i-a31-i2c";
1345 reg = <0x01f02400 0x4 1302 reg = <0x01f02400 0x400>;
1346 interrupts = <GIC_SPI 1303 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1347 clocks = <&r_ccu CLK_ 1304 clocks = <&r_ccu CLK_APB0_I2C>;
1348 resets = <&r_ccu RST_ 1305 resets = <&r_ccu RST_APB0_I2C>;
1349 status = "disabled"; 1306 status = "disabled";
1350 #address-cells = <1>; 1307 #address-cells = <1>;
1351 #size-cells = <0>; 1308 #size-cells = <0>;
1352 }; 1309 };
1353 1310
1354 r_ir: ir@1f02000 { 1311 r_ir: ir@1f02000 {
1355 compatible = "allwinn 1312 compatible = "allwinner,sun50i-a64-ir",
1356 "allwinn 1313 "allwinner,sun6i-a31-ir";
1357 reg = <0x01f02000 0x4 1314 reg = <0x01f02000 0x400>;
1358 clocks = <&r_ccu CLK_ 1315 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
1359 clock-names = "apb", 1316 clock-names = "apb", "ir";
1360 resets = <&r_ccu RST_ 1317 resets = <&r_ccu RST_APB0_IR>;
1361 interrupts = <GIC_SPI 1318 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1362 pinctrl-names = "defa 1319 pinctrl-names = "default";
1363 pinctrl-0 = <&r_ir_rx 1320 pinctrl-0 = <&r_ir_rx_pin>;
1364 status = "disabled"; 1321 status = "disabled";
1365 }; 1322 };
1366 1323
1367 r_pwm: pwm@1f03800 { 1324 r_pwm: pwm@1f03800 {
1368 compatible = "allwinn 1325 compatible = "allwinner,sun50i-a64-pwm",
1369 "allwinn 1326 "allwinner,sun5i-a13-pwm";
1370 reg = <0x01f03800 0x4 1327 reg = <0x01f03800 0x400>;
1371 clocks = <&osc24M>; 1328 clocks = <&osc24M>;
1372 pinctrl-names = "defa 1329 pinctrl-names = "default";
1373 pinctrl-0 = <&r_pwm_p 1330 pinctrl-0 = <&r_pwm_pin>;
1374 #pwm-cells = <3>; 1331 #pwm-cells = <3>;
1375 status = "disabled"; 1332 status = "disabled";
1376 }; 1333 };
1377 1334
1378 r_pio: pinctrl@1f02c00 { 1335 r_pio: pinctrl@1f02c00 {
1379 compatible = "allwinn 1336 compatible = "allwinner,sun50i-a64-r-pinctrl";
1380 reg = <0x01f02c00 0x4 1337 reg = <0x01f02c00 0x400>;
1381 interrupt-parent = <& 1338 interrupt-parent = <&r_intc>;
1382 interrupts = <GIC_SPI 1339 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1383 clocks = <&r_ccu CLK_ 1340 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
1384 clock-names = "apb", 1341 clock-names = "apb", "hosc", "losc";
1385 gpio-controller; 1342 gpio-controller;
1386 #gpio-cells = <3>; 1343 #gpio-cells = <3>;
1387 interrupt-controller; 1344 interrupt-controller;
1388 #interrupt-cells = <3 1345 #interrupt-cells = <3>;
1389 1346
1390 r_i2c_pl89_pins: r-i2 1347 r_i2c_pl89_pins: r-i2c-pl89-pins {
1391 pins = "PL8", 1348 pins = "PL8", "PL9";
1392 function = "s 1349 function = "s_i2c";
1393 }; 1350 };
1394 1351
1395 r_ir_rx_pin: r-ir-rx- 1352 r_ir_rx_pin: r-ir-rx-pin {
1396 pins = "PL11" 1353 pins = "PL11";
1397 function = "s 1354 function = "s_cir_rx";
1398 }; 1355 };
1399 1356
1400 r_pwm_pin: r-pwm-pin 1357 r_pwm_pin: r-pwm-pin {
1401 pins = "PL10" 1358 pins = "PL10";
1402 function = "s 1359 function = "s_pwm";
1403 }; 1360 };
1404 1361
1405 r_rsb_pins: r-rsb-pin 1362 r_rsb_pins: r-rsb-pins {
1406 pins = "PL0", 1363 pins = "PL0", "PL1";
1407 function = "s 1364 function = "s_rsb";
1408 }; 1365 };
1409 }; 1366 };
1410 1367
1411 r_rsb: rsb@1f03400 { 1368 r_rsb: rsb@1f03400 {
1412 compatible = "allwinn 1369 compatible = "allwinner,sun8i-a23-rsb";
1413 reg = <0x01f03400 0x4 1370 reg = <0x01f03400 0x400>;
1414 interrupts = <GIC_SPI 1371 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1415 clocks = <&r_ccu 6>; 1372 clocks = <&r_ccu 6>;
1416 clock-frequency = <30 1373 clock-frequency = <3000000>;
1417 resets = <&r_ccu 2>; 1374 resets = <&r_ccu 2>;
1418 pinctrl-names = "defa 1375 pinctrl-names = "default";
1419 pinctrl-0 = <&r_rsb_p 1376 pinctrl-0 = <&r_rsb_pins>;
1420 status = "disabled"; 1377 status = "disabled";
1421 #address-cells = <1>; 1378 #address-cells = <1>;
1422 #size-cells = <0>; 1379 #size-cells = <0>;
1423 }; 1380 };
1424 }; 1381 };
1425 }; 1382 };
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