1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2016 ARM Ltd. 2 // Copyright (C) 2016 ARM Ltd.
3 // based on the Allwinner H3 dtsi: 3 // based on the Allwinner H3 dtsi:
4 // Copyright (C) 2015 Jens Kuske <jenskuske@ 4 // Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
5 5
6 #include <dt-bindings/clock/sun50i-a64-ccu.h> 6 #include <dt-bindings/clock/sun50i-a64-ccu.h>
7 #include <dt-bindings/clock/sun6i-rtc.h> 7 #include <dt-bindings/clock/sun6i-rtc.h>
8 #include <dt-bindings/clock/sun8i-de2.h> 8 #include <dt-bindings/clock/sun8i-de2.h>
9 #include <dt-bindings/clock/sun8i-r-ccu.h> 9 #include <dt-bindings/clock/sun8i-r-ccu.h>
10 #include <dt-bindings/interrupt-controller/arm 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/sun50i-a64-ccu.h> 11 #include <dt-bindings/reset/sun50i-a64-ccu.h>
12 #include <dt-bindings/reset/sun8i-de2.h> 12 #include <dt-bindings/reset/sun8i-de2.h>
13 #include <dt-bindings/reset/sun8i-r-ccu.h> 13 #include <dt-bindings/reset/sun8i-r-ccu.h>
14 #include <dt-bindings/thermal/thermal.h> 14 #include <dt-bindings/thermal/thermal.h>
15 15
16 / { 16 / {
17 interrupt-parent = <&gic>; 17 interrupt-parent = <&gic>;
18 #address-cells = <1>; 18 #address-cells = <1>;
19 #size-cells = <1>; 19 #size-cells = <1>;
20 20
21 chosen { 21 chosen {
22 #address-cells = <1>; 22 #address-cells = <1>;
23 #size-cells = <1>; 23 #size-cells = <1>;
24 ranges; 24 ranges;
25 25
26 simplefb_lcd: framebuffer-lcd 26 simplefb_lcd: framebuffer-lcd {
27 compatible = "allwinne 27 compatible = "allwinner,simple-framebuffer",
28 "simple-f 28 "simple-framebuffer";
29 allwinner,pipeline = " 29 allwinner,pipeline = "mixer0-lcd0";
30 clocks = <&ccu CLK_TCO 30 clocks = <&ccu CLK_TCON0>,
31 <&display_clo 31 <&display_clocks CLK_MIXER0>;
32 status = "disabled"; 32 status = "disabled";
33 }; 33 };
34 34
35 simplefb_hdmi: framebuffer-hdm 35 simplefb_hdmi: framebuffer-hdmi {
36 compatible = "allwinne 36 compatible = "allwinner,simple-framebuffer",
37 "simple-f 37 "simple-framebuffer";
38 allwinner,pipeline = " 38 allwinner,pipeline = "mixer1-lcd1-hdmi";
39 clocks = <&display_clo 39 clocks = <&display_clocks CLK_MIXER1>,
40 <&ccu CLK_TCO 40 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
41 status = "disabled"; 41 status = "disabled";
42 }; 42 };
43 }; 43 };
44 44
45 cpus { 45 cpus {
46 #address-cells = <1>; 46 #address-cells = <1>;
47 #size-cells = <0>; 47 #size-cells = <0>;
48 48
49 cpu0: cpu@0 { 49 cpu0: cpu@0 {
50 compatible = "arm,cort 50 compatible = "arm,cortex-a53";
51 device_type = "cpu"; 51 device_type = "cpu";
52 reg = <0>; 52 reg = <0>;
53 enable-method = "psci" 53 enable-method = "psci";
54 clocks = <&ccu CLK_CPU 54 clocks = <&ccu CLK_CPUX>;
55 clock-names = "cpu"; 55 clock-names = "cpu";
56 #cooling-cells = <2>; 56 #cooling-cells = <2>;
57 i-cache-size = <0x8000 57 i-cache-size = <0x8000>;
58 i-cache-line-size = <6 58 i-cache-line-size = <64>;
59 i-cache-sets = <256>; 59 i-cache-sets = <256>;
60 d-cache-size = <0x8000 60 d-cache-size = <0x8000>;
61 d-cache-line-size = <6 61 d-cache-line-size = <64>;
62 d-cache-sets = <128>; 62 d-cache-sets = <128>;
63 next-level-cache = <&l 63 next-level-cache = <&l2_cache>;
64 }; 64 };
65 65
66 cpu1: cpu@1 { 66 cpu1: cpu@1 {
67 compatible = "arm,cort 67 compatible = "arm,cortex-a53";
68 device_type = "cpu"; 68 device_type = "cpu";
69 reg = <1>; 69 reg = <1>;
70 enable-method = "psci" 70 enable-method = "psci";
71 clocks = <&ccu CLK_CPU 71 clocks = <&ccu CLK_CPUX>;
72 clock-names = "cpu"; 72 clock-names = "cpu";
73 #cooling-cells = <2>; 73 #cooling-cells = <2>;
74 i-cache-size = <0x8000 74 i-cache-size = <0x8000>;
75 i-cache-line-size = <6 75 i-cache-line-size = <64>;
76 i-cache-sets = <256>; 76 i-cache-sets = <256>;
77 d-cache-size = <0x8000 77 d-cache-size = <0x8000>;
78 d-cache-line-size = <6 78 d-cache-line-size = <64>;
79 d-cache-sets = <128>; 79 d-cache-sets = <128>;
80 next-level-cache = <&l 80 next-level-cache = <&l2_cache>;
81 }; 81 };
82 82
83 cpu2: cpu@2 { 83 cpu2: cpu@2 {
84 compatible = "arm,cort 84 compatible = "arm,cortex-a53";
85 device_type = "cpu"; 85 device_type = "cpu";
86 reg = <2>; 86 reg = <2>;
87 enable-method = "psci" 87 enable-method = "psci";
88 clocks = <&ccu CLK_CPU 88 clocks = <&ccu CLK_CPUX>;
89 clock-names = "cpu"; 89 clock-names = "cpu";
90 #cooling-cells = <2>; 90 #cooling-cells = <2>;
91 i-cache-size = <0x8000 91 i-cache-size = <0x8000>;
92 i-cache-line-size = <6 92 i-cache-line-size = <64>;
93 i-cache-sets = <256>; 93 i-cache-sets = <256>;
94 d-cache-size = <0x8000 94 d-cache-size = <0x8000>;
95 d-cache-line-size = <6 95 d-cache-line-size = <64>;
96 d-cache-sets = <128>; 96 d-cache-sets = <128>;
97 next-level-cache = <&l 97 next-level-cache = <&l2_cache>;
98 }; 98 };
99 99
100 cpu3: cpu@3 { 100 cpu3: cpu@3 {
101 compatible = "arm,cort 101 compatible = "arm,cortex-a53";
102 device_type = "cpu"; 102 device_type = "cpu";
103 reg = <3>; 103 reg = <3>;
104 enable-method = "psci" 104 enable-method = "psci";
105 clocks = <&ccu CLK_CPU 105 clocks = <&ccu CLK_CPUX>;
106 clock-names = "cpu"; 106 clock-names = "cpu";
107 #cooling-cells = <2>; 107 #cooling-cells = <2>;
108 i-cache-size = <0x8000 108 i-cache-size = <0x8000>;
109 i-cache-line-size = <6 109 i-cache-line-size = <64>;
110 i-cache-sets = <256>; 110 i-cache-sets = <256>;
111 d-cache-size = <0x8000 111 d-cache-size = <0x8000>;
112 d-cache-line-size = <6 112 d-cache-line-size = <64>;
113 d-cache-sets = <128>; 113 d-cache-sets = <128>;
114 next-level-cache = <&l 114 next-level-cache = <&l2_cache>;
115 }; 115 };
116 116
117 l2_cache: l2-cache { 117 l2_cache: l2-cache {
118 compatible = "cache"; 118 compatible = "cache";
119 cache-level = <2>; 119 cache-level = <2>;
120 cache-unified; 120 cache-unified;
121 cache-size = <0x80000> 121 cache-size = <0x80000>;
122 cache-line-size = <64> 122 cache-line-size = <64>;
123 cache-sets = <512>; 123 cache-sets = <512>;
124 }; 124 };
125 }; 125 };
126 126
127 de: display-engine { 127 de: display-engine {
128 compatible = "allwinner,sun50i 128 compatible = "allwinner,sun50i-a64-display-engine";
129 allwinner,pipelines = <&mixer0 129 allwinner,pipelines = <&mixer0>,
130 <&mixer1 130 <&mixer1>;
131 status = "disabled"; 131 status = "disabled";
132 }; 132 };
133 133
134 gpu_opp_table: opp-table-gpu { 134 gpu_opp_table: opp-table-gpu {
135 compatible = "operating-points 135 compatible = "operating-points-v2";
136 136
137 opp-432000000 { 137 opp-432000000 {
138 opp-hz = /bits/ 64 <43 138 opp-hz = /bits/ 64 <432000000>;
139 }; 139 };
140 }; 140 };
141 141
142 osc24M: osc24M-clk { 142 osc24M: osc24M-clk {
143 #clock-cells = <0>; 143 #clock-cells = <0>;
144 compatible = "fixed-clock"; 144 compatible = "fixed-clock";
145 clock-frequency = <24000000>; 145 clock-frequency = <24000000>;
146 clock-output-names = "osc24M"; 146 clock-output-names = "osc24M";
147 }; 147 };
148 148
149 osc32k: osc32k-clk { 149 osc32k: osc32k-clk {
150 #clock-cells = <0>; 150 #clock-cells = <0>;
151 compatible = "fixed-clock"; 151 compatible = "fixed-clock";
152 clock-frequency = <32768>; 152 clock-frequency = <32768>;
153 clock-output-names = "ext-osc3 153 clock-output-names = "ext-osc32k";
154 }; 154 };
155 155
156 pmu { 156 pmu {
157 compatible = "arm,cortex-a53-p 157 compatible = "arm,cortex-a53-pmu";
158 interrupts = <GIC_SPI 116 IRQ_ 158 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 117 IRQ_ 159 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 118 IRQ_ 160 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 119 IRQ_ 161 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
162 interrupt-affinity = <&cpu0>, 162 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
163 }; 163 };
164 164
165 psci { 165 psci {
166 compatible = "arm,psci-0.2"; 166 compatible = "arm,psci-0.2";
167 method = "smc"; 167 method = "smc";
168 }; 168 };
169 169
170 sound: sound { 170 sound: sound {
171 #address-cells = <1>; 171 #address-cells = <1>;
172 #size-cells = <0>; 172 #size-cells = <0>;
173 compatible = "simple-audio-car 173 compatible = "simple-audio-card";
174 simple-audio-card,name = "sun5 174 simple-audio-card,name = "sun50i-a64-audio";
175 simple-audio-card,aux-devs = < 175 simple-audio-card,aux-devs = <&codec_analog>;
176 simple-audio-card,routing = 176 simple-audio-card,routing =
177 "Left DAC", "D 177 "Left DAC", "DACL",
178 "Right DAC", " 178 "Right DAC", "DACR",
179 "ADCL", "Left 179 "ADCL", "Left ADC",
180 "ADCR", "Right 180 "ADCR", "Right ADC";
181 status = "disabled"; 181 status = "disabled";
182 182
183 simple-audio-card,dai-link@0 { 183 simple-audio-card,dai-link@0 {
184 format = "i2s"; 184 format = "i2s";
185 frame-master = <&link0 185 frame-master = <&link0_cpu>;
186 bitclock-master = <&li 186 bitclock-master = <&link0_cpu>;
187 mclk-fs = <128>; 187 mclk-fs = <128>;
188 188
189 link0_cpu: cpu { 189 link0_cpu: cpu {
190 sound-dai = <& 190 sound-dai = <&dai>;
191 }; 191 };
192 192
193 link0_codec: codec { 193 link0_codec: codec {
194 sound-dai = <& 194 sound-dai = <&codec 0>;
195 }; 195 };
196 }; 196 };
197 }; 197 };
198 198
199 timer { 199 timer {
200 compatible = "arm,armv8-timer" 200 compatible = "arm,armv8-timer";
201 allwinner,erratum-unknown1; 201 allwinner,erratum-unknown1;
202 arm,no-tick-in-suspend; 202 arm,no-tick-in-suspend;
203 interrupts = <GIC_PPI 13 203 interrupts = <GIC_PPI 13
204 (GIC_CPU_MASK_SIMPLE(4 204 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
205 <GIC_PPI 14 205 <GIC_PPI 14
206 (GIC_CPU_MASK_SIMPLE(4 206 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
207 <GIC_PPI 11 207 <GIC_PPI 11
208 (GIC_CPU_MASK_SIMPLE(4 208 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
209 <GIC_PPI 10 209 <GIC_PPI 10
210 (GIC_CPU_MASK_SIMPLE(4 210 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
211 }; 211 };
212 212
213 thermal-zones { 213 thermal-zones {
214 cpu_thermal: cpu0-thermal { 214 cpu_thermal: cpu0-thermal {
215 /* milliseconds */ 215 /* milliseconds */
216 polling-delay-passive 216 polling-delay-passive = <0>;
217 polling-delay = <0>; 217 polling-delay = <0>;
218 thermal-sensors = <&th 218 thermal-sensors = <&ths 0>;
219 219
220 cooling-maps { 220 cooling-maps {
221 map0 { 221 map0 {
222 trip = 222 trip = <&cpu_alert0>;
223 coolin 223 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
224 224 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
225 225 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
226 226 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
227 }; 227 };
228 map1 { 228 map1 {
229 trip = 229 trip = <&cpu_alert1>;
230 coolin 230 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
231 231 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
232 232 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
233 233 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
234 }; 234 };
235 }; 235 };
236 236
237 trips { 237 trips {
238 cpu_alert0: cp 238 cpu_alert0: cpu-alert0 {
239 /* mil 239 /* milliCelsius */
240 temper 240 temperature = <75000>;
241 hyster 241 hysteresis = <2000>;
242 type = 242 type = "passive";
243 }; 243 };
244 244
245 cpu_alert1: cp 245 cpu_alert1: cpu-alert1 {
246 /* mil 246 /* milliCelsius */
247 temper 247 temperature = <90000>;
248 hyster 248 hysteresis = <2000>;
249 type = 249 type = "hot";
250 }; 250 };
251 251
252 cpu_crit: cpu- 252 cpu_crit: cpu-crit {
253 /* mil 253 /* milliCelsius */
254 temper 254 temperature = <110000>;
255 hyster 255 hysteresis = <2000>;
256 type = 256 type = "critical";
257 }; 257 };
258 }; 258 };
259 }; 259 };
260 260
261 gpu0_thermal: gpu0-thermal { 261 gpu0_thermal: gpu0-thermal {
262 /* milliseconds */ 262 /* milliseconds */
263 polling-delay-passive 263 polling-delay-passive = <0>;
264 polling-delay = <0>; 264 polling-delay = <0>;
265 thermal-sensors = <&th 265 thermal-sensors = <&ths 1>;
266 266
267 trips { 267 trips {
268 gpu0_crit: gpu 268 gpu0_crit: gpu0-crit {
269 temper 269 temperature = <110000>;
270 hyster 270 hysteresis = <2000>;
271 type = 271 type = "critical";
272 }; 272 };
273 }; 273 };
274 }; 274 };
275 275
276 gpu1_thermal: gpu1-thermal { 276 gpu1_thermal: gpu1-thermal {
277 /* milliseconds */ 277 /* milliseconds */
278 polling-delay-passive 278 polling-delay-passive = <0>;
279 polling-delay = <0>; 279 polling-delay = <0>;
280 thermal-sensors = <&th 280 thermal-sensors = <&ths 2>;
281 281
282 trips { 282 trips {
283 gpu1_crit: gpu 283 gpu1_crit: gpu1-crit {
284 temper 284 temperature = <110000>;
285 hyster 285 hysteresis = <2000>;
286 type = 286 type = "critical";
287 }; 287 };
288 }; 288 };
289 }; 289 };
290 }; 290 };
291 291
292 soc { 292 soc {
293 compatible = "simple-bus"; 293 compatible = "simple-bus";
294 #address-cells = <1>; 294 #address-cells = <1>;
295 #size-cells = <1>; 295 #size-cells = <1>;
296 ranges; 296 ranges;
297 297
298 bus@1000000 { 298 bus@1000000 {
299 compatible = "allwinne 299 compatible = "allwinner,sun50i-a64-de2";
300 reg = <0x1000000 0x400 300 reg = <0x1000000 0x400000>;
301 allwinner,sram = <&de2 301 allwinner,sram = <&de2_sram 1>;
302 #address-cells = <1>; 302 #address-cells = <1>;
303 #size-cells = <1>; 303 #size-cells = <1>;
304 ranges = <0 0x1000000 304 ranges = <0 0x1000000 0x400000>;
305 305
306 display_clocks: clock@ 306 display_clocks: clock@0 {
307 compatible = " 307 compatible = "allwinner,sun50i-a64-de2-clk";
308 reg = <0x0 0x1 308 reg = <0x0 0x10000>;
309 clocks = <&ccu 309 clocks = <&ccu CLK_BUS_DE>,
310 <&ccu 310 <&ccu CLK_DE>;
311 clock-names = 311 clock-names = "bus",
312 312 "mod";
313 resets = <&ccu 313 resets = <&ccu RST_BUS_DE>;
314 #clock-cells = 314 #clock-cells = <1>;
315 #reset-cells = 315 #reset-cells = <1>;
316 }; 316 };
317 317
318 rotate: rotate@20000 { 318 rotate: rotate@20000 {
319 compatible = " 319 compatible = "allwinner,sun50i-a64-de2-rotate",
320 " 320 "allwinner,sun8i-a83t-de2-rotate";
321 reg = <0x20000 321 reg = <0x20000 0x10000>;
322 interrupts = < 322 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&dis 323 clocks = <&display_clocks CLK_BUS_ROT>,
324 <&dis 324 <&display_clocks CLK_ROT>;
325 clock-names = 325 clock-names = "bus",
326 326 "mod";
327 resets = <&dis 327 resets = <&display_clocks RST_ROT>;
328 }; 328 };
329 329
330 mixer0: mixer@100000 { 330 mixer0: mixer@100000 {
331 compatible = " 331 compatible = "allwinner,sun50i-a64-de2-mixer-0";
332 reg = <0x10000 332 reg = <0x100000 0x100000>;
333 clocks = <&dis 333 clocks = <&display_clocks CLK_BUS_MIXER0>,
334 <&dis 334 <&display_clocks CLK_MIXER0>;
335 clock-names = 335 clock-names = "bus",
336 336 "mod";
337 resets = <&dis 337 resets = <&display_clocks RST_MIXER0>;
338 338
339 ports { 339 ports {
340 #addre 340 #address-cells = <1>;
341 #size- 341 #size-cells = <0>;
342 342
343 mixer0 343 mixer0_out: port@1 {
344 344 #address-cells = <1>;
345 345 #size-cells = <0>;
346 346 reg = <1>;
347 347
348 348 mixer0_out_tcon0: endpoint@0 {
349 349 reg = <0>;
350 350 remote-endpoint = <&tcon0_in_mixer0>;
351 351 };
352 352
353 353 mixer0_out_tcon1: endpoint@1 {
354 354 reg = <1>;
355 355 remote-endpoint = <&tcon1_in_mixer0>;
356 356 };
357 }; 357 };
358 }; 358 };
359 }; 359 };
360 360
361 mixer1: mixer@200000 { 361 mixer1: mixer@200000 {
362 compatible = " 362 compatible = "allwinner,sun50i-a64-de2-mixer-1";
363 reg = <0x20000 363 reg = <0x200000 0x100000>;
364 clocks = <&dis 364 clocks = <&display_clocks CLK_BUS_MIXER1>,
365 <&dis 365 <&display_clocks CLK_MIXER1>;
366 clock-names = 366 clock-names = "bus",
367 367 "mod";
368 resets = <&dis 368 resets = <&display_clocks RST_MIXER1>;
369 369
370 ports { 370 ports {
371 #addre 371 #address-cells = <1>;
372 #size- 372 #size-cells = <0>;
373 373
374 mixer1 374 mixer1_out: port@1 {
375 375 #address-cells = <1>;
376 376 #size-cells = <0>;
377 377 reg = <1>;
378 378
379 379 mixer1_out_tcon0: endpoint@0 {
380 380 reg = <0>;
381 381 remote-endpoint = <&tcon0_in_mixer1>;
382 382 };
383 383
384 384 mixer1_out_tcon1: endpoint@1 {
385 385 reg = <1>;
386 386 remote-endpoint = <&tcon1_in_mixer1>;
387 387 };
388 }; 388 };
389 }; 389 };
390 }; 390 };
391 }; 391 };
392 392
393 syscon: syscon@1c00000 { 393 syscon: syscon@1c00000 {
394 compatible = "allwinne 394 compatible = "allwinner,sun50i-a64-system-control";
395 reg = <0x01c00000 0x10 395 reg = <0x01c00000 0x1000>;
396 #address-cells = <1>; 396 #address-cells = <1>;
397 #size-cells = <1>; 397 #size-cells = <1>;
398 ranges; 398 ranges;
399 399
400 sram_c: sram@18000 { 400 sram_c: sram@18000 {
401 compatible = " 401 compatible = "mmio-sram";
402 reg = <0x00018 402 reg = <0x00018000 0x28000>;
403 #address-cells 403 #address-cells = <1>;
404 #size-cells = 404 #size-cells = <1>;
405 ranges = <0 0x 405 ranges = <0 0x00018000 0x28000>;
406 406
407 de2_sram: sram 407 de2_sram: sram-section@0 {
408 compat 408 compatible = "allwinner,sun50i-a64-sram-c";
409 reg = 409 reg = <0x0000 0x28000>;
410 }; 410 };
411 }; 411 };
412 412
413 sram_c1: sram@1d00000 413 sram_c1: sram@1d00000 {
414 compatible = " 414 compatible = "mmio-sram";
415 reg = <0x01d00 415 reg = <0x01d00000 0x40000>;
416 #address-cells 416 #address-cells = <1>;
417 #size-cells = 417 #size-cells = <1>;
418 ranges = <0 0x 418 ranges = <0 0x01d00000 0x40000>;
419 419
420 ve_sram: sram- 420 ve_sram: sram-section@0 {
421 compat 421 compatible = "allwinner,sun50i-a64-sram-c1",
422 422 "allwinner,sun4i-a10-sram-c1";
423 reg = 423 reg = <0x000000 0x40000>;
424 }; 424 };
425 }; 425 };
426 }; 426 };
427 427
428 dma: dma-controller@1c02000 { 428 dma: dma-controller@1c02000 {
429 compatible = "allwinne 429 compatible = "allwinner,sun50i-a64-dma";
430 reg = <0x01c02000 0x10 430 reg = <0x01c02000 0x1000>;
431 interrupts = <GIC_SPI 431 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&ccu CLK_BUS 432 clocks = <&ccu CLK_BUS_DMA>;
433 dma-channels = <8>; 433 dma-channels = <8>;
434 dma-requests = <27>; 434 dma-requests = <27>;
435 resets = <&ccu RST_BUS 435 resets = <&ccu RST_BUS_DMA>;
436 #dma-cells = <1>; 436 #dma-cells = <1>;
437 }; 437 };
438 438
439 tcon0: lcd-controller@1c0c000 439 tcon0: lcd-controller@1c0c000 {
440 compatible = "allwinne 440 compatible = "allwinner,sun50i-a64-tcon-lcd",
441 "allwinne 441 "allwinner,sun8i-a83t-tcon-lcd";
442 reg = <0x01c0c000 0x10 442 reg = <0x01c0c000 0x1000>;
443 interrupts = <GIC_SPI 443 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
444 clocks = <&ccu CLK_BUS 444 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
445 clock-names = "ahb", " 445 clock-names = "ahb", "tcon-ch0";
446 clock-output-names = " 446 clock-output-names = "tcon-data-clock";
447 #clock-cells = <0>; 447 #clock-cells = <0>;
448 resets = <&ccu RST_BUS 448 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
449 reset-names = "lcd", " 449 reset-names = "lcd", "lvds";
450 450
451 ports { 451 ports {
452 #address-cells 452 #address-cells = <1>;
453 #size-cells = 453 #size-cells = <0>;
454 454
455 tcon0_in: port 455 tcon0_in: port@0 {
456 #addre 456 #address-cells = <1>;
457 #size- 457 #size-cells = <0>;
458 reg = 458 reg = <0>;
459 459
460 tcon0_ 460 tcon0_in_mixer0: endpoint@0 {
461 461 reg = <0>;
462 462 remote-endpoint = <&mixer0_out_tcon0>;
463 }; 463 };
464 464
465 tcon0_ 465 tcon0_in_mixer1: endpoint@1 {
466 466 reg = <1>;
467 467 remote-endpoint = <&mixer1_out_tcon0>;
468 }; 468 };
469 }; 469 };
470 470
471 tcon0_out: por 471 tcon0_out: port@1 {
472 #addre 472 #address-cells = <1>;
473 #size- 473 #size-cells = <0>;
474 reg = 474 reg = <1>;
475 475
476 tcon0_ 476 tcon0_out_dsi: endpoint@1 {
477 477 reg = <1>;
478 478 remote-endpoint = <&dsi_in_tcon0>;
479 479 allwinner,tcon-channel = <1>;
480 }; 480 };
481 }; 481 };
482 }; 482 };
483 }; 483 };
484 484
485 tcon1: lcd-controller@1c0d000 485 tcon1: lcd-controller@1c0d000 {
486 compatible = "allwinne 486 compatible = "allwinner,sun50i-a64-tcon-tv",
487 "allwinne 487 "allwinner,sun8i-a83t-tcon-tv";
488 reg = <0x01c0d000 0x10 488 reg = <0x01c0d000 0x1000>;
489 interrupts = <GIC_SPI 489 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&ccu CLK_BUS 490 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
491 clock-names = "ahb", " 491 clock-names = "ahb", "tcon-ch1";
492 resets = <&ccu RST_BUS 492 resets = <&ccu RST_BUS_TCON1>;
493 reset-names = "lcd"; 493 reset-names = "lcd";
494 494
495 ports { 495 ports {
496 #address-cells 496 #address-cells = <1>;
497 #size-cells = 497 #size-cells = <0>;
498 498
499 tcon1_in: port 499 tcon1_in: port@0 {
500 #addre 500 #address-cells = <1>;
501 #size- 501 #size-cells = <0>;
502 reg = 502 reg = <0>;
503 503
504 tcon1_ 504 tcon1_in_mixer0: endpoint@0 {
505 505 reg = <0>;
506 506 remote-endpoint = <&mixer0_out_tcon1>;
507 }; 507 };
508 508
509 tcon1_ 509 tcon1_in_mixer1: endpoint@1 {
510 510 reg = <1>;
511 511 remote-endpoint = <&mixer1_out_tcon1>;
512 }; 512 };
513 }; 513 };
514 514
515 tcon1_out: por 515 tcon1_out: port@1 {
516 #addre 516 #address-cells = <1>;
517 #size- 517 #size-cells = <0>;
518 reg = 518 reg = <1>;
519 519
520 tcon1_ 520 tcon1_out_hdmi: endpoint@1 {
521 521 reg = <1>;
522 522 remote-endpoint = <&hdmi_in_tcon1>;
523 }; 523 };
524 }; 524 };
525 }; 525 };
526 }; 526 };
527 527
528 video-codec@1c0e000 { 528 video-codec@1c0e000 {
529 compatible = "allwinne 529 compatible = "allwinner,sun50i-a64-video-engine";
530 reg = <0x01c0e000 0x10 530 reg = <0x01c0e000 0x1000>;
531 clocks = <&ccu CLK_BUS 531 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
532 <&ccu CLK_DRA 532 <&ccu CLK_DRAM_VE>;
533 clock-names = "ahb", " 533 clock-names = "ahb", "mod", "ram";
534 resets = <&ccu RST_BUS 534 resets = <&ccu RST_BUS_VE>;
535 interrupts = <GIC_SPI 535 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
536 allwinner,sram = <&ve_ 536 allwinner,sram = <&ve_sram 1>;
537 }; 537 };
538 538
539 mmc0: mmc@1c0f000 { 539 mmc0: mmc@1c0f000 {
540 compatible = "allwinne 540 compatible = "allwinner,sun50i-a64-mmc";
541 reg = <0x01c0f000 0x10 541 reg = <0x01c0f000 0x1000>;
542 clocks = <&ccu CLK_BUS 542 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
543 clock-names = "ahb", " 543 clock-names = "ahb", "mmc";
544 resets = <&ccu RST_BUS 544 resets = <&ccu RST_BUS_MMC0>;
545 reset-names = "ahb"; 545 reset-names = "ahb";
546 interrupts = <GIC_SPI 546 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
547 max-frequency = <15000 547 max-frequency = <150000000>;
548 status = "disabled"; 548 status = "disabled";
549 #address-cells = <1>; 549 #address-cells = <1>;
550 #size-cells = <0>; 550 #size-cells = <0>;
551 }; 551 };
552 552
553 mmc1: mmc@1c10000 { 553 mmc1: mmc@1c10000 {
554 compatible = "allwinne 554 compatible = "allwinner,sun50i-a64-mmc";
555 reg = <0x01c10000 0x10 555 reg = <0x01c10000 0x1000>;
556 clocks = <&ccu CLK_BUS 556 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
557 clock-names = "ahb", " 557 clock-names = "ahb", "mmc";
558 resets = <&ccu RST_BUS 558 resets = <&ccu RST_BUS_MMC1>;
559 reset-names = "ahb"; 559 reset-names = "ahb";
560 interrupts = <GIC_SPI 560 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
561 max-frequency = <15000 561 max-frequency = <150000000>;
562 status = "disabled"; 562 status = "disabled";
563 #address-cells = <1>; 563 #address-cells = <1>;
564 #size-cells = <0>; 564 #size-cells = <0>;
565 }; 565 };
566 566
567 mmc2: mmc@1c11000 { 567 mmc2: mmc@1c11000 {
568 compatible = "allwinne 568 compatible = "allwinner,sun50i-a64-emmc";
569 reg = <0x01c11000 0x10 569 reg = <0x01c11000 0x1000>;
570 clocks = <&ccu CLK_BUS 570 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
571 clock-names = "ahb", " 571 clock-names = "ahb", "mmc";
572 resets = <&ccu RST_BUS 572 resets = <&ccu RST_BUS_MMC2>;
573 reset-names = "ahb"; 573 reset-names = "ahb";
574 interrupts = <GIC_SPI 574 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
575 max-frequency = <15000 575 max-frequency = <150000000>;
576 status = "disabled"; 576 status = "disabled";
577 #address-cells = <1>; 577 #address-cells = <1>;
578 #size-cells = <0>; 578 #size-cells = <0>;
579 }; 579 };
580 580
581 sid: eeprom@1c14000 { 581 sid: eeprom@1c14000 {
582 compatible = "allwinne 582 compatible = "allwinner,sun50i-a64-sid";
583 reg = <0x1c14000 0x400 583 reg = <0x1c14000 0x400>;
584 #address-cells = <1>; 584 #address-cells = <1>;
585 #size-cells = <1>; 585 #size-cells = <1>;
586 586
587 ths_calibration: therm 587 ths_calibration: thermal-sensor-calibration@34 {
588 reg = <0x34 0x 588 reg = <0x34 0x8>;
589 }; 589 };
590 }; 590 };
591 591
592 crypto: crypto@1c15000 { 592 crypto: crypto@1c15000 {
593 compatible = "allwinne 593 compatible = "allwinner,sun50i-a64-crypto";
594 reg = <0x01c15000 0x10 594 reg = <0x01c15000 0x1000>;
595 interrupts = <GIC_SPI 595 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
596 clocks = <&ccu CLK_BUS 596 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
597 clock-names = "bus", " 597 clock-names = "bus", "mod";
598 resets = <&ccu RST_BUS 598 resets = <&ccu RST_BUS_CE>;
599 }; 599 };
600 600
601 msgbox: mailbox@1c17000 { 601 msgbox: mailbox@1c17000 {
602 compatible = "allwinne 602 compatible = "allwinner,sun50i-a64-msgbox",
603 "allwinne 603 "allwinner,sun6i-a31-msgbox";
604 reg = <0x01c17000 0x10 604 reg = <0x01c17000 0x1000>;
605 clocks = <&ccu CLK_BUS 605 clocks = <&ccu CLK_BUS_MSGBOX>;
606 resets = <&ccu RST_BUS 606 resets = <&ccu RST_BUS_MSGBOX>;
607 interrupts = <GIC_SPI 607 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
608 #mbox-cells = <1>; 608 #mbox-cells = <1>;
609 }; 609 };
610 610
611 usb_otg: usb@1c19000 { 611 usb_otg: usb@1c19000 {
612 compatible = "allwinne 612 compatible = "allwinner,sun8i-a33-musb";
613 reg = <0x01c19000 0x04 613 reg = <0x01c19000 0x0400>;
614 clocks = <&ccu CLK_BUS 614 clocks = <&ccu CLK_BUS_OTG>;
615 resets = <&ccu RST_BUS 615 resets = <&ccu RST_BUS_OTG>;
616 interrupts = <GIC_SPI 616 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
617 interrupt-names = "mc" 617 interrupt-names = "mc";
618 phys = <&usbphy 0>; 618 phys = <&usbphy 0>;
619 phy-names = "usb"; 619 phy-names = "usb";
620 extcon = <&usbphy 0>; 620 extcon = <&usbphy 0>;
621 dr_mode = "otg"; 621 dr_mode = "otg";
622 status = "disabled"; 622 status = "disabled";
623 }; 623 };
624 624
625 usbphy: phy@1c19400 { 625 usbphy: phy@1c19400 {
626 compatible = "allwinne 626 compatible = "allwinner,sun50i-a64-usb-phy";
627 reg = <0x01c19400 0x14 627 reg = <0x01c19400 0x14>,
628 <0x01c1a800 0x4> 628 <0x01c1a800 0x4>,
629 <0x01c1b800 0x4> 629 <0x01c1b800 0x4>;
630 reg-names = "phy_ctrl" 630 reg-names = "phy_ctrl",
631 "pmu0", 631 "pmu0",
632 "pmu1"; 632 "pmu1";
633 clocks = <&ccu CLK_USB 633 clocks = <&ccu CLK_USB_PHY0>,
634 <&ccu CLK_USB 634 <&ccu CLK_USB_PHY1>;
635 clock-names = "usb0_ph 635 clock-names = "usb0_phy",
636 "usb1_ph 636 "usb1_phy";
637 resets = <&ccu RST_USB 637 resets = <&ccu RST_USB_PHY0>,
638 <&ccu RST_USB 638 <&ccu RST_USB_PHY1>;
639 reset-names = "usb0_re 639 reset-names = "usb0_reset",
640 "usb1_re 640 "usb1_reset";
641 status = "disabled"; 641 status = "disabled";
642 #phy-cells = <1>; 642 #phy-cells = <1>;
643 }; 643 };
644 644
645 ehci0: usb@1c1a000 { 645 ehci0: usb@1c1a000 {
646 compatible = "allwinne 646 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
647 reg = <0x01c1a000 0x10 647 reg = <0x01c1a000 0x100>;
648 interrupts = <GIC_SPI 648 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
649 clocks = <&ccu CLK_BUS 649 clocks = <&ccu CLK_BUS_OHCI0>,
650 <&ccu CLK_BUS 650 <&ccu CLK_BUS_EHCI0>,
651 <&ccu CLK_USB 651 <&ccu CLK_USB_OHCI0>;
652 resets = <&ccu RST_BUS 652 resets = <&ccu RST_BUS_OHCI0>,
653 <&ccu RST_BUS 653 <&ccu RST_BUS_EHCI0>;
654 phys = <&usbphy 0>; 654 phys = <&usbphy 0>;
655 phy-names = "usb"; 655 phy-names = "usb";
656 status = "disabled"; 656 status = "disabled";
657 }; 657 };
658 658
659 ohci0: usb@1c1a400 { 659 ohci0: usb@1c1a400 {
660 compatible = "allwinne 660 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
661 reg = <0x01c1a400 0x10 661 reg = <0x01c1a400 0x100>;
662 interrupts = <GIC_SPI 662 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
663 clocks = <&ccu CLK_BUS 663 clocks = <&ccu CLK_BUS_OHCI0>,
664 <&ccu CLK_USB 664 <&ccu CLK_USB_OHCI0>;
665 resets = <&ccu RST_BUS 665 resets = <&ccu RST_BUS_OHCI0>;
666 phys = <&usbphy 0>; 666 phys = <&usbphy 0>;
667 phy-names = "usb"; 667 phy-names = "usb";
668 status = "disabled"; 668 status = "disabled";
669 }; 669 };
670 670
671 ehci1: usb@1c1b000 { 671 ehci1: usb@1c1b000 {
672 compatible = "allwinne 672 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
673 reg = <0x01c1b000 0x10 673 reg = <0x01c1b000 0x100>;
674 interrupts = <GIC_SPI 674 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
675 clocks = <&ccu CLK_BUS 675 clocks = <&ccu CLK_BUS_OHCI1>,
676 <&ccu CLK_BUS 676 <&ccu CLK_BUS_EHCI1>,
677 <&ccu CLK_USB 677 <&ccu CLK_USB_OHCI1>;
678 resets = <&ccu RST_BUS 678 resets = <&ccu RST_BUS_OHCI1>,
679 <&ccu RST_BUS 679 <&ccu RST_BUS_EHCI1>;
680 phys = <&usbphy 1>; 680 phys = <&usbphy 1>;
681 phy-names = "usb"; 681 phy-names = "usb";
682 status = "disabled"; 682 status = "disabled";
683 }; 683 };
684 684
685 ohci1: usb@1c1b400 { 685 ohci1: usb@1c1b400 {
686 compatible = "allwinne 686 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
687 reg = <0x01c1b400 0x10 687 reg = <0x01c1b400 0x100>;
688 interrupts = <GIC_SPI 688 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
689 clocks = <&ccu CLK_BUS 689 clocks = <&ccu CLK_BUS_OHCI1>,
690 <&ccu CLK_USB 690 <&ccu CLK_USB_OHCI1>;
691 resets = <&ccu RST_BUS 691 resets = <&ccu RST_BUS_OHCI1>;
692 phys = <&usbphy 1>; 692 phys = <&usbphy 1>;
693 phy-names = "usb"; 693 phy-names = "usb";
694 status = "disabled"; 694 status = "disabled";
695 }; 695 };
696 696
697 ccu: clock@1c20000 { 697 ccu: clock@1c20000 {
698 compatible = "allwinne 698 compatible = "allwinner,sun50i-a64-ccu";
699 reg = <0x01c20000 0x40 699 reg = <0x01c20000 0x400>;
700 clocks = <&osc24M>, <& 700 clocks = <&osc24M>, <&rtc CLK_OSC32K>;
701 clock-names = "hosc", 701 clock-names = "hosc", "losc";
702 #clock-cells = <1>; 702 #clock-cells = <1>;
703 #reset-cells = <1>; 703 #reset-cells = <1>;
704 }; 704 };
705 705
706 pio: pinctrl@1c20800 { 706 pio: pinctrl@1c20800 {
707 compatible = "allwinne 707 compatible = "allwinner,sun50i-a64-pinctrl";
708 reg = <0x01c20800 0x40 708 reg = <0x01c20800 0x400>;
709 interrupt-parent = <&r 709 interrupt-parent = <&r_intc>;
710 interrupts = <GIC_SPI 710 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
711 <GIC_SPI 711 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
712 <GIC_SPI 712 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&ccu CLK_BUS 713 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
714 <&rtc CLK_OSC 714 <&rtc CLK_OSC32K>;
715 clock-names = "apb", " 715 clock-names = "apb", "hosc", "losc";
716 gpio-controller; 716 gpio-controller;
717 #gpio-cells = <3>; 717 #gpio-cells = <3>;
718 interrupt-controller; 718 interrupt-controller;
719 #interrupt-cells = <3> 719 #interrupt-cells = <3>;
720 720
721 /omit-if-no-ref/ 721 /omit-if-no-ref/
722 aif2_pins: aif2-pins { 722 aif2_pins: aif2-pins {
723 pins = "PB4", 723 pins = "PB4", "PB5", "PB6", "PB7";
724 function = "ai 724 function = "aif2";
725 }; 725 };
726 726
727 /omit-if-no-ref/ 727 /omit-if-no-ref/
728 aif3_pins: aif3-pins { 728 aif3_pins: aif3-pins {
729 pins = "PG10", 729 pins = "PG10", "PG11", "PG12", "PG13";
730 function = "ai 730 function = "aif3";
731 }; 731 };
732 732
733 csi_pins: csi-pins { 733 csi_pins: csi-pins {
734 pins = "PE0", 734 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
735 "PE7", 735 "PE7", "PE8", "PE9", "PE10", "PE11";
736 function = "cs 736 function = "csi";
737 }; 737 };
738 738
739 /omit-if-no-ref/ 739 /omit-if-no-ref/
740 csi_mclk_pin: csi-mclk 740 csi_mclk_pin: csi-mclk-pin {
741 pins = "PE1"; 741 pins = "PE1";
742 function = "cs 742 function = "csi";
743 }; 743 };
744 744
745 i2c0_pins: i2c0-pins { 745 i2c0_pins: i2c0-pins {
746 pins = "PH0", 746 pins = "PH0", "PH1";
747 function = "i2 747 function = "i2c0";
748 }; 748 };
749 749
750 i2c1_pins: i2c1-pins { 750 i2c1_pins: i2c1-pins {
751 pins = "PH2", 751 pins = "PH2", "PH3";
752 function = "i2 752 function = "i2c1";
753 }; 753 };
754 754
755 i2c2_pins: i2c2-pins { 755 i2c2_pins: i2c2-pins {
756 pins = "PE14", 756 pins = "PE14", "PE15";
757 function = "i2 757 function = "i2c2";
758 }; 758 };
759 759
760 /omit-if-no-ref/ 760 /omit-if-no-ref/
761 lcd_rgb666_pins: lcd-r 761 lcd_rgb666_pins: lcd-rgb666-pins {
762 pins = "PD0", 762 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
763 "PD5", 763 "PD5", "PD6", "PD7", "PD8", "PD9",
764 "PD10", 764 "PD10", "PD11", "PD12", "PD13",
765 "PD14", 765 "PD14", "PD15", "PD16", "PD17",
766 "PD18", 766 "PD18", "PD19", "PD20", "PD21";
767 function = "lc 767 function = "lcd0";
768 }; 768 };
769 769
770 mmc0_pins: mmc0-pins { 770 mmc0_pins: mmc0-pins {
771 pins = "PF0", 771 pins = "PF0", "PF1", "PF2", "PF3",
772 "PF4", 772 "PF4", "PF5";
773 function = "mm 773 function = "mmc0";
774 drive-strength 774 drive-strength = <30>;
775 bias-pull-up; 775 bias-pull-up;
776 }; 776 };
777 777
778 mmc1_pins: mmc1-pins { 778 mmc1_pins: mmc1-pins {
779 pins = "PG0", 779 pins = "PG0", "PG1", "PG2", "PG3",
780 "PG4", 780 "PG4", "PG5";
781 function = "mm 781 function = "mmc1";
782 drive-strength 782 drive-strength = <30>;
783 bias-pull-up; 783 bias-pull-up;
784 }; 784 };
785 785
786 mmc2_pins: mmc2-pins { 786 mmc2_pins: mmc2-pins {
787 pins = "PC5", 787 pins = "PC5", "PC6", "PC8", "PC9",
788 "PC10", 788 "PC10","PC11", "PC12", "PC13",
789 "PC14", 789 "PC14", "PC15", "PC16";
790 function = "mm 790 function = "mmc2";
791 drive-strength 791 drive-strength = <30>;
792 bias-pull-up; 792 bias-pull-up;
793 }; 793 };
794 794
795 mmc2_ds_pin: mmc2-ds-p 795 mmc2_ds_pin: mmc2-ds-pin {
796 pins = "PC1"; 796 pins = "PC1";
797 function = "mm 797 function = "mmc2";
798 drive-strength 798 drive-strength = <30>;
799 bias-pull-up; 799 bias-pull-up;
800 }; 800 };
801 801
802 pwm_pin: pwm-pin { 802 pwm_pin: pwm-pin {
803 pins = "PD22"; 803 pins = "PD22";
804 function = "pw 804 function = "pwm";
805 }; 805 };
806 806
807 rmii_pins: rmii-pins { 807 rmii_pins: rmii-pins {
808 pins = "PD10", 808 pins = "PD10", "PD11", "PD13", "PD14", "PD17",
809 "PD18", 809 "PD18", "PD19", "PD20", "PD22", "PD23";
810 function = "em 810 function = "emac";
811 drive-strength 811 drive-strength = <40>;
812 }; 812 };
813 813
814 rgmii_pins: rgmii-pins 814 rgmii_pins: rgmii-pins {
815 pins = "PD8", 815 pins = "PD8", "PD9", "PD10", "PD11", "PD12",
816 "PD13", 816 "PD13", "PD15", "PD16", "PD17", "PD18",
817 "PD19", 817 "PD19", "PD20", "PD21", "PD22", "PD23";
818 function = "em 818 function = "emac";
819 drive-strength 819 drive-strength = <40>;
820 }; 820 };
821 821
822 spdif_tx_pin: spdif-tx 822 spdif_tx_pin: spdif-tx-pin {
823 pins = "PH8"; 823 pins = "PH8";
824 function = "sp 824 function = "spdif";
825 }; 825 };
826 826
827 spi0_pins: spi0-pins { 827 spi0_pins: spi0-pins {
828 pins = "PC0", 828 pins = "PC0", "PC1", "PC2", "PC3";
829 function = "sp 829 function = "spi0";
830 }; 830 };
831 831
832 spi1_pins: spi1-pins { 832 spi1_pins: spi1-pins {
833 pins = "PD0", 833 pins = "PD0", "PD1", "PD2", "PD3";
834 function = "sp 834 function = "spi1";
835 }; 835 };
836 836
837 uart0_pb_pins: uart0-p 837 uart0_pb_pins: uart0-pb-pins {
838 pins = "PB8", 838 pins = "PB8", "PB9";
839 function = "ua 839 function = "uart0";
840 }; 840 };
841 841
842 uart1_pins: uart1-pins 842 uart1_pins: uart1-pins {
843 pins = "PG6", 843 pins = "PG6", "PG7";
844 function = "ua 844 function = "uart1";
845 }; 845 };
846 846
847 uart1_rts_cts_pins: ua 847 uart1_rts_cts_pins: uart1-rts-cts-pins {
848 pins = "PG8", 848 pins = "PG8", "PG9";
849 function = "ua 849 function = "uart1";
850 }; 850 };
851 851
852 uart2_pins: uart2-pins 852 uart2_pins: uart2-pins {
853 pins = "PB0", 853 pins = "PB0", "PB1";
854 function = "ua 854 function = "uart2";
855 }; 855 };
856 856
857 uart3_pins: uart3-pins 857 uart3_pins: uart3-pins {
858 pins = "PD0", 858 pins = "PD0", "PD1";
859 function = "ua 859 function = "uart3";
860 }; 860 };
861 861
862 uart4_pins: uart4-pins 862 uart4_pins: uart4-pins {
863 pins = "PD2", 863 pins = "PD2", "PD3";
864 function = "ua 864 function = "uart4";
865 }; 865 };
866 866
867 uart4_rts_cts_pins: ua 867 uart4_rts_cts_pins: uart4-rts-cts-pins {
868 pins = "PD4", 868 pins = "PD4", "PD5";
869 function = "ua 869 function = "uart4";
870 }; 870 };
871 }; 871 };
872 872
873 timer@1c20c00 { 873 timer@1c20c00 {
874 compatible = "allwinne 874 compatible = "allwinner,sun50i-a64-timer",
875 "allwinne 875 "allwinner,sun8i-a23-timer";
876 reg = <0x01c20c00 0xa0 876 reg = <0x01c20c00 0xa0>;
877 interrupts = <GIC_SPI 877 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
878 <GIC_SPI 878 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
879 clocks = <&osc24M>; 879 clocks = <&osc24M>;
880 }; 880 };
881 881
882 wdt0: watchdog@1c20ca0 { 882 wdt0: watchdog@1c20ca0 {
883 compatible = "allwinne 883 compatible = "allwinner,sun50i-a64-wdt",
884 "allwinne 884 "allwinner,sun6i-a31-wdt";
885 reg = <0x01c20ca0 0x20 885 reg = <0x01c20ca0 0x20>;
886 interrupts = <GIC_SPI 886 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
887 clocks = <&osc24M>; 887 clocks = <&osc24M>;
888 }; 888 };
889 889
890 spdif: spdif@1c21000 { 890 spdif: spdif@1c21000 {
891 #sound-dai-cells = <0> 891 #sound-dai-cells = <0>;
892 compatible = "allwinne 892 compatible = "allwinner,sun50i-a64-spdif",
893 "allwinne 893 "allwinner,sun8i-h3-spdif";
894 reg = <0x01c21000 0x40 894 reg = <0x01c21000 0x400>;
895 interrupts = <GIC_SPI 895 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
896 clocks = <&ccu CLK_BUS 896 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
897 resets = <&ccu RST_BUS 897 resets = <&ccu RST_BUS_SPDIF>;
898 clock-names = "apb", " 898 clock-names = "apb", "spdif";
899 dmas = <&dma 2>; 899 dmas = <&dma 2>;
900 dma-names = "tx"; 900 dma-names = "tx";
901 pinctrl-names = "defau 901 pinctrl-names = "default";
902 pinctrl-0 = <&spdif_tx 902 pinctrl-0 = <&spdif_tx_pin>;
903 status = "disabled"; 903 status = "disabled";
904 }; 904 };
905 905
906 lradc: lradc@1c21800 { 906 lradc: lradc@1c21800 {
907 compatible = "allwinne 907 compatible = "allwinner,sun50i-a64-lradc",
908 "allwinne 908 "allwinner,sun8i-a83t-r-lradc";
909 reg = <0x01c21800 0x40 909 reg = <0x01c21800 0x400>;
910 interrupt-parent = <&r 910 interrupt-parent = <&r_intc>;
911 interrupts = <GIC_SPI 911 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
912 status = "disabled"; 912 status = "disabled";
913 }; 913 };
914 914
915 i2s0: i2s@1c22000 { 915 i2s0: i2s@1c22000 {
916 #sound-dai-cells = <0> 916 #sound-dai-cells = <0>;
917 compatible = "allwinne 917 compatible = "allwinner,sun50i-a64-i2s",
918 "allwinne 918 "allwinner,sun8i-h3-i2s";
919 reg = <0x01c22000 0x40 919 reg = <0x01c22000 0x400>;
920 interrupts = <GIC_SPI 920 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
921 clocks = <&ccu CLK_BUS 921 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
922 clock-names = "apb", " 922 clock-names = "apb", "mod";
923 resets = <&ccu RST_BUS 923 resets = <&ccu RST_BUS_I2S0>;
924 dma-names = "rx", "tx" 924 dma-names = "rx", "tx";
925 dmas = <&dma 3>, <&dma 925 dmas = <&dma 3>, <&dma 3>;
926 status = "disabled"; 926 status = "disabled";
927 }; 927 };
928 928
929 i2s1: i2s@1c22400 { 929 i2s1: i2s@1c22400 {
930 #sound-dai-cells = <0> 930 #sound-dai-cells = <0>;
931 compatible = "allwinne 931 compatible = "allwinner,sun50i-a64-i2s",
932 "allwinne 932 "allwinner,sun8i-h3-i2s";
933 reg = <0x01c22400 0x40 933 reg = <0x01c22400 0x400>;
934 interrupts = <GIC_SPI 934 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
935 clocks = <&ccu CLK_BUS 935 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
936 clock-names = "apb", " 936 clock-names = "apb", "mod";
937 resets = <&ccu RST_BUS 937 resets = <&ccu RST_BUS_I2S1>;
938 dma-names = "rx", "tx" 938 dma-names = "rx", "tx";
939 dmas = <&dma 4>, <&dma 939 dmas = <&dma 4>, <&dma 4>;
940 status = "disabled"; 940 status = "disabled";
941 }; 941 };
942 942
943 i2s2: i2s@1c22800 { 943 i2s2: i2s@1c22800 {
944 #sound-dai-cells = <0> 944 #sound-dai-cells = <0>;
945 compatible = "allwinne 945 compatible = "allwinner,sun50i-a64-i2s",
946 "allwinne 946 "allwinner,sun8i-h3-i2s";
947 reg = <0x01c22800 0x40 947 reg = <0x01c22800 0x400>;
948 interrupts = <GIC_SPI 948 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
949 clocks = <&ccu CLK_BUS 949 clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
950 clock-names = "apb", " 950 clock-names = "apb", "mod";
951 resets = <&ccu RST_BUS 951 resets = <&ccu RST_BUS_I2S2>;
952 dma-names = "rx", "tx" 952 dma-names = "rx", "tx";
953 dmas = <&dma 27>, <&dm 953 dmas = <&dma 27>, <&dma 27>;
954 status = "disabled"; 954 status = "disabled";
955 }; 955 };
956 956
957 dai: dai@1c22c00 { 957 dai: dai@1c22c00 {
958 #sound-dai-cells = <0> 958 #sound-dai-cells = <0>;
959 compatible = "allwinne 959 compatible = "allwinner,sun50i-a64-codec-i2s";
960 reg = <0x01c22c00 0x20 960 reg = <0x01c22c00 0x200>;
961 interrupts = <GIC_SPI 961 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
962 clocks = <&ccu CLK_BUS 962 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
963 clock-names = "apb", " 963 clock-names = "apb", "mod";
964 resets = <&ccu RST_BUS 964 resets = <&ccu RST_BUS_CODEC>;
965 dmas = <&dma 15>, <&dm 965 dmas = <&dma 15>, <&dma 15>;
966 dma-names = "rx", "tx" 966 dma-names = "rx", "tx";
967 status = "disabled"; 967 status = "disabled";
968 }; 968 };
969 969
970 codec: codec@1c22e00 { 970 codec: codec@1c22e00 {
971 #sound-dai-cells = <1> 971 #sound-dai-cells = <1>;
972 compatible = "allwinne 972 compatible = "allwinner,sun50i-a64-codec",
973 "allwinne 973 "allwinner,sun8i-a33-codec";
974 reg = <0x01c22e00 0x60 974 reg = <0x01c22e00 0x600>;
975 interrupts = <GIC_SPI 975 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
976 clocks = <&ccu CLK_BUS 976 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
977 clock-names = "bus", " 977 clock-names = "bus", "mod";
978 status = "disabled"; 978 status = "disabled";
979 }; 979 };
980 980
981 ths: thermal-sensor@1c25000 { 981 ths: thermal-sensor@1c25000 {
982 compatible = "allwinne 982 compatible = "allwinner,sun50i-a64-ths";
983 reg = <0x01c25000 0x10 983 reg = <0x01c25000 0x100>;
984 clocks = <&ccu CLK_BUS 984 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
985 clock-names = "bus", " 985 clock-names = "bus", "mod";
986 interrupts = <GIC_SPI 986 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
987 resets = <&ccu RST_BUS 987 resets = <&ccu RST_BUS_THS>;
988 nvmem-cells = <&ths_ca 988 nvmem-cells = <&ths_calibration>;
989 nvmem-cell-names = "ca 989 nvmem-cell-names = "calibration";
990 #thermal-sensor-cells 990 #thermal-sensor-cells = <1>;
991 }; 991 };
992 992
993 uart0: serial@1c28000 { 993 uart0: serial@1c28000 {
994 compatible = "snps,dw- 994 compatible = "snps,dw-apb-uart";
995 reg = <0x01c28000 0x40 995 reg = <0x01c28000 0x400>;
996 interrupts = <GIC_SPI 996 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
997 reg-shift = <2>; 997 reg-shift = <2>;
998 reg-io-width = <4>; 998 reg-io-width = <4>;
999 clocks = <&ccu CLK_BUS 999 clocks = <&ccu CLK_BUS_UART0>;
1000 resets = <&ccu RST_BU 1000 resets = <&ccu RST_BUS_UART0>;
1001 status = "disabled"; 1001 status = "disabled";
1002 }; 1002 };
1003 1003
1004 uart1: serial@1c28400 { 1004 uart1: serial@1c28400 {
1005 compatible = "snps,dw 1005 compatible = "snps,dw-apb-uart";
1006 reg = <0x01c28400 0x4 1006 reg = <0x01c28400 0x400>;
1007 interrupts = <GIC_SPI 1007 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1008 reg-shift = <2>; 1008 reg-shift = <2>;
1009 reg-io-width = <4>; 1009 reg-io-width = <4>;
1010 clocks = <&ccu CLK_BU 1010 clocks = <&ccu CLK_BUS_UART1>;
1011 resets = <&ccu RST_BU 1011 resets = <&ccu RST_BUS_UART1>;
1012 status = "disabled"; 1012 status = "disabled";
1013 }; 1013 };
1014 1014
1015 uart2: serial@1c28800 { 1015 uart2: serial@1c28800 {
1016 compatible = "snps,dw 1016 compatible = "snps,dw-apb-uart";
1017 reg = <0x01c28800 0x4 1017 reg = <0x01c28800 0x400>;
1018 interrupts = <GIC_SPI 1018 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1019 reg-shift = <2>; 1019 reg-shift = <2>;
1020 reg-io-width = <4>; 1020 reg-io-width = <4>;
1021 clocks = <&ccu CLK_BU 1021 clocks = <&ccu CLK_BUS_UART2>;
1022 resets = <&ccu RST_BU 1022 resets = <&ccu RST_BUS_UART2>;
1023 status = "disabled"; 1023 status = "disabled";
1024 }; 1024 };
1025 1025
1026 uart3: serial@1c28c00 { 1026 uart3: serial@1c28c00 {
1027 compatible = "snps,dw 1027 compatible = "snps,dw-apb-uart";
1028 reg = <0x01c28c00 0x4 1028 reg = <0x01c28c00 0x400>;
1029 interrupts = <GIC_SPI 1029 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1030 reg-shift = <2>; 1030 reg-shift = <2>;
1031 reg-io-width = <4>; 1031 reg-io-width = <4>;
1032 clocks = <&ccu CLK_BU 1032 clocks = <&ccu CLK_BUS_UART3>;
1033 resets = <&ccu RST_BU 1033 resets = <&ccu RST_BUS_UART3>;
1034 status = "disabled"; 1034 status = "disabled";
1035 }; 1035 };
1036 1036
1037 uart4: serial@1c29000 { 1037 uart4: serial@1c29000 {
1038 compatible = "snps,dw 1038 compatible = "snps,dw-apb-uart";
1039 reg = <0x01c29000 0x4 1039 reg = <0x01c29000 0x400>;
1040 interrupts = <GIC_SPI 1040 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1041 reg-shift = <2>; 1041 reg-shift = <2>;
1042 reg-io-width = <4>; 1042 reg-io-width = <4>;
1043 clocks = <&ccu CLK_BU 1043 clocks = <&ccu CLK_BUS_UART4>;
1044 resets = <&ccu RST_BU 1044 resets = <&ccu RST_BUS_UART4>;
1045 status = "disabled"; 1045 status = "disabled";
1046 }; 1046 };
1047 1047
1048 i2c0: i2c@1c2ac00 { 1048 i2c0: i2c@1c2ac00 {
1049 compatible = "allwinn 1049 compatible = "allwinner,sun6i-a31-i2c";
1050 reg = <0x01c2ac00 0x4 1050 reg = <0x01c2ac00 0x400>;
1051 interrupts = <GIC_SPI 1051 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1052 clocks = <&ccu CLK_BU 1052 clocks = <&ccu CLK_BUS_I2C0>;
1053 resets = <&ccu RST_BU 1053 resets = <&ccu RST_BUS_I2C0>;
1054 pinctrl-names = "defa 1054 pinctrl-names = "default";
1055 pinctrl-0 = <&i2c0_pi 1055 pinctrl-0 = <&i2c0_pins>;
1056 status = "disabled"; 1056 status = "disabled";
1057 #address-cells = <1>; 1057 #address-cells = <1>;
1058 #size-cells = <0>; 1058 #size-cells = <0>;
1059 }; 1059 };
1060 1060
1061 i2c1: i2c@1c2b000 { 1061 i2c1: i2c@1c2b000 {
1062 compatible = "allwinn 1062 compatible = "allwinner,sun6i-a31-i2c";
1063 reg = <0x01c2b000 0x4 1063 reg = <0x01c2b000 0x400>;
1064 interrupts = <GIC_SPI 1064 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1065 clocks = <&ccu CLK_BU 1065 clocks = <&ccu CLK_BUS_I2C1>;
1066 resets = <&ccu RST_BU 1066 resets = <&ccu RST_BUS_I2C1>;
1067 pinctrl-names = "defa 1067 pinctrl-names = "default";
1068 pinctrl-0 = <&i2c1_pi 1068 pinctrl-0 = <&i2c1_pins>;
1069 status = "disabled"; 1069 status = "disabled";
1070 #address-cells = <1>; 1070 #address-cells = <1>;
1071 #size-cells = <0>; 1071 #size-cells = <0>;
1072 }; 1072 };
1073 1073
1074 i2c2: i2c@1c2b400 { 1074 i2c2: i2c@1c2b400 {
1075 compatible = "allwinn 1075 compatible = "allwinner,sun6i-a31-i2c";
1076 reg = <0x01c2b400 0x4 1076 reg = <0x01c2b400 0x400>;
1077 interrupts = <GIC_SPI 1077 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1078 clocks = <&ccu CLK_BU 1078 clocks = <&ccu CLK_BUS_I2C2>;
1079 resets = <&ccu RST_BU 1079 resets = <&ccu RST_BUS_I2C2>;
1080 pinctrl-names = "defa 1080 pinctrl-names = "default";
1081 pinctrl-0 = <&i2c2_pi 1081 pinctrl-0 = <&i2c2_pins>;
1082 status = "disabled"; 1082 status = "disabled";
1083 #address-cells = <1>; 1083 #address-cells = <1>;
1084 #size-cells = <0>; 1084 #size-cells = <0>;
1085 }; 1085 };
1086 1086
1087 spi0: spi@1c68000 { 1087 spi0: spi@1c68000 {
1088 compatible = "allwinn 1088 compatible = "allwinner,sun8i-h3-spi";
1089 reg = <0x01c68000 0x1 1089 reg = <0x01c68000 0x1000>;
1090 interrupts = <GIC_SPI 1090 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1091 clocks = <&ccu CLK_BU 1091 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
1092 clock-names = "ahb", 1092 clock-names = "ahb", "mod";
1093 dmas = <&dma 23>, <&d 1093 dmas = <&dma 23>, <&dma 23>;
1094 dma-names = "rx", "tx 1094 dma-names = "rx", "tx";
1095 pinctrl-names = "defa 1095 pinctrl-names = "default";
1096 pinctrl-0 = <&spi0_pi 1096 pinctrl-0 = <&spi0_pins>;
1097 resets = <&ccu RST_BU 1097 resets = <&ccu RST_BUS_SPI0>;
1098 status = "disabled"; 1098 status = "disabled";
1099 num-cs = <1>; 1099 num-cs = <1>;
1100 #address-cells = <1>; 1100 #address-cells = <1>;
1101 #size-cells = <0>; 1101 #size-cells = <0>;
1102 }; 1102 };
1103 1103
1104 spi1: spi@1c69000 { 1104 spi1: spi@1c69000 {
1105 compatible = "allwinn 1105 compatible = "allwinner,sun8i-h3-spi";
1106 reg = <0x01c69000 0x1 1106 reg = <0x01c69000 0x1000>;
1107 interrupts = <GIC_SPI 1107 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1108 clocks = <&ccu CLK_BU 1108 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
1109 clock-names = "ahb", 1109 clock-names = "ahb", "mod";
1110 dmas = <&dma 24>, <&d 1110 dmas = <&dma 24>, <&dma 24>;
1111 dma-names = "rx", "tx 1111 dma-names = "rx", "tx";
1112 pinctrl-names = "defa 1112 pinctrl-names = "default";
1113 pinctrl-0 = <&spi1_pi 1113 pinctrl-0 = <&spi1_pins>;
1114 resets = <&ccu RST_BU 1114 resets = <&ccu RST_BUS_SPI1>;
1115 status = "disabled"; 1115 status = "disabled";
1116 num-cs = <1>; 1116 num-cs = <1>;
1117 #address-cells = <1>; 1117 #address-cells = <1>;
1118 #size-cells = <0>; 1118 #size-cells = <0>;
1119 }; 1119 };
1120 1120
1121 emac: ethernet@1c30000 { 1121 emac: ethernet@1c30000 {
1122 compatible = "allwinn 1122 compatible = "allwinner,sun50i-a64-emac";
1123 syscon = <&syscon>; 1123 syscon = <&syscon>;
1124 reg = <0x01c30000 0x1 1124 reg = <0x01c30000 0x10000>;
1125 interrupts = <GIC_SPI 1125 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1126 interrupt-names = "ma 1126 interrupt-names = "macirq";
1127 resets = <&ccu RST_BU 1127 resets = <&ccu RST_BUS_EMAC>;
1128 reset-names = "stmmac 1128 reset-names = "stmmaceth";
1129 clocks = <&ccu CLK_BU 1129 clocks = <&ccu CLK_BUS_EMAC>;
1130 clock-names = "stmmac 1130 clock-names = "stmmaceth";
1131 status = "disabled"; 1131 status = "disabled";
1132 1132
1133 mdio: mdio { 1133 mdio: mdio {
1134 compatible = 1134 compatible = "snps,dwmac-mdio";
1135 #address-cell 1135 #address-cells = <1>;
1136 #size-cells = 1136 #size-cells = <0>;
1137 }; 1137 };
1138 }; 1138 };
1139 1139
1140 mali: gpu@1c40000 { 1140 mali: gpu@1c40000 {
1141 compatible = "allwinn 1141 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400";
1142 reg = <0x01c40000 0x1 1142 reg = <0x01c40000 0x10000>;
1143 interrupts = <GIC_SPI 1143 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1144 <GIC_SPI 1144 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1145 <GIC_SPI 1145 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1146 <GIC_SPI 1146 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1147 <GIC_SPI 1147 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1148 <GIC_SPI 1148 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1149 <GIC_SPI 1149 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1150 interrupt-names = "gp 1150 interrupt-names = "gp",
1151 "gp 1151 "gpmmu",
1152 "pp 1152 "pp0",
1153 "pp 1153 "ppmmu0",
1154 "pp 1154 "pp1",
1155 "pp 1155 "ppmmu1",
1156 "pm 1156 "pmu";
1157 clocks = <&ccu CLK_BU 1157 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
1158 clock-names = "bus", 1158 clock-names = "bus", "core";
1159 resets = <&ccu RST_BU 1159 resets = <&ccu RST_BUS_GPU>;
1160 operating-points-v2 = 1160 operating-points-v2 = <&gpu_opp_table>;
1161 }; 1161 };
1162 1162
1163 gic: interrupt-controller@1c8 1163 gic: interrupt-controller@1c81000 {
1164 compatible = "arm,gic 1164 compatible = "arm,gic-400";
1165 reg = <0x01c81000 0x1 1165 reg = <0x01c81000 0x1000>,
1166 <0x01c82000 0x2 1166 <0x01c82000 0x2000>,
1167 <0x01c84000 0x2 1167 <0x01c84000 0x2000>,
1168 <0x01c86000 0x2 1168 <0x01c86000 0x2000>;
1169 interrupts = <GIC_PPI 1169 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1170 interrupt-controller; 1170 interrupt-controller;
1171 #interrupt-cells = <3 1171 #interrupt-cells = <3>;
1172 }; 1172 };
1173 1173
1174 pwm: pwm@1c21400 { 1174 pwm: pwm@1c21400 {
1175 compatible = "allwinn 1175 compatible = "allwinner,sun50i-a64-pwm",
1176 "allwinn 1176 "allwinner,sun5i-a13-pwm";
1177 reg = <0x01c21400 0x4 1177 reg = <0x01c21400 0x400>;
1178 clocks = <&osc24M>; 1178 clocks = <&osc24M>;
1179 pinctrl-names = "defa 1179 pinctrl-names = "default";
1180 pinctrl-0 = <&pwm_pin 1180 pinctrl-0 = <&pwm_pin>;
1181 #pwm-cells = <3>; 1181 #pwm-cells = <3>;
1182 status = "disabled"; 1182 status = "disabled";
1183 }; 1183 };
1184 1184
1185 mbus: dram-controller@1c62000 1185 mbus: dram-controller@1c62000 {
1186 compatible = "allwinn 1186 compatible = "allwinner,sun50i-a64-mbus";
1187 reg = <0x01c62000 0x1 1187 reg = <0x01c62000 0x1000>,
1188 <0x01c63000 0x1 1188 <0x01c63000 0x1000>;
1189 reg-names = "mbus", " 1189 reg-names = "mbus", "dram";
1190 clocks = <&ccu CLK_MB 1190 clocks = <&ccu CLK_MBUS>,
1191 <&ccu CLK_DR 1191 <&ccu CLK_DRAM>,
1192 <&ccu CLK_BU 1192 <&ccu CLK_BUS_DRAM>;
1193 clock-names = "mbus", 1193 clock-names = "mbus", "dram", "bus";
1194 interrupts = <GIC_SPI 1194 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
1195 #address-cells = <1>; 1195 #address-cells = <1>;
1196 #size-cells = <1>; 1196 #size-cells = <1>;
1197 dma-ranges = <0x00000 1197 dma-ranges = <0x00000000 0x40000000 0xc0000000>;
1198 #interconnect-cells = 1198 #interconnect-cells = <1>;
1199 }; 1199 };
1200 1200
1201 csi: csi@1cb0000 { 1201 csi: csi@1cb0000 {
1202 compatible = "allwinn 1202 compatible = "allwinner,sun50i-a64-csi";
1203 reg = <0x01cb0000 0x1 1203 reg = <0x01cb0000 0x1000>;
1204 interrupts = <GIC_SPI 1204 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1205 clocks = <&ccu CLK_BU 1205 clocks = <&ccu CLK_BUS_CSI>,
1206 <&ccu CLK_CS 1206 <&ccu CLK_CSI_SCLK>,
1207 <&ccu CLK_DR 1207 <&ccu CLK_DRAM_CSI>;
1208 clock-names = "bus", 1208 clock-names = "bus", "mod", "ram";
1209 resets = <&ccu RST_BU 1209 resets = <&ccu RST_BUS_CSI>;
1210 pinctrl-names = "defa 1210 pinctrl-names = "default";
1211 pinctrl-0 = <&csi_pin 1211 pinctrl-0 = <&csi_pins>;
1212 status = "disabled"; 1212 status = "disabled";
1213 }; 1213 };
1214 1214
1215 dsi: dsi@1ca0000 { 1215 dsi: dsi@1ca0000 {
1216 compatible = "allwinn 1216 compatible = "allwinner,sun50i-a64-mipi-dsi";
1217 reg = <0x01ca0000 0x1 1217 reg = <0x01ca0000 0x1000>;
1218 interrupts = <GIC_SPI 1218 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1219 clocks = <&ccu CLK_BU 1219 clocks = <&ccu CLK_BUS_MIPI_DSI>;
1220 resets = <&ccu RST_BU 1220 resets = <&ccu RST_BUS_MIPI_DSI>;
1221 phys = <&dphy>; 1221 phys = <&dphy>;
1222 phy-names = "dphy"; 1222 phy-names = "dphy";
1223 status = "disabled"; 1223 status = "disabled";
1224 #address-cells = <1>; 1224 #address-cells = <1>;
1225 #size-cells = <0>; 1225 #size-cells = <0>;
1226 1226
1227 port { 1227 port {
1228 dsi_in_tcon0: 1228 dsi_in_tcon0: endpoint {
1229 remot 1229 remote-endpoint = <&tcon0_out_dsi>;
1230 }; 1230 };
1231 }; 1231 };
1232 }; 1232 };
1233 1233
1234 dphy: d-phy@1ca1000 { 1234 dphy: d-phy@1ca1000 {
1235 compatible = "allwinn 1235 compatible = "allwinner,sun50i-a64-mipi-dphy",
1236 "allwinn 1236 "allwinner,sun6i-a31-mipi-dphy";
1237 reg = <0x01ca1000 0x1 1237 reg = <0x01ca1000 0x1000>;
1238 interrupts = <GIC_SPI 1238 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1239 clocks = <&ccu CLK_BU 1239 clocks = <&ccu CLK_BUS_MIPI_DSI>,
1240 <&ccu CLK_DS 1240 <&ccu CLK_DSI_DPHY>;
1241 clock-names = "bus", 1241 clock-names = "bus", "mod";
1242 resets = <&ccu RST_BU 1242 resets = <&ccu RST_BUS_MIPI_DSI>;
1243 status = "disabled"; 1243 status = "disabled";
1244 #phy-cells = <0>; 1244 #phy-cells = <0>;
1245 }; 1245 };
1246 1246
1247 deinterlace: deinterlace@1e00 1247 deinterlace: deinterlace@1e00000 {
1248 compatible = "allwinn 1248 compatible = "allwinner,sun50i-a64-deinterlace",
1249 "allwinn 1249 "allwinner,sun8i-h3-deinterlace";
1250 reg = <0x01e00000 0x2 1250 reg = <0x01e00000 0x20000>;
1251 clocks = <&ccu CLK_BU 1251 clocks = <&ccu CLK_BUS_DEINTERLACE>,
1252 <&ccu CLK_DE 1252 <&ccu CLK_DEINTERLACE>,
1253 <&ccu CLK_DR 1253 <&ccu CLK_DRAM_DEINTERLACE>;
1254 clock-names = "bus", 1254 clock-names = "bus", "mod", "ram";
1255 resets = <&ccu RST_BU 1255 resets = <&ccu RST_BUS_DEINTERLACE>;
1256 interrupts = <GIC_SPI 1256 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1257 interconnects = <&mbu 1257 interconnects = <&mbus 9>;
1258 interconnect-names = 1258 interconnect-names = "dma-mem";
1259 }; 1259 };
1260 1260
1261 hdmi: hdmi@1ee0000 { 1261 hdmi: hdmi@1ee0000 {
1262 compatible = "allwinn 1262 compatible = "allwinner,sun50i-a64-dw-hdmi",
1263 "allwinn 1263 "allwinner,sun8i-a83t-dw-hdmi";
1264 reg = <0x01ee0000 0x1 1264 reg = <0x01ee0000 0x10000>;
1265 reg-io-width = <1>; 1265 reg-io-width = <1>;
1266 interrupts = <GIC_SPI 1266 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1267 clocks = <&ccu CLK_BU 1267 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1268 <&ccu CLK_HD 1268 <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>;
1269 clock-names = "iahb", 1269 clock-names = "iahb", "isfr", "tmds", "cec";
1270 resets = <&ccu RST_BU 1270 resets = <&ccu RST_BUS_HDMI1>;
1271 reset-names = "ctrl"; 1271 reset-names = "ctrl";
1272 phys = <&hdmi_phy>; 1272 phys = <&hdmi_phy>;
1273 phy-names = "phy"; 1273 phy-names = "phy";
1274 status = "disabled"; 1274 status = "disabled";
1275 1275
1276 ports { 1276 ports {
1277 #address-cell 1277 #address-cells = <1>;
1278 #size-cells = 1278 #size-cells = <0>;
1279 1279
1280 hdmi_in: port 1280 hdmi_in: port@0 {
1281 reg = 1281 reg = <0>;
1282 1282
1283 hdmi_ 1283 hdmi_in_tcon1: endpoint {
1284 1284 remote-endpoint = <&tcon1_out_hdmi>;
1285 }; 1285 };
1286 }; 1286 };
1287 1287
1288 hdmi_out: por 1288 hdmi_out: port@1 {
1289 reg = 1289 reg = <1>;
1290 }; 1290 };
1291 }; 1291 };
1292 }; 1292 };
1293 1293
1294 hdmi_phy: hdmi-phy@1ef0000 { 1294 hdmi_phy: hdmi-phy@1ef0000 {
1295 compatible = "allwinn 1295 compatible = "allwinner,sun50i-a64-hdmi-phy";
1296 reg = <0x01ef0000 0x1 1296 reg = <0x01ef0000 0x10000>;
1297 clocks = <&ccu CLK_BU 1297 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1298 <&ccu CLK_PL 1298 <&ccu CLK_PLL_VIDEO0>;
1299 clock-names = "bus", 1299 clock-names = "bus", "mod", "pll-0";
1300 resets = <&ccu RST_BU 1300 resets = <&ccu RST_BUS_HDMI0>;
1301 reset-names = "phy"; 1301 reset-names = "phy";
1302 #phy-cells = <0>; 1302 #phy-cells = <0>;
1303 }; 1303 };
1304 1304
1305 rtc: rtc@1f00000 { 1305 rtc: rtc@1f00000 {
1306 compatible = "allwinn 1306 compatible = "allwinner,sun50i-a64-rtc",
1307 "allwinn 1307 "allwinner,sun8i-h3-rtc";
1308 reg = <0x01f00000 0x4 1308 reg = <0x01f00000 0x400>;
1309 interrupt-parent = <& 1309 interrupt-parent = <&r_intc>;
1310 interrupts = <GIC_SPI 1310 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1311 <GIC_SPI 1311 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1312 clock-output-names = 1312 clock-output-names = "osc32k", "osc32k-out", "iosc";
1313 clocks = <&osc32k>; 1313 clocks = <&osc32k>;
1314 #clock-cells = <1>; 1314 #clock-cells = <1>;
1315 }; 1315 };
1316 1316
1317 r_intc: interrupt-controller@ 1317 r_intc: interrupt-controller@1f00c00 {
1318 compatible = "allwinn 1318 compatible = "allwinner,sun50i-a64-r-intc",
1319 "allwinn 1319 "allwinner,sun6i-a31-r-intc";
1320 interrupt-controller; 1320 interrupt-controller;
1321 #interrupt-cells = <3 1321 #interrupt-cells = <3>;
1322 reg = <0x01f00c00 0x4 1322 reg = <0x01f00c00 0x400>;
1323 interrupts = <GIC_SPI 1323 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1324 }; 1324 };
1325 1325
1326 r_ccu: clock@1f01400 { 1326 r_ccu: clock@1f01400 {
1327 compatible = "allwinn 1327 compatible = "allwinner,sun50i-a64-r-ccu";
1328 reg = <0x01f01400 0x1 1328 reg = <0x01f01400 0x100>;
1329 clocks = <&osc24M>, < 1329 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
1330 <&ccu CLK_PL 1330 <&ccu CLK_PLL_PERIPH0>;
1331 clock-names = "hosc", 1331 clock-names = "hosc", "losc", "iosc", "pll-periph";
1332 #clock-cells = <1>; 1332 #clock-cells = <1>;
1333 #reset-cells = <1>; 1333 #reset-cells = <1>;
1334 }; 1334 };
1335 1335
1336 codec_analog: codec-analog@1f 1336 codec_analog: codec-analog@1f015c0 {
1337 compatible = "allwinn 1337 compatible = "allwinner,sun50i-a64-codec-analog";
1338 reg = <0x01f015c0 0x4 1338 reg = <0x01f015c0 0x4>;
1339 status = "disabled"; 1339 status = "disabled";
1340 }; 1340 };
1341 1341
1342 r_i2c: i2c@1f02400 { 1342 r_i2c: i2c@1f02400 {
1343 compatible = "allwinn 1343 compatible = "allwinner,sun50i-a64-i2c",
1344 "allwinn 1344 "allwinner,sun6i-a31-i2c";
1345 reg = <0x01f02400 0x4 1345 reg = <0x01f02400 0x400>;
1346 interrupts = <GIC_SPI 1346 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1347 clocks = <&r_ccu CLK_ 1347 clocks = <&r_ccu CLK_APB0_I2C>;
1348 resets = <&r_ccu RST_ 1348 resets = <&r_ccu RST_APB0_I2C>;
1349 status = "disabled"; 1349 status = "disabled";
1350 #address-cells = <1>; 1350 #address-cells = <1>;
1351 #size-cells = <0>; 1351 #size-cells = <0>;
1352 }; 1352 };
1353 1353
1354 r_ir: ir@1f02000 { 1354 r_ir: ir@1f02000 {
1355 compatible = "allwinn 1355 compatible = "allwinner,sun50i-a64-ir",
1356 "allwinn 1356 "allwinner,sun6i-a31-ir";
1357 reg = <0x01f02000 0x4 1357 reg = <0x01f02000 0x400>;
1358 clocks = <&r_ccu CLK_ 1358 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
1359 clock-names = "apb", 1359 clock-names = "apb", "ir";
1360 resets = <&r_ccu RST_ 1360 resets = <&r_ccu RST_APB0_IR>;
1361 interrupts = <GIC_SPI 1361 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1362 pinctrl-names = "defa 1362 pinctrl-names = "default";
1363 pinctrl-0 = <&r_ir_rx 1363 pinctrl-0 = <&r_ir_rx_pin>;
1364 status = "disabled"; 1364 status = "disabled";
1365 }; 1365 };
1366 1366
1367 r_pwm: pwm@1f03800 { 1367 r_pwm: pwm@1f03800 {
1368 compatible = "allwinn 1368 compatible = "allwinner,sun50i-a64-pwm",
1369 "allwinn 1369 "allwinner,sun5i-a13-pwm";
1370 reg = <0x01f03800 0x4 1370 reg = <0x01f03800 0x400>;
1371 clocks = <&osc24M>; 1371 clocks = <&osc24M>;
1372 pinctrl-names = "defa 1372 pinctrl-names = "default";
1373 pinctrl-0 = <&r_pwm_p 1373 pinctrl-0 = <&r_pwm_pin>;
1374 #pwm-cells = <3>; 1374 #pwm-cells = <3>;
1375 status = "disabled"; 1375 status = "disabled";
1376 }; 1376 };
1377 1377
1378 r_pio: pinctrl@1f02c00 { 1378 r_pio: pinctrl@1f02c00 {
1379 compatible = "allwinn 1379 compatible = "allwinner,sun50i-a64-r-pinctrl";
1380 reg = <0x01f02c00 0x4 1380 reg = <0x01f02c00 0x400>;
1381 interrupt-parent = <& 1381 interrupt-parent = <&r_intc>;
1382 interrupts = <GIC_SPI 1382 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1383 clocks = <&r_ccu CLK_ 1383 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
1384 clock-names = "apb", 1384 clock-names = "apb", "hosc", "losc";
1385 gpio-controller; 1385 gpio-controller;
1386 #gpio-cells = <3>; 1386 #gpio-cells = <3>;
1387 interrupt-controller; 1387 interrupt-controller;
1388 #interrupt-cells = <3 1388 #interrupt-cells = <3>;
1389 1389
1390 r_i2c_pl89_pins: r-i2 1390 r_i2c_pl89_pins: r-i2c-pl89-pins {
1391 pins = "PL8", 1391 pins = "PL8", "PL9";
1392 function = "s 1392 function = "s_i2c";
1393 }; 1393 };
1394 1394
1395 r_ir_rx_pin: r-ir-rx- 1395 r_ir_rx_pin: r-ir-rx-pin {
1396 pins = "PL11" 1396 pins = "PL11";
1397 function = "s 1397 function = "s_cir_rx";
1398 }; 1398 };
1399 1399
1400 r_pwm_pin: r-pwm-pin 1400 r_pwm_pin: r-pwm-pin {
1401 pins = "PL10" 1401 pins = "PL10";
1402 function = "s 1402 function = "s_pwm";
1403 }; 1403 };
1404 1404
1405 r_rsb_pins: r-rsb-pin 1405 r_rsb_pins: r-rsb-pins {
1406 pins = "PL0", 1406 pins = "PL0", "PL1";
1407 function = "s 1407 function = "s_rsb";
1408 }; 1408 };
1409 }; 1409 };
1410 1410
1411 r_rsb: rsb@1f03400 { 1411 r_rsb: rsb@1f03400 {
1412 compatible = "allwinn 1412 compatible = "allwinner,sun8i-a23-rsb";
1413 reg = <0x01f03400 0x4 1413 reg = <0x01f03400 0x400>;
1414 interrupts = <GIC_SPI 1414 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1415 clocks = <&r_ccu 6>; 1415 clocks = <&r_ccu 6>;
1416 clock-frequency = <30 1416 clock-frequency = <3000000>;
1417 resets = <&r_ccu 2>; 1417 resets = <&r_ccu 2>;
1418 pinctrl-names = "defa 1418 pinctrl-names = "default";
1419 pinctrl-0 = <&r_rsb_p 1419 pinctrl-0 = <&r_rsb_pins>;
1420 status = "disabled"; 1420 status = "disabled";
1421 #address-cells = <1>; 1421 #address-cells = <1>;
1422 #size-cells = <0>; 1422 #size-cells = <0>;
1423 }; 1423 };
1424 }; 1424 };
1425 }; 1425 };
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